A method for decrypting an encrypted bitstream of an FPGA
By modifying the ciphertext at specific positions in the FPGA encrypted bitstream and utilizing the error propagation characteristics of the AES-CBC decryption mode, the plaintext is modified line by line. A TCL script is written to automate the operation, solving the problems of complex decryption and low accuracy in existing technologies. This achieves efficient decryption of Xilinx 7 series FPGA encrypted bitstreams.
Patent Information
- Application Number
- CN202311219109.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-20
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2043-09-20
AI Technical Summary
Existing technologies struggle to efficiently decrypt encrypted bitstreams from FPGAs, especially those from Xilinx 7 series FPGAs, as the process is complex and inaccurate.
By modifying the ciphertext at specific locations in the FPGA encrypted bitstream and utilizing the error propagation characteristics of the AES-CBC decryption mode, the plaintext is modified line by line. A TCL script is written to automate the operation, generate, and burn the bitstream.
It enables simple and efficient decryption of encrypted bit streams from Xilinx 7 series FPGAs, improving the ease of operation and accuracy.
Smart Images

Figure CN119670168B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of hardware security, and more specifically to a method for decrypting encrypted bit streams from an FPGA. Background Technology
[0002] A Field-Programmable Gate Array (FPGA) is an integrated circuit device whose hardware structure can be reconfigured according to user needs to implement various logic functions. It has a wide range of applications in many fields.
[0003] FPGAs are configured via binary bitstreams, which contain all the design information. Previously, obtaining this design information from the bitstream typically required reverse engineering to analyze the bitstream file structure and extract FPGA configuration details. However, this method is technically challenging and has low accuracy. Furthermore, to enhance bitstream security, mainstream FPGA manufacturers employ various methods, including encryption and authentication. Encryption encrypts the bitstream content, making it difficult to parse; authentication verifies the legitimacy of the bitstream during configuration, ensuring only authorized bitstreams are loaded. This invention aims to propose a simple and efficient method for decrypting encrypted FPGA bitstreams. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide a simple and efficient method for decrypting encrypted bit streams from Xilinx 7 series FPGAs.
[0005] Technical solution: A method for decrypting FPGA encrypted bitstreams, comprising the following steps:
[0006] S1. Obtain the encrypted bit stream from the FPGA.
[0007] S2. Determine the location of the command to write to the WBSTAR register based on the position of the start of decryption and ciphertext length command in the encrypted bit stream and the length of the HMAC Header area.
[0008] S3. Modify the ciphertext C to be modified, and write it to the plaintext line 3 after the line containing the WBSTAR command, i.e., P. 10 -P 13 Write it to the register.
[0009] S4. Modify the ciphertext C to be modified, and write it to the plaintext line 2 after the line containing the WBSTAR command, i.e., P6-P9, and write it to the register.
[0010] S5. Write all subsequent plaintext to the register.
[0011] S6. Write a TCL script to automate steps S3-S5, including modifying ciphertext, generating bitstream, burning bitstream, and reading register data. Attached Figure Description
[0012] Figure 1 The diagram shown is a flowchart of a method for decrypting an FPGA encrypted bit stream according to an embodiment of the present invention.
[0013] Figure 2 The image shows the encrypted bitstream data format of the Xilinx 7 series FPGA provided in this embodiment of the invention.
[0014] Figure 3 The diagram shown illustrates the error propagation of the AES-CBC decryption mode provided in an embodiment of the present invention. Detailed Implementation
[0015] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0016] This invention provides a method for decrypting encrypted bitstreams from an FPGA, such as... Figure 1 As shown, it includes the following steps S1-S7:
[0017] S1. Obtain the encrypted bit stream from the FPGA.
[0018] Currently, SRAM-based FPGAs typically store bitstreams in external non-volatile memory, such as Flash or EEPROM. These bitstreams can usually be read directly or obtained by monitoring the configuration bus of the FPGA during power-on.
[0019] S2. Determine the location of the command to write to the WBSTAR register based on the position of the start of decryption and ciphertext length command in the encrypted bit stream and the length of the HMAC Header area.
[0020] Figure 2 The diagram shows the data format of the encrypted bitstream in a Xilinx 7 series FPGA. The encryption section begins after the start of decryption and the ciphertext length. The encryption section starts with a 512-bit (4-line) HMAC Header area. The command to write to the WBSTAR register is the second configuration command after the HMAC Header. Initially, the command to write to the WBSTAR register is 0x30020001, which writes a 32-bit word following the command to the register.
[0021] S3. Modify the ciphertext C to be modified, and write it to the plaintext line 3 after the line containing the WBSTAR command, i.e., P. 10 -P 13Write it to the register.
[0022] The bitstream encryption and decryption method of Xilinx 7 series FPGAs is AES-CBC, the encryption and decryption algorithm is Advanced Encryption Standard (AES), and the encryption and decryption mode is Cipher Block Chaining (CBC) mode.
[0023] Partial decryption process such as Figure 3 As shown, each 128-bit ciphertext is divided into blocks. After the ciphertext C1 is decrypted by AES, it is XORed with the 128-bit initial vector to obtain the plaintext P1. At the same time, P1 also becomes the initial vector of the next decryption block, and so on, until all ciphertext is decrypted.
[0024] CBC decryption mode has error propagation characteristics: modifying a block of ciphertext will cause changes to the corresponding block of plaintext and the next block of plaintext. If Δ is used with a block of ciphertext C... n Perform an XOR operation; once decryption is complete, the plaintext P... n This will become a random number, plaintext P n+1 The ciphertext will be XORed with Δ. Based on this property, the plaintext can be indirectly modified by modifying the ciphertext. Since step S2 has determined the location of the command to be written to the WBSTAR register, the ciphertext C to be modified is located at the corresponding position in the line above the command.
[0025] Step S3 specifically includes the following sub-steps S31-S36:
[0026] S31, P 13 Write to the register.
[0027] By modifying C to change the WBSTAR command to 0x3002000D, the plaintext of the 13th word after the command, i.e., P, is... 13 Write to the register, and its expression is as follows:
[0028]
[0029] At the same time, to avoid configuration logic errors, C also needs to be configured. 14 Change it to 0x20000000 (empty command), its expression is as follows:
[0030] C 14 = 0x20000000
[0031] In all expressions, C represents the initial value of the ciphertext to be modified; C' represents the modified value of the ciphertext; C i This represents the initial value of the ciphertext for the i-th word after writing the WBSTAR command; C i' indicates the modified value of the ciphertext of the i-th character after being written using the WBSTAR command; P i This represents the plaintext of the i-th word written after the WBSTAR command; This represents the XOR operation.
[0032] S32, P 12 Write to the register.
[0033] By modifying C to change the WBSTAR command to 0x3002000C, the plaintext of the 12th word after the command, i.e., P, is then processed. 12 Write to the register, and its expression is as follows:
[0034]
[0035] At the same time, by modifying C9, P 13 To change to an empty command, its expression is as follows:
[0036]
[0037] S33, P 11 Write to the register.
[0038] By modifying C to change the WBSTAR command to 0x3002000B, the plaintext of the 11th word after the command, i.e., P, is... 11 Write to the register, and its expression is as follows:
[0039]
[0040] At the same time, by modifying C8, P 12 To change to an empty command, its expression is as follows:
[0041]
[0042] S34, P 10 Write to the register.
[0043] By modifying C to change the WBSTAR command to 0x3002000A, the plaintext of the 10th word after the command, i.e., P, is... 10 Write to the register, and its expression is as follows:
[0044]
[0045] At the same time, by modifying C7, P 11 To change to an empty command, its expression is as follows:
[0046]
[0047] S4. Modify the ciphertext C to be modified, and write it to the plaintext line 2 after the line containing the WBSTAR command, i.e., P6-P9, and write it to the register.
[0048] Modify C in step S3 14 Revert C9, C8, and C7 back to their initial values. Referring to the modification method in step S3, modify C in sequence, changing the WBSTAR command to 0x30020009, 0x30020008, 0x30020007, and 0x30020006. Simultaneously, modify C in sequence... 10 C5, C4, C3, and C 10 Change P5, P4, and P3 to null commands to write P9, P8, P7, and P6 into the registers.
[0049] S5. Write all subsequent plaintext to the register.
[0050] Deleting lines 1-2 of the ciphertext, i.e., C2-C9, has the following effect on the plaintext in AES-CBC decryption mode: After decryption, only the next line after the deleted part, i.e., line 3, will be decrypted into a random number, while the subsequent plaintext content will not be affected.
[0051] Referring to the modification methods in steps S3-S4, first, modify C sequentially, changing the WBSTAR command to 0x3002000D, 0x3002000C, 0x3002000B, and 0x3002000A. Simultaneously, modify C sequentially... 22 C 17 C 16 C 15 , will C 22 P 21 P 20 P 19 Change to an empty command to set P 21 P 20 P 19 P 18 Write to the register. Then, modify C. 22 C 17 C 16 C 15 Revert to its initial value, and then modify C sequentially to change the WBSTAR command to 0x30020009, 0x30020008, 0x30020007, and 0x30020006. Simultaneously, modify C sequentially. 18 C 13 C 12 C 11 , will C 18 P 17 P 16 P 15Change to an empty command to set P 17 P 16 P 15 P 14 Write to the register.
[0052] At this point, plaintext lines 2-5 have been written into the register in sequence. Repeat this step to delete ciphertext lines 3-4 and write plaintext lines 6-7 into the register, and so on. Each time, delete 2 lines of ciphertext and then write 2 lines of plaintext into the register, until all the plaintext of the encrypted part has been written into the register.
[0053] S6. Write a TCL script to automate steps S3-S5, including modifying ciphertext, generating bitstream, burning bitstream, and reading register data.
[0054] After obtaining the encrypted bitstream from the FPGA, following steps S3-S5, a TCL script is written to modify the ciphertext of the bitstream, then a bitstream file is generated, burned to the FPGA, and the WBSTAR register value is read. When generating the bitstream file, the time required to generate a complete bitstream is long, resulting in low reading efficiency. Therefore, only a small portion of the ciphertext is used each time a bitstream is generated to improve the speed of bitstream file generation. Simultaneously, since the length of the encrypted portion of the generated bitstream has been tampered with, the ciphertext length command needs to be modified to reduce the number of words to be decrypted, in order to avoid decryption logic errors.
Claims
1. A method of decrypting an encrypted bitstream for an FPGA, the method comprising: The method comprises the following steps: S1, obtaining the encrypted bit stream of the FPGA; The bit stream is obtained from the Flash or EEPROM external non-volatile memory or by monitoring the configuration bus of the FPGA during power-on; S2, determining the position of the write WBSTAR register command according to the position of the start decryption and ciphertext length command in the encrypted bit stream and the length of the HMAC Header region; The write WBSTAR register command is the second configuration command after the HMAC Header region; S3, modifying the to-be-modified ciphertext C, and writing the plaintext in the third row after the row where the write WBSTAR command is located, i.e., P10-P13, into the register; The error propagation characteristic of the AES-CBC decryption mode is utilized to indirectly modify the write WBSTAR register command by modifying the ciphertext in the corresponding position of the row above the write WBSTAR register command; S4, modifying the to-be-modified ciphertext C, and writing the plaintext in the second row after the row where the write WBSTAR command is located, i.e., P6-P9, into the register; S5, writing all subsequent plaintexts into the register; All plaintexts are written into the register by repeatedly deleting the ciphertext and referring to the modification method in steps S3-S4; S6, writing a TCL script to realize the automation operation of steps S3-S5, modifying the ciphertext, generating the bit stream, burning the bit stream and reading the register data.
2. The method of claim 1, wherein: The method for modifying the register command is based on the error propagation characteristic of the AES-CBC decryption mode, and the plaintext of the next row is affected by modifying the ciphertext.
3. The method of claim 1, wherein: The plaintext of the subsequent word is read by repeatedly deleting the ciphertext.
4. The method of claim 1, wherein: When the TCL script is used to generate the bit stream file, the length thereof is limited to improve the generation speed, and the ciphertext length command is modified to reduce the number of decrypted words.
Citation Information
Patent Citations
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CN101431407A
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CN106357608A