Driving circuit and display module

Abstract

The invention provides a driving circuit and a display module, and belongs to the technical field of display. The driving circuit is used for driving a display panel; according to the display panel, a row enabling module is arranged between a shift register and a scanning line of a gate drive circuit; the row enabling module enables the shifting register and the scanning line to be electrically connected or electrically disconnected under the control of a row enabling signal on the column enabling line; the driving circuit is configured to receive external data and generate a row enable signal which can be loaded to the row enable wire according to the external data. The driving circuit can control the display panel to realize local free refreshing.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a driving circuit and a display module. Background Art

[0002] With the development of display technology, frame rate switching has become a strong demand in the driving of consumer electronic products. When users watch videos or play games, set the display module to a high refresh rate state to obtain a smoother experience. When reading and other scenes, set it to a low refresh rate state to reduce power consumption.

[0003] However, in actual usage scenarios, there are often scenes such as half-screen video and half-screen text. If the full screen uses a high refresh rate at this time, the power consumption will be relatively high; if all use a low refresh rate, applications such as videos will appear stuck.

[0004] Therefore, it is necessary to develop display technology that can achieve local refresh.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a driving circuit and a display module to achieve partial refresh of the display module.

[0007] According to one aspect of the present disclosure, a driving circuit is provided for driving a display panel; wherein the display panel is provided with a row enable module between a shift register and a scan line of a gate driving circuit; the row enable module enables electrical conduction or electrical disconnection between the shift register and the scan line under the control of a row enable signal on the row enable line;

[0008] The driving circuit is configured to receive external data and generate an enable signal that can be loaded onto the enable trace according to the external data.

[0009] According to an embodiment of the present disclosure, the driving circuit includes:

[0010] A memory, configured to store data information of the area to be refreshed according to the external data;

[0011] A logic module, configured to determine a waveform parameter of the row enable signal according to an address of the data information in the memory;

[0012] The signal generating module is configured to generate the row enable signal according to the waveform parameters of the row enable signal.

[0013] According to an embodiment of the present disclosure, the logic module is configured as follows:

[0014] Determining the starting position of the conduction level of the row enable signal according to the address of the starting data of the data information of the area to be refreshed in the memory;

[0015] The end position of the conduction level of the row enable signal is determined according to the address of the end data of the data information of the area to be refreshed in the memory.

[0016] According to an embodiment of the present disclosure, the external data includes a row enable signal update instruction; the driving circuit includes:

[0017] a parameter determination module configured to store reference row enable signal waveform parameters, and configured to generate target row enable signal waveform parameters according to the row enable signal update instruction and the reference row enable signal waveform parameters;

[0018] The signal generating module is configured to generate the row enable signal according to the target row enable signal waveform parameter.

[0019] According to an embodiment of the present disclosure, the waveform parameters of the enable signal include the number of conduction level bands of the enable signal, the starting position of each conduction level band of the enable signal, and the ending position of each conduction level band of the enable signal.

[0020] According to an embodiment of the present disclosure, the driving circuit includes a mode selection module, a memory, a logic module, a signal generation module and a parameter determination module;

[0021] The mode selection module is configured to switch between the first working mode and the second working mode in response to the mode selection instruction;

[0022] In the first working mode, the memory is configured to store data information of the area to be refreshed according to the external data; the logic module is configured to determine the waveform parameters of the row enable signal according to the address of the data information in the memory; the signal generation module is configured to generate the row enable signal according to the waveform parameters of the row enable signal;

[0023] In the second working mode, the parameter determination module is configured to store reference row enable signal waveform parameters, and is configured to generate target row enable signal waveform parameters based on the row enable signal update instruction and the reference row enable signal waveform parameters; the signal generation module is configured to generate the row enable signal based on the target row enable signal waveform parameters.

[0024] According to an embodiment of the present disclosure, the external data includes data information of a whole frame; the driving circuit includes:

[0025] A memory, configured to store data information of the entire frame;

[0026] A content comparison module is configured to compare the data of a pixel row of a current frame with the data of the same pixel row of a previous frame;

[0027] The signal generating module is configured to generate a row enable signal according to the comparison result; wherein, when the data of the pixel row of the current frame image is the same as the data of the same pixel row of the previous frame image, the level of the row enable signal is made the cut-off level of the row enable signal; when the data of the pixel row of the current frame image is different from the data of the same pixel row of the previous frame image, the level of the row enable signal is made the on-level of the row enable signal.

[0028] According to an embodiment of the present disclosure, the memory is configured to overwrite the data of the pixel row of the previous frame with the data of the same pixel row of the current frame after the content comparison module reads out the data of the pixel row of the previous frame.

[0029] According to an embodiment of the present disclosure, the signal generating module is configured as follows:

[0030] Starting to output the conduction level of the enable signal at the starting position of the conduction level of the enable signal;

[0031] The cut-off level of the row enable signal starts to be outputted at the end position of the on-level of the row enable signal.

[0032] According to an embodiment of the present disclosure, the driving circuit is further configured as follows:

[0033] When the level of the row enable signal is the cut-off level of the row enable signal, the clock signal driving the shift register cannot be loaded into the clock signal.

[0034] According to an embodiment of the present disclosure, the driving circuit is configured as follows:

[0035] When the level of the row enable signal is the cut-off level of the row enable signal, the clock line for driving the shift register is loaded with a high-level power supply voltage, a low-level power supply voltage or presents a high-impedance state.

[0036] According to an embodiment of the present disclosure, the driving circuit is further configured as follows:

[0037] Determine whether the pixel row needs to be refreshed;

[0038] When the pixel row does not need to be refreshed, no data voltage is loaded on each data line.

[0039] According to an embodiment of the present disclosure, the input end of the data line is connected to a column enable module; the column enable module is configured to load the data voltage to the data line under the control of the conduction level of the column enable signal;

[0040] The driving circuit is configured to, when the level of the row enable signal is the cut-off level of the row enable signal, load the cut-off level of the column enable signal to each of the column enable modules so that the data voltage cannot be loaded to the data line.

[0041] According to an embodiment of the present disclosure, the display panel includes a data line and a latch signal routing line arranged corresponding to the data line;

[0042] The pixel driving circuit of the display panel includes a data module for writing a data voltage to a storage capacitor, the data module includes a data writing subcircuit and a data latching subcircuit connected in series; the input end of the data module is electrically connected to the data line of the display panel, the control end of the data writing subcircuit is electrically connected to the scanning line, and the control end of the data latching subcircuit is electrically connected to the latch signal routing line;

[0043] The driving circuit is configured to determine whether a sub-pixel needs to be refreshed; when the sub-pixel does not need to be refreshed, when driving the pixel row where the sub-pixel is located, the cut-off level of the latch signal is loaded to the latch signal line corresponding to the sub-pixel so as to electrically disconnect the storage capacitor of the pixel driving circuit of the sub-pixel from the data line.

[0044] According to an embodiment of the present disclosure, the input end of the data line is connected to a column enable module; the column enable module is configured to load the data voltage to the data line under the control of the conduction level of the column enable signal;

[0045] The driving circuit is also configured to, when the sub-pixel does not need to be refreshed, load a cutoff level of a column enable signal to a column enable module corresponding to the sub-pixel when driving a pixel row where the sub-pixel is located so that the data voltage is not loaded on a data line electrically connected to the sub-pixel.

[0046] According to another embodiment of the present disclosure, a display module is provided, comprising the above-mentioned driving circuit and a display panel driven by the driving circuit.

[0047] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0049] Figure 1 It is a schematic diagram of the structure of a display module in one embodiment of the present disclosure.

[0050] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0051] Figure 3 The figure is a schematic diagram of the structure of a driving circuit in one embodiment of the present disclosure.

[0052] Figure 4 The figure is a schematic diagram of the structure of a driving circuit in one embodiment of the present disclosure.

[0053] Figure 5 The figure is a schematic diagram of the structure of a driving circuit in one embodiment of the present disclosure.

[0054] Figure 6 The figure is a schematic diagram of a conduction band and a cutoff band of an enable signal according to an embodiment of the present disclosure.

[0055] Figure 7 The figure is a schematic diagram of the structure of a driving circuit in one embodiment of the present disclosure.

[0056] Figure 8 It is a schematic diagram of the timing coordination relationship between multiple signals of a display module in one embodiment of the present disclosure.

[0057] Fig. 9 The present invention is a schematic diagram of the timing coordination of an enable signal and a clock signal in one embodiment of the present invention.

[0058] Fig.10 The figure is a schematic diagram of the timing coordination between an enable signal and a data voltage on a data line in one embodiment of the present disclosure.

[0059] Fig.11 It is a schematic diagram of the structure of a display module in one embodiment of the present disclosure.

[0060] Fig.12 The figure is a schematic diagram of the structure of a pixel driving circuit in one embodiment of the present disclosure.

[0061] Fig.13 The figure is a schematic diagram of the structure of a pixel driving circuit in one embodiment of the present disclosure.

[0062] Fig.14 It is a schematic diagram of the timing coordination relationship between multiple signals of a display module in one embodiment of the present disclosure.

[0063] Fig.15 It is a schematic diagram of the timing coordination relationship between multiple signals of a display module in one embodiment of the present disclosure.

[0064] Description of reference numerals:

[0065] AA, display area; BB, peripheral area; CLK, clock signal; CLKL, clock routing; CTR, driving circuit; DE, latch signal; DEL, latch signal routing; DEU, data latch sub-circuit; DH, row direction; DL, data line; DU, data write sub-circuit; DV, column direction; GE, row enable signal; GEA, on-level of row enable signal GE; GEB, off-level of row enable signal GE; GED, signal generation module; GEL, row enable routing; GEM, parameter determination module; GEU, row enable module; GL, scan line; GOA, gate drive circuit; GS, selection signal; PDC, pixel drive circuit; PIX, sub-pixel; PNL, display panel; RAM, memory; SE, column enable signal; SED, column enable signal generation module; SEL, column enable routing; SEU, column enable module; SR, shift register; SRAM, memory; UU, display unit. DETAILED DESCRIPTION

[0066] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0067] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0068] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0069] The present disclosure provides a display module and a display device. Figure 1 The display module includes a display panel PNL and a driving circuit CTR for driving the display panel PNL.

[0070] See also Figure 2 The display panel PNL includes display units UU distributed in an array, and the display units UU include sub-pixels PIX and pixel driving circuits PDC driving the sub-pixels PIX. The display panel PNL is provided with a plurality of scan lines GL arranged along a row direction DH in the display area AA, and each scan line GL is arranged in one-to-one correspondence with each display unit row HUU; the scan line GL is connected to each pixel driving circuit PDC of the corresponding display unit row HUU.

[0071] The display panel PNL is provided with a plurality of data lines DL arranged along the column direction DV in the display area AA, and each data line DL is arranged in one-to-one correspondence with each display unit column; the data line DL is connected to each pixel driving circuit PDC of the corresponding display unit column. In this way, the pixel driving circuit PDC of each display unit UU is connected to a scan line GL and a data line DL. When the scanning line GL is loaded with a selection signal GS, the data voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written data voltage.

[0072] In an example of the present disclosure, the sub-pixel PIX is a current-driven light-emitting element such as OLED, QLED, Micro LED or MiNi LED.

[0073] In the embodiments of the present disclosure, see Figure 1, the peripheral area BB of the display panel PNL may be provided with a gate drive circuit GOA, and the gate drive circuit GOA may include a plurality of shift registers SR cascaded in sequence. Among them, the scan line GL is connected to at least part of the shift registers SR in a one-to-one correspondence, so that the gating signal GS generated by the shift register SR can be loaded onto the corresponding scan line GL. Moreover, in this embodiment, the display panel PNL is further provided with a plurality of row enable modules GEU corresponding to each scan line GL in the peripheral area BB, and the scan line GL is electrically connected to the corresponding shift register SR through the corresponding row enable module GEU. For example, the first end of the row enable module GEU is electrically connected to the output end of the shift register SR, the second end of the row enable module GEU is electrically connected to the scan line GL, and the control end of the row enable module GEU is used to load the row enable signal GE. The row enable module GEU can be turned on in response to the conduction level of the row enable signal GE, thereby electrically connecting the scan line GL to the corresponding shift register SR; at this time, if the gating signal GS is generated on the shift register SR, the gating signal GS can be loaded onto the corresponding scan line GL. The row enable module GEU can be cut off in response to the cut-off level of the row enable signal GE, thereby electrically disconnecting the scan line GL and the corresponding shift register SR; at this time, even if the select signal GS is generated on the shift register SR, the select signal GS cannot be loaded to the corresponding scan line GL; the pixel driving circuit PDC of each display unit UU connected to the scan line GL cannot receive the data voltage from the data line DL.

[0074] Therefore, in the embodiment of the present disclosure, by controlling the level of the row enable signal GE loaded on the row enable module GEU to be the on-level of the row enable signal GE or the off-level of the row enable signal GE, it is possible to control whether the display unit UU corresponding to the scan line GL connected to the row enable module GEU can be refreshed.

[0075] See also Figure 1 The display panel PNL is provided with an enabling line GEL for loading the enabling signal GE in the peripheral area BB, and the control end of the enabling module GEU can be electrically connected to the enabling line GEL. The driving circuit CTR can generate the enabling signal GE and load it to the enabling line GEL, thereby controlling each enabling module GEU.

[0076] In one embodiment of the present disclosure, the control end of each row enable module GEU is connected to the same row enable wire GEL. When the on-level of the row enable signal GE is loaded to the row enable wire GEL, each row enable module GEU is turned on; when the off-level of the row enable signal GE is loaded to the row enable wire GEL, each row enable module GEU is turned off. In this way, the timing of the row enable signal GE loaded on the row enable wire GEL can be controlled, for example, the starting position (relative time) and the ending position (relative time) of the on-level of the row enable signal GE can be controlled to cooperate with the shift register SR. When the screen displayed by the display unit UU connected to a certain scan line GL needs to be refreshed, the on-level of the row enable signal GE can be loaded on the row enable wire GEL within the time period when the shift register SR connected to the scan line GL outputs the selection signal GS. When the display unit UU connected to a certain scan line GL does not need to refresh the screen, the off-level of the row enable signal GE can be loaded on the row enable wire GEL within the time period when the shift register SR connected to the scan line GL outputs the selection signal GS. In this way, by controlling the timing of the row enable signal GE on the row enable line GEL, the area that can be refreshed on the display panel PNL can be controlled.

[0077] In one embodiment of the present disclosure, the driving circuit CTR may be provided with a signal generating module GED, and the signal generating module GED may generate a row enable signal GE and load it to the row enable trace GEL. Of course, the driving circuit CTR may also have other functions.

[0078] For example, in one example, the driving circuit CTR can control the timing of the gate driving circuit GOA by loading STV (column synchronization signal) and the clock signal CLK to the gate driving circuit GOA; specifically, it controls the moment when each shift register SR outputs the selection signal GS. It can be understood that the number of clock signals CLK can be one or more; the specific number and type of clock signals CLK can be set according to the needs of the gate driving circuit GOA.

[0079] For another example, in one example, the driving circuit CTR may apply the data voltage Vdata to the data lines DL of each display panel PNL.

[0080] In the embodiment of the present disclosure, the driving circuit CTR is configured to receive external data, and generate an enable signal GE according to the external data and load it to the enable routing GEL. For example, the driving circuit CTR can determine the start position and end position of the conduction level of the enable signal GE according to the external data, and then control the waveform of the enable signal GE. In this embodiment, the position information of the conduction level of the enable signal GE (such as the start position and the end position) is the position on the time axis, that is, a moment or a relative moment. For example, see Figure 6 , the starting position of the conduction level of the row enable signal GE may refer to the time when the start time of the conduction level of the row enable signal GE is relative to V-SyNc (column synchronization signal). The end position of the conduction level of the row enable signal GE may refer to the time when the end time of the conduction level of the row enable signal GE is relative to V-SyNc. It can be understood that there may be one or more conduction bands in a frame, or there may be no conduction band.

[0081] In the first exemplary embodiment of the present disclosure, see Figure 3 The driving circuit CTR has a memory RAM, a logic module and a signal generating module GED.

[0082] A memory RAM, configured to store data information of the area to be refreshed according to the external data;

[0083] A logic module, configured to determine a waveform parameter of the row enable signal GE according to an address of the data information in the memory RAM;

[0084] The signal generating module GED is configured to generate the row enable signal GE according to the waveform parameters of the row enable signal GE.

[0085] In an example of this implementation, the external data may include refresh address information and refresh data information. The refresh address information can be used to determine the address of the pixel that needs to be refreshed on the display panel PNL, and the refresh data information can be used to determine the data of the pixel that needs to be refreshed on the display panel PNL (for example, the grayscale of the sub-pixel). The host computer can determine which or which area of ​​the display panel PNL needs to be refreshed, and send the refresh data information required for the area that needs to be refreshed (i.e., the area to be refreshed) to the memory RAM of the driving circuit CTR. Sent together with the refresh data information, refresh address information is also included, such as the address information of the first data in the first refresh data information. For example, the host computer determines the area to be refreshed by comparing the current frame image with the previous frame image; then the address information of the first data of the area to be refreshed, and the data of the area to be refreshed are sent as a whole to the memory RAM as external data.

[0086] In one example, the host computer is a processor of an electronic device that uses the display module as an image output device, such as a mainboard of a mobile terminal, a host of a computer, etc.

[0087] In an example, the data information of the area to be refreshed may include data information of a row of pixels or a plurality of rows of pixels. In this example, the display panel PNL may be partially refreshed in units of pixel rows.

[0088] In other words, when the data of a certain pixel changes, the pixel row where the pixel is located is located in the area to be refreshed. From another perspective, the data of each pixel in the area to be refreshed does not necessarily change. In the area to be refreshed, the data of a certain pixel may or may not change.

[0089] In an example of this implementation, the memory RAM can store the data information of the area to be refreshed according to the refresh address information and the refresh data information. The data information of the area to be refreshed comes from the refresh data information, and the address of the data information of the area to be refreshed is determined according to the refresh address information. For example, the driving circuit CTR can determine the address of each data in the refresh data information in the memory RAM according to the refresh address information and the refresh data information of the external data, and write the data at the respective addresses.

[0090] In an example of this implementation, the logic module may access the memory RAM to obtain the address of the data information, and determine the waveform parameter of the row enable signal GE according to the address of the data information.

[0091] For example, the logic module can determine the starting position of the conduction level of the row enable signal GE according to the address of the starting data of the data information of the area to be refreshed in the memory RAM; and can determine the ending position of the conduction level of the row enable signal GE according to the address of the ending data of the data information of the area to be refreshed in the memory RAM. In this way, the waveform parameters of the row enable signal GE can include the starting position of the conduction level of the row enable signal GE and the ending position of the conduction level of the row enable signal GE. It can be understood that when the data information of multiple areas to be refreshed is stored in the memory RAM, the waveform parameters of the row enable signal GE can include the starting positions and ending positions of the conduction levels of multiple row enable signals GE, which makes the row enable signal GE have multiple conduction bands, and each conduction band corresponds to each area to be refreshed one by one.

[0092] In an example of this implementation, the signal generation module GED can generate the enable signal GE according to the waveform parameters of the enable signal GE, and load the enable signal GE to the enable routing GEL. For example, the signal generation module GED can start outputting the on-level of the enable signal GE at the start position of the on-level of the enable signal GE, and stop outputting the on-level of the enable signal GE and start outputting the off-level of the enable signal GE at the end position of the on-level of the enable signal GE.

[0093] In this way, it can be ensured that the waveform of the area to be refreshed corresponds to the waveform of the row enable signal GE. When the area to be refreshed needs to refresh the sub-pixel, the shift register SR and the row enable module GEU corresponding to the scan line GL in the area to be refreshed can be made to work synchronously, that is, the row enable module GEU is turned on when the shift register SR outputs the selection signal GS.

[0094] In this embodiment, the external data sent by the host computer to the driving circuit CTR may change with different display frames, and the row enable signal GE generated by the signal generation module GED may change accordingly with different external data. In this way, the frame-by-frame partial refresh of the display panel PNL may be achieved. Furthermore, the picture data sent by the host computer to the driving circuit CTR may only include pixel data of the area to be refreshed, and may not include pixel data of the non-refresh area.

[0095] In an example of this implementation, the memory RAM and the logic module may be located in the same display driver chip. Furthermore, the memory RAM, the logic module and the signal generation module GED may be located in the same display driver chip.

[0096] In a second exemplary embodiment of the present disclosure, see Figure 4 , the external data includes an enable signal GE update instruction; the drive circuit CTR includes:

[0097] a parameter determination module GEM configured to store a reference row enable signal GE waveform parameter, and to generate a target row enable signal GE waveform parameter according to the row enable signal GE update instruction and the reference row enable signal GE waveform parameter;

[0098] The signal generating module GED is configured to generate the row enable signal GE according to the waveform parameters of the target row enable signal GE.

[0099] In this embodiment, the parameter determination module GEM may pre-store the reference row enable signal GE waveform parameters, and may generate the target row enable signal GE waveform parameters according to the row enable signal GE update instruction. It is understandable that when the parameter determination module GEM does not receive the row enable signal GE update instruction, the parameter determination module GEM may use the reference row enable signal GE reference waveform parameters as the target row enable signal GE waveform parameters.

[0100] In one example, the waveform parameters of the enable signal GE may include the number of on-level bands of the enable signal GE, the starting position of each on-level band of the enable signal GE, and the ending position of each on-level band of the enable signal GE. Furthermore, the waveform parameters of the enable signal GE may also include the level of the on-level of the enable signal GE, that is, determining whether the on-level of the enable signal GE is a high level or a low level. It is understandable that the waveform parameters of the enable signal GE may also be presented in other equivalent forms, such as the number of on-level bands of the enable signal GE, the position where the enable signal GE performs level conversion, and the level conversion performed at the level conversion position. It is understandable that when the enable signal GE changes from the on-level of the enable signal GE to the cut-off level of the enable signal GE at a certain position, the position is the ending position of the on-level of the enable signal GE; when the enable signal GE changes from the cut-off level of the enable signal GE to the on-level of the enable signal GE at a certain position, the position is the starting position of the on-level of the enable signal GE.

[0101] In this embodiment, the external data includes a row enable signal GE update instruction. According to the row enable signal GE update instruction, the parameter determination module GEM can update the reference row enable signal GE waveform parameters called, and then generate the target row enable signal GE waveform parameters. In one example, the reference row enable signal GE waveform parameters are burned into the parameter determination module GEM; the row enable signal GE update instruction can be used to generate the target row enable signal GE waveform parameters, but will not change the reference row enable signal GE waveform parameters. In another example, the row enable signal GE update instruction can modify the reference row enable signal GE waveform parameters, that is, the reference row enable signal GE waveform parameters can be updated in response to the row enable signal GE update instruction. The parameter determination module GEM can mobilize the updated reference waveform parameters as the target row enable signal GE waveform parameters.

[0102] In one example, the external data may also include pixel data of an entire frame. The pixel data of the entire frame may be stored in the memory RAM of the driving circuit CTR so as to drive the display panel PNL. Compared with the first exemplary embodiment, the driving circuit CTR does not need to determine the waveform of the row enable signal GE through the data information in the memory RAM, but directly obtains the row enable signal GE update instruction from the host computer to determine the waveform of the row enable signal GE.

[0103] In one embodiment of the present disclosure, see Figure 5 The driving circuit CTR includes a mode selection module, a memory RAM, a logic module, a signal generation module GED and a parameter determination module GEM.

[0104] The mode selection module is configured to switch between the first working mode and the second working mode in response to the mode selection instruction;

[0105] In the first working mode, the memory RAM is configured to store data information of the area to be refreshed according to the external data; the logic module is configured to determine the waveform parameters of the row enable signal GE according to the address of the data information in the memory RAM; the signal generation module GED is configured to generate the row enable signal GE according to the waveform parameters of the row enable signal GE;

[0106] In the second working mode, the parameter determination module GEM is configured to store the reference row enable signal GE waveform parameters, and is configured to generate the target row enable signal GE waveform parameters according to the row enable signal GE update instruction and the reference row enable signal GE waveform parameters; the signal generation module GED is configured to generate the row enable signal GE according to the target row enable signal GE waveform parameters.

[0107] In other words, the working mode of the drive circuit CTR can be configured by the host computer, and then choose to work in the first working mode or in the second working mode. When working in the first working mode, the host computer sends the data information of the area to be refreshed to the drive circuit CTR, and the drive circuit CTR determines the waveform of the row enable signal GE based on the data information of the area to be refreshed. When working in the second working mode, the host computer determines the waveform of the row enable signal GE, and sends the relevant information of the waveform of the row enable signal GE to the parameter determination module GEM of the drive circuit CTR in the form of an row enable signal GE update instruction; the host computer also sends the pixel data of the entire frame to the drive circuit CTR for storage in the memory RAM. This can greatly improve the convenience of the application of the drive circuit CTR.

[0108] Optionally, in the first exemplary embodiment and the second exemplary embodiment, the display panel PNL may be pre-divided into a plurality of row partitions, each row partition including a plurality of pixel rows, for example, 10 to 100 pixel rows. Of course, when the host computer determines the area to be refreshed of the display panel PNL, it determines the row partition to be refreshed. In this way, local refresh can be performed in units of row partitions, rather than in units of each pixel row, which can greatly reduce the amount of external data and the complexity of the generation logic.

[0109] For example, when determining the area to be refreshed, the host computer determines whether there are pixels in each row partition that need to be refreshed. When at least one pixel in a row partition needs to be refreshed, the row partition is regarded as part of the area to be refreshed. Accordingly, when the drive circuit CTR generates the row enable signal GE, the level of the row enable signal GE is maintained at the conduction level of the row enable signal GE during the time period when each pixel row of the row partition is driven.

[0110] For another example, when the host computer determines the row enable signal GE update instruction, it determines whether there are pixels in each row partition that need to be refreshed. When at least one pixel in the row partition needs to be refreshed, the row enable signal GE update instruction needs to ensure that the level of the row enable signal GE corresponding to each pixel row of the row partition (the row enable signal GE when driving the pixel row) is maintained at the conduction level of the row enable signal GE.

[0111] Of course, in some specific cases or requirements, at least one row partition may include only one pixel row.

[0112] Under some other implementation strategies of the first exemplary embodiment and the second exemplary embodiment, the row enable modules GEU of each row partition can be connected to their own row enable lines GEL respectively. In other words, the display panel PNL can be provided with row enable lines GEL corresponding to each row partition, and the row enable modules GEU connected to the scan lines GL of the row partition are connected to the row enable lines GEL corresponding to the row partition; the row enable modules GEU of different row partitions are connected to different row enable lines GEL. The signal generation module GED can load the row enable signal GE to the corresponding row enable line GEL; that is, when the shift register SR of the gate drive circuit GOA generates the selection signal GS corresponding to the row partition, the signal generation module GED can load the row enable signal GE to the row enable line GEL corresponding to the row partition.

[0113] For example, when driving a row partition, the row enable signal GE can be loaded onto the row enable routing line GEL corresponding to the row partition, so that the selection signal GS corresponding to the row partition can be loaded or not loaded onto the scan line GL of the row partition under the control of the row enable module GEU.

[0114] In a third exemplary embodiment of the present disclosure, the external data includes data information of the entire frame, rather than data information of only the area to be refreshed. The driving circuit CTR may include:

[0115] A memory SRAM is configured to store data information of the entire frame;

[0116] A content comparison module is configured to compare the data of a pixel row of a current frame with the data of the same pixel row of a previous frame;

[0117] The signal generating module GED is configured to generate a row enable signal GE according to the comparison result; wherein, when the data of the pixel row of the current frame image is the same as the data of the same pixel row of the previous frame image, the level of the row enable signal GE is the cut-off level of the row enable signal GE; when the data of the pixel row of the current frame image is different from the data of the same pixel row of the previous frame image, the level of the row enable signal GE is the on-level of the row enable signal GE.

[0118] In this exemplary embodiment, the driving circuit CTR compares the data information of the current frame picture with the data information of the previous frame picture pixel by pixel row, and automatically determines the level of the row enable signal GE corresponding to each pixel row row by pixel row, whether it should be the on level of the row enable signal GE or the off level of the row enable signal GE, so that the local refresh of the display panel PNL can be efficiently realized in units of pixel rows. The host computer does not need to process the data information of the picture so that the external data directly or indirectly contains the relevant information of the waveform of the row enable signal GE. This can greatly reduce the number of commands for the host computer to generate external data and simplify the generation logic of external data.

[0119] In an example of this implementation, the content comparison module can compare the data of the pixel rows of the current frame with the data of the pixel rows of the previous frame row by row. When comparing the pixel data of any pixel row, if it is determined that there is a difference between the two, it indicates that the pixel row needs to be refreshed. For example, the data of the Nth row of pixels of the current frame can be compared with the data of the Nth row of pixels of the previous frame; if the two are the same, the Nth row of pixels does not need to be refreshed; if the two are different, the Nth row of pixels needs to be refreshed.

[0120] When the comparison result shows that the data of a pixel row is different between the previous and next frames, the signal generating module GED makes the level of the enable signal GE when the pixel row is driven equal to the on-level of the enable signal GE according to the comparison result; for example, when the shift register SR of the pixel row starts to generate the selection signal GS, the level of the enable signal GE is equal to the on-level of the enable signal GE.

[0121] When the comparison result shows that there is no difference between the data of a pixel row in the previous and next frames, the signal generating module GED makes the level of the enable signal GE when the pixel row is driven the cut-off level of the enable signal GE according to the comparison result; for example, when the shift register SR of the pixel row starts to generate the selection signal GS, the level of the enable signal GE is made the cut-off level of the enable signal GE.

[0122] In one example, the memory SRAM is further configured to overwrite the data of a pixel row of the previous frame with the data of the same pixel row of the current frame after the content comparison module reads the data of a pixel row of the previous frame. In this way, the content comparison function of the drive circuit CTR and the module self-refresh function (updating the screen data) can share the same memory, avoiding the cost increase caused by setting up an additional memory. Figure 8 , which results in a time difference between reading the data of the previous frame from the memory SRAM and writing the data of the current frame into the memory SRAM; the driving circuit CTR first reads the data of the pixel row of the previous frame, and then writes the data of the pixel row of the current frame.

[0123] For example, the driving circuit CTR can receive the data of the current frame picture from the host computer pixel by pixel row, for example, receiving the data of each pixel of a pixel row each time. Before the driving circuit CTR receives the new data of a pixel row (the data of the current frame picture), the content comparison module pre-reads the data of the pixel row from the memory SRAM (not yet covered by the new data, so it is the data of the previous frame picture, also referred to as the old data here). After the driving circuit CTR receives the new data of the pixel row, on the one hand, the new data of the pixel row is used to update the data of the pixel row in the memory SRAM (covering the old data of the pixel row), so that the data stored in the memory SRAM is the data of the current frame picture of the pixel row. On the other hand, the driving circuit CTR transmits the new data of the pixel row to the content comparison module for comparison with the old data of the pixel row. The comparison result can be sent to the signal generation module GED. The signal generation module GED can determine whether the level of the row enable signal GE corresponding to the row is the conduction level of the row enable signal GE or the cut-off level of the row enable signal GE based on the comparison result.

[0124] In one example, see Figure 7 The driving circuit CTR is provided with a data receiving module, which can receive the data of the current frame picture pixel by pixel row, and send the data of the current frame picture to the memory SRAM and the content comparison module.

[0125] In one example, see Figure 7 and Figure 8 The data receiving module can also directly or indirectly load the data of the current frame picture to the display panel PNL line by line. For example, the data receiving module can also transmit the data of the current frame picture to the source driver, and the source driver generates a driving voltage according to the data of the sub-pixel and loads it to the corresponding data line DL. In this example, the drive circuit CTR receives the data of the current frame picture and the display panel PNL displays the current frame picture, which can be basically synchronized, and the data of the current frame picture stored in the memory SRAM can be slightly delayed.

[0126] In some embodiments of the present disclosure, see Fig. 9 , the driving circuit CTR is further configured as:

[0127] When the level of the row enable signal GE is the cut-off level of the row enable signal GE, the clock signal driving the shift register SR cannot be loaded into the clock signal CLK.

[0128] For example, the driving circuit CTR is configured to not load the clock signal for driving the shift register SR to the gate driving circuit GOA when the level of the row enable signal GE is the cut-off level of the row enable signal GE. At this time, even if the clock signal is loaded to the gate driving circuit GOA so that the gate driving circuit GOA generates the strobe signal GS, the strobe signal GS cannot be loaded to the scanning line GL through the row enable module GEU; therefore, stopping loading the clock signal to the gate driving circuit GOA causes the shift register SR to be unable to generate the shift register SR, which does not affect the normal driving of the display panel PNL, but can reduce the power consumption generated by the clock signal.

[0129] In this embodiment, the driving circuit CTR drives the shift register SR of the gate driving circuit GOA by loading a clock signal onto the clock line of the display panel PNL. In one example, when the level of the row enable signal GE is the cut-off level of the row enable signal GE, the clock line used to drive the shift register SR is loaded with a high-level power supply voltage, a low-level power supply voltage, or presents a high-impedance state.

[0130] In one example, the gate drive circuit GOA may include a plurality of gate drive circuit GOA partitions, each of which is used to control one or more row partitions. Two adjacent gate drive circuit GOA partitions may not be cascaded with each other, but each independently receives STV from the drive circuit CTR. The gate drive circuit GOA partition may respond to STV so that each shift register SR sequentially outputs a selection signal GS. The drive circuit CTR may determine whether each row partition corresponding to the gate drive circuit GOA partition needs to be refreshed. When each row partition corresponding to the gate drive circuit GOA partition does not need to be refreshed, the drive circuit CTR may not provide the conduction level of the row enable signal GE when driving each row partition corresponding to the gate drive circuit GOA partition, but may disconnect the scan line GL from the shift register SR. On the other hand, the clock signal required to drive the shift register SR may not be loaded to the gate drive circuit GOA partition, so that the gate drive circuit GOA partition does not start, thereby reducing the power consumption of each shift register SR of the gate drive circuit GOA partition when working and the power consumption generated by clock flipping. It can be understood that when at least one row partition corresponding to a gate drive circuit GOA partition needs to be refreshed, the gate drive circuit GOA partition needs to work normally, that is, the drive circuit CTR needs to provide STV and clock signals to the gate drive circuit GOA partition.

[0131] For example, a clock line CLKL is provided on the display panel PNL, and the clock line CLKL is used to load the clock signal CLK to the clock signal end of each shift register SR. When each row partition corresponding to a certain gate drive circuit GOA partition does not need to be refreshed, during the driving time period corresponding to the gate drive circuit GOA partition, the high-level power supply voltage VGH or the low-level power supply voltage VGL is loaded on the clock line CLKL, or the clock line CLKL is disconnected from the clock generator. At the same time, the drive circuit CTR loads the cut-off level of the row enable signal GE to the row enable line GEL, so that the shift register SR of the gate drive circuit GOA partition is electrically disconnected from the corresponding scan line GL, thereby preventing the signal at the output end of the shift register SR from being loaded to the scan line GL. Furthermore, when the row partition corresponding to a certain gate drive circuit GOA partition needs to be refreshed, during the driving time period corresponding to the gate drive circuit GOA partition, the drive circuit CTR needs to provide the required STV and clock signal CLK to the gate drive circuit GOA partition.

[0132] In some embodiments of the present disclosure, see Fig.10 , the driving circuit CTR is further configured as:

[0133] Determine whether the pixel row needs to be refreshed;

[0134] When the pixel row does not need to be refreshed, the data voltage Vdata is not loaded on each data line DL. For example, when the pixel row does not need to be refreshed, the data voltage Vdata is not loaded on each data line DL; for example, the driving circuit CTR may not generate or output the required data voltage Vdata, or the output data voltage Vdata cannot be loaded on the data line DL.

[0135] In this way, when the pixel row does not need to be refreshed, it is not necessary to load the data voltage Vdata onto the data line DL, thereby avoiding power consumption caused by voltage inversion on the data line DL.

[0136] In an example of this implementation, the input end of the data line DL is connected to a column enable module SEU; the column enable module SEU is configured to load the data voltage Vdata to the data line DL under the control of the conduction level of the column enable signal SE;

[0137] The driving circuit CTR is configured to, when the level of the row enable signal GE is the off level of the row enable signal GE, load the off level of the column enable signal SE to each of the column enable modules SEU so that the data voltage Vdata cannot be loaded to the data line DL.

[0138] In this example, a first end of the column enable module SEU is electrically connected to an input end of the data line DL, a second end of the column enable module SEU is used to load the data voltage Vdata, and a control end of the column enable module SEU is used to load the column enable signal SE. The column enable module SEU can be electrically turned on in response to the on level of the column enable signal SE, so that the data voltage Vdata generated by the driving circuit CTR can be loaded to the data line DL through the column enable module SEU. The column enable module SEU can be electrically disconnected in response to the off level of the column enable signal SE, so that the data voltage Vdata generated by the driving circuit CTR cannot be loaded to the data line DL.

[0139] In one example of this implementation, see Fig.11 , the column enable module SEU can be arranged in the peripheral area BB of the display panel PNL. Further, a column enable wire SEL for loading the column enable signal SE is arranged on the peripheral area BB of the display panel PNL, and the column enable wire SEL is electrically connected to the control end of each column enable module SEU. The driving circuit CTR can generate the column enable signal SE and load the column enable signal SE to the column enable wire SEL, thereby controlling whether the data voltage Vdata can be loaded to the data line DL. Of course, if necessary, the column enable module SEU and the column enable wire SEL can also be arranged on the driving circuit CTR.

[0140] In an example of this implementation, the driving circuit CTR may generate the column enable signal SE according to the row enable signal GE. For example, the driving circuit CTR may make the level of the column enable signal SE the on-level of the column enable signal SE when the level of the row enable signal GE is the on-level of the row enable signal GE; the driving circuit CTR may make the level of the column enable signal SE the off-level of the column enable signal SE when the level of the row enable signal GE is the off-level of the row enable signal GE.

[0141] For example, the driving circuit CTR may be provided with a column enable signal generating module, which may generate a column enable signal SE under the control of the row enable signal GE and load it onto the column enable wiring SEL. Optionally, the conduction level of the row enable signal GE and the conduction level of the column enable signal SE may be inverted levels, for example, one is a high level and the other is a low level. Of course, the conduction level of the row enable signal GE and the conduction level of the column enable signal SE may also be the same level, for example, both are high levels or both are low levels. For another example, the driving circuit CTR may load the row enable signal GE onto the column enable wiring SEL so that the column enable signal SE and the row enable signal GE are the same signal.

[0142] In this example, the row enable signal GE and the column enable signal SE can be synchronized, so that the strobe signal GS and the data voltage Vdata can be synchronously loaded to the display area AA of the display panel PNL. When the strobe signal GS is loaded to the scan line GL, the data voltage Vdata can be loaded to the data line DL; when the strobe signal GS cannot be loaded to the scan line GL, the data voltage Vdata cannot be loaded to the data line DL. In this way, power consumption can be reduced more efficiently.

[0143] In other embodiments of the present disclosure, see Figure 12 to Figure 15 , the display panel PNL includes a data line DL and a latch signal line DEL arranged corresponding to the data line DL;

[0144] The pixel driving circuit of the display panel PNL includes a data module for writing data voltage to a storage capacitor, and the data module includes a data writing sub-circuit DU and a data latching sub-circuit DEU connected in series; the input end of the data module is electrically connected to the data line DL of the display panel PNL, the control end of the data writing sub-circuit DU is electrically connected to the scanning line GL, and the control end of the data latching sub-circuit DEU is electrically connected to the latch signal line DEL.

[0145] When writing data voltage Vdata to pixel driving circuit PDC, it is necessary to load strobe signal GS to scan line GL so that data writing sub-circuit DU is turned on, and it is necessary to load latch signal DE with the on-level of latch signal DE to latch signal line DEL so that data latch sub-circuit DEU is turned on, and data voltage Vdata is loaded to data line DL. When strobe signal GS is loaded to scan line GL and latch signal line DEL is loaded with the off-level of latch signal DE, data line DL is disconnected from storage capacitor of pixel driving circuit PDC by data latch sub-circuit DEU, so that data voltage stored in pixel driving circuit PDC will not be refreshed; for example, when new data voltage Vdata is loaded on data line DL, the new data voltage Vdata will not be written into pixel driving circuit PDC; for another example, when data line DL is floating or high impedance (for example, electrically disconnected from driving circuit CTR), charge in pixel driving circuit PDC will not flow to data line DL.

[0146] The driving circuit CTR is configured to determine whether a sub-pixel needs to be refreshed. When the sub-pixel does not need to be refreshed, when driving the pixel row where the sub-pixel is located, the latch signal routing line DEL corresponding to the sub-pixel is loaded with the cut-off level of the latch signal DE so that the storage capacitor of the pixel driving circuit of the sub-pixel and the data line DL are electrically disconnected; in this way, no matter whether the scanning line GL electrically connected to the sub-pixel is loaded with the selection signal GS, the sub-pixel will not be refreshed. In this way, free refreshing of each sub-pixel can be achieved.

[0147] In this exemplary embodiment, when it is determined that a sub-pixel needs to be refreshed, when driving the pixel row where the sub-pixel is located, the conduction level of the latch signal DE is loaded to the latch signal routing DEL corresponding to the sub-pixel so that the storage capacitor of the pixel driving circuit of the sub-pixel is electrically connected to the data line DL.

[0148] In one example, see Fig.12 , a first end of the data latch subcircuit DEU is electrically connected to the data line DL, a second end of the data latch subcircuit DEU is electrically connected to a first end of the data write subcircuit DU, and a second end of the data write subcircuit DU is directly or indirectly electrically connected to a storage capacitor of the pixel drive circuit PDC. In this example, the first end of the data latch subcircuit DEU serves as an input end of the data module, and the second end of the data write subcircuit DU serves as an output end of the data module.

[0149] In another example, see Fig.13, the first end of the data writing sub-circuit DU is electrically connected to the data line DL, the first end of the data writing sub-circuit DU is electrically connected to the first end of the data latching sub-circuit DEU, and the second end of the data latching sub-circuit DEU is directly or indirectly electrically connected to the storage capacitor of the pixel driving circuit PDC. In this example, the first end of the data writing sub-circuit DU serves as the input end of the data module, and the second end of the data latching sub-circuit DEU serves as the output end of the data module.

[0150] In some examples of this implementation, see Fig.14 and Fig.15 , the input end of the data line DL is connected to a column enable module SEU; the column enable module SEU is configured to load a data voltage Vdata to the data line DL under the control of a conduction level of a column enable signal SE;

[0151] The driving circuit CTR is further configured to, when the sub-pixel does not need to be refreshed, load the off level of the column enable signal SE to the column enable module SEU corresponding to the sub-pixel when driving the pixel row where the sub-pixel is located so that the data line DL electrically connected to the sub-pixel is not loaded with the data voltage Vdata. When the sub-pixel needs to be refreshed, when the pixel row where the sub-pixel is located is driven, load the on level of the column enable signal SE to the column enable module SEU corresponding to the sub-pixel when driving the pixel row where the sub-pixel is located so that the data voltage Vdata can be loaded on the data line DL electrically connected to the sub-pixel.

[0152] For example, the first end of the column enable module SEU is used to receive the data voltage Vdata, the second end of the column enable module SEU is electrically connected to the data line DL, and the control end of the column enable module SEU is used to respond to the column enable signal SE to be turned on or off. When a sub-pixel does not need to be refreshed, when driving the pixel row where the sub-pixel is located, the column enable signal SE cut-off level can be loaded to the column enable module SEU corresponding to the sub-pixel so that the data voltage Vdata cannot be loaded to the data line DL, and the data latch sub-circuit DEU of the pixel driving circuit PDC of the sub-pixel is loaded with the cut-off level of the latch signal DE so that the storage capacitor of the pixel driving circuit PDC is disconnected from the data line DL. In this way, even if the scan line GL connected to the pixel row is loaded with the selection signal GS to refresh other sub-pixels, the pixel driving circuit PDC of the sub-pixel will not be refreshed. In this way, the power consumption of the data line DL can be reduced while realizing the function of free refresh in units of sub-pixels.

[0153] In one example, the driving circuit CTR can generate a column enable signal SE and a latch signal DE corresponding to the data line DL, and load the column enable signal SE to the control end of the column enable module SEU electrically connected to the data line DL, and load the latch signal DE to the control end of the data latch sub-circuit DEU of each pixel driving circuit PDC driven by the data line DL.

[0154] In another example, the column enable signal SE and the latch signal DE may be the same signal. Fig.15 The control end of the column enable module SEU is electrically connected to the latch signal trace DEL. In this way, the driving circuit CTR can generate a latch signal DE and load the latch signal DE as the column enable signal SE to the column enable module SEU.

[0155] In one example, the host computer can process the current frame and the previous frame to generate external data and load it to the driving circuit CTR, and the external data directly or indirectly includes waveform-related information of the latch signal DE corresponding to each data line DL and waveform-related information of the column enable signal SE. The driving circuit CTR can generate the latch signal DE according to the waveform-related information of the latch signal DE corresponding to the data line DL and load it to each pixel driving circuit PDC connected to the data line DL. The driving circuit CTR can generate the column enable signal SE according to the waveform-related information of the column enable signal SE corresponding to the data line DL and load it to each column enable module SEU connected to the data line DL.

[0156] For example, in one example, the external data includes data information of the area to be refreshed. The driving circuit CTR can determine the waveform parameters of the latch signal DE corresponding to each data line DL according to the data information of the area to be refreshed, for example, according to the address of each sub-pixel to be refreshed, such as determining the starting position of the conduction level of the latch signal DE and the ending position of the conduction level of the latch signal DE.

[0157] For another example, in one example, the external data includes a latch signal DE modification instruction corresponding to each data line DL. The driving circuit CTR pre-stores the reference latch signal DE waveform parameters corresponding to each data line DL. The driving circuit CTR can determine the target latch signal DE waveform parameters corresponding to the data line DL according to the reference latch signal DE waveform parameters corresponding to the data line DL and the latch signal DE modification instruction corresponding to the data line DL, and generate the latch signal DE according to the target latch signal DE waveform parameters.

[0158] In one embodiment of the present disclosure, the driving circuit CTR may include one or more display driver chips, which may be directly bound to the display panel PNL, or may be disposed on a circuit board (e.g., a flexible circuit board) bound to the display panel PNL, or may be disposed on a flip chip. Of course, the driving circuit CTR may also be presented in other forms, for example, some modules in the driving circuit CTR may also be other circuits other than the display driver chip, and in particular, may be other chips other than the display driver chip.

[0159] The present disclosure also provides an electronic device, which includes any one of the display modules described in the above display module embodiments. The electronic device may be a smart phone, a smart watch, a laptop computer, or other types of electronic devices, especially a mobile electronic device. Since the electronic device has any one of the display modules described in the above display module embodiments, it has the same beneficial effects, and the present disclosure will not be repeated here.

[0160] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A driving circuit for driving a display panel; wherein: The display panel is provided with a row enable module between the shift register of the gate drive circuit and the scan line; the row enable module enables electrical conduction or disconnection between the shift register and the scan line under the control of the row enable signal on the row enable line; The driving circuit is configured to receive external data and generate an enable signal that can be loaded onto the enable trace according to the external data.

2. The driving circuit according to claim 1, wherein: The driving circuit comprises: A memory, configured to store data information of the area to be refreshed according to the external data; A logic module, configured to determine a waveform parameter of the row enable signal according to an address of the data information in the memory; The signal generating module is configured to generate the row enable signal according to the waveform parameters of the row enable signal.

3. The driving circuit according to claim 2, wherein: The logic module is configured as follows: Determining the starting position of the conduction level of the row enable signal according to the address of the starting data of the data information of the area to be refreshed in the memory; The end position of the conduction level of the row enable signal is determined according to the address of the end data of the data information of the area to be refreshed in the memory.

4. The driving circuit according to claim 1, wherein: The external data includes an enable signal update instruction; the driving circuit includes: a parameter determination module configured to store reference row enable signal waveform parameters, and configured to generate target row enable signal waveform parameters according to the row enable signal update instruction and the reference row enable signal waveform parameters; The signal generating module is configured to generate the row enable signal according to the target row enable signal waveform parameter.

5. The driving circuit according to claim 4, wherein: The waveform parameters of the enabling signal include the number of conduction level bands of the enabling signal, the starting position of each conduction level band of the enabling signal, and the ending position of each conduction level band of the enabling signal.

6. The driving circuit according to claim 1, wherein: The driving circuit includes a mode selection module, a memory, a logic module, a signal generation module and a parameter determination module; The mode selection module is configured to switch between the first working mode and the second working mode in response to the mode selection instruction; In the first working mode, the memory is configured to store data information of the area to be refreshed according to the external data; The logic module is configured to determine the waveform parameters of the row enable signal according to the address of the data information in the memory; The signal generating module is configured to generate the row enable signal according to the waveform parameter of the row enable signal; In the second working mode, the parameter determination module is configured to store reference row enable signal waveform parameters, and is configured to generate target row enable signal waveform parameters according to the row enable signal update instruction and the reference row enable signal waveform parameters; The signal generating module is configured to generate the row enable signal according to the target row enable signal waveform parameter.

7. The driving circuit according to claim 1, wherein: The external data includes data information of a whole frame; the driving circuit includes: A memory, configured to store data information of the entire frame; A content comparison module is configured to compare the data of a pixel row of a current frame with the data of the same pixel row of a previous frame; The signal generating module is configured to generate a row enable signal according to the comparison result; wherein, when the data of the pixel row of the current frame image is the same as the data of the same pixel row of the previous frame image, the level of the row enable signal is made the cut-off level of the row enable signal; when the data of the pixel row of the current frame image is different from the data of the same pixel row of the previous frame image, the level of the row enable signal is made the on-level of the row enable signal.

8. The driving circuit according to claim 7, wherein: The memory is configured to overwrite the data of the pixel row of the previous frame with the data of the same pixel row of the current frame after the content comparison module reads out the data of the pixel row of the previous frame.

9. The driving circuit according to any one of claims 2 to 8, wherein: The signal generation module is configured as follows: Starting to output the conduction level of the enable signal at the starting position of the conduction level of the enable signal; The cut-off level of the row enable signal starts to be outputted at the end position of the on-level of the row enable signal.

10. The driving circuit according to any one of claims 1 to 8, wherein: The driving circuit is further configured as: When the level of the row enable signal is the cut-off level of the row enable signal, the clock signal driving the shift register cannot be loaded into the clock signal.

11. The driving circuit according to claim 10, wherein: The driving circuit is configured as follows: When the level of the row enable signal is the cut-off level of the row enable signal, the clock line for driving the shift register is loaded with a high-level power supply voltage, a low-level power supply voltage or presents a high-impedance state.

12. The driving circuit according to any one of claims 1 to 8, wherein: The driving circuit is further configured as: Determine whether the pixel row needs to be refreshed; When the pixel row does not need to be refreshed, no data voltage is loaded on each data line.

13. The driving circuit according to claim 12, wherein: The input end of the data line is connected to a column enable module; the column enable module is configured to load the data voltage to the data line under the control of the conduction level of the column enable signal; The driving circuit is configured to, when the level of the row enable signal is the cut-off level of the row enable signal, load the cut-off level of the column enable signal to each of the column enable modules so that the data voltage cannot be loaded to the data line.

14. The driving circuit according to any one of claims 1 to 8, wherein: The display panel includes a data line and a latch signal routing line arranged corresponding to the data line; The pixel driving circuit of the display panel includes a data module for writing a data voltage to a storage capacitor, the data module includes a data writing subcircuit and a data latching subcircuit connected in series; the input end of the data module is electrically connected to the data line of the display panel, the control end of the data writing subcircuit is electrically connected to the scanning line, and the control end of the data latching subcircuit is electrically connected to the latch signal routing line; The driving circuit is configured to determine whether a sub-pixel needs to be refreshed; when the sub-pixel does not need to be refreshed, when driving the pixel row where the sub-pixel is located, the cut-off level of the latch signal is loaded to the latch signal line corresponding to the sub-pixel so as to electrically disconnect the storage capacitor of the pixel driving circuit of the sub-pixel from the data line.

15. The driving circuit according to claim 14, wherein: The input end of the data line is connected to a column enable module; the column enable module is configured to load a data voltage to the data line under the control of a conduction level of a column enable signal; The driving circuit is also configured to, when the sub-pixel does not need to be refreshed, load a cutoff level of a column enable signal to a column enable module corresponding to the sub-pixel when driving a pixel row where the sub-pixel is located so that the data voltage is not loaded on a data line electrically connected to the sub-pixel.

16. A display module, comprising the driving circuit according to any one of claims 1 to 15, and a display panel driven by the driving circuit.

Images