Chip-on-glass driver chip and display device including same

Abstract

The present disclosure relates to a chip-on-glass driver chip and a display device including the same. A chip-on-glass (COG) type driver chip includes a base substrate, at least one insulating layer and at least one wire layer alternately stacked on the base substrate, and a bump array disposed on an uppermost layer on the base substrate, the bump array includes: a plurality of input bumps passing through the at least one insulating layer and connected to the metal lines of the at least one line layer; a plurality of output bumps passing through the at least one insulating layer and connected to the metal lines of the at least one line layer; and a plurality of dummy bumps electrically disconnected from the at least one line layer, where the at least one insulating layer is between the plurality of dummy bumps and the at least one line layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0124045, filed on September 18, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a chip on glass (COG) type driver chip and a display device including the driver chip. Background Art

[0004] The display device includes a display panel where a plurality of pixels are disposed and a driver integrated circuit (IC) that supplies driving signals to the pixels.

[0005] The driver IC can be implemented as a chip on glass (COG) type driver chip, which is mounted on the substrate of the display panel through a COG process. The COG process is a process in which heat and pressure are applied to the driver chip for a certain period of time by using an anisotropic conductive film (ACF), and the driver chip is thus bonded to the display panel. The resin of the ACF melts due to heat and pressure, and the conductive balls in the resin are compressed between the driver chip and the substrate, whereby the bumps of the driver chip are electrically connected to the signal pads of the display panel. Compared to the chip on film (COF) process, this COG process can realize a driver chip with relatively good electrical characteristics and reduced mounting area and thickness. Summary of the invention

[0006] The COG type driver chip may have a warping problem, which occurs due to the difference in thermal expansion coefficients between different materials having different physical properties. When the degree of warping is large, the bonding quality of the COG process may deteriorate. In addition, micro cracks may occur in the driver chip due to stress applied from the outside for the COG bonding process.

[0007] In order to overcome the above-mentioned problems of the related art, the present disclosure may provide a chip on glass (COG) type driver chip having a reduced degree of warpage and a display device including the driver chip.

[0008] In addition, the present embodiment can provide a chip-on-glass (COG) type driver chip with reduced warpage and a display device including the driver chip. In addition, the preferred embodiment of the present disclosure can provide a COG type driver chip with reduced warpage and robustness to microcracks and a display device including the driver chip.

[0009] To achieve these objectives and other advantages, and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a chip on glass (COG) type driver chip includes: a base substrate, at least one insulating layer and at least one wire layer alternately stacked on the base substrate, and a bump array arranged on the topmost layer on the base substrate, wherein the bump array includes: a plurality of input bumps of metal wires passing through the at least one insulating layer and connected to the at least one wire layer; a plurality of output bumps of metal wires passing through the at least one insulating layer and connected to the at least one wire layer; and a plurality of dummy bumps electrically disconnected from the at least one wire layer, wherein the at least one insulating layer is between the plurality of dummy bumps and the at least one wire layer.

[0010] In another aspect of the present disclosure, a display device includes: a display panel, the display panel including a display area where pixels are set and a frame area outside the display area; and a COG-type driver chip, the COG-type driver chip is directly mounted on a substrate of the display panel set in the frame area. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0012] Figure 1 is a block diagram showing a display device according to the present embodiment;

[0013] Figure 2 and Figure 3 is a diagram showing a source driver integrated circuit (IC) implemented using a chip on glass (COG) type driver chip;

[0014] Figure 4 is a diagram showing a bump arrangement mounted on the surface of a driver chip according to the present embodiment;

[0015] Figure 5 is a diagram showing an internal stacking configuration of a driver chip according to the present embodiment;

[0016] Figure 6 is a diagram showing a connection structure between input bumps and metal lines in a driver chip according to the present embodiment;

[0017] Figure 7 is a diagram showing a connection structure between output bumps and metal wires in a driver chip according to the present embodiment;

[0018] Figure 8is a diagram showing a floating structure of a dummy bump corresponding to a metal line in one driver chip according to the present embodiment;

[0019] Fig. 9 is a diagram showing an example of a line layer included in one driver chip according to the present embodiment;

[0020] Fig.10 It is shown along Fig. 9 A diagram of a cross-sectional surface taken along line AA' of FIG.

[0021] Figures 11 to 13 is a diagram showing another example of a line layer included in one driver chip according to the present embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0023] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0024] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings used to describe various embodiments of the present disclosure are exemplary only, and the present disclosure is not limited thereto. Throughout the entire text, similar reference numerals refer to similar elements. Throughout this specification, the same elements are represented by the same reference numerals. As used herein, unless the term "only" is used, the terms "comprising", "having", "including", etc. imply that other parts can be added. As used herein, the singular forms "one", "an", and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0025] Even if not explicitly stated, elements in the various embodiments of the present disclosure should be construed as including a margin of error.

[0026] When describing a positional relationship, for example, when the positional relationship between two parts is described as “on,” “above,” “below,” and “beside,” one or more other parts may be set between the two parts, unless “exactly” or “directly” is used.

[0027] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0028] In the following description, when a detailed description of a related known function or configuration is determined to unnecessarily obscure the gist of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 is a block diagram showing a display device according to the present embodiment. Figure 2 and Figure 3 is a diagram showing a source driver integrated circuit (IC) implemented using a chip on glass (COG) type driver chip.

[0030] Reference Figures 1 to 3 The display device according to the present embodiment can be implemented as a flat panel display device, such as a liquid crystal display (LCD) device, an electroluminescent display device, an electrophoretic display device, an electrowetting display device, an organic light-emitting display device, or a quantum dot display device. In addition, the display device according to the present embodiment is not limited to a flat panel display device, and can be implemented as various types such as a curved display device, a foldable display device, a rollable display device, and a transparent display device.

[0031] In the following embodiments, the display device may be described as a flat panel LCD device, but the inventive concept is not limited thereto.

[0032] The display panel 100 may include two glass substrates 10 and 20 and a liquid crystal layer formed therebetween. A plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and pixel electrodes may be formed on the lower glass substrate 20 of the display panel 100.

[0033] A black matrix, a color filter, and a common electrode may be formed on the upper glass substrate 10 of the display panel 100. The common electrode may be formed on the upper glass substrate 10 of the display panel 100. The common electrode may be formed on the upper glass substrate 10 in a vertical electric field mode such as a twisted nematic (TN) mode or a vertical alignment (VA) mode, and may be formed on the upper glass substrate 10 together with the pixel electrode in a lateral electric field mode such as an in-plane switching (IPS) mode or a fringe field switching (FFS) mode.

[0034] Liquid crystal cells may be arranged in a matrix type based on a crossing structure between data lines DL and gate lines GL in the display panel 100. Each of the liquid crystal cells may include a thin film transistor (TFT), a pixel electrode connected to the TFT, and a storage capacitor.

[0035] In the display panel 100, the liquid crystal cells may configure a screen AA that reproduces an input image. The screen AA may include a pixel array that displays pixel data (hereinafter referred to as image data) DATA of the input image. The pixel array may include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, and a plurality of pixels. On the screen AA, the pixels may be arranged in various types, such as a matrix type, a stripe type, or a diamond type. Each of the pixels may include a red (R) liquid crystal cell 101, a green (G) liquid crystal cell 101, and a blue (B) liquid crystal cell 101, so as to realize color.

[0036] A polarizer may be attached on each of the upper glass substrate 10 and the lower glass substrate 20 of the display panel 100 , and an alignment layer for setting a pre-tilt angle of the liquid crystal layer may be formed on an inner surface contacting the liquid crystal layer.

[0037] The pixel array may include a plurality of pixel columns and a plurality of pixel rows L1 to Ln intersecting the pixel columns. Each of the pixel columns may include pixels arranged in the Y-axis direction. The pixel rows may include pixels arranged in the X-axis direction. One vertical period may be one frame period required to write image data DATA of one frame in all pixels of the screen. One horizontal period may be the time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period may be the time required to write image data DATA of one pixel row of a shared gate line GL in pixels of one pixel row. Figure 1 , “D1 to D3” shown in circles may be data lines, and “Gn-2 to Gn” may be gate lines.

[0038] The display panel driver may include a source driver 110 and a gate driver 120. The display panel driver may write image data DATA into pixels of the display panel 100 based on the control of the timing controller 130.

[0039] The source driver 110 may include a digital-to-analog converter (DAC). The DAC may receive image data DATA and a source timing control signal DDC from the timing controller 130. The DAC may convert the image data DATA into a gamma compensation voltage based on the source timing control signal DDC to generate a data voltage, and may supply the data voltage to the data line DL during one horizontal period. The data voltage may be supplied to the data line DL and may then be applied to the pixel electrode of the liquid crystal unit 101 through the TFT.

[0040] The source driver 110 may be disposed outside the screen AA in the display panel 100, and may be formed in a first frame area BZ (i.e., a Y-axis frame area) where no image is displayed. The source driver 110 may include a plurality of source driver chips SIC. Each of the plurality of source driver chips SIC may be implemented as a chip on glass (COG) type source driver chip SIC directly mounted on the lower glass substrate 20 of the display panel 100 by a COG process. Based on the COG process using an anisotropic conductive film (ACF), the first output bump of the source driver chip SIC may be bonded to the data input pad of the lower glass substrate 20 (here, it may be connected to the data line DL). The resin of the ACF 50 may be melted due to heat and pressure, and the conductive balls in the resin of the ACF 50 may be compressed between the source driver chip SIC and the lower glass substrate 20, whereby the first output bump of the source driver chip SIC may be electrically connected to the data input pad of the display panel 100. Such a COG type source driver chip SIC may have good electrical characteristics and may be small in mounting area and thickness, compared to a case of being implemented as a chip on film (COF) type.

[0041] The COG type source driver chip SIC may include a first output bump, a first output pad connected to the first output bump, a first input bump connected to the timing controller 130 through an internal interface circuit, and a first input pad electrically connecting the first input bump to the DAC.

[0042] The gate driver 120 may sequentially supply a gate signal synchronized with a data voltage to the gate line GL according to the control of the timing controller 130. The gate signal may simultaneously activate each pixel in a pixel row charged with the data voltage during at least one horizontal period. The gate driver 120 may include one or more gate shift registers. Based on the gate timing control signal GDC, the gate shift register may output a gate signal while shifting the gate signal in a row progressive / row non-progressive scheme. The gate signal may include one or more scan signals.

[0043] The gate driver 120 may be disposed outside the screen AA in the display panel 100, and may be formed in a second border area BZ (i.e., an X-axis border area) where no image is displayed. The gate driver 120 may include a plurality of gate driver chips. Each of the plurality of gate driver chips may be implemented as a COG-type gate driver chip mounted directly on the lower glass substrate 20 of the display panel 100 through a COG process. Based on the COG process using ACF, the second output bump of the gate driver chip may be bonded to the gate input pad of the lower glass substrate 20 (here, it may be connected to the gate line GL). The resin of the ACF 50 may melt due to heat and pressure, and the conductive balls in the resin of the ACF 50 may be compressed between the gate driver chip and the lower glass substrate 20, whereby the second output bump of the gate driver chip may be electrically connected to the gate input pad of the display panel 100.

[0044] The COG type gate driver chip may include a second output bump, a second output pad connected to the second output bump, a second input bump connected to the level shifter 140 through a line-on-glass (LOG) line, and a second input pad electrically connecting the second input bump to the gate shift register.

[0045] The timing controller 130 may receive the video data DATA and a timing signal synchronized with the video data DATA from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync may define a vertical period (i.e., a frame). The horizontal synchronization signal Hsync may define a horizontal period. The data enable signal DE may define the time for transmitting the video data DATA in a vertical period or a horizontal period. The vertical period and the horizontal period may be detected by counting the data enable signal DE, and thus the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted.

[0046] The timing controller 130 may generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system. The source timing control signal DDC may include a source sampling clock for sampling the image data DATA and a source output enable signal for setting the output timing of the data voltage.

[0047] The timing controller 130 may multiply the input frame frequency by i times (where i may be a natural number) to control the operation timing of each of the source driver 110 and the gate driver 120 of the display panel based on a frame frequency of the input frame frequency×i Hz. The input frame frequency may be about 60 Hz in the National Television Standards Committee (NTSC) scheme and may be about 50 Hz in the Phase Alternating Line (PAL) scheme.

[0048] The host system is one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, a car display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and the level shifter 140 may be integrated into one driver integrated circuit (IC).

[0049] The level shifter 140 may shift the logic voltage of the gate timing control signal GDC having a first amplitude input from the timing controller 130 into a gate high voltage VGH or a gate low voltage VGL having a second amplitude greater than the first amplitude to be supplied to the gate driver 120. Based on the level shifter, the low logic voltage of the gate timing control signal GDC may be shifted into the gate low voltage VGL, and the high logic voltage of the gate timing control signal GDC may be shifted into the gate high voltage VGH.

[0050] The timing controller 130 may transmit the image data DATA and the source timing control signal DDC to the source driver chip SIC through an internal interface circuit. The internal interface circuit may be implemented as an embedded clock point-to-point interface (EPI), but is not limited thereto.

[0051] Figure 4 : is a diagram showing a bump arrangement mounted on the surface of one driver chip according to the present embodiment. Figure 5 is a diagram showing an internal stacking configuration of one driver chip according to the present embodiment. Figure 6 is a diagram showing a connection structure between input bumps and metal lines in one driver chip according to the present embodiment. Figure 7 is a diagram showing a connection structure between output bumps and metal lines in one driver chip according to the present embodiment. Figure 8 is a diagram showing a floating structure of a dummy bump corresponding to a metal line in one driver chip according to the present embodiment.

[0052] Figures 4 to 8 One driver chip may be described as a source driver chip SIC, but the inventive concept is not limited to the source driver chip SIC and may be equally applied to gate driver chips.

[0053] Reference Figure 4and Figure 5 , the source driver chip SIC according to the present embodiment may include a base substrate WF, one or more insulating layers IL and one or more line layers CL alternately stacked on the base substrate WF, and a bump array BU-AR disposed in the uppermost layer of the base substrate WF.

[0054] The base substrate WF may be a glass substrate or a plastic substrate, but is not limited thereto.

[0055] The bump array BU-AR may include: metal lines ( Figure 6 A plurality of input bumps IB of the ML in the insulating layer IL and a metal line ( Figure 7 and a plurality of dummy bumps DB electrically disconnected from the line layer CL, wherein the insulating layer IL is between the dummy bumps DB and the line layer CL.

[0056] The COG type source driver chip SIC may have a warping problem, which occurs due to the difference in thermal expansion coefficients between different materials with different physical properties. When the lateral length and longitudinal length of the source driver chip SIC are different, the degree of warping in the lateral direction (hereinafter referred to as the X-axis direction) and the degree of warping in the longitudinal direction (hereinafter referred to as the Y-axis direction) may change. The degree of warping may be proportional to the length of the source driver chip SIC and may be inversely proportional to the thickness of the source driver chip SIC, and as the degree of warping increases, the COG bonding indentation may be affected, resulting in degradation of the bonding quality of the COG process.

[0057] Considering the basic purpose of COG processing, it may be difficult to apply the operation of increasing the thickness of the source driver chip SIC to reduce the degree of warpage to the present disclosure. In this embodiment, the bump array BU-AR may include dummy bumps DB to reduce the degree of warpage without increasing the thickness of the source driver chip SIC.

[0058] The dummy bump DB may be disposed at a central portion of the bump array BU-AR where the input bump IB and the output bump OB are not disposed to serve as a support for reducing the degree of warpage.

[0059] In detail, when the bump array BU-AR includes a first area AR1, a second area AR2 facing the first area AR1, and a third area AR3 disposed between the first area AR1 and the second area AR2, the input bump IB may be disposed in the first area AR1, and the output bump OB may be disposed in the second area AR2. In this case, the dummy bump DB may be disposed in the third area AR3 corresponding to the center portion of the bump array BU-AR. Figure 4 , it is shown that the bump array BU-AR is divided into the first to third areas AR1 to AR3 in the Y-axis direction, but the first to third areas AR1 to AR3 may be designed to be divided in the X-axis direction.

[0060] In order to further enhance the function of the support for reducing the degree of warpage, the dummy bumps DB can be arranged in a plurality of rows in the third area AR3 of the bump array BU-AR, and thus can be arranged in a predetermined mounting area at a high density. In performing the COG bonding process, the plurality of rows of dummy bumps DB can disperse the relatively high compressive stress in the third area AR3.

[0061] In addition, the input bumps IB may be arranged in a single row in the first area AR1 of the bump array BU-AR, but are not limited thereto. Figure 4 and Figure 5 As shown, the output bumps OB can be arranged in a plurality of rows having a zigzag shape in the second area AR2 of the bump array BU-AR, and thus can be arranged in a predetermined mounting area at a high density. Because the output bumps OB should be connected to the data input pads of the display panel, the number of the output bumps OB can be greater than the number of the input bumps IB.

[0062] In order to ensure ease of design, at least one of the input bump IB, the output bump OB, and the dummy bump DB may have a relatively large individual planar size. Figure 4 and Figure 5 As shown, each input bump IB may have a relatively larger individual planar size than each output bump OB or each dummy bump DB. Each output bump OB or each dummy bump DB may have the same individual planar size, but is not limited thereto. Each output bump OB and each dummy bump DB may have different individual planar sizes.

[0063] In addition, the first area AR1 to the third area AR3 configuring the bump array BU-AR may have different individual plane sizes. The second area AR2 provided with the output bump OB may be relatively the largest, the third area AR3 provided with the dummy bump DB for preventing warping may be the second largest, and the first area AR1 provided with the input bump IB may be relatively the smallest.

[0064] In order to further reduce the degree of warping, the metal lines ML of the line layer CL may be disposed under the bump array BU-AR and may be disposed to correspond to the entire area of ​​the bump array BU-AR. In other words, the metal lines ML of the line layer CL may be disposed under the first area AR1 and the second area AR2, and further, may be disposed under the third area AR3. The metal lines ML of the line layer CL may be electrically disconnected from each other.

[0065] Reference Figure 6 In the first region AR1, an under bump metallization (UBM) in contact with the lower surface of the input bump IB may pass through the insulating layer IL and may be connected to the metal line ML. The metal line ML electrically connected to the input bump IB may be an input pad of the source driver chip SIC.

[0066] Reference Figure 7 , in the second area AR2, the UBM in contact with the lower surface of the output bump OB may pass through the insulating layer IL and may be connected to the metal line ML. The metal line ML electrically connected to the output bump OB may be an output pad of the source driver chip SIC. The output pad may be connected to the data input pad of the display panel through the output bump OB. The data input pad may extend from the data line and may be included in the display panel.

[0067] Reference Figure 8 In the third area AR3, the UBM in contact with the lower surface of the dummy bump DB may be electrically disconnected from the metal line ML by the insulating layer IL. The dummy bump DB may not be connected to any metal line ML, may not be connected to any data input pad, and may be electrically floating. Because the dummy bump DB does not need to be connected to any metal line ML, the degree of freedom in the design of the dummy bump DB may be increased.

[0068] In addition, in the source driver chip SIC, the topmost line layer CL may be covered by the topmost insulating layer IL, but due to the space between the metal lines ML arranged in the topmost line layer CL, a valley may appear in the topmost insulating layer IL. Due to the valley, compressive stress and tensile stress may be applied to the topmost insulating layer IL when performing the COG bonding process. In addition, compared with the input bump IB and the output bump OB, a relatively high compressive stress may be applied to the dummy bump DB, and a relatively high tensile stress may be applied to the periphery of the dummy bump DB. Due to the influence of complex stress, microcracks may appear in the COG type source driver chip SIC.

[0069] Fig. 9 is a diagram showing an example of a line layer included in one driver chip according to the present embodiment. Fig.10 It is shown along Fig. 9 A diagram of a cross-sectional surface taken along the line A-A'. Fig.10 In the figure, the above-mentioned bump array is omitted.

[0070] Reference Fig. 9 and Fig.10 , the source driver chip SIC according to the present embodiment can be designed to reduce the degree of warping and be robust to microcracks. To this end, each of the line layers CL included in the source driver chip SIC according to the embodiment may also include an anti-vibration pattern SRP disposed in a region between adjacent metal lines ML. When stress is applied to the metal line ML, the anti-vibration pattern SRP may absorb the impact caused by the stress. Because the anti-vibration pattern SRP is used for impact absorption, the anti-vibration pattern SRP may be electrically insulated from the metal line ML, and may also be electrically insulated from the input bump IB, the output bump OB, and the dummy bump DB.

[0071] The shock resistant pattern SRP may include a conductive material or a non-conductive material and may be implemented in a structure robust to external stress. To this end, a plurality of insulating patterns having a hexagonal shape may be connected to each other, and thus, the shock resistant pattern SRP may be designed in a honeycomb structure. Fig. 9 and Fig.10 Schematically labeled and illustrated are multiple constituent parts P1, P2, P3, and P4 of a honeycomb structure for forming a shock-resistant pattern SRP. The honeycomb structure may be a structure in which stress is uniformly and stably distributed. According to a tensile test, graphene having a honeycomb shape may have a strength of about 200 times that of steel and may have good physical properties for shock absorption.

[0072] Figures 11 to 13 is a diagram showing another example of a line layer included in one driver chip according to the present embodiment.

[0073] Reference Figures 11 to 13 In order to realize a structure robust to external stress, a plurality of insulating patterns having polygonal shapes may be connected to each other, and therefore, the anti-seismic patterns SRP1, SRP2, and SRP3 according to another embodiment may be designed in a grid shape. Here, the polygonal shape may include a triangular shape, a quadrilateral shape, or a hemispherical shape. In addition, the polygonal shape may also include a combination of two or more of the above various shapes, or a combination of other polygonal shapes, as long as it can realize a structure robust to external stress.

[0074] This embodiment can achieve the following effects.

[0075] According to this embodiment, dummy bumps that are electrically insulated from each other can also be set in the bump array of the COG type driver chip, and in this case, because the dummy bumps are set in the central part of the bump array where the input bumps and output bumps are not set, the degree of warping of the driver chip caused by external stress can be effectively reduced during the COG bonding process.

[0076] According to this embodiment, the metal wires of the line layer included in the COG type driver chip can be arranged in the entire area of ​​the bump array, that is, under the dummy bumps and the input bumps / output bumps, and therefore, the degree of warping of the driver chip due to external stress can be effectively reduced during the COG bonding process.

[0077] According to the present embodiment, anti-vibration patterns electrically insulated from each other may also be provided in regions between metal wires in a wire layer included in the COG type driver chip, thereby realizing a COG type driver chip having reduced warpage and being robust against microcracks.

[0078] According to the present embodiment, the anti-seismic pattern may be designed such that a plurality of insulating patterns having a hexagonal shape are connected to each other to form a honeycomb shape, and thus, the degree of warpage may be considerably reduced and micro cracks may be reduced.

[0079] The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.

[0080] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A chip-on-glass COG type driver chip, comprising: Basic substrate; at least one insulating layer and at least one wire layer alternately stacked on the base substrate; as well as a bump array disposed on the uppermost layer on the base substrate, Wherein, the bump array comprises: a plurality of input bumps passing through the at least one insulating layer and connected to metal wires of the at least one wire layer; a plurality of output bumps passing through the at least one insulating layer and connected to the metal wires of the at least one wire layer; and A plurality of dummy bumps are electrically disconnected from the at least one wire layer, wherein the at least one insulating layer is between the plurality of dummy bumps and the at least one wire layer.

2. The COG type driver chip according to claim 1, wherein: The bump array includes a first area, a second area facing the first area, and a third area disposed between the first area and the second area. The plurality of input bumps are disposed in the first region, The plurality of output bumps are disposed in the second region, and The plurality of dummy bumps are disposed in the third region.

3. The COG type driver chip according to claim 2, wherein: The plurality of dummy bumps are arranged in a plurality of rows in the third region.

4. The COG type driver chip according to claim 1, wherein: The metal wires of the at least one wire layer are disposed under the bump array and are disposed to correspond to an entire area of ​​the bump array.

5. The COG type driver chip according to claim 1, wherein: The at least one line layer further includes an anti-shock pattern disposed between adjacent metal lines.

6. The COG type driver chip according to claim 5, wherein: The shock-resistant pattern is electrically insulated from the metal line.

7. The COG type driver chip according to claim 5, wherein: The anti-shock pattern is electrically insulated from the plurality of input bumps, the plurality of output bumps, and the plurality of dummy bumps.

8. The COG type driver chip according to claim 5, wherein: The anti-seismic pattern has a honeycomb shape in which a plurality of insulating patterns having a hexagonal shape are connected to each other.

9. The COG type driver chip according to claim 5, wherein: The anti-seismic pattern has a mesh shape in which a plurality of insulating patterns having polygonal shapes are connected to each other.

10. The COG type driver chip according to claim 1, wherein: Each of the plurality of input bumps has an individual planar dimension that is larger than each of the plurality of output bumps and / or each of the plurality of dummy bumps.

11. The COG type driver chip according to claim 2, wherein: Among the first region, the second region, and the third region, the second region has the largest size, the third region has the second largest size, and the first region has the smallest size.

12. A display device comprising: A display panel, the display panel comprising a display area where pixels are arranged and a frame area outside the display area; as well as According to one of claims 1 to 11, the COG type driver chip is directly mounted on a substrate of the display panel provided in the bezel area.

13. The display device according to claim 12, wherein: The COG type driver chip is included in at least one of: a source driver configured to drive a data line connected to the pixel, and a gate driver configured to drive a gate line connected to the pixel.

14. The display device according to claim 13, wherein: In the case where the COG type driver chip is included in the source driver, the data input pad extending from the data line of the display panel is electrically connected to the multiple output bumps included in the COG type driver chip, and is not electrically connected to the multiple dummy bumps included in the COG type driver chip.

15. The display device according to claim 13, wherein: In the case where the COG type driver chip is included in the gate driver, the gate input pad extending from the gate line of the display panel is electrically connected to the multiple output bumps included in the COG type driver chip, and is not electrically connected to the multiple dummy bumps included in the COG type driver chip.

16. The display device according to claim 14 or 15, wherein: The plurality of output bumps included in the COG type driver chip are electrically connected to corresponding input pads of the display panel through an anisotropic conductive film.

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