Nonvolatile memory device and memory system

Abstract

The invention discloses a nonvolatile memory device and a memory system. The nonvolatile memory device includes: a memory cell array for storing original setting data; a page buffer circuit connected to the memory cell array through a plurality of bit lines; and a safety buffer and a control circuit. The secure buffer includes an access control circuit and a plurality of registers with limited access, and the plurality of registers store original setting data dumped down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the safety buffer. The plurality of registers includes a first register and a second register. In response to the first register being accessed, the access control circuit accesses at least a portion of the second register concurrently with accessing the first register.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0126361 filed on September 21, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a nonvolatile memory device and a memory system. Background Art

[0003] Non-volatile memory devices (such as flash memory devices, resistive memory devices, etc.) can store data by programming each memory cell to have a threshold voltage distribution or a resistance distribution corresponding to a different logical state. The initialization of the non-volatile memory device may include a process of moving the setting data stored in the non-volatile memory device to another memory component. Three-dimensional non-volatile memory devices (such as vertical NAND flash memory devices) are developed to increase the integration of memory cells. As the integration and memory capacity of non-volatile memory devices increase, the time for initializing and programming non-volatile memory devices increases. Summary of the invention

[0004] Some embodiments provide a nonvolatile memory device capable of preventing setup data from being hooked.

[0005] Some embodiments provide a memory system including a nonvolatile memory device capable of preventing setup data from being hooked.

[0006] According to some embodiments, a nonvolatile memory device includes: a memory cell array for storing original setting data; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a security buffer and a control circuit. The security buffer includes an access control circuit and a plurality of registers with restricted access, and the plurality of registers store the original setting data dumped down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the security buffer. The plurality of registers include a first register and a second register. In response to the first register being accessed, the access control circuit accesses at least a portion of the second registers simultaneously with accessing the first register.

[0007] According to some embodiments, a memory system includes: a nonvolatile memory device; and a memory controller for controlling the nonvolatile memory device. The nonvolatile memory device includes: a memory cell array for storing original setting data; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a security buffer and a control circuit. The security buffer includes an access control circuit and a plurality of registers with restricted access, and the plurality of registers store the original setting data dumped down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the security buffer. The plurality of registers include a first register and a second register. In response to the first register being accessed, the access control circuit accesses at least a portion of the second registers simultaneously with accessing the first register.

[0008] According to some embodiments, a nonvolatile memory device includes: a memory cell array for storing original setting data; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a security buffer and a control circuit. The security buffer includes an access control circuit and a plurality of registers with restricted access, and the plurality of registers store the original setting data dumped down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the security buffer. The plurality of registers include a first register and a second register. In response to the first register being accessed, the access control circuit accesses at least a portion of the second registers simultaneously with accessing the first register. When the first register is accessed and the first setting data stored in the first register is changed, the access control circuit changes the corresponding setting data stored in each of the second registers by accessing the second register simultaneously with accessing the first register, and restores the changed corresponding setting data stored in each of the second registers to the corresponding original setting data. The control circuit performs a core operation based on the changed first setting data and the restored original setting data stored in the first register and the second register.

[0009] Therefore, according to a non-volatile memory device and a memory system based on some embodiments, when a first register is selected and accessed from among a plurality of registers with restricted access in a security buffer, a portion of the second registers or all of the registers are accessed simultaneously (e.g., simultaneously) with accessing the first register. When the setting data stored in the first register is changed, the corresponding setting data stored in a portion of the second registers or all of the registers accessed simultaneously with the first register is changed to the same setting data as the setting data stored in the first register, and thus the setting data stored in the plurality of registers is invalidated. Therefore, hooking the setting data can be prevented. Data "hooking" means changing or augmenting data or software components by intercepting function calls, messages, events, data, etc. passed between software and / or hardware components. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features of the present disclosure will become more apparent by describing in detail examples of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a flow chart illustrating a method of operating a non-volatile memory device according to some embodiments.

[0012] Figure 2 is a block diagram illustrating a memory system according to some embodiments.

[0013] Figure 3 It is shown Figure 1 A table of control signals in a memory system.

[0014] Figure 4 is a diagram showing that according to some embodiments Figure 2 A block diagram of an example of a memory controller in a memory system of FIG.

[0015] Figure 5 is a diagram showing that according to some embodiments Figure 2 A block diagram of an example of a non-volatile memory device in a memory system of FIG.

[0016] Figure 6 is a diagram showing that according to some embodiments Figure 5 A block diagram of an example of a security buffer in a non-volatile memory device.

[0017] Figure 7 is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0018] Fig. 8A is a diagram showing that according to some embodiments Figure 7 0048] Figure 2 is a diagram of an example operation of a security buffer.

[0019] Figure 8B Show and visit Fig. 8A The signal associated with the first register in .

[0020] Fig. 9 It is shown in Fig. 8A FIG. 1 is a diagram showing an example of restoring changed setting data of a second register in a security buffer of FIG.

[0021] Fig.10 Show and visit Fig. 9 The signal associated with the second register in.

[0022] Fig.11A is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0023] Fig. 11B Show and visit Fig.11A The signals associated with the registers in the first group.

[0024] Fig. 11C Show and visit Fig.11A The signals associated with the registers in the second group.

[0025] Fig. 12A is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0026] Fig. 12B Show and visit Fig. 12A The signal associated with the first register in .

[0027] Fig.13 is a diagram showing that according to some embodiments Figure 5 Schematic diagram of an example of a memory cell array in a nonvolatile memory device.

[0028] Fig.14 An example of raw setup data according to some implementations is shown.

[0029] Fig.15 is a diagram showing that according to some embodiments Figure 5 A block diagram of an example of a memory cell array in a nonvolatile memory device.

[0030] Fig.16 It is shown Fig.15 A circuit diagram of one of the memory blocks.

[0031] Fig.17 It is shown Fig.16 A diagram of an example of a structure of a cell string in a memory block.

[0032] Fig.18 According to some embodiments Figure 5 Schematic diagram of the connection of the memory cell array to the page buffer circuit.

[0033] Fig.19 is a diagram illustrating a page buffer according to some embodiments.

[0034] Fig. 20 is a circuit diagram illustrating an example of a cache unit according to some embodiments.

[0035] Fig.21 is a diagram showing that according to some embodiments Figure 5 A block diagram of a control circuit in a nonvolatile memory device.

[0036] Fig. 22 is a diagram showing that according to some embodiments Figure 5 Block diagram of a voltage generator in a nonvolatile memory device.

[0037] Fig.23 is a flow chart illustrating initialization operations of a memory system according to some embodiments.

[0038] Fig.24 is a diagram illustrating a method of operating a memory system according to some embodiments.

[0039] Fig.25 is a block diagram illustrating a storage device including a nonvolatile memory device according to some embodiments.

[0040] Fig.26 is a cross-sectional view of a nonvolatile memory device according to some embodiments.

[0041] Fig. 27 is a diagram illustrating a manufacturing process of a stacked semiconductor device according to some embodiments.

[0042] Fig.28 is a block diagram illustrating an electronic system including a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0043] Some embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may represent the same elements.

[0044] Figure 1 is a flow chart illustrating a method of operating a non-volatile memory device according to some embodiments.

[0045] exist Figure 1A method of operating a nonvolatile memory device is provided, the nonvolatile memory device including a memory cell array, a page buffer circuit, a security buffer including a plurality of registers with restricted access, and a control circuit.

[0046] Reference Figure 1 , the original setting data stored in the memory cell array is dumped down from the memory cell array to the plurality of registers through the page buffer circuit in an initialization sequence (operation S110). The plurality of registers may include a first register and a second register.

[0047] When the first register is accessed by the inside of the nonvolatile memory device or the outside of the nonvolatile memory device, at least a portion of the second registers (eg, one or more of the second registers) are selected simultaneously with the first register (operation S130).

[0048] When the first register is accessed and the first setting data stored in the first register is changed, setting data stored in at least a portion of the second registers selected simultaneously with the first register is changed (operation S150).

[0049] The changed setting data stored in at least a portion of the selected registers is restored to obtain corresponding original setting data (operation S170).

[0050] The control circuit performs a memory operation on the memory cell array based on the changed setting data stored in the first register and the original setting data stored in the second register (operation S190).

[0051] The setting data includes information for initialization of the nonvolatile memory device, which may be referred to as IDR (Information Data Read) data. The same setting data may be stored in a plurality of memory areas of the nonvolatile memory device. Even if the same setting data is stored in a plurality of memory areas, the read setting data may be distorted and different from the written setting data due to deviations in programming operations, deviations in reading operations, degradation of memory cells, etc. Therefore, when the read setting data from one memory area has an uncorrectable error, the read setting data may be loaded from another memory area.

[0052] The replication scheme of the setup data differs in different devices, device models, etc. In some embodiments, the setup data may include plane copy data for correcting bit line defects and string select line (SSL) copy data for correcting SSL defects.

[0053] The initialization sequence or IDR sequence may include "sensing" for reading out the setting data from the memory cell to the page buffer circuit, "dumping" for verifying the validity of the data stored in the page buffer circuit and storing the valid setting data in the buffer, and "following process" for setting the operating conditions of the non-volatile memory device based on the valid setting data in the buffer. For example, the following process may include: setting the level of the operating voltage, WOR scanning for eliminating the faulty column from the pass / fail operation, etc.

[0054] The boot time of a product is directly affected by the initialization time, and reducing the initialization time is important. In order to reduce the initialization time or IRD time, since the dump sequence occupies most of the initialization time, it may be useful to perform the dump sequence efficiently.

[0055] In addition, the processing described herein can prevent setting data from being hooked. According to some embodiments, when a first register is selected and accessed from a plurality of registers with restricted access in a security buffer, a portion of or all of the second registers are accessed at the same time (e.g., simultaneously) as the first register is accessed, and when the setting data stored in the first register is changed, the corresponding setting data stored in a portion of or all of the second registers accessed at the same time as the first register is changed to the same setting data as the setting data stored in the first register, and thus, the setting data stored in the plurality of registers is invalidated. Therefore, setting data can be prevented from being hooked. In addition, the changed setting data stored in a portion of or all of the second registers accessed at the same time as the first register is restored to the corresponding original setting data, and core operations can be performed based on the setting data stored in the plurality of registers.

[0056] Figure 2 is a block diagram illustrating a memory system according to some embodiments.

[0057] Reference Figure 2 , the memory system 50 may include a memory controller 200 and a nonvolatile memory device NVM 400 .

[0058] In some embodiments, each of the memory controller 200 and the non-volatile memory device 400 may be provided in the form of a chip, a package, or a module. In some embodiments, the memory controller 200 and the non-volatile memory device 400 may be packaged into one of various packages and may be provided as a storage device (such as a memory card).

[0059] The nonvolatile memory device 400 may perform an erase operation, a program operation, or a read operation under the control of the memory controller 200. The nonvolatile memory device 400 may receive a command CMD, an address ADDR, and data DTA from the memory controller 200 through an input / output line to perform these operations. The data DTA may include write data WD and read data RD. In addition, the nonvolatile memory device 400 may receive a control signal CTRL from the memory controller 200 through a control line. In addition, the nonvolatile memory device 400 may receive power PWR from the memory controller 200 through a power line.

[0060] The memory controller 200 may include a processor 210 and an error correction code (ECC) engine 300. The processor 210 may control the overall operation of the memory controller 200, for example, may apply an IDR command IDR_CMD to the nonvolatile memory device 400 in an initialization sequence. The IDR command IDR_CMD may also be referred to as a set data read command or an information data read command. The ECC engine 300 may perform an ECC encoding operation on data to be stored in the nonvolatile memory device 400, and may perform an ECC decoding operation on data read from the nonvolatile memory device 400.

[0061] The nonvolatile memory device 400 may include a memory cell array MCA 405 , a control circuit 450 , and a security buffer 500 .

[0062] The memory cell array 405 may store the original setting data OSD, and the security buffer 500 may store the original setting data OSD dumped down from the memory cell array 405 through the page buffer circuit in the initialization sequence. The control circuit 450 may perform a core operation on the memory cell array 405 based on the original setting data OSD stored in the security buffer 500.

[0063] Figure 3 It is shown Figure 1 A table of control signals in a memory system.

[0064] Reference Figure 2 and Figure 3 , the control signal CTRL applied by the memory controller 200 to the nonvolatile memory device 400 may include a command latch enable signal CLE, an address latch enable signal ALE, a chip enable signal nCE, a read enable signal nRE, and a write enable signal nWE.

[0065] The memory controller 200 may transmit a command latch enable signal CLE to the nonvolatile memory device 400. The memory controller 200 may transmit the command latch enable signal CLE to the nonvolatile memory device 400 via a separately allocated control pin. The command latch enable signal CLE may be a signal indicating that information transmitted via an input / output line is a command.

[0066] The memory controller 200 may transmit the address latch enable signal ALE to the nonvolatile memory device 400. The memory controller 200 may transmit the address latch enable signal ALE to the nonvolatile memory device 400 via a separately allocated control pin. The address latch enable signal ALE may be a signal indicating that information transferred via an input / output line is an address.

[0067] The memory controller 200 may transmit a chip enable signal nCE to the nonvolatile memory device 400. The memory controller 200 may transmit the chip enable signal nCE to the nonvolatile memory device 400 via a separately allocated control pin. When the nonvolatile memory device includes a plurality of memory chips, the chip enable signal nCE may indicate a memory chip selected from among the plurality of memory chips.

[0068] The memory controller 200 may transmit a read enable signal nRE to the nonvolatile memory device 400. The memory controller 200 may transmit the read enable signal nRE to the nonvolatile memory device 400 via a separately allocated control pin. The nonvolatile memory device 400 may transmit read data to the memory controller 200 based on the read enable signal nRE.

[0069] The memory controller 200 may transmit a write enable signal nWE to the nonvolatile memory device 400. The memory controller 200 may transmit the write enable signal nWE to the nonvolatile memory device 400 via a separately allocated control pin. When the write enable signal nWE is activated, the nonvolatile memory device 400 may store a data input signal provided from the memory controller 200 as a command CMD or an address ADDR.

[0070] Figure 4 is a diagram showing that according to some embodiments Figure 2 A block diagram of an example of a memory controller in a memory system of FIG.

[0071] Reference Figure 4 , the memory controller 200 may include a processor 210 , an ECC engine 300 , an on-chip memory 230 , an Advanced Encryption Standard (AES) engine 240 , a host interface 250 , a ROM 260 , a memory interface 270 , and a read manager 280 connected via a bus 205 .

[0072] The processor 210 controls the overall operation of the memory controller 200. The processor 210 may control the ECC engine 300, the on-chip memory 230, the AES engine 240, the host interface 250, the ROM 260, the memory interface 270, and the read manager 280. The processor 210 may include one or more cores (e.g., homogeneous multi-cores or heterogeneous multi-cores). The processor 210 may be or include, for example, at least one of a central processing unit (CPU), an image signal processor (ISP), a digital signal processor (DSP), a graphics processor (GPU), a visual processing unit (VPU), and a neural processing unit (NPU). The processor 210 may execute various application programs (e.g., a flash translation layer (FTL) 235 and firmware) loaded on the on-chip memory 230.

[0073] The on-chip memory 230 may store various application programs that can be executed by the processor 210. The on-chip memory 230 may operate as a cache memory adjacent to the processor 210. The on-chip memory 230 may store commands, addresses, and data to be processed by the processor 210, or may store processing results of the processor 210. The on-chip memory 230 may be, for example, a working memory or storage medium including latches, registers, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a tightly coupled memory (TCM), etc.

[0074] The processor 210 may execute the FTL 235 loaded onto the on-chip memory 230. The FTL 235 may be loaded onto the on-chip memory 230 as a firmware or program stored in the non-volatile memory device 400. The FTL 235 may manage the mapping between the logical address provided from the host and the physical address of the non-volatile memory device 400, and may include an address mapping table manager configured to perform management and update of the address mapping table. The FTL 235 may also perform garbage collection operations, wear leveling operations, etc., as well as the above-mentioned address mapping. The FTL 235 may be executed by the processor 210 to address one or more of the following aspects of the non-volatile memory device 400: rewrite-or in-place write-impossible, life of the memory cell, a limited number of program-erase (PE) cycles, and an erase speed slower than a write speed.

[0075] Memory cells of the nonvolatile memory device 400 may have physical characteristics in which threshold voltage distribution varies due to various reasons, such as programming elapsed time, temperature, program disturbance, read disturbance, etc. For example, data stored in the nonvolatile memory device 400 may become erroneous due to the above reasons.

[0076] The memory controller 200 may utilize various error correction techniques to correct such errors. For example, the memory controller 200 may include an ECC engine 300. The ECC engine 300 may correct errors occurring in data stored in the nonvolatile memory device 400. The ECC engine 300 may include an ECC encoder 310 and an ECC decoder 320. The ECC encoder 310 may perform an ECC encoding operation on data to be stored in the nonvolatile memory device 400. The ECC decoder 320 may perform an ECC decoding operation on data read from the nonvolatile memory device 400.

[0077] The ROM 260 may store various information required to operate the memory controller 200 in firmware.

[0078] The AES engine 240 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 200 by using a symmetric key algorithm. Although not shown in detail, the AES engine 240 may include an encryption module and a decryption module. For example, the encryption module and the decryption module may be implemented as separate modules. As another example, one module capable of performing both encryption and decryption operations may be implemented in the AES engine 240.

[0079] The read manager 280 may adjust and manage a plurality of read voltages associated with reading the data DTA stored in the nonvolatile memory device 400. For example, when the ECC engine 300 cannot correct an error in the data DTA read from the nonvolatile memory device 400, the read manager 280 may adjust a plurality of read voltages used in the nonvolatile memory device 400. The read manager 280 may include a read history table (e.g., a history table) 285, and may adjust a plurality of read voltages based on the read history table 285. The read manager 280 may read the data DTA stored in the nonvolatile memory device 400 at least twice, and may adjust a plurality of read voltages based on the read data DTA.

[0080] In some embodiments, the ECC engine 300 may have a given error correction capability. Data including error bits (or failed bits) in a number exceeding the error correction capability of the ECC engine 300 is referred to as "uncorrectable ECC (UECC) data". When the data DTA read from the nonvolatile memory device 400 is UECC data, the read manager 280 may adjust a plurality of read voltages and may perform a read operation again.

[0081] The read history table 285 may store the history of previous read voltages. For example, the read history table 285 may include information of read voltages that have been read through in previous read operations. The expression “read through” indicates that data read by a specific read voltage is normal data that does not include an error, or that an error included in the read data is correctable by the ECC engine 300.

[0082] In some embodiments, the read manager 280 may adjust the plurality of read voltages based on the read history table 285. That is, because the read voltage is adjusted based on the read voltage of the previous read pass, and the data DTA is read by using the adjusted read voltage (or read voltage level), the probability of an error of the read data DTA being corrected by the ECC engine 300 may be increased. That is, the probability of a read pass may be improved.

[0083] The read voltage of the previous read pass stored and managed in the read history table 285 is referred to as a “historical read voltage.” The read history table 285 may include information about the historical read voltage of each of the plurality of pages included in the nonvolatile memory device 400. For example, the read history table 285 may include information about the read voltage of the previous read pass of each word line.

[0084] The read manager 280 may update the read history table 285. For example, the read manager 280 may detect an optimal read voltage. The optimal read voltage indicates a read voltage that is read through when reading data. In some embodiments, the read manager 280 may read data from the nonvolatile memory device 400 at least twice or more, and may detect an optimal read voltage based on the read data. The operation of detecting the optimal read voltage is also referred to as a valley search operation.

[0085] The memory controller 200 may communicate with the host through the host interface 250. For example, the host interface 250 may include a universal serial bus (USB), a multimedia card (MMC), an embedded MMC, a peripheral component interconnect (PCI), PCI-Express, an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a mobile industry processor interface (MIPI), a non-volatile memory express (NVMe), a universal flash memory (UFS), etc. The memory controller 200 may communicate with the non-volatile memory device 400 through the memory interface 270.

[0086] Figure 5 is a diagram showing that according to some embodiments Figure 2 A block diagram of an example of a non-volatile memory device in a memory system of FIG.

[0087] Reference Figure 5 , the nonvolatile memory device 400 may include a memory cell array 405, an address decoder 430, a page buffer circuit 410, a data input / output (I / O) circuit 420, a control circuit 450, a security buffer 500, and a voltage generator 470.

[0088] The memory cell array 405 may be coupled to the address decoder 430 through a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL. In addition, the memory cell array 405 may be coupled to the page buffer circuit 410 through a plurality of bit lines BL. The memory cell array 405 may include a plurality of nonvolatile memory cells coupled to the plurality of word lines WL and the plurality of bit lines BL.

[0089] In some embodiments, the memory cell array 405 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 405 may include a (vertical) cell string oriented vertically such that at least one memory cell is located above another memory cell.

[0090] The control circuit 450 may receive a command (signal) CMD and an address (signal) ADDR from the memory controller 200, and control an erase cycle, a program cycle, and a read operation of the nonvolatile memory device 400 based on the command signal CMD and the address signal ADDR. A program cycle may include a program operation and a program verification operation. An erase cycle may include an erase operation and an erase verification operation.

[0091] For example, the control circuit 450 may generate a control signal CTL for controlling the voltage generator 470, and may generate a page buffer control signal PCTL for controlling the page buffer circuit 410 based on the command signal CMD. The control circuit 450 may generate a buffer control signal BCTL for controlling the security buffer 500, and may provide the buffer control signal BCTL to the security buffer 500. The control circuit 450 may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 450 may provide the row address R_ADDR to the address decoder 430 and provide the column address C_ADDR to the data input / output circuit 420.

[0092] The address decoder 430 may be coupled to the memory cell array 405 through the string selection line SSL, the plurality of word lines WL, and the ground selection line GSL. During a program operation or a read operation, the address decoder 430 may determine one of the plurality of word lines WL as a selected word line based on the row address R_ADDR, and determine the remaining word lines WL of the plurality of word lines WL except the selected word line as unselected word lines.

[0093] The voltage generator 470 may generate a word line voltage VWL associated with the operation of the nonvolatile memory device 400 based on the control signal CTL. The voltage generator 470 may receive power PWR from the memory controller 200. The word line voltage VWL may be applied to the plurality of word lines WL through the address decoder 430.

[0094] For example, during an erase operation, the voltage generator 470 may apply an erase voltage to a channel of a cell string of a memory block, and may apply a ground voltage to all word lines of the memory block. During an erase verification operation, the voltage generator 470 may apply an erase verification voltage to all word lines of the memory block, or sequentially apply the erase verification voltage to the word lines on a word line basis.

[0095] For example, during a program operation, the voltage generator 470 may apply a program voltage to a selected word line and may apply a program pass voltage to unselected word lines. In addition, during a program verification operation, the voltage generator 470 may apply a program verification voltage to a selected word line and may apply a verification pass voltage to unselected word lines. For example, during a read operation, the voltage generator 470 may apply a read voltage to a selected word line and may apply a read pass voltage to unselected word lines.

[0096] The page buffer circuit 410 may be coupled to the memory cell array 405 through a plurality of bit lines BL. The page buffer circuit 410 may include a plurality of page buffers PB. The page buffer circuit 410 may temporarily store data to be programmed into a selected page or data read out from a selected page.

[0097] The data input / output circuit 420 may be coupled to the page buffer circuit 410 through a plurality of data lines DL. During a program operation, the data input / output circuit 420 may receive program data DTA from the memory controller 200 and provide the program data DTA to the page buffer circuit 410 based on a column address C_ADDR received from the control circuit 450. During a read operation, the data input / output circuit 420 may provide read data DTA stored in the page buffer circuit 410 to the memory controller 200 based on the column address C_ADDR received from the control circuit 450.

[0098] In an initialization sequence, the memory cell array 405 may store the original setting data OSD, and the page buffer circuit 410 may sense the original setting data OSD and dump the original setting data OSD down to the security buffer 500 .

[0099] The control circuit 450 may perform a core operation on the memory cell array 405 based on the original setting data OSD stored in the security buffer 500. The security buffer 500 may include a plurality of registers with restricted access. The plurality of registers include a first register and a second register. When an internal module or an external module / device of the nonvolatile memory device 400 selects and accesses the first register, a portion of the second register or all of the registers are accessed at the same time (e.g., simultaneously) as the first register is accessed, and when the setting data stored in the first register is changed, the corresponding setting data stored in a portion of the second register or all of the registers accessed at the same time as the first register is changed to the same setting data as the setting data stored in the first register, and therefore, the setting data stored in the plurality of registers is invalidated. Therefore, it is possible to prevent the setting data from being hooked.

[0100] Figure 6 is a diagram showing that according to some embodiments Figure 5 A block diagram of an example of a security buffer in a non-volatile memory device.

[0101] Reference Figure 6 , the security buffer 500 may include a plurality of registers 511, 512, 513, and 514 with restricted access and an access control circuit 520. The plurality of registers 511, 512, 513, and 514 may be connected to an input / output I / O line I / O[0:7]. Each of the plurality of registers 511, 512, 513, and 514 may be implemented using an e-fuse, and the plurality of registers 511, 512, 513, and 514 may include a first register 511 and a second register 512, 513, and 514.

[0102] The access control circuit 520 may generate selection signals SEL1 , SEL2 , SEL3 , and SEL4 , each of which is used to select a corresponding one of the plurality of registers 511 , 512 , 513 , and 514 based on the register access mode signal UIB_IN and the register address RG_ADDR.

[0103] When the first selection signal SEL1 is activated and the first register 511 is accessed, by activating at least a portion of the second selection signals SEL2, SEL3 and SEL4 simultaneously with accessing the first selection signal SEL1, the access control circuit 520 can access at least a portion of the second registers 512, 513 and 514 simultaneously with accessing the first register 511.

[0104] Figure 7 is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0105] Reference Figure 7 , the security buffer 500a may include a plurality of registers 511, 512, 513, and 514 with restricted access and an access control circuit 520a. Each of the plurality of registers 511, 512, 513, and 514 may be implemented using an electric fuse, and the plurality of registers 511, 512, 513, and 514 may include a first register 511 and a second register 512, 513, and 514. Each of the original setting data OSD1, OSD2, OSD3, and OSD4 may be stored in a corresponding one of the first register 511 and the second register 512, 513, and 514.

[0106] The access control circuit 520a may include a first AND gate 531, second AND gates 532, 533, and 534, and OR gates 541a, 542a, and 543a.

[0107] The first AND gate 531 may generate a first selection signal SEL1 for selecting the first register 511 based on the register access mode signal UIB_IN and bits RG_ADDR_M1 and RG_ADDR_L1 specifying a first register address of the first register 511 .

[0108] The second AND gate 532 may generate an intermediate selection signal ISEL1 associated with selecting the second register 512 based on the register access mode signal UIB_IN and the bits RG_ADDR_M2 and RG_ADDR_L2 specifying the second register address of the second register 512. The second AND gate 533 may generate an intermediate selection signal ISEL2 associated with selecting the second register 513 based on the register access mode signal UIB_IN and the bits RG_ADDR_M3 and RG_ADDR_L3 specifying the second register address of the second register 513. The second AND gate 534 may generate an intermediate selection signal ISEL3 associated with selecting the second register 514 based on the register access mode signal UIB_IN and the bits RG_ADDR_M4 and RG_ADDR_L4 specifying the second register address of the second register 514.

[0109] The OR gates 541a, 542a, and 543a may generate second selection signals SEL2, SEL3, and SEL4 for selecting corresponding ones of the second registers 512, 513, and 514 by performing an OR operation on the first selection signal SEL1 and corresponding ones of the intermediate selection signals ISEL1, ISL2, and ISEL3.

[0110] Fig. 8A According to some embodiments Figure 7 Example operation of the safety buffer.

[0111] exist Fig. 8A In FIG. 5 , it is assumed that the first register 511 is accessed.

[0112] Reference Fig. 8A , when the first selection signal SEL1 is activated at a logic high level ("H"), each of the second selection signals SEL2, SEL3, and SEL4 is activated by the OR gates 541a, 542a, and 543a. Therefore, when the first register 511 is accessed and the first setting data stored in the first register 511 is changed to the target setting data TSD, the access control circuit 520a can change the corresponding setting data stored in each of the second registers 512, 513, and 514 to the target setting data TSD by accessing the second registers 512, 513, and 514 simultaneously with accessing the first register 511.

[0113] Figure 8B Show and visit Fig. 8A The signal associated with the first register in .

[0114] Reference Figure 8B , the first register 511 is accessed based on the consecutive commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and the bits RGAM1 and RGAL1 specifying the register address of the first register 511 having the value "00", and the first setting data stored in the first register 511 is changed to the target setting data TSD.

[0115] Fig. 9 Shown in Fig. 8A An example of restoring the changed setting data of the second register in the security buffer.

[0116] exist Fig. 9 In the Fig. 8A Duplicate description.

[0117] Reference Fig. 9 After the first setting data stored in the first register 511 is changed to the target setting data TSD, the access control circuit 520a deactivates the first selection signal SEL1 with a logic low level ("L"). After deactivating the first selection signal SEL1, the access control circuit 520a sequentially activates the second selection signals SEL2, SEL3, and SEL4 by sequentially changing the bits RGAM2 and RGAL2, RGAM3 and RGAL3, and RGAM4 and RGAL4 of the second register address to sequentially activate the intermediate selection signals ISEL1, ISL2, and ISEL3.

[0118] The access control circuit 520a sequentially accesses the second registers 512, 513 and 514 by sequentially activating second selection signals SEL2, SEL3 and SEL4, and may restore the target setting data TSD stored in each of the second registers 512, 513 and 514 to a corresponding one of the original setting data OSD2, OSD3 and OSD4.

[0119] Figure 5 The control circuit 450 in the memory cell array 405 may perform a core operation on the memory cell array 405 based on the target setting data TSD stored in the first register 511 and the original setting data OSD2 , OSD3 , and OSD4 stored in the second registers 512 , 513 , and 514 .

[0120] Fig.10 Show and visit Fig. 9 The signal associated with the second register in.

[0121] Reference Fig.10 , the second register 512 is accessed (e.g., selected) based on the continuous commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and the bits RGAM2 and RGAL2 of the second register address specifying the second register 512 having the value "01", and the target setting data TSD stored in the second register 512 is changed to the original setting data OSD2.

[0122] The second register 513 is accessed (e.g., selected) based on consecutive commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and bits RGAM3 and RGAL3 of the second register address specifying the second register 513 having a value of "10", and the target setting data TSD stored in the second register 513 is changed to the original setting data OSD3.

[0123] The second register 514 is accessed (e.g., selected) based on consecutive commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and bits RGAM4 and RGAL4 of the second register address specifying the second register 514 having a value of "11", and the target setting data TSD stored in the second register 514 is changed to the original setting data OSD4.

[0124] Fig.11A is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0125] Reference Fig.11A, the security buffer 500b may include a plurality of registers 511, 512, 513, and 514 with restricted access and an access control circuit 520b. Each of the plurality of registers 511, 512, 513, and 514 may be implemented using an electrical fuse, and the plurality of registers 511, 512, 513, and 514 may include a first register 511 and a second register 512, 513, and 514.

[0126] The access control circuit 520b may include a first AND gate 531, second AND gates 532, 533, and 534, third AND gates 536 and 537, and OR gates 541b, 542b, and 543b. The access control circuit 520b may group the second registers 512, 513, and 514 into at least two groups.

[0127] The first AND gate 531 may generate a first selection signal SEL1 for selecting the first register 511 based on the register access mode signal UIB_IN and bits RG_ADDR_M1 and RG_ADDR_L1 specifying a first register address of the first register 511 .

[0128] The second AND gate 532 may generate an intermediate selection signal ISEL1 associated with selecting the second register 512 based on the register access mode signal UIB_IN and the bits RG_ADDR_M2 and RG_ADDR_L2 specifying the second register address of the second register 512. The second AND gate 533 may generate an intermediate selection signal ISEL2 associated with selecting the second register 513 based on the register access mode signal UIB_IN and the bits RG_ADDR_M3 and RG_ADDR_L3 specifying the second register address of the second register 513. The second AND gate 534 may generate an intermediate selection signal ISEL3 associated with selecting the second register 514 based on the register access mode signal UIB_IN and the bits RG_ADDR_M4 and RG_ADDR_L4 specifying the second register address of the second register 514.

[0129] The third AND gates 536 and 537 may generate group selection signals GSEL1 and GSEL2 for selecting corresponding groups of at least two groups GR1 and GR2 based on the group selection information GSI1 and GSI2. The group selection information GSI1 and GSI2 ​​may be determined based on a combination of consecutive commands applied after OSD-down of the original setting data.

[0130] OR gates 541b, 542b and 543b can generate second selection signals SEL2, SEL3 and SEL4 for selecting a corresponding one of the second registers 512, 513 and 514 by performing an OR operation on the first selection signal SEL1, one of the group selection signals GSEL1 and GSEL2, and a corresponding one of the intermediate selection signals ISEL1, ISEL2 and ISEL3.

[0131] exist Fig.11A In the example of , the access control circuit 520 b groups the second registers 512 , 513 and 514 into two groups, the two groups including the first group GR1 selected by the group selection signal GSEL1 and the second group GR2 selected by the group selection signal GSEL2 . The first group GR1 may include the second registers 512 and 513 , and the second group GR2 may include the second register 514 .

[0132] When the first selection signal SEL1 is activated at a logic high level ("H") and the group selection signal GSEL1 is activated at a logic high level, each of the second selection signals SEL2 and SEL3 is activated by the OR gates 541b and 542b. Therefore, when the first register 511 is accessed and the first setting data stored in the first register 511 is changed to the target setting data TSD, the access control circuit 520b can change the corresponding setting data stored in each of the second registers 512 and 513 to the target setting data TSD by accessing the second registers 512 and 513 simultaneously with accessing the first register 511.

[0133] In addition, although not shown, when the first selection signal SEL1 is activated at a logic high level ("H") and the group selection signal GSEL2 is activated at a logic high level, the second selection signal SEL4 is activated by the OR gate 543b. Therefore, when the first register 511 is accessed and the first setting data stored in the first register 511 is changed to the target setting data TSD, the access control circuit 520b can change the setting data stored in the second register 514 to the target setting data TSD by accessing the second register 514 simultaneously with accessing the first register 511.

[0134] The access control circuit 520b may select one of the first group GR1 and the second group GR2 based on the number of consecutive commands applied after the original setting data OSD is dumped down. For example, in some embodiments, when the number of consecutive commands applied after the original setting data OSD is dumped down is an odd number, the access control circuit 520b may select the first group GR1, and when the number of consecutive commands applied after the original setting data OSD is dumped down is an even number, the access control circuit 520b may select the second group GR2. In some embodiments, when the number of consecutive commands applied after the original setting data OSD is dumped down is an even number, the access control circuit 520b may select the first group GR1, and when the number of consecutive commands applied after the original setting data OSD is dumped down is an odd number, the access control circuit 520b may select the second group GR2.

[0135] That is, the access control circuit 520b may group the second registers 512, 513, and 514 into at least two groups. When the first register 511 is accessed and the first setting data stored in the first register 511 is changed, the access control circuit 520b may change the setting data stored in at least one of the two groups by accessing the second register in at least one of the two groups simultaneously with accessing the first register 511.

[0136] As reference Fig.10 As described, by individually accessing registers in at least one of the two groups accessed simultaneously with the first register 511 , the changed setting data stored in at least one of the two groups can be restored to the corresponding original setting data.

[0137] Fig. 11B Show and visit Fig.11A The signals associated with the registers in the first group.

[0138] Reference Fig. 11B , the second register 512 is accessed (e.g., selected) based on the continuous commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and the bits RGAM2 and RGAL2 of the second register address specifying the second register 512 having the value "01", and the target setting data TSD stored in the second register 512 is changed to the original setting data OSD2.

[0139] The second register 513 is accessed (e.g., selected) based on consecutive commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and bits RGAM3 and RGAL3 of the second register address specifying the second register 513 having a value of "10", and the target setting data TSD stored in the second register 513 is changed to the original setting data OSD3.

[0140] Fig. 11C Show and visit Fig.11A The signals associated with the registers in the second group.

[0141] Reference Fig. 11C , the second register 514 is accessed (e.g., selected) based on the continuous commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN and the bits RGAM4 and RGAL4 of the second register address specifying the second register 514 having the value "11", and the target setting data TSD stored in the second register 514 is changed to the original setting data OSD4.

[0142] Fig. 12A is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of a security buffer.

[0143] Reference Fig. 12A , the security buffer 500c may include a plurality of registers 511, 512, 513, and 514 with restricted access and an access control circuit 520c. Each of the plurality of registers 511, 512, 513, and 514 may be implemented using an electrical fuse, and the plurality of registers 511, 512, 513, and 514 may include a first register 511 and a second register 512, 513, and 514.

[0144] When the first register 511 is accessed and the first setting data stored in the first register 511 is changed, the access control circuit 520c may cut off access to the second registers 512, 513 and 514 in the first mode, and may change the corresponding setting data stored in each of the second registers 512, 513 and 514 by accessing the second registers 512, 513 and 514 simultaneously with accessing the first register 511 in the second mode.

[0145] The access control circuit 520c may include a first AND gate 538, a second AND gate 539, third AND gates 532c, 533c, and 534c, a first OR gate 544c, and second OR gates 541c, 542c, and 543c.

[0146] The first AND gate 538 may generate a first mode selection signal MSEL1 activated in the first mode based on the set data dump signal IDR_DMP designating the first mode, the register access mode signal UIB_IN, and bits RG_ADDR_M1 and RG_ADDR_L1 designating the first register address of the first register 511 .

[0147] The second AND gate 539 may generate a second mode selection signal MSEL2 activated in the second mode based on the pin reduction mode signal PRM designating the second mode, the register access mode signal UIB_IN, and bits RG_ADDR_M1 and RG_ADDR_L1 designating the first register address of the first register 511 .

[0148] The third AND gate 532c may generate an intermediate selection signal ISEL1 associated with selecting the second register 512 based on the register access mode signal UIB_IN and the bits RG_ADDR_M2 and RG_ADDR_L2 specifying the second register address of the second register 512. The third AND gate 533c may generate an intermediate selection signal ISEL2 associated with selecting the second register 513 based on the register access mode signal UIB_IN and the bits RG_ADDR_M3 and RG_ADDR_L3 specifying the second register address of the second register 513. The third AND gate 534c may generate an intermediate selection signal ISEL3 associated with selecting the second register 514 based on the register access mode signal UIB_IN and the bits RG_ADDR_M4 and RG_ADDR_L4 specifying the second register address of the second register 514.

[0149] The first OR gate 544 c may generate a first selection signal SEL for selecting the first register 511 by performing an OR operation on the first mode selection signal MSEL1 and the second mode selection signal MSEL2 .

[0150] The second OR gates 541c, 542c, and 542c may generate second selection signals SEL2, SEL3, and SEL4 for selecting a corresponding one of the second registers 512, 513, and 514 by performing an OR operation on the second mode selection signal MSEL2 and a corresponding one of the intermediate selection signals ISEL1, ISEL2, and ISEL3.

[0151] Therefore, the access control circuit 520c can cut off access to the second registers 512, 513 and 514 in the first mode, in which the original setting data is dumped by activating the first mode selection signal MSEL1 and by deactivating the second mode selection signal MSEL2 when the first register 511 is accessed.

[0152] In addition, the access control circuit 520c may allow access to the second registers 512, 513, and 514 in the second mode in which a test is performed on the nonvolatile memory device 400 by deactivating the first mode selection signal MSEL1 and by activating the second mode selection signal MSEL2 when the first register 511 is accessed. Signals associated with the test in the second mode may be input to specific pins of the nonvolatile memory device 400 (e.g., pin reduction mode).

[0153] Figures 6 to 12A The register access mode signal UIB_IN, the group selection information GSI1 and GSI2, the set data dump signal IDR_DMP and the pin reduction mode signal PRM may be included in Figure 5 The buffer control signal BCTL in.

[0154] Fig. 12B Show and visit Fig. 12A The signal associated with the first register in .

[0155] Reference Fig. 12B , the first register 511 is accessed based on the pin reduction mode signal PRM, the consecutive commands CMD, ..., CMD corresponding to the register access mode signal UIB_IN, and the bits RGAM1 and RGAL1 of the register address designating the first register 511 having the value "00", and the first setting data stored in the first register 511 is changed to the target setting data TSD. The second selection signals SEL2, SEL3, and SEL4 for selecting the second registers 512, 513, and 514 may be activated simultaneously with the activation of the first selection signal SEL1.

[0156] Fig. 12A and 12B The pin reduction mode signal PRM in may be activated in a wafer parallel test mode on the nonvolatile memory device 400. For example, the pin reduction mode may correspond to a wafer parallel test mode on the nonvolatile memory device 400.

[0157] Fig.13 According to some embodiments Figure 5 An example of a memory cell array in a nonvolatile memory device.

[0158] Reference Fig.13 , the memory cell array 405 may include a meta area 406 and a user area 407 .

[0159] The meta area 406 may include original setting data OSD and replica setting data OSD_R1 and OSD_R2 generated by replicating the original setting data OSD. The user area 407 may store user data DTA.

[0160] The original setting data OSD may include first type setting data OSD_A and second type setting data OSD_B.

[0161] Fig.14 An example of raw setup data according to some implementations is shown.

[0162] Reference Fig.14 , the first type setting data OSD_A may include performance parameters related to the nonvolatile memory device 400 , and the second type setting data OSD_B may include reliability parameters related to the nonvolatile memory device 400 .

[0163] In some embodiments, the performance parameters may include a read time tR, a program time tPROG, an erase time tERS, etc. In some embodiments, the reliability parameters may include retention-related parameters, endurance-related parameters, the width and level of a step pulse of incremental step pulse programming (ISPP), a recovery voltage, a verification method, the number of verification target states, etc. It should be understood that the performance parameters and reliability parameters of the present disclosure are not limited thereto.

[0164] Fig.15 is a diagram showing that according to some embodiments Figure 5 A block diagram of an example of a memory cell array in a nonvolatile memory device.

[0165] Reference Fig.15 , the memory cell array 405 may include a plurality of memory blocks BLK1 to BLKz extending along a first direction HD1 (e.g., a first horizontal direction), a second direction HD2 (e.g., a second horizontal direction), and a third direction VD (e.g., a vertical direction). Here, z may be a natural number greater than two. In some embodiments, the memory blocks BLK1 to BLKz are composed of Figure 5 For example, the address decoder 430 may select a memory block BLK corresponding to the block address from among the memory blocks BLK1 to BLKz.

[0166] Fig.16 It is shown Fig.15 A circuit diagram of one of the memory blocks.

[0167] Fig.16The memory block BLKi may be formed in a three-dimensional structure (or a vertical structure) on the substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi may be formed along a third direction VD perpendicular to the substrate SUB.

[0168] Reference Fig.16 , the memory block BLKi may include (memory) cell strings NS11 to NS33 coupled between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the cell strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. In FIG. 12 , each of the cell strings NS11 to NS33 is shown as including eight memory cells MC1 to MC8. However, the present disclosure is not limited thereto. In some embodiments, each of the cell strings NS11 to NS33 may include any number of memory cells.

[0169] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0170] Word lines (eg, WL1 ) having the same height may be commonly connected, and ground selection lines GSL1 to GSL3 and string selection lines SSL1 to SSL3 may be separated.

[0171] Fig.17 Show Fig.16 An example of the structure of a cell string in a memory block.

[0172] Reference Fig.16 and Fig.17 , in the cell string NS11 , the pillars PL may be disposed on the substrate SUB such that the pillars PL extend in a direction perpendicular to the substrate SUB to make contact with the substrate SUB. Fig.17 Each of the ground selection line GSL1, word lines WL1 to WL8, and string selection line SSL1 shown in FIG. 4 may be formed of a conductive material (eg, a metal material) parallel to the substrate SUB. The pillars PL may contact the substrate SUB through the conductive material forming the string selection line SSL, word lines WL1 to WL8, and ground selection line GSL.

[0173] exist Fig.17A cross-sectional view taken along line V-V' is also shown in FIG. In some embodiments, a cross-sectional view of a first memory cell MC1 corresponding to a first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in an inner portion of the body BD.

[0174] The body BD may include P-type silicon and may be a region where a channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. The blocking insulating layer BI may be disposed between the first word line WL1 and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trapping layer CT, the blocking insulating layer BI, and the first word line WL1 may constitute or be included in a charge trapping transistor, which is formed in a direction perpendicular to the substrate SUB or in a direction perpendicular to the upper surface of the substrate SUB. The string selection transistor SST, the ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0175] Fig.18 According to some embodiments Figure 5 Schematic diagram of the connection of the memory cell array to the page buffer circuit.

[0176] Reference Fig.18 , the memory cell array 405 may include first to m-th cell strings NS1, NS2, NS3, ..., NSm, each of which may include a ground selection transistor GST connected to a ground selection line GSL, a plurality of memory cells MC respectively connected to first to n-th word lines WL1, ..., WLn, and a string selection transistor SST connected to a string selection line SSL, and the ground selection transistor GST, the plurality of memory cells MC and the string selection transistor SST may be connected in series to each other. In this case, n may be a positive integer greater than three.

[0177] The page buffer circuit 410 may include a first page buffer unit to an mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm. The first page buffer unit PB1 may be connected to the first cell string NS1 via the first bit line BL1, and the mth page buffer unit PBUm may be connected to the mth cell string NSm via the mth bit line BLm. For example, m may be 8, and the page buffer circuit 410 may have a structure in which eight levels of page buffer units or the first page buffer unit to the mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm are in a row. For example, the first page buffer unit to the mth page buffer unit PBU1, PBU2, PBU3, ..., PBUm may be in a row along the first bit line to the mth bit line BL1, BL2, BL3, ..., BLm.

[0178] The page buffer circuit 410 may also include first to m-th cache latches CL1, CL2, CL3, ..., CLm corresponding to the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm, respectively. For example, the page buffer circuit 410 may have a structure in which eight levels of cache latches or the first to m-th cache latches CL1, CL2, CL3, ..., CLm are in a row. For example, the first to m-th cache latches CL1, CL2, CL3, ..., CLm may be in a row along the extension direction of the first bit line to the m-th bit line BL1, BL2, BL3, ..., BLm.

[0179] The sensing node of each of the first to m-th page buffer units PBU1, PBU2, PBU3, ..., PBUm may be connected in common to the combined sensing node SOC. In addition, the first to m-th cache latches CL1, CL2, CL3, ..., CLm may be connected in common to the combined sensing node SOC. Therefore, the first to m-th page buffer units BU1, PBU2, PBU3, ..., PBUm may be connected to the first to m-th cache latches CL1, CL2, CL3, ..., CLm via the combined sensing node SOC. The first to m-th cache latches CL1, CL2, CL3, ..., CLm may output hard decision data HDRD.

[0180] The page buffer circuit 410 may further include a verification circuit 440 .

[0181] The verification circuit 440 may verify the original setting data OSD based on the original setting data OSD and the replica setting data OSD_R1 and OSD_R2 stored in the memory cell array 405 and sensed by the first to m-th page buffer units PBU1, PBU2, PBU3, . . . , PBUm, and may provide the verified original setting data OSD to the memory cell array 405. Figure 5 The safety buffer 500 shown in FIG.

[0182] The verification circuit 440 may perform a majority voting operation on the original setting data OSD and the replica setting data OSD_R1 and OSD_R2 , and may verify the original setting data OSD based on a result of the majority voting operation.

[0183] Fig.19 A page buffer according to some embodiments is shown in detail.

[0184] Reference Fig.19 , the page buffer PB can be used with Figure 5 The page buffer PB corresponds to the example of the page buffer PB in . The page buffer PB may include a page buffer unit PBU and a cache unit CU. Because the cache unit CU includes a cache latch (C-latch (C-LATCH)) CL, and the C-latch CL is connected to the data input / output line, the cache unit CU may be adjacent to the data input / output line. Therefore, the page buffer unit PBU and the cache unit CU may be separated from each other, and the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separated from each other.

[0185] The page buffer unit PBU may include a main unit MU. The main unit MU may include a main transistor in the page buffer PB. The page buffer unit PBU may also include a bit line selection transistor TR_hv connected to the bit line BL and driven by the bit line selection signal BLSLT. The bit line selection transistor TR_hv may include a high-voltage transistor, and thus the bit line selection transistor TR_hv may be in a well region different from the main unit MU (e.g., in the high-voltage unit HVU).

[0186] The main unit MU may include a sense latch (S-Latch) SL, a force latch (F-Latch) FL, an upper latch (M-Latch) ML, and a lower latch (L-Latch) LL. In some embodiments, the S-latch SL, the F-latch FL, the M-latch ML, or the L-latch LL may be referred to as a master latch. The main unit MU may also include a precharge circuit PC capable of controlling a precharge operation of a bit line BL or a sense node SO based on a bit line clamp control signal BLCLAMP, and may also include a transistor PM' driven by a bit line setup signal BLSETUP.

[0187] The S latch SL can store the data stored in the memory cell MC or the sensing result of the threshold voltage of the memory cell MC during the read verification operation or the program verification operation. In addition, during the programming operation, the S latch SL can be used to apply the programming bit line voltage or the program inhibition voltage to the bit line BL. The F latch FL can be used to improve the threshold voltage distribution during the programming operation. The F latch FL can store forced data. After the forced data is initially set to "1", when the threshold voltage of the memory cell MC enters a forced area with a voltage lower than the target area, the forced data can be converted to "0". By using the forced data during the program execution operation, the bit line voltage can be controlled, and a narrower programming threshold voltage distribution can be formed.

[0188] The M latch ML, L latch LL and C latch CL can be used to store data input externally during a programming operation, and can be referred to as a data latch. When 3 bits of data are programmed in one memory cell MC, the 3 bits of data can be stored in the M latch ML, L latch LL and C latch CL, respectively. Until the programming of the memory cell MC is completed, the M latch ML, L latch LL and C latch CL can maintain the stored data. In addition, the C latch CL can receive data read from the memory cell MC during a read operation from the S latch SL, and output the received data to the outside via the data input / output line.

[0189] In addition, the main unit MU may further include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the sensing node SO and the S latch SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the sensing node SO and the F latch FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected between the sensing node SO and the M latch ML, and may be driven by the higher bit monitoring signal MON_M. The fourth transistor NM4 may be connected between the sensing node SO and the L latch LL, and may be driven by the lower bit monitoring signal MON_L.

[0190] In addition, the main unit MU may further include a fifth transistor NM5 and a sixth transistor NM6 connected in series to each other between the bit line selection transistor TV_hv and the sensing node SO. The fifth transistor NM5 may be driven by the bit line shutoff signal BLSHF, and the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. In addition, the main unit MU may further include a precharge transistor PM. The precharge transistor PM may be connected to the sensing node SO driven by the load signal LOAD, and precharge the sensing node SO to a precharge level in a precharge cycle.

[0191] In some embodiments, the main unit MU may further include a pair of transfer transistors connected to the sensing node SO, or a first transfer transistor TR and a second transfer transistor TR'. In some embodiments, the first transfer transistor TR and the second transfer transistor TR' may also be referred to as a first sensing node connection transistor and a second sensing node connection transistor, respectively. The first transfer transistor TR and the second transfer transistor TR' may be driven in response to a transfer control signal SO_PASS. In some embodiments, the transfer control signal SO_PASS may be referred to as a sensing node connection control signal. The first transfer transistor TR may be connected between the first terminal SOC_U and the sensing node SO, and the second transfer transistor TR' may be between the sensing node SO and the second terminal SOC_D.

[0192] For example, when the page buffer unit PBU is connected to Fig.18 When the first page buffer unit PBU2 corresponds to the second page buffer unit PBU1, the first terminal SOC_U may be connected to one end of the pass transistor included in the first page buffer unit PBU1, and the second terminal SOC_D may be connected to one end of the pass transistor included in the third page buffer unit PBU3. In this way, the sense node SO may be electrically connected to the combined sense node SOC via the pass transistor included in each of the third to m-th page buffer units PBU3 to PBUM.

[0193] During a program operation, the page buffer PB may verify whether programming is completed in a memory cell MC selected from among the memory cells MC included in the NAND string connected to the bit line BL. The page buffer PB may store data sensed via the bit line BL during a program verification operation in the S latch SL. The M latch ML and the L latch LL storing target data may be set according to the sensed data stored in the S latch SL.

[0194] For example, when the sensed data indicates that programming is complete, the M latch ML and the L latch LL may be switched to a program inhibit setting for the selected memory cell MC in a subsequent programming cycle. The C latch CL may temporarily store input data provided from the outside. During a programming operation, target data to be stored in the C latch CL may be stored in the M latch ML and the L latch LL.

[0195] The description herein assumes that the signals for controlling the elements in the page buffer circuit 410 are included in Figure 5 The page buffer control signal PCTL in.

[0196] Fig. 20 is a circuit diagram illustrating an example of a cache unit according to some embodiments.

[0197] Reference Fig.19 and Fig. 20 , the cache unit CU may include a monitoring transistor NM7 and a C latch CL, and the C latch CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131 and 133 to 135. The monitoring transistor NM7 may be driven based on a cache monitoring signal MON_C, and may control a connection between a combined sensing node SOC and the C latch CL.

[0198] The first inverter INV1 may be connected between the first node ND1 and the second node ND2, the second inverter INV2 may be connected between the second node ND2 and the first node ND1, and thus, the first inverter INV1 and the second inverter INV2 may form a latch. The transistor 131 may include a gate connected to the combined sensing node SOC, and may be connected between the dump transistor 132 and the ground voltage VSS.

[0199] The dump transistor 132 may be driven by the dump signal Dump_C and may transmit the data stored in the C latch CL to the master latch (e.g., the S latch SL in the page buffer unit PBU). The transistor 133 may be driven by the data signal DI, the transistor 134 may be driven by the data inversion signal nDI, and the transistor 135 may be driven by the write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 may be determined based on the data signal DI and the data inversion signal nDI, respectively.

[0200] The cache unit CU may be connected to a data I / O line (or data I / O terminal) RDi via transistors 136 and 137. Transistor 136 may include a gate connected to a second node ND2, and may be turned on or off based on the voltage level of the second node ND2. Transistor 137 may be driven by a read control signal DIO_R. When the read control signal DIO_R is activated and transistor 137 is turned on, the voltage level of the input / output terminal RDi may be determined to be "1" or "0" based on the state of the C latch CL.

[0201] Fig.21 is a diagram showing that according to some embodiments Figure 5 A block diagram of a control circuit in a nonvolatile memory device.

[0202] Reference Fig.21 , the control circuit 450 includes a command decoder 451 , an address buffer 452 , and a control signal generator 453 .

[0203] The command decoder 451 decodes the command CMD and supplies the decoded command D_CMD to the control signal generator 453 .

[0204] The address buffer 452 receives the address signal ADDR, provides a row address R_ADDR to the address decoder 430 , and provides a column address C_ADDR to the data input / output circuit 420 .

[0205] The control signal generator 453 receives the decoded command D_CMD, generates a control signal CTL based on the operation pointed to by the decoded command D_CMD and the voltage level of the programming pass voltage pointed to by the voltage level signal VLS, provides the control signal CTL to the voltage generator 470, generates a page buffer control signal PCTL, provides the page buffer control signal PCTL to the page buffer circuit 410, generates a buffer control signal BCTL, and provides the buffer control signal BCTL to the security buffer 500.

[0206] Fig. 22 is a diagram showing that according to some embodiments Figure 5 Block diagram of a voltage generator in a nonvolatile memory device.

[0207] Reference Fig. 22 The voltage generator 470 may include a high voltage HV generator 475 and a low voltage LV generator 480 . The voltage generator 470 may further include a negative voltage NV generator 485 .

[0208] The high voltage generator 470 may generate a program voltage VPGM, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS, and an erase voltage VERS according to an operation indicated by a command CMD in response to a first control signal CTL1. The program pass voltage VPPASS, the verification pass voltage VVPASS, and the read pass voltage VRPASS may be referred to as a pass voltage VPASS.

[0209] A program voltage PGM is applied to a selected word line, a program pass voltage VPPASS, a verification pass voltage VVPASS, a read pass voltage VRPASS may be applied to unselected word lines, and an erase voltage VERS may be applied to a well of a memory block. The first control signal CTL1 may include a plurality of bits indicating an operation directed by a decoded command D_CMD.

[0210] The low voltage generator 480 may generate a program verification voltage VPV, an erase verification voltage VER, and a read voltage VRD according to an operation indicated by the command CMD in response to the second control signal CTL2. The program verification voltage VPV, the read voltage VRD, and the erase verification voltage VER may be applied to a selected word line according to an operation of the nonvolatile memory device 400. The second control signal CTL2 may include a plurality of bits indicating an operation indicated by the decoding command D_CMD.

[0211] The negative voltage generator 485 may generate a first negative voltage VNEG1 and a second negative voltage VNEG2 having a negative level according to an operation indicated by the command CMD in response to the third control signal CTL3. The third control signal CTL3 may include a plurality of bits indicating the operation indicated by the decoded command D_CMD. The first negative voltage VNEG1 may be applied to the selected word line and the unselected word line during the program recovery period, and the second negative voltage VNEG2 may be applied to the unselected word line during the bit line setting period.

[0212] Fig.23 is a flow chart illustrating initialization operations of a memory system according to some embodiments.

[0213] Reference Figures 1 to 23 , the initialization operation of the memory system 50 may be performed as follows.

[0214] When power is supplied, a power-on operation may be performed (operation S210). In this case, the nonvolatile memory device 400 reads the original setting data OSD from the memory cell array (operation S220). After the read operation of the original setting data OSD, an application use may be selected in the memory controller 200 (operation S230).

[0215] The original setting data OSD may be dumped down in the security buffer 500 including the first register and the second register. When a portion of the setting data OSD dumped down in the security buffer 500 is changed according to the selected application, the security register in the security buffer 500 may be set by changing the setting data stored in at least one of the second registers simultaneously with the setting data stored in the first register, and by restoring the changed setting data stored in at least one of the second registers to the corresponding original setting data (operation S240) to prevent the hooking of the register.

[0216] Fig.24 A method of operating a memory system according to some embodiments is shown.

[0217] Reference Figures 1 to 24 , the method of operating the memory system 50 may be performed as follows.

[0218] The host may send a power-on request to the memory controller 200 of the memory system 50 (operation S310). In this case, the power-on request may be directly performed according to the power supply, or may be performed according to a separate command from the host. The memory controller 200 may select an application use of the nonvolatile memory device 400 according to the power-on request (operation S320). Thereafter, the memory controller 200 may send a read request (e.g., an initial read request) for the original setting data according to the selected application use (operation S330). The initial read request may include a read command and a corresponding address.

[0219] In some embodiments, the initial read request may be arbitrarily sent to the nonvolatile memory device 400 according to a power-on operation or an operation for optimizing performance or reliability. The nonvolatile memory device 400 may perform the initial read operation in response to the read request for the original setting data (operation S340).

[0220] Based on the initial read operation, original setting data OSD may be read from the meta region 406 of the memory cell array 405 .

[0221] The nonvolatile memory device 400 may store the original setting data OSD in Figure 6 The registers 511, 512, 513, and 514 in the security buffer 500 are changed (operation S350). When the setting data stored in the first register 511 is changed, the hooking of the registers can be prevented by changing the setting data stored in at least one of the second registers 512, 513, and 514 simultaneously with the changing of the setting data stored in the first register 511, and by restoring the changed setting data stored in at least one of the second registers 512, 513, and 514 to the corresponding original setting data.

[0222] Thereafter, the host may send an operation request (e.g., a read / write / delete request) to the memory controller 200 (operation S360). The memory controller 200 may send a read / program / erase command corresponding to the operation request to the nonvolatile memory device 400 (operation S370). The nonvolatile memory device 400 may perform an operation corresponding to the received command based on the setting data stored in the registers 511, 512, 513, and 514 in the security buffer 500 (operation S380).

[0223] Fig.25 is a block diagram illustrating a storage device including a nonvolatile memory device according to some embodiments.

[0224] Reference Fig.25 , the storage device 1000 includes a plurality of nonvolatile memory devices NVM 1100 and a controller 1200. For example, the storage device 1000 may be any storage device (such as an embedded multimedia card (eMMC), a universal flash memory (UFS), a solid state disk or a solid state drive (SSD), etc.).

[0225] Controller 1200 may be connected to nonvolatile memory device 1100 via a plurality of channels CCH1, CCH2, CCH3, . . . , CCHk. Controller 1200 may include one or more processors 1210, buffer memory 1220, error correction code (ECC) engine 1230, host interface 1250, and nonvolatile memory (NVM) interface 1260.

[0226] The buffer memory 1220 may store data for driving the controller 1200. The ECC engine 1230 may calculate an error correction code value of data to be programmed during a programming operation, and may use the error correction code value to correct errors of read data during a read operation. In a data recovery operation, the ECC engine 1230 may correct errors of data recovered from the nonvolatile memory device 1100. The host interface 1250 may provide an interface with an external device. The nonvolatile memory interface 1260 may provide an interface with the nonvolatile memory device 1100.

[0227] Each of the nonvolatile memory devices 1100 may correspond to a nonvolatile memory device according to some embodiments, and may be selectively provided with an external high voltage VPP.

[0228] Fig.26 is a cross-sectional view of a nonvolatile memory device according to some embodiments.

[0229] Reference Fig.26, the nonvolatile memory device (or memory device) 5000 may have a chip to chip (C2C, chip to chip) structure. At least one upper chip including a cell area and a lower chip including a peripheral circuit area PREG may be manufactured separately, and then, at least one upper chip and a lower chip may be connected to each other by a bonding method to realize a C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0230] The memory device 5000 may include at least one upper chip including a cell region. Fig.26 As shown in , the memory device 5000 may include two upper chips. However, the number of upper chips is not limited thereto. When the memory device 5000 includes two upper chips, a first upper chip including a first cell region CREG1, a second upper chip including a second cell region CREG2, and a lower chip including a peripheral circuit region PREG may be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 5000. The first upper chip may be flipped and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower parts of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped. In other words, in Fig.26 In the embodiment, the upper portion of the lower chip may represent the upper portion defined based on the positive third direction VD, and the upper portion of each of the first upper chip and the second upper chip may represent the upper portion defined based on the negative third direction VD. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, one of the first upper chip and the second upper chip may be flipped and then connected to the corresponding chip by a bonding method.

[0231] Each of the peripheral circuit region PREG and the first and second cell regions CREG1 and CREG2 of the memory device 5000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0232] The peripheral circuit region PREG may include a first substrate 5210 and a plurality of circuit elements 5220a, 5220b, and 5220c formed on the first substrate 5210. An interlayer insulating layer 5215 including one or more insulating layers may be provided on the plurality of circuit elements 5220a, 5220b, and 5220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 5220a, 5220b, and 5220c may be provided in the interlayer insulating layer 5215. For example, the plurality of metal lines may include first metal lines 5230a, 5230b, and 5230c connected to the plurality of circuit elements 5220a, 5220b, and 5220c, and second metal lines 5240a, 5240b, and 5240c formed on the first metal lines 5230a, 5230b, and 5230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 5230a, 5230b, and 5230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 5240a, 5240b, and 5240c may be formed of copper having a relatively low resistivity.

[0233] In the present embodiment, the first metal lines 5230a, 5230b, and 5230c and the second metal lines 5240a, 5240b, and 5240c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may be further formed on the second metal lines 5240a, 5240b, and 5240c. In this case, the second metal lines 5240a, 5240b, and 5240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 5240a, 5240b, and 5240c may be formed of copper, which has a resistivity lower than the resistivity of the aluminum of the second metal lines 5240a, 5240b, and 5240c.

[0234] The interlayer insulating layer 5215 may be disposed on the first substrate 5210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0235] Each of the first cell region CREG1 and the second cell region CREG2 may include at least one memory block. The first cell region CREG1 may include a second substrate 5310 and a common source line 5320. A plurality of word lines 5330 (5331 to 5338) may be stacked on the second substrate 5310 along a third direction VD perpendicular to the upper surface of the second substrate 5310. A string selection line and a ground selection line may be disposed above and below the word line 5330, and a plurality of word lines 5330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CREG2 may include a third substrate 5410 and a common source line 5420, and a plurality of word lines 5430 (5431 to 5438) may be stacked on the third substrate 5410 along a direction perpendicular to the upper surface of the third substrate 5410 (e.g., a Z-axis direction). Each of the second substrate 5310 and the third substrate 5410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CREG1 and the second cell region CREG2.

[0236] In some embodiments, as shown in region "A1", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the upper surface of the second substrate 5310 to penetrate the word line 5330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 5350c and the second metal line 5360c in the bit line bonding region BLBA. For example, the second metal line 5360c may be a bit line and may be connected to the channel structure CH through the first metal line 5350c. The bit line 5360c may extend in a second direction HD2 parallel to the upper surface of the second substrate 5310.

[0237] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process of forming a lower channel LCH and a process of forming an upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate 5310 to penetrate the common source line 5320 and the lower word lines 5331 and 5332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 5333 to 5338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 5350c and the second metal line 5360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 5000 according to some embodiments may include a channel having improved width uniformity due to a lower channel LCH and an upper channel UCH formed through sequentially performed processes.

[0238] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 5332 and 5333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Optionally, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the normal word lines. The level of the voltage applied to the dummy word line may be different from the level of the voltage applied to the normal word line, and therefore it is feasible to reduce the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device 5000.

[0239] At the same time, in region "A2", the number of lower word lines 5331 and 5332 penetrated by the lower channel LCH is less than the number of upper word lines 5333 to 5338 penetrated by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the structural features and connection relationships of the channel structure CH disposed in the second cell region CREG2 may be substantially the same as the structural features and connection relationships of the channel structure CH disposed in the first cell region CREG1.

[0240] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell region CREG1, and the second through electrode THV2 may be disposed in the second cell region CREG2. Fig.26 As shown in , the first through electrode THV1 may penetrate the common source line 5320 and the plurality of word lines 5330. In some embodiments, the first through electrode THV1 may also penetrate the second substrate 5310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0241] In some embodiments, the first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other through the first through metal pattern 5372d and the second through metal pattern 5472d. The first through metal pattern 5372d may be formed at the bottom end of the first upper chip including the first unit region CREG1, and the second through metal pattern 5472d may be formed at the top end of the second upper chip including the second unit region CREG2. The first through electrode THV1 may be electrically connected to the first metal wire 5350c and the second metal wire 5360c. The lower via 5371d may be formed between the first through electrode THV1 and the first through metal pattern 5372d, and the upper via 5471d may be formed between the second through electrode THV2 and the second through metal pattern 5472d. The first through metal pattern 5372d and the second through metal pattern 5472d may be connected to each other by a bonding method.

[0242] In addition, in the bit line bonding area BLBA, an upper metal pattern 5252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 5392 having the same shape as the upper metal pattern 5252 may be formed in the uppermost metal layer of the first cell area CREG1. The upper metal pattern 5392 of the first cell area CREG1 and the upper metal pattern 5252 of the peripheral circuit area PREG may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 5360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 5220c of the peripheral circuit area PREG may constitute a page buffer, and the bit line 5360c may be electrically connected to the circuit elements 5220c constituting the page buffer through the upper bonding metal pattern 5370c of the first cell area CREG1 and the upper bonding metal pattern 5270c of the peripheral circuit area PERI.

[0243] Continue to refer to Fig.26, in the word line bonding area WLBA, the word lines 5330 of the first cell region CREG1 may extend along a first direction HD1 parallel to the upper surface of the second substrate 5310, and may be connected to a plurality of cell contact plugs 5340 (5341 to 5347). The first metal line 5350b and the second metal line 5360b may be sequentially connected to the cell contact plugs 5340 connected to the word lines 5330. In the word line bonding area WLBA, the cell contact plugs 5340 may be connected to the peripheral circuit region PREG through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI.

[0244] The cell contact plug 5340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 5220b of the peripheral circuit region PREG may constitute a row decoder, and the cell contact plug 5340 may be electrically connected to the circuit element 5220b constituting the row decoder through the upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit element 5220b constituting the row decoder may be different from the operating voltage of the circuit element 5220c constituting the page buffer. For example, the operating voltage of the circuit element 5220c constituting the page buffer may be greater than the operating voltage of the circuit element 5220b constituting the row decoder.

[0245] Similarly, in the word line bonding area WLBA, the word lines 5430 of the second cell region CREG2 may extend in a first direction HD1 parallel to the upper surface of the third substrate 5410 and may be connected to a plurality of cell contact plugs 5440 (5441 to 5447). The cell contact plugs 5440 may be connected to the peripheral circuit region PREG through the upper metal pattern of the second cell region CREG2 and the lower metal pattern, the upper metal pattern, and the cell contact plugs 5348 of the first cell region CREG1.

[0246] In the word line bonding area WLBA, the upper bonding metal pattern 5370b may be formed in the first cell region CREG1, and the upper bonding metal pattern 5270b may be formed in the peripheral circuit region PERI. The upper bonding metal pattern 5370b of the first cell region CREG1 and the upper bonding metal pattern 5270b of the peripheral circuit region PREG may be electrically connected to each other by a bonding method. The upper bonding metal pattern 5370b and the upper bonding metal pattern 5270b may be formed of aluminum, copper, or tungsten.

[0247] In the external pad (or pad) bonding area PA, the lower metal pattern 5371e may be formed in the lower portion of the first unit region CREG1, and the upper metal pattern 5472a may be formed in the upper portion of the second unit region CREG2. The lower metal pattern 5371e of the first unit region CREG1 and the upper metal pattern 5472a of the second unit region CREG2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 5372a may be formed in the upper portion of the first unit region CREG1, and the upper metal pattern 5272a may be formed in the upper portion of the peripheral circuit region PERI. The upper metal pattern 5372a of the first unit region CREG1 and the upper metal pattern 5272a of the peripheral circuit region PREG may be connected to each other by a bonding method.

[0248] The common source line contact plugs 5380 and 5480 may be disposed in the external pad bonding area PA. The common source line contact plugs 5380 and 5480 may be formed of a conductive material such as a metal, a metal compound, and / or doped polysilicon. The common source line contact plug 5380 of the first unit region CREG1 may be electrically connected to the common source line 5320, and the common source line contact plug 5480 of the second unit region CREG2 may be electrically connected to the common source line 5420. The first metal line 5350a and the second metal line 5360a may be sequentially stacked on the common source line contact plug 5380 of the first unit region CREG1, and the first metal line 5450a and the second metal line 5460a may be sequentially stacked on the common source line contact plug 5480 of the second unit region CREG2.

[0249] The input / output pads 5205, 5405, and 5406 may be disposed in the external pad bonding area PA. Fig.26 , a lower insulating layer 5201 may cover the bottom surface of the first substrate 5210, and a first input / output pad 5205 may be formed on the lower insulating layer 5201. The first input / output pad 5205 may be connected to at least one of a plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through a first input / output contact plug 5203, and may be separated from the first substrate 5210 by the lower insulating layer 5201. In addition, a side insulating layer may be disposed between the first input / output contact plug 5203 and the first substrate 5210 to electrically isolate the first input / output contact plug 5203 from the first substrate 5210.

[0250] An upper insulating layer 5401 covering the upper surface of the third substrate 5410 may be formed on the third substrate 5410. Second input / output pads 5405 and / or third input / output pads 5406 may be disposed on the upper insulating layer 5401. The second input / output pads 5405 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through second input / output contact plugs 5403 and 5303, and the third input / output pads 5406 may be connected to at least one of the plurality of circuit elements 5220a disposed in the peripheral circuit region PREG through third input / output contact plugs 5404 and 5304.

[0251] In some embodiments, the third substrate 5410 may not be disposed in the region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 5404 may be separated from the third substrate 5410 in a direction parallel to the upper surface of the third substrate 5410, and may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 to be connected to the third input / output pad 5406. In this case, the third input / output contact plug 5404 may be formed by at least one of various processes.

[0252] In some embodiments, as shown in region "B1", the third input / output contact plug 5404 may extend along the third direction VD, and the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 5401, but the diameter of the third input / output contact plug 5404 may gradually increase toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded by a bonding method.

[0253] In some embodiments, as shown in region "B2", the third input / output contact plug 5404 may extend along the third direction VD, and the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. In other words, similar to the channel structure CH, the diameter of the third input / output contact plug 5404 may gradually decrease toward the upper insulating layer 5401. For example, the third input / output contact plug 5404 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0254] In some embodiments, the input / output contact plug may overlap the third substrate 5410. For example, as shown in region "C", the second input / output contact plug 5403 may penetrate the interlayer insulating layer 5415 of the second cell region CREG2 along the third direction VD and may be electrically connected to the second input / output pad 5405 through the third substrate 5410. In this case, the connection structure of the second input / output contact plug 5403 and the second input / output pad 5405 may be implemented by various methods.

[0255] In some embodiments, as shown in region "C1", the opening 5408 may be formed to penetrate the third substrate 5410, and the second input / output contact plug 5403 may be directly connected to the second input / output pad 5405 through the opening 5408 formed in the third substrate 5410. In this case, as shown in region "C1", the diameter of the second input / output contact plug 5403 may gradually become larger toward the second input / output pad 5405. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 5403 may gradually become smaller toward the second input / output pad 5405.

[0256] In some embodiments, as shown in region "C2", an opening 5408 penetrating the third substrate 5410 may be formed, and a contact 5407 may be formed in the opening 5408. One end of the contact 5407 may be connected to the second input / output pad 5405, and the other end of the contact 5407 may be connected to the second input / output contact plug 5403. Therefore, the second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 in the opening 5408. In this case, as shown in region "C2", the diameter of the contact 5407 may gradually become larger toward the second input / output pad 5405, and the diameter of the second input / output contact plug 5403 may gradually become smaller toward the second input / output pad 5405. For example, the second input / output contact plug 5403 may be formed together with the cell contact plug 5440 before the second cell region CREG2 and the first cell region CREG1 are bonded to each other, and the contact 5407 may be formed after the second cell region CREG2 and the first cell region CREG1 are bonded to each other.

[0257] In some embodiments shown in region "C3", compared to the embodiments of region "C2", a stopper 5409 may be further formed on the bottom end of the opening 5408 of the third substrate 5410. The stopper 5409 may be a metal line formed in the same layer as the common source line 5420. Alternatively, the stopper 5409 may be a metal line formed in the same layer as at least one of the word lines 5430. The second input / output contact plug 5403 may be electrically connected to the second input / output pad 5405 through the contact 5407 and the stopper 5409.

[0258] Similar to the second input / output contact plug 5403 and the third input / output contact plug 5404 of the second unit region CREG2, the diameter of each of the second input / output contact plug 5303 and the third input / output contact plug 5304 of the first unit region CREG1 may gradually become smaller toward the lower metal pattern 5371e, or may gradually become larger toward the lower metal pattern 5371e.

[0259] Meanwhile, in some embodiments, a slit 5411 may be formed in the third substrate 5410. For example, the slit 5411 may be formed at a specific position of the external pad landing area PA. For example, as shown in area "D", when viewed in a plan view, the slit 5411 may be located between the second input / output pad 5405 and the cell contact plug 5440. Alternatively, when viewed in a plan view, the second input / output pad 5405 may be located between the slit 5411 and the cell contact plug 5440.

[0260] In some embodiments, as shown in region "D1", the slit 5411 may be formed to penetrate the third substrate 5410. For example, when forming the opening 5408, the slit 5411 may be used to prevent the third substrate 5410 from being finely broken. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slit 5411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 5410.

[0261] In some embodiments, as shown in region "D2", a conductive material 5412 may be formed in the slit 5411. For example, the conductive material 5412 may be used to discharge leakage current that occurs when driving circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 5412 may be connected to an external ground line.

[0262] In some embodiments, as shown in region "D3", an insulating material 5413 may be formed in the slit 5411. For example, the insulating material 5413 may be used to electrically isolate the second input / output pad 5405 and the second input / output contact plug 5403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Since the insulating material 5413 is formed in the slit 5411, a voltage provided through the second input / output pad 5405 may be prevented from affecting a metal layer on the third substrate 5410 disposed in the word line bonding region WLBA.

[0263] Meanwhile, in some embodiments, the first to third input / output pads 5205, 5405, and 5406 may be selectively formed. For example, the memory device 5000 may be implemented to include only the first input / output pad 5205 disposed on the first substrate 5210, only the second input / output pad 5405 disposed on the third substrate 5410, or only the third input / output pad 5406 disposed on the upper insulating layer 5401.

[0264] In some embodiments, at least one of the second substrate 5310 of the first unit region CREG1 or the third substrate 5410 of the second unit region CREG2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate is removed. For example, the second substrate 5310 of the first unit region CREG1 may be removed before or after the bonding process of the peripheral circuit region PREG and the first unit region CREG1, and then an insulating layer covering the upper surface of the common source line 5320 or a conductive layer for connection may be formed. Similarly, the third substrate 5410 of the second unit region CREG2 may be removed before or after the bonding process of the first unit region CREG1 and the second unit region CREG2, and then an upper insulating layer 5401 covering the upper surface of the common source line 5420 or a conductive layer for connection may be formed.

[0265] Fig. 27 is a diagram illustrating a manufacturing process of a stacked semiconductor device according to some embodiments.

[0266] Reference Fig. 27 , corresponding integrated circuits may be formed on the first wafer WF1 and the second wafer WF2. A memory cell array may be formed in the first wafer WF1, and a peripheral circuit may be formed in the second wafer WF2.

[0267] After various integrated circuits have been formed on the first wafer WF1 and the second wafer WF2, respectively, the first wafer WF1 and the second wafer WF2 may be bonded together. The bonded wafers WF1 and WF2 may then be cut (or divided) into separate chips, each of which corresponds to a semiconductor device (such as, for example, a memory device 5000), the memory device 5000 including a vertically stacked first semiconductor die SD1 and a second semiconductor die SD2 (for example, the first semiconductor die SD1 is stacked on the second semiconductor die SD2, etc.). Each cut portion of the first wafer WF1 corresponds to the first semiconductor die SD1, and each cut portion of the second wafer WF2 corresponds to the second semiconductor die SD2. For example, Fig.26 The memory device 5000 may be based on Fig. 27 Manufacturing process to manufacture.

[0268] Fig.28 is a block diagram illustrating an electronic system including a semiconductor device according to some embodiments.

[0269] Reference Fig.28 , the electronic system 3000 may include a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100. The electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including a storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or more semiconductor devices 3100.

[0270] The semiconductor device 3100 may be a nonvolatile memory device (eg, see Figures 5 to 22 The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0271] In the second structure 3100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary according to various embodiments.

[0272] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0273] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be in an erase operation for erasing data stored in the memory cell transistor MCT by a gate-induced drain leakage (GIDL) phenomenon.

[0274] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 3110 through the first connection wiring 1115 extending to the second structure 3110S in the first structure 3100F. The bit line BL may be electrically connected to the page buffer circuit 3120 through the second connection wiring 3125 extending to the second structure 3100S in the first structure 3100F.

[0275] In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 may perform a control operation on at least one memory cell transistor selected from among the plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by the logic circuit 3130. The semiconductor device 3100 may communicate with the controller 3200 through the input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 may be electrically connected to the logic circuit 3130 through the input / output connection wiring 3135 extending to the second structure 3100S in the first structure 3100F.

[0276] The controller 3200 may include a processor 3210, a NAND controller 3220, and a host interface (I / F) 3230. The electronic system 3000 may include a plurality of semiconductor devices 3100, and in this case, the controller 3200 may control the plurality of semiconductor devices 3100.

[0277] The processor 3210 may control the operation of the electronic system 3000 including the controller 3200. The processor 3210 may be operated by firmware, and may control the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 may include a NAND interface (I / F) 3221 for communicating with the semiconductor device 3100. Through the NAND interface 3221, a control command for controlling the semiconductor device 3100, data to be written into the memory cell transistor MCT of the semiconductor device 3100, data to be read from the memory cell transistor MCT of the semiconductor device 3100, etc. may be transmitted. The host interface 3230 may provide communication between the electronic system 3000 and an external host. When a control command is received from the external host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.

[0278] Nonvolatile memory devices or storage devices according to some embodiments may be packaged using various package types or package configurations.

[0279] The present disclosure may be applied to various electronic devices and systems including non-volatile memory devices and memory packages. For example, the present disclosure may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0280] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the protection that can be claimed. Specific features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in a specific combination, one or more features from the combination may be deleted from the combination in some cases, and the combination may point to a sub-combination or a variation of the sub-combination.

[0281] The foregoing illustrates examples and should not be construed as limiting them. Although some examples have been described, it will be readily appreciated by those skilled in the art that many modifications are possible without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. A non-volatile memory device, comprising: a memory cell array configured to store original setting data; a page buffer circuit connected to the memory cell array via a plurality of bit lines; a security buffer including an access control circuit and a plurality of registers with restricted access, the plurality of registers being configured to store original setup data dumped down from the memory cell array via the page buffer circuit in an initialization sequence; as well as a control circuit configured to control the page buffer circuit and the security buffer, The plurality of registers include a first register and a second register, and The access control circuit is configured to: in response to the first register being accessed, access at least a portion of the second registers simultaneously with accessing the first register.

2. The nonvolatile memory device according to claim 1, wherein: The first register is accessed causing the first setting data stored in the first register to be changed, and Wherein the access control circuit is configured to change the corresponding setting data stored in each of the second registers by accessing the second registers simultaneously with accessing the first registers.

3. The nonvolatile memory device according to claim 2, wherein: The access control circuit includes: A first AND gate configured to generate a first selection signal for selecting the first register based on the register access mode signal and a bit of a first register address specifying the first register; a second AND gate configured to generate an intermediate selection signal associated with selecting the second register based on the register access mode signal and a bit of a second register address specifying the second register; and The OR gate is configured to generate a second selection signal for selecting a corresponding second register among the second registers by performing an OR operation on the first selection signal and a corresponding intermediate selection signal among the intermediate selection signals.

4. The nonvolatile memory device according to claim 3, wherein: In response to activation of the first selection signal, the first register is accessed and the first setting data stored in the first register is changed, Wherein the access control circuit is configured to change the corresponding setting data stored in each of the second registers by accessing the second registers simultaneously with accessing the first register by activating the second selection signal.

5. The nonvolatile memory device according to claim 4, wherein: The access control circuit is configured as follows: after the corresponding setting data stored in each of the second registers is changed, the first selection signal is deactivated, and The changed corresponding setting data in each of the second registers is restored to the corresponding original setting data.

6. The nonvolatile memory device according to claim 5, wherein: The control circuit is configured to perform a core operation based on the changed first setting data stored in the first register and the restored corresponding original setting data stored in the second register.

7. The nonvolatile memory device according to claim 1, wherein: The access control circuit is configured as follows: grouping the second register into at least two groups; When the first register is accessed and the first setting data stored in the first register is changed, accessing a first group of the at least two groups simultaneously with accessing the first register; and Setting data stored in at least one register in the first group is changed.

8. The nonvolatile memory device according to claim 7, wherein: The access control circuit includes: A first AND gate configured to generate a first selection signal for selecting the first register based on the register access mode signal and a bit of a first register address specifying the first register; a second AND gate configured to generate an intermediate selection signal associated with selecting the second register based on the register access mode signal and a bit of a second register address specifying the second register; a third AND gate configured to generate a group selection signal for selecting a corresponding group of the at least two groups based on group selection information, the group selection information being based on a combination of consecutive commands; and The OR gate is configured to generate a second selection signal for selecting a corresponding second register among the second registers by performing an OR operation on the first selection signal, a corresponding group selection signal among the group selection signals, and a corresponding intermediate selection signal among the intermediate selection signals.

9. The nonvolatile memory device according to claim 8, wherein: The at least two groups include a first group and a second group, and Wherein, the access control circuit is configured to: when the first register is accessed and the first setting data stored in the first register is changed in response to the activation of the first selection signal, change the setting data stored in at least one second register in the first group by activating the first group selection signal in the group selection signal.

10. The nonvolatile memory device according to claim 9, wherein: The access control circuit is configured as follows: after the setting data stored in the at least one second register is changed, deactivating the first selection signal, selecting the at least one second register, and The changed setting data in the at least one second register is restored to the original setting data.

11. The nonvolatile memory device according to claim 8, wherein: The at least two groups include a first group and a second group, and The access control circuit is configured to change the setting data stored in at least one second register in the second group by activating a second group selection signal in the group selection signal when the first register is accessed and the first setting data stored in the first register is changed in response to activation of the first selection signal.

12. The nonvolatile memory device according to claim 11, wherein: The access control circuit is configured as follows: after the setting data stored in the at least one second register is changed, deactivating the first selection signal, selecting the at least one second register, and The changed setting data in the at least one second register is restored to the original setting data.

13. The nonvolatile memory device according to any one of claims 1 to 12, wherein: The access control circuit is configured to: when the first register is accessed and the first setting data stored in the first register is changed: cutting off access to the second register based on being configured in the first mode; or Based on being configured in the second mode, corresponding setting data stored in each of the second registers is changed by accessing the second registers simultaneously with accessing the first registers.

14. The nonvolatile memory device according to claim 1, wherein: The access control circuit includes: a first AND gate configured to generate a first mode selection signal activated in the first mode based on a set data dump signal specifying the first mode, a register access mode signal, and a bit of a first register address specifying the first register; a second AND gate configured to generate a second mode selection signal activated in the second mode based on the pin reduction mode signal specifying the second mode, the register access mode signal, and the bit of the first register address; a third AND gate configured to generate an intermediate selection signal associated with selecting the second register based on the register access mode signal and a bit of a second register address specifying the second register; a first OR gate configured to generate a first selection signal for selecting the first register by performing an OR operation on the first mode selection signal and the second mode selection signal; and The second OR gate is configured to generate a second selection signal for selecting a corresponding second register among the second registers by performing an OR operation on the second mode selection signal and a corresponding intermediate selection signal among the intermediate selection signals.

15. The nonvolatile memory device according to claim 14, wherein: The first mode is a mode in which the original setting data is dumped down, and wherein the access control circuit is configured to: Based on being configured in the first mode, when the first register is accessed by activating the first mode selection signal and deactivating the second mode selection signal, access to the second register is cut off.

16. The nonvolatile memory device according to claim 14, wherein: The second mode is a mode in which a test is performed on the non-volatile memory device, and wherein the access control circuit is configured to: Based on being configured in the second mode, when the first register is accessed by deactivating the first mode selection signal and activating the second mode selection signal, access to the second register is permitted.

17. The nonvolatile memory device according to any one of claims 1 to 12, in, The memory cell array includes at least one memory block including a plurality of cell strings, wherein each of the plurality of cell strings comprises a string selection transistor, a plurality of memory cells, and a ground selection transistor, the string selection transistor, the plurality of memory cells, and the ground selection transistor being connected in series and arranged between each of the plurality of bit lines and a common source line along a vertical direction, wherein the memory cell array is configured to store replica setting data generated by replicating original setting data, and The page buffer circuit includes a verification circuit configured to perform verification on the original setting data based on the original setting data and the replica setting data.

18. A memory system comprising: a non-volatile memory device; as well as a memory controller configured to control the nonvolatile memory device, Wherein, the non-volatile memory device comprises: a memory cell array configured to store original setting data; a page buffer circuit connected to the memory cell array via a plurality of bit lines; a security buffer including an access control circuit and a plurality of registers with restricted access, the plurality of registers being configured to store original setup data that is dumped down from the memory cell array through the page buffer circuit in an initialization sequence; and a control circuit configured to control the page buffer circuit and the security buffer, The plurality of registers include a first register and a second register, and The access control circuit is configured to: in response to the first register being accessed, access at least a portion of the second registers simultaneously with accessing the first register.

19. The memory system of claim 18, wherein: The access control circuit includes: A first AND gate configured to generate a first selection signal for selecting the first register based on the register access mode signal and a bit of a first register address specifying the first register; a second AND gate configured to generate an intermediate selection signal associated with selecting the second register based on the register access mode signal and a bit of a second register address specifying the second register; and The OR gate is configured to generate a second selection signal for selecting a corresponding second register among the second registers by performing an OR operation on the first selection signal and a corresponding intermediate selection signal among the intermediate selection signals.

20. A non-volatile memory device comprising: a memory cell array configured to store original setting data; a page buffer circuit connected to the memory cell array via a plurality of bit lines; a security buffer including an access control circuit and a plurality of registers with restricted access, the plurality of registers being configured to store original setup data dumped down from the memory cell array via the page buffer circuit in an initialization sequence; as well as a control circuit configured to control the page buffer circuit and the security buffer, The plurality of registers include a first register and a second register, and The access control circuit is configured to: in response to the first register being accessed, access at least a portion of the second registers simultaneously with accessing the first register; Wherein, the access control circuit is configured as follows: When the first register is accessed and the first setting data stored in the first register is changed, the corresponding setting data stored in each of the second registers is changed by accessing the second register simultaneously with accessing the first register, and restoring the changed corresponding setting data stored in each of the second registers to the corresponding original setting data, and The control circuit is configured to perform a core operation based on the changed first setting data stored in the first register and the restored corresponding original setting data stored in the second register.

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