A method for analyzing non-associative, packetized memory failure cells

Abstract

The application provides a non-associated grouping memory failure unit analysis method, first, the position information of all memory failure units is obtained through a chip tester to form a fault bit map; then, based on the position information characteristics in the fault bit map, all the failure units in the fault bit map are grouped based on a grouping principle to form a multi-failure group and a single-failure group; then, based on the repair principle of the memory failure unit, the failure units in each group are analyzed for repair to determine whether the failure units of the memory chip can be repaired; if the failure units of the memory chip can be repaired, a repair solution is given. The application divides all the failure units of the memory chip into independent multi-failure groups and single-failure groups based on the non-associated grouping memory failure unit analysis method, and then analyzes and finds the redundancy repair solution of each failure group, which can more reasonably allocate the redundancy resources and effectively improve the repair efficiency of the memory failure units.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for analyzing failed cells in non-associative grouped memory. Background Technology

[0002] The development of deep submicron technology in semiconductor manufacturing has not only increased the integration scale of memory devices but also increased the probability of memory defects. Memory is an indispensable and important component in many modern electronic devices and can be divided into DRAM (Dynamic Random Access Memory), Flash memory, etc. DRAM memory is mainly composed of an array of memory cells, each of which can only store one bit of valid data. Its performance directly affects whether the entire memory device can function properly.

[0003] A chip tester is a machine specifically designed to test whether the performance of semiconductor chips meets standards. It plays a crucial role in the chip design and manufacturing process. Chip testers can typically test various types of chips, with memory chips being the primary target for testing. The test programs on the machine analyze the chip's performance based on its characteristics, thereby ensuring the production yield of memory chips.

[0004] Memory repair analysis is a crucial component of memory fault repair. The circuitry used to repair failed memory cells is called redundant cell circuitry. Redundant cells are typically divided into row redundant cells and column redundant cells, used to replace memory failure cells detected by the chip testing machine. With the increasing integration of memory chips, the problem of redundant repair schemes for memory failure cells has become more complex. When the number of failure cells is large and their distribution is scattered, exhaustive search-based repair schemes are no longer applicable because they involve listing each failure cell individually to find a redundant repair solution, which inevitably consumes a significant amount of redundancy analysis time. Furthermore, in other redundancy repair schemes, only a portion of the redundant cells may be needed to repair all memory failure cells, while replacing an entire redundant row or column may lead to a waste of redundant resources.

[0005] Considering that all memory failure cells can be repaired using a limited number of redundant rows and columns, this paper proposes a non-associative grouping analysis method that can find redundant repair schemes for memory failure cells in a short time, thereby obtaining the optimal solution for memory failure cell repair. Summary of the Invention

[0006] The purpose of this invention is to provide a method for analyzing faulty cells in non-associative grouped memory, thereby overcoming the shortcomings of the prior art.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A method for analyzing faulty cells in a non-associative grouped memory includes the following steps:

[0009] S1. The performance of the memory chip is detected by running test vectors through a chip tester, and the location information of all memory failure cells is obtained to form a fault bitmap.

[0010] S2. Based on the basic principle of fault grouping, all fault units in the fault bitmap are grouped according to the location information characteristics of different failure units in the fault bitmap to form multi-fault groups and single-fault groups.

[0011] S3. Based on the repair principles of memory failure units, perform repair analysis on the failure units in each group to determine whether the failure units of the memory chip can be repaired.

[0012] S4. If the faulty cell of the memory chip can be repaired, provide a repair solution.

[0013] Furthermore, the fault bitmap described in step S1 is a rectangular table with a similar structure to the memory storage cell array. The table contains the location information of all failed cells and redundant rows and columns of the memory that can be repaired. Each failed cell in the fault bitmap contains a horizontal coordinate and a vertical coordinate, namely the X address and the Y address.

[0014] Further, the basic principle of fault grouping in step S2 includes: dividing all fault units in the fault bitmap into multi-fault groups and single-fault groups; the multi-fault group refers to a set of multiple fault units that do not share the same row address or column address as fault units in other fault groups; the single-fault group refers to a single fault unit that does not share a row address or column address with other faults; the set of fault units in the multi-fault groups and the set of fault units in the single-fault groups are represented by the following equations (1) and (2), respectively:

[0015] M = {…F ij …} (1)

[0016] S={f ij} (2)

[0017] In equations (1) and (2): F ij f represents a faulty unit in a multi-fault group set; ij This represents the faulty unit in the single fault group set; i and j represent the x-coordinate and y-coordinate of the faulty unit, respectively.

[0018] Furthermore, the repair principle for the memory failure unit described in step S3 includes: if the sum of the number of fault groups is greater than the sum of the number of redundant rows and columns that can be repaired, then the memory failure unit is determined to be unrepairable; during the repair process, multiple fault groups in the memory fault bitmap are repaired first, and then single fault groups are repaired.

[0019] Furthermore, step S4 is specifically implemented through the following steps:

[0020] S41. Model a single multi-fault group, connect the fault units on the same line in the multi-fault group, and construct a multi-fault group mode.

[0021] S42. Based on the location information of each fault unit in the multi-fault group, count the number of fault rows Nfr and the number of fault columns Nfc in the multi-fault group mode as the number of redundant unit rows or redundant unit columns required to repair the multi-fault group, and form a repair scheme table for the multi-fault group.

[0022] S43. Repeat the above steps to obtain the repair plan table for each multi-fault group;

[0023] S44. Based on the repair scheme table, allocate redundant resources reasonably to generate the final memory failure unit repair solution: After obtaining the repair scheme for each multi-fault group, use the remaining redundant units to repair the single fault group.

[0024] As can be seen from the above technical solutions, the present invention is based on a non-associative grouped memory failure cell analysis method, which divides all fault cells of the memory chip into independent multi-fault groups and single-fault groups, and then analyzes and finds redundant repair schemes for each fault group separately, so that each fault group can find repair schemes for fault cells in parallel; it can allocate redundant resources more rationally and effectively improve the repair efficiency of memory failure cells. Attached Figure Description

[0025] Figure 1 This is a schematic flowchart of the non-associative grouped memory failure cell analysis method of the present invention;

[0026] Figure 2 This is a schematic diagram of memory failure cells and redundant cells;

[0027] Figure 3 This is a schematic diagram of fault grouping corresponding to the fault bitmap of the memory;

[0028] Figure 4 This is a schematic diagram of the fault group mode;

[0029] Figure 5 This is a schematic diagram of the redundancy repair scheme analysis. Detailed Implementation

[0030] A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0031] like Figure 1 The non-associative grouped memory failure cell analysis method shown includes the following steps:

[0032] S1. The performance of the memory chip is detected by running test vectors through a chip tester, and the location information of all memory failure cells is obtained to form a fault bitmap.

[0033] like Figure 2 As shown, the fault bitmap described in this preferred embodiment is a rectangular table with a structure similar to the memory storage cell array. The table contains the location information of all failed cells and redundant rows and columns of the memory that can be repaired. Each failed cell in the fault bitmap contains a horizontal coordinate and a vertical coordinate, namely the X address and the Y address.

[0034] S2. Based on the basic principle of fault grouping, and considering the location information characteristics of different failure units in the fault bitmap, all fault units in the fault bitmap are grouped to form multi-fault groups and single-fault groups.

[0035] Specifically, such as Figure 3 The multi-fault groups 1, 2, and 3 and the single-fault group 1 shown are based on the following fundamental principles:

[0036] All fault units in the fault bitmap are divided into multi-fault groups and single-fault groups;

[0037] The term "multi-fault group" refers to a set of multiple fault units that do not share the same row address or column address as fault units in other fault groups. Based on this principle, fault units with the same row or column in the fault bitmap are grouped together to form several sets of multi-fault groups.

[0038] The single fault group refers to a single fault unit that does not share row or column addresses with other faults. Based on this principle, fault units in the fault bitmap that do not have the same row or column addresses as any other fault units are identified to form several single fault group sets.

[0039] The set of fault units in the multi-fault group and the set of fault units in the single-fault group are represented by the following equations (1) and (2), respectively:

[0040] M = {…F ij …} (1)

[0041] S={f ij} (2)

[0042] In equations (1) and (2): F ijf represents a faulty unit in a multi-fault group set; ij This represents the faulty unit in the single fault group set; i and j represent the x-coordinate and y-coordinate of the faulty unit, respectively.

[0043] S3. Based on the repair principles of memory failure units, perform repair analysis on the failure units in each group to determine whether the failure units of the memory chip can be repaired.

[0044] The repair principles for memory failure cells described in this preferred embodiment include:

[0045] If the sum of the number of fault groups is greater than the sum of the number of redundant rows and columns available for repair, then the memory failure unit is determined to be unrepairable, and the repair process is terminated in advance, thus avoiding the waste of redundancy analysis time.

[0046] For repair processes, multiple fault groups in the memory fault bitmap can be repaired first, followed by single fault groups.

[0047] S4. If the faulty cell of the memory chip can be repaired, provide a repair solution.

[0048] The basic idea of ​​the repair solution is to first repair multiple fault groups, and then use the remaining redundant units to repair single fault groups; in specific operation, step S4 is implemented through the following steps:

[0049] S41. Model a single multi-fault group, connect the fault units on the same line in the multi-fault group, and construct a multi-fault group mode.

[0050] S42. Based on the location information of each fault unit in the multi-fault group, count the number of fault rows Nfr and the number of fault columns Nfc in the multi-fault group mode as the number of redundant unit rows or redundant unit columns required to repair the multi-fault group, and form a repair scheme table for the multi-fault group.

[0051] S43. Repeat the above steps to obtain the repair plan table for each multi-fault group;

[0052] S44. Based on the repair scheme table, allocate redundant resources reasonably to generate the final memory failure unit repair solution: After obtaining the repair scheme for each multi-fault group, use the remaining redundant units to repair the remaining single-fault groups.

[0053] For example Figure 3 The diagram shown illustrates fault grouping in a memory device, and its multi-fault grouping mode is as follows: Figure 4 As shown in the table, the corresponding repair plan is as follows: Figure 5 As shown; by Figure 3As can be seen, four redundant columns and three redundant rows are used to repair all the faulty units in the diagram. Considering the number of faulty rows Nfr and faulty columns Nfc in each fault group, the final repair scheme is as follows: multi-fault group 1 is repaired by three redundant columns, multi-fault group 2 is repaired by two redundant rows, multi-fault group 3 is repaired by one redundant row, and single-fault group is repaired by the last remaining redundant column. Based on this, all memory failure units are repaired.

[0054] The above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made by those skilled in the art to the technical solutions of the present invention without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for analyzing failed cells in a non-associative grouped memory, characterized in that, Includes the following steps: S1. The performance of the memory chip is detected by running test vectors through a chip tester, and the location information of all memory failure cells is obtained to form a fault bitmap. S2. Based on the basic principle of fault grouping, all fault units in the fault bitmap are grouped according to the location information characteristics of different failure units in the fault bitmap to form multi-fault groups and single-fault groups. The basic principles of fault grouping include: dividing all fault units in the fault bitmap into multi-fault groups and single-fault groups; a multi-fault group refers to a set of multiple fault units that do not share the same row address or column address as fault units in other fault groups; a single-fault group refers to a single fault unit that does not share a row address or column address with other faults; the set of fault units in the multi-fault groups and the set of fault units in the single-fault groups are represented by the following equations (1) and (2), respectively: （1） （2） In equations (1) and (2): This represents a faulty unit in a set of multiple fault groups; This represents a faulty unit within a single fault group set; and These represent the x-coordinate and y-coordinate of the faulty unit, respectively. S3. Based on the repair principles of memory failure units, perform repair analysis on the failure units in each group to determine whether the failure units of the memory chip can be repaired. S4. If the faulty cells of the memory chip can be repaired, provide a repair solution. Specifically, step S4 is implemented through the following steps: S41. Model a single multi-fault group, connect the fault units on the same line in the multi-fault group, and construct a multi-fault group mode. S42. Based on the location information of each fault unit in the multi-fault group, count the number of fault rows in the multi-fault group mode. and number of fault columns The number of redundant unit rows or columns required to repair the multi-fault group is used to form a repair scheme table for the multi-fault group. S43. Repeat the above steps to obtain the repair plan table for each multi-fault group; S44. Based on the repair scheme table, allocate redundant resources reasonably to generate the final memory failure unit repair solution: After obtaining the repair scheme for each multi-fault group, use the remaining redundant units to repair the single fault group.

2. The method for analyzing failure cells in a non-associative grouped memory according to claim 1, characterized in that, The fault bitmap described in step S1 is a rectangular table with a structure similar to the memory cell array. The table contains the location information of all failed cells and redundant rows and columns of the memory that can be repaired. Each failed cell in the fault bitmap contains a horizontal coordinate and a vertical coordinate, namely the X address and the Y address.

3. The method for analyzing failure cells in a non-associative grouped memory according to claim 1, characterized in that, The repair principle of the memory failure unit in step S3 includes: if the sum of the number of fault groups is greater than the sum of the number of redundant rows and columns that can be repaired, then the memory failure unit is determined to be unrepairable; during the repair process, multiple fault groups in the memory fault bitmap are repaired first, and then single fault groups are repaired.

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