A semiconductor device, an etching method thereof, and a manufacturing method thereof

Abstract

The present invention discloses a semiconductor device, an etching method thereof and a manufacturing method thereof. A first etching process is used to etch a dummy gate to remove a first thickness of the dummy gate and retain a second thickness of the dummy gate, where the first thickness is greater than the second thickness. A second etching process is used to etch the dummy gate with the second thickness to remove the dummy gate with the second thickness. The second etching process includes a gasification process, and the gasification process is used to convert the dummy gate with the second thickness into gaseous substances and let them escape. Since the corrosiveness of the second etching process, such as the gasification process, to the barrier layer is less than that of the first etching process, such as a dry etching process or a wet etching process, to the barrier layer, the damage to the barrier layer caused by the etching of the dummy gate can be reduced. Furthermore, the metal blocking ability of the barrier layer will not decrease significantly, and furthermore, the probability of the metal in the metal gate diffusing into the high-k gate dielectric layer can be reduced, and furthermore, the reliability of the semiconductor device can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device, an etching method thereof, and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices (such as transistors) is continuously decreasing, while the leakage current and power consumption of semiconductor devices are continuously increasing. Although by replacing the traditional gate dielectric material with a high-k gate dielectric material and replacing the polysilicon gate with a metal gate, the leakage current and power consumption of semiconductor devices can be effectively reduced, however, in the process of forming a metal gate by using a post-gate process, after replacing the dummy gate with a metal gate, the metal blocking ability of the barrier layer between the gate and the high-k gate dielectric layer will significantly decrease, resulting in an increased probability of the metal in the metal gate diffusing into the high-k gate dielectric layer, and thus the reliability of the semiconductor device becomes poor. Summary of the Invention

[0003] The present invention discloses a semiconductor device, an etching method thereof, and a manufacturing method thereof, so that the metal blocking ability of the barrier layer will not significantly decrease.

[0004] In a first aspect, the present invention discloses an etching method of a semiconductor device, including: providing a semiconductor device to be etched, the semiconductor device including a substrate, a dummy gate structure located on the substrate, and an interlayer dielectric layer, the dummy gate structure including a high-k gate dielectric layer, a barrier layer, and a dummy gate sequentially stacked on the substrate, doping regions being provided on both sides of the substrate of the dummy gate structure, the interlayer dielectric layer being filled between the dummy gate structures and exposing the dummy gate; etching the dummy gate by using a first etching process to remove a first thickness of the dummy gate and retain a second thickness of the dummy gate; the first thickness being greater than the second thickness; etching the dummy gate by using a second etching process to remove the second thickness of the dummy gate; the second etching process being less corrosive to the barrier layer than the first etching process; and, the second etching process includes a gasification process, and the gasification process is used to convert the second thickness of the dummy gate into gaseous substances and escape.

[0005] In some embodiments of the present invention, the material of the dummy gate is polysilicon, and the etching of the dummy gate by using the second etching process includes: using a first sub-process to convert a part of the polysilicon of the second thickness of the dummy gate into silicon dioxide; using a second sub-process to react the silicon dioxide with the remaining part of the polysilicon of the second thickness of the dummy gate to generate silicon monoxide, and making the silicon monoxide escape in a gaseous form.

[0006] In some embodiments of the present invention, the first sub-process includes an oxidation process; the oxidation process includes one or more of a dry oxidation process, a wet oxidation process, and an in-situ steam generation process.

[0007] In some embodiments of the present invention, the first sub-process includes a wet cleaning process; the cleaning solution of the wet cleaning process includes an APM cleaning solution.

[0008] In some embodiments of the present invention, the thickness range of the polysilicon partially converted into silicon dioxide is 8 Å to 12 Å.

[0009] In some embodiments of the present invention, the second sub-process includes a rapid annealing process; the rapid annealing process includes a rapid annealing process under an inert atmosphere.

[0010] In some embodiments of the present invention, the first etching process includes one or more of a dry etching process and a wet etching process.

[0011] In some embodiments of the present invention, the second thickness is less than or equal to 100 Å.

[0012] In a second aspect, the present invention discloses a method for manufacturing a semiconductor device, including: forming a pseudo-gate structure on a substrate, and making the pseudo-gate structure include a high-k gate dielectric layer, a barrier layer, and a pseudo-gate electrode stacked in sequence on the substrate, and forming doping regions in the substrate on both sides of the pseudo-gate structure; forming an interlayer dielectric layer on the substrate, and making the interlayer dielectric layer fill between the pseudo-gate structures and expose the pseudo-gate electrode; etching the pseudo-gate electrode by using the etching method described in any one of the above; forming a metal work function layer and a metal gate electrode in sequence in the opening where the pseudo-gate electrode is etched away.

[0013] In a third aspect, the present invention discloses a semiconductor device manufactured by using the manufacturing method described above.

[0014] For the semiconductor device, etching method, and manufacturing method disclosed by the present invention, the first etching process is used to etch the pseudo-gate electrode to remove the pseudo-gate electrode with a first thickness and retain the pseudo-gate electrode with a second thickness, where the first thickness is greater than the second thickness. The second etching process is used to etch the pseudo-gate electrode with the second thickness to remove the pseudo-gate electrode with the second thickness. The second etching process includes a gasification process, and the gasification process is used to convert the pseudo-gate electrode with the second thickness into a gaseous substance and escape. Because the corrosion of the barrier layer by the second etching process such as the gasification process is less than the corrosion of the barrier layer by the first etching process such as the dry etching process or the wet etching process, the damage to the barrier layer caused by the etching of the pseudo-gate electrode can be reduced. Furthermore, the metal barrier ability of the barrier layer will not decrease significantly, and furthermore, the probability of the metal in the metal gate diffusing into the high-k gate dielectric layer can be reduced, and furthermore, the reliability of the semiconductor device can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the following will describe the drawings required to be used in the embodiments of the present invention or the background art.

[0016] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor device with a pseudo gate to be etched.

[0017] Figures 2 to 4 It is a schematic cross-sectional structure diagram of a semiconductor device in each step of replacing a pseudo gate with a metal gate by using a back-gate process.

[0018] Figure 5 It is a flowchart of an etching method for a semiconductor device disclosed in an embodiment of the present invention.

[0019] Figure 6 It is a schematic cross-sectional structure diagram of a semiconductor device to be etched disclosed in an embodiment of the present invention.

[0020] Figure 7 It is a schematic cross-sectional structure diagram of a semiconductor device for removing a pseudo gate with a first thickness disclosed in an embodiment of the present invention.

[0021] Figure 8 It is a schematic cross-sectional structure diagram of a semiconductor device for removing a pseudo gate with a second thickness disclosed in an embodiment of the present invention.

[0022] Figure 9 It is a schematic cross-sectional structure diagram of a semiconductor device after a first sub-process disclosed in an embodiment of the present invention.

[0023] Figure 10 It is a schematic cross-sectional structure diagram of a semiconductor device after a second sub-process disclosed in an embodiment of the present invention.

[0024] Figure 11 It is a flowchart of a manufacturing method for a semiconductor device disclosed in an embodiment of the present invention.

[0025] Figures 12 to 16 It is a schematic cross-sectional structure diagram of a semiconductor device in each step of manufacturing a semiconductor device by using a back-gate process. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0027] As described in the background art, replacing the conventional gate dielectric material with a high-k gate dielectric material and replacing the polysilicon gate with a metal gate can effectively reduce the leakage current and power consumption of semiconductor devices. However, because the metal gate is not resistant to high temperatures, in order to avoid the influence of high-temperature annealing during the source / drain region doping process on the performance of the metal gate, a post-gate process is usually used to form the metal gate. In the post-gate process, a polysilicon dummy gate is first formed on the substrate, then the source region and the drain region on both sides of the dummy gate are doped and subjected to high-temperature annealing, and then the dummy gate is replaced with a metal gate.

[0028] Hereinafter, taking a semiconductor device including a transistor as an example, the replacement process of the dummy gate and the metal gate will be described. As Figure 1 shown, the semiconductor device to etch the dummy gate includes a substrate 10, a dummy gate structure 11 on the substrate 10, and an interlayer dielectric layer 12. The interlayer dielectric layer 12 covers the dummy gate structure 11 and fills the gaps between the dummy gate structures 11. The substrate 10 on both sides of the dummy gate structure 11 has doping regions, etc. The dummy gate structure 11 includes a high-k gate dielectric layer 110, a barrier layer 111, and a dummy gate 112 that are sequentially stacked on the substrate 10.

[0029] As Figures 2 to 4 shown, first, a chemical mechanical polishing process is performed on the interlayer dielectric layer 10 to remove a part of the interlayer dielectric layer 10 and expose the dummy gate 112; then, the dummy gate 112 is etched and the etching is stopped at the top of the barrier layer 111; then, a metal work function layer 13 and a metal gate 14 are sequentially formed in the opening where the dummy gate 112 is removed.

[0030] The inventors have found that although silicon can be diffused from the polysilicon dummy gate 112 to the barrier layer 111 to improve the metal barrier ability of the barrier layer 111, using a conventional etching process such as a dry etching process or a wet etching process to etch the dummy gate 112 will cause damage to the barrier layer 111, resulting in a significant decrease in the metal barrier ability of the barrier layer 111, an increase in the probability of the metal in the metal gate 14 diffusing into the high-k gate dielectric layer 110, and a deterioration in the reliability of the semiconductor device.

[0031] Based on this, the present invention discloses an etching solution. First, a dry etching process or a wet etching process with a relatively large corrosiveness is used to remove most of the dummy gate 112, and then a gasification process with a relatively small corrosiveness is used to remove the remaining small part of the dummy gate 112, so as to reduce the damage of the etching of the dummy gate 112 to the barrier layer 111. Furthermore, the metal barrier ability of the barrier layer 111 will not decrease significantly, and furthermore, the probability of the metal in the metal gate 14 diffusing into the high-k gate dielectric layer 110 can be reduced, and furthermore, the reliability of the semiconductor device can be ensured.

[0032] As an alternative implementation of the disclosure of the present invention, embodiments of the present invention disclose an etching method for a semiconductor device, as Figure 5 shown, the etching method includes:

[0033] S101: Provide a semiconductor device to be etched, the semiconductor device including a substrate, a dummy gate structure on the substrate, and an interlayer dielectric layer, the dummy gate structure including a high-k gate dielectric layer, a barrier layer, and a dummy gate sequentially stacked on the substrate, doping regions existing on both sides of the dummy gate structure in the substrate, and the interlayer dielectric layer filling between the dummy gate structures and exposing the dummy gate.

[0034] In some embodiments of the present invention, as Figure 6 shown, the semiconductor device includes a substrate 10, a dummy gate structure 11 on the substrate 10, and an interlayer dielectric layer 12. Among them, the substrate 10 includes a first region 101, a second region 102, and a shallow trench isolation structure 103 between the first region 101 and the second region 102. The first region 101 is used to form PMOS transistors, the second region 102 is used to form NMOS transistors, and the shallow trench isolation structure 103 is used to isolate the first region 101 and the second region 102. Moreover, both the first region 101 and the second region 102 include a lightly doped region 1000, a heavily doped region 1001, a metal silicide layer 1002, etc. The dummy gate structure 11 includes a high-k gate dielectric layer 110, a barrier layer 111, and a dummy gate 112 sequentially stacked on the substrate 10. Sidewalls 113 are provided on the sidewalls of the dummy gate structure 11. The interlayer dielectric layer 12 fills between the dummy gate structures 11 and exposes the top of the dummy gate 112.

[0035] Among them, after forming the interlayer dielectric layer 12 that fills between the dummy gate structures 11 and covers the dummy gate structures 11, a chemical mechanical polishing process can be performed on the interlayer dielectric layer 12 to expose the dummy gate 112. In addition, a gate oxide layer 104, etc., may also exist between the substrate 10 and the dummy gate structure 11. And the material of the substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide, gallium nitride, aluminum nitride, indium nitride, indium phosphide, gallium arsenide, silicon germanium, sapphire, or silicon wafer, etc.; the shallow trench isolation structure 103 is a shallow trench structure filled with an insulating material such as silicon oxide; the material of the high-k gate dielectric layer 110 can be one or several of hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium oxynitride, zirconium oxynitridosilicate, hafnium silicate, hafnium oxynitridosilicate, lanthanum oxynitride hafnium, or hafnium aluminum oxide, etc.; the material of the barrier layer 111 can be titanium nitride, etc.; the material of the dummy gate 112 can be polysilicon, etc.; the material of the interlayer dielectric layer 12 can be silicon oxide, etc.; the sidewall 113 can be a stacked structure composed of silicon oxide and silicon nitride; the material of the gate oxide layer 104 can be silicon oxide, etc.

[0036] It should be noted that, in the embodiments of the present invention, only taking a semiconductor device including a PMOS transistor and an NMOS transistor as an example for illustration, and it is not limited thereto. In some other embodiments, the semiconductor device may further include a PMOS transistor, an NMOS transistor, a static random access memory, an image sensor, or a power device, etc., which will not be elaborated herein.

[0037] S102: Etch the dummy gate using a first etching process to remove the dummy gate with a first thickness and retain the dummy gate with a second thickness; wherein, the first thickness is greater than the second thickness.

[0038] In some embodiments of the present invention, as Figure 7 shown, after etching the dummy gate 112 using the first etching process, the dummy gate 112 with a first thickness D1 is removed, and the dummy gate 112 with a second thickness D2 is retained. Wherein, the first thickness D1 is greater than the second thickness D2. In some embodiments of the present invention, the second thickness D2 is less than or equal to 100 Å to ensure that the subsequent second etching process can completely remove the dummy gate 112.

[0039] Wherein, the first etching process includes one or more of a dry etching process and a wet etching process. Specifically, a photoresist layer may be first formed on the surface of the semiconductor device. After the photoresist layer is exposed and developed, the photoresist layer exposes the dummy gate 112, and then the dummy gate 112 is etched using an etching gas of the dry etching process or an etching solution of the wet etching process, etc.

[0040] S103: Etch the dummy gate with the second thickness using a second etching process to remove the dummy gate with the second thickness; wherein, the corrosiveness of the second etching process to the barrier layer is less than that of the first etching process to the barrier layer, and the second etching process includes a vaporization process, and the vaporization process is used to convert the dummy gate with the second thickness into a gaseous substance and escape.

[0041] In some embodiments of the present invention, as Figure 8 shown, the dummy gate 112 can be etched using the second etching process to remove the dummy gate 112 with the second thickness D2. Wherein, the corrosiveness of the second etching process to the barrier layer 111 is less than that of the first etching process to the barrier layer 111, and the second etching process includes a vaporization process, and the vaporization process is used to convert the dummy gate 112 with the second thickness D2 into a gaseous substance and escape.

[0042] Since the corrosion of the barrier layer 111 by the second etching process, such as the vaporization process, is less than that by the first etching process, such as the dry etching process or the wet etching process, the damage to the barrier layer 111 caused by the etching of the dummy gate 112 can be reduced. Furthermore, the metal barrier ability of the barrier layer 111 will not decrease significantly, and then the probability of metal in the metal gate diffusing into the high-k gate dielectric layer 110 can be reduced, thus ensuring the reliability of the semiconductor device.

[0043] Moreover, since the etching rate of the dummy gate 112 by the first etching process is greater than that by the second etching process, and the first thickness D1 is greater than the second thickness D2, the etching rate of the dummy gate 112 can be ensured not to decrease significantly, and then the fabrication efficiency of the semiconductor device can be ensured not to decrease significantly.

[0044] In some embodiments of the present invention, the material of the dummy gate 112 is polysilicon. As Figure 9 shown, a first sub-process can be used to convert part of the polysilicon of the dummy gate 112 with the second thickness D2 into silicon dioxide. As Figure 10 shown, a second sub-process is then used to react the silicon dioxide with the remaining polysilicon of the dummy gate 112 with the second thickness D2 to generate silicon monoxide, and the silicon monoxide escapes in a gaseous form, which can be expressed by the formula SiO2 + Si → SiO↑.

[0045] In some embodiments of the present invention, the first sub-process may include an oxidation process. Among them, the oxidation process may include one or more of a dry oxidation process, a wet oxidation process, or an in-situ steam generation (ISSG) process. In some embodiments, a dry oxidation process can be used to form silicon dioxide. Specifically, the semiconductor device can be placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced into the furnace tube so that part of the polysilicon of the dummy gate 112 reacts with oxygen at high temperature to form a dense silicon dioxide layer.

[0046] Of course, the present invention is not limited to this. In some other embodiments, the first sub-process may further include a wet cleaning process. The cleaning solution for the wet cleaning process includes an APM cleaning solution. The APM cleaning solution, also known as the SC1 cleaning solution, is a mixture of ammonium hydroxide, hydrogen peroxide, and deionized water. The APM cleaning solution can not only remove mild organic contamination and partial metal contamination on the surface of the dummy gate 112 with the second thickness D2, but also oxidize the polysilicon into silicon dioxide. Of course, the present invention is not limited to this. In some other embodiments, other processes can also be used to convert part of the polysilicon of the dummy gate 112 with the second thickness D2 into silicon dioxide, which will not be elaborated here.

[0047] In some embodiments of the present invention, the thickness range of the polysilicon converted into silicon dioxide is 8 Å to 12 Å. In some embodiments, the thickness of the polysilicon converted into silicon dioxide is about 10 Å. Based on this, silicon dioxide can fully react with the remaining polysilicon to generate silicon monoxide, so as to completely remove the dummy gate 112 with the second thickness D2.

[0048] In some embodiments of the present invention, the second sub-process may include a rapid annealing process, which includes a rapid annealing process in an inert atmosphere, and the inert atmosphere includes nitrogen or argon, etc. Among them, the annealing temperature and time of the rapid annealing process can be set according to requirements, which will not be elaborated here.

[0049] It should be noted that when the material of the dummy gate 112 is polysilicon, a gasification process including an oxidation process or a wet cleaning process and a rapid annealing process can be used to remove the dummy gate 112 with the second thickness D2. However, the present invention is not limited to this. When the material of the dummy gate 112 is not polysilicon, a gasification process including other sub-processes can be used to remove the dummy gate 112 with the second thickness D2.

[0050] As an optional implementation of the disclosed content of the present invention, embodiments of the present invention disclose a method for manufacturing a semiconductor device, as Figure 11 shown, the etching method includes:

[0051] S201: Form a dummy gate structure on the substrate, and make the dummy gate structure include a high-k gate dielectric layer, a barrier layer, and a dummy gate sequentially stacked on the substrate, and form doped regions on the substrate on both sides of the dummy gate structure.

[0052] In some embodiments of the present invention, the substrate 10 may be provided first, a hard mask including a silicon oxide layer and a silicon nitride layer may be formed on the substrate 10, and through a photolithography process, the hard mask has a plurality of openings, and the hard mask and a part of the substrate 10 at the opening positions are removed to form shallow trenches, and then an insulating material, etc. is filled in the shallow trenches to form a shallow trench isolation structure 103 as Figure 12 shown. Then, ion implantation is performed on the substrate 10 to form a first region 101 and a second region 102 with different doping types. Then, a gate oxide layer 104 is formed on the surface of the substrate 10, a high-k gate dielectric layer 110, a barrier layer 111, and a dummy gate 112 are sequentially formed on the surface of the substrate 10, and they are etched to form a dummy gate structure 11 as Figure 13 shown.

[0053] As Figure 14As shown, after forming the dummy gate structure 11, the substrate 10 on both sides of the dummy gate structure 11 is lightly doped to form the lightly doped regions 1000. Then, spacers 113 are formed on both sides of the dummy gate structure 11. Subsequently, the substrate 10 on both sides of the dummy gate structure 11 is heavily doped to form the heavily doped regions 1001, and the heavily doped regions 1001 are subjected to high-temperature annealing to activate them. Then, a metal silicide layer 1002 is formed on the heavily doped regions 1001 to improve the contact resistance of the conductive plugs formed on the source and drain subsequently.

[0054] S202: Form an interlayer dielectric layer on the substrate, such that the interlayer dielectric layer fills between the dummy gate structures and exposes the dummy gates.

[0055] As Figure 15 shown, an etch stop layer 20 and an interlayer dielectric layer 12 are formed on the substrate 10, and chemical mechanical polishing is performed on the interlayer dielectric layer 12 to expose the dummy gate 112.

[0056] S203: Etch the dummy gate using the etching method of any of the above embodiments.

[0057] As Figure 7 、 Figure 9 and Figure 10 shown, after first etching the dummy gate 112 using the first etching process, the dummy gate 112 with the first thickness D1 is removed, and the dummy gate 112 with the second thickness D2 is retained. Then, an oxidation process is used to convert a part of the polysilicon of the dummy gate 112 with the second thickness D2 into silicon dioxide. Then, a rapid annealing process is used to react the silicon dioxide with the remaining polysilicon of the dummy gate 112 with the second thickness D2 to generate silicon monoxide, and the silicon monoxide escapes in a gaseous form.

[0058] S204: Sequentially form a metal work function layer and a metal gate in the opening where the dummy gate is etched away.

[0059] As Figure 16 shown, a metal work function layer 13 and a metal gate 14 are sequentially formed in the opening where the dummy gate 112 is removed. Among them, the metal work function layer 13 includes one or more of tantalum nitride, titanium nitride, titanium aluminide, titanium aluminum nitride, tungsten nitride, etc. The metal gate 14 can be a metal material with good conductivity such as aluminum, tungsten, copper, or silver, and the metal gate 14 can include structures such as a single-layer metal, a multi-layer metal, or a stack of metal compounds. Of course, a source and a drain, etc. can also be formed on the substrate 10 subsequently, which will not be elaborated here.

[0060] As an optional implementation of the disclosure of the present invention, embodiments of the present invention disclose a semiconductor device, which is prepared by using the preparation method described in the above embodiments. In some embodiments of the present invention, as Figure 16As shown, the semiconductor device includes a substrate 10, a gate structure located on the substrate 10, and an interlayer dielectric layer 12. Among them, the gate structure includes a high-k gate dielectric layer 110, a barrier layer 111, a metal work function layer 13, and a metal gate 14 that are sequentially stacked on the substrate 10. Of course, the present invention is not limited thereto. In some other embodiments, the semiconductor device further includes a source electrode and a drain electrode, etc.

[0061] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0062] The above embodiments only represent several implementation manners of this specification. The description is relatively specific and detailed, but it cannot be understood as a limitation to the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several deformations and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. An etching method for a semiconductor device, characterized in that, Comprising: Providing a semiconductor device to be etched, the semiconductor device comprising a substrate, a pseudo-gate structure located on the substrate, and an interlayer dielectric layer, the pseudo-gate structure comprising a high-k gate dielectric layer, a barrier layer, and a pseudo-gate electrode stacked in sequence on the substrate, doping regions being provided on the substrate on both sides of the pseudo-gate structure, and the interlayer dielectric layer being filled between the pseudo-gate structures and exposing the pseudo-gate electrode; Etching the pseudo-gate electrode using a first etching process to remove a first thickness of the pseudo-gate electrode and retain a second thickness of the pseudo-gate electrode; The first thickness is greater than the second thickness; Etching the pseudo-gate electrode using a second etching process to remove the second thickness of the pseudo-gate electrode; The second etching process has less corrosiveness to the barrier layer than the first etching process has to the barrier layer; Wherein, the material of the pseudo-gate electrode is polysilicon; the etching of the pseudo-gate electrode using the second etching process comprises: using a first sub-process to convert a part of the polysilicon of the second thickness of the pseudo-gate electrode into silicon dioxide; using a second sub-process to react the silicon dioxide with the remaining part of the polysilicon of the second thickness of the pseudo-gate electrode to generate silicon monoxide and cause the silicon monoxide to escape in a gaseous form.

2. The etching method according to claim 1, wherein The first sub-process comprises an oxidation process; the oxidation process comprises one or more of a dry oxidation process, a wet oxidation process, and an in-situ steam generation process.

3. The etching method according to claim 1, wherein The first sub-process comprises a wet cleaning process; the cleaning liquid of the wet cleaning process comprises an APM cleaning liquid.

4. The etching method according to claim 1, wherein The thickness range of the part of the polysilicon converted into silicon dioxide is 8 Å to 12 Å.

5. The etching method according to claim 1, wherein The second sub-process comprises a rapid annealing process; the rapid annealing process comprises a rapid annealing process in an inert atmosphere.

6. The etching method according to claim 1, wherein The first etching process comprises one or more of a dry etching process and a wet etching process.

7. The etching method according to claim 1, characterized in that, The second thickness is less than or equal to 100 Å.

8. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a pseudo-gate structure on a substrate, and making the pseudo-gate structure comprise a high-k gate dielectric layer, a barrier layer, and a pseudo-gate electrode stacked in sequence on the substrate, and forming doping regions on the substrate on both sides of the pseudo-gate structure; Forming an interlayer dielectric layer on the substrate, and making the interlayer dielectric layer be filled between the pseudo-gate structures and expose the pseudo-gate electrode; Etching the pseudo-gate electrode using the etching method according to any one of claims 1 to 7; Sequentially forming a metal work function layer and a metal gate in the opening where the pseudo-gate electrode is etched away.

9. A semiconductor device, characterized in that, Prepared by the preparation method according to claim 8.

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