Chiplet Stacking Method on Wafer and Semiconductor Device

Abstract

The present invention provides a method for stacking die on a wafer and a semiconductor device. The method includes: Step S1, setting the wafer with the side having a circuit pattern structure facing down in a bonding device; Step S2, using a wafer suction device to adsorb the upper surface of the wafer from top to bottom, and placing the wafer with the side having a circuit pattern structure facing up into the bonding device; Step S3, performing bonding with the direction from bottom to top as the die-to-wafer bonding direction to complete the stacking of die on the wafer. By using the present invention, particulate contamination introduced by intermediate processes in the processing engineering (such as processes of cutting, picking up, flipping of chips, etc.) is avoided, thereby largely avoiding technical problems of reducing the bonding strength and causing bonding electrical failure.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and particularly relates to a method for stacking dies on a wafer and a semiconductor device. Background Art

[0002] One of the difficulties in die-to-wafer hybrid bonding lies in the control of contamination. Compared with the process of wafer-to-wafer hybrid bonding, since the process involves die cutting, picking, flipping, etc., and there are many moving operations, particulate contamination will inevitably be introduced. When these particles fall onto the bonding interface, it will cause problems such as a decrease in bonding strength and bonding electrical failure. Summary of the Invention

[0003] To this end, the present invention provides a method for stacking dies on a wafer, which includes: Step S1, setting the wafer with the side having the circuit pattern structure facing down in a bonding device; Step S2, using a die suction device to adsorb the upper surface of the die from top to bottom, and placing the die with the side having the circuit pattern structure facing up into the bonding device; Step S3, performing bonding in the direction from bottom to top as the die-to-wafer bonding direction to complete the stacking of dies on the wafer.

[0004] In addition, preferably, in the method for stacking dies on a wafer of the present invention, in Step S3, it further includes: preheating the die and the wafer bonded to the die by using the heating functional component of the bonding device before bonding.

[0005] In addition, preferably, in the method for stacking dies on a wafer of the present invention, in Step S3, it further includes: heating the back surface of the die while aligning and bonding the die with the wafer.

[0006] In addition, preferably, in the method for stacking dies on a wafer of the present invention, in Step S3, it further includes: using a chuck adsorbed on the back surface of the wafer to heat the wafer under the conditions of 10 s - 180 s and 80°C - 150°C to achieve heating only at the die bonding position.

[0007] In addition, preferably, in the method for stacking dies on a wafer of the present invention, in Step S3, it further includes: depositing a specific band heat-absorbing material of 50 Å - 10000 Å on the bonding interface.

[0008] In addition, preferably, in the method for stacking dies on a wafer of the present invention, the specific band heat-absorbing material is TiN or amorphous silicon.

[0009] In addition, preferably, in the method for stacking die on a wafer of the present invention, after the bonding is completed, the positions of the wafer and the chip are flipped by 180°, and high-temperature annealing is performed at 300°C - 500°C for an annealing time of 30 min - 180 min.

[0010] In addition, the present invention also provides a semiconductor device, which is generated by obtaining die on a wafer using the method for stacking die on a wafer according to any one of the above, and completing wafer-level stacking through a hybrid bonding process.

[0011] By using the present invention, particulate contamination introduced by intermediate processes in the processing engineering (such as die dicing, pick-up, flipping, etc.) is avoided, thereby largely avoiding the technical problems of reducing the bonding strength and causing bonding electrical failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flowchart showing a method for stacking die on a wafer according to an embodiment of the present invention.

[0013] Figure 2 is a schematic diagram showing the structure of a Bernoulli non-contact pick-up device according to an embodiment of the present invention.

[0014] Figure 3 is a schematic diagram showing the process flow of wafer-to-wafer hybrid bonding according to an embodiment of the present invention.

[0015] Figure 4 is a schematic diagram showing the process flow of wafer-to-wafer hybrid bonding according to an embodiment of the present invention.

[0016] Figure 5 is a schematic diagram showing the machine table air flow system according to an embodiment of the present invention.

[0017] Figure 6 is a schematic diagram showing the heating structure in a bonding device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Other embodiments or variant examples obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts all fall within the scope of protection of the present application.

[0019] Figure 1 is a flowchart showing a method for stacking die on a wafer according to an embodiment of the present invention.

[0020] One of the difficulties in die to wafer hybrid bonding lies in the control of contamination. Compared with the process of wafer to wafer hybrid bonding, since processes such as die cutting, picking, and flipping are involved in the middle, and there are many moving operations, particulate contamination will inevitably be introduced. When these particles fall on the bonding interface, it will cause problems such as a decrease in bonding strength and bonding electrical failure. Therefore, the control of the cleanliness of the surface bonding of the die and the wafer is crucial.

[0021] Currently, the cleanliness of the die and the wafer during bonding is mainly controlled through the following aspects:

[0022] 1. Die cutting: Laser cutting will have a great thermal effect, which is likely to cause the recast phenomenon on the edge of the cut die, resulting in a change in the bonding surface topography; mechanical cutting will generate a large amount of particles and cause greater contamination; therefore, currently, plasma etching is used to cut the die using the plasma etching process in the front-end Fab, minimizing the particulate contamination introduced during the die cutting process; both recast and particulate contamination will cause bubble defects to appear at the bonding interface.

[0023] 2. Die picking: Upgrade the original contact die picking device to a non-contact Bernoulli picking device, thus avoiding the contamination caused by the contact between the equipment and the die; the Bernoulli non-contact picking device is as Figure 1 shown.

[0024] 3. Other aspects: Include the optimization of the environment of moving parts and the entire chamber interior to ensure that no additional particulate contamination is introduced during the bonding process due to the movement of these mechanical structures; optimize the cleaning process formula or process flow of the die and wafer surfaces to improve the cleanliness of their surfaces.

[0025] Through the above process optimization, the cleanliness of the material surface is improved, thus ensuring the final bonding effect.

[0026] Although the current solution optimizes the cleanliness of die to wafer hybrid bonding from several aspects, there are still the following problems:

[0027] 1. During the bonding process, since the wafer is below and facing up, and the chip is picked up with the front side up. Therefore, after picking up the chip, the placement device is located on the back side of the chip. After the placement device sucks up the chip, we need to flip the chip so that the front side is down and bond it to the wafer to complete the process of placing the chip. This step involves the flip chip bonding process of the chip and the mechanical structure that holds and flips the chip. Since the mechanical rotation inevitably generates particle contamination, it has a great impact on the bonding interface of the chip and the wafer and the cleanliness inside the cavity.

[0028] 2. The bonding efficiency of the wafer-to-wafer hybrid bonding machine is relatively low. It usually takes dozens of minutes to complete the bonding of one wafer (the wafer in the wafer-to-wafer hybrid bonding). During this process, the robotic arm constantly picks up dielets and bonds them to the wafer above. Such moving parts generate a large number of particles. Coupled with the action of gravity, many particles will fall onto the wafer, thus causing contamination to the wafer. More seriously, there are also corresponding gaps between the bonded dielets. There is also circuit design at these gaps, which is prepared for subsequent electrical testing. During the entire bonding process, the circuit at this position will always be exposed, and there is always a risk of being contaminated by falling particles. In addition, the area of the wafer is very large, and the probability of being contaminated due to falling particles is also very high.

[0029] Figure 2 It is a schematic diagram showing the structure of the Bernoulli non-contact pick-up device in an embodiment of the present invention.

[0030] Regarding the die (also known as chip die), the current technical solutions mainly ensure the cleanliness of the die by controlling the number of particles on the die and the particles introduced by the machine flipping device.

[0031] Regarding the wafer, currently, the cleanliness inside the bonding cavity is mainly ensured to reduce the number of particles falling on the wafer and control the cleanliness of the wafer. At the same time, the exposure time of the wafer during the entire bonding process is minimized, usually achieved by accelerating the bonding rate, etc., to ensure the cleanliness of the wafer.

[0032] However, the above methods can only improve the contamination problem and cannot fundamentally solve the problem.

[0033] In the present invention, the wafer-to-wafer hybrid bonding machine is divided into two parts, one part is the equipment related to the die, and the other part is the equipment related to the wafer.

[0034] The equipment for wafers mainly consists of two parts: picking and placing. The picking device is responsible for picking up the wafers from the dicing tape; the placing device adsorbs the wafers from the back, flips them together with the wafers, and bonds them to the wafer. In this way, one wafer bonding is completed. Next, repeat the above steps to bond the wafers to the wafer one by one; The equipment for the wafer mainly consists of a chuck, which holds the wafer to complete the hybrid bonding of the wafer to the wafer. The machine position is that the wafer is located above with the front side facing down, and the wafer is located below with the front side facing up. The schematic diagram is as Figure 3 shown.

[0035] The present invention exchanges the relative positions of the original conventional equipment for wafers and wafers, with the wafer located below with the front side facing up and the wafer located above with the front side facing down. After the chip is picked up, the placing device directly picks it up from the back of the chip without the need for a flipping process, and bonds the wafer face-to-face with the wafer above from bottom to top. The schematic diagram is as Figure 4 shown.

[0036] The advantages of the present invention are elaborated from the following two aspects: the flip-chip flipping of the die and the contamination caused by the gravity-induced dropping of the particles

[0037] 1. Flip-chip flipping of the die: The die is obtained by dicing the chip. The dicing process of the die is as follows: a whole wafer is fixed on the dicing tape. After dicing, the film expansion process is carried out to obtain individual separated dice. At this time, the front circuit structure of the die faces upward. Therefore, in the original position where the wafer is below and the circuit structure is upward, the die flipping process is necessarily involved. In the flipping process, the mechanical structure involves more movements, and more particles will be generated, which will cause greater contamination to the chip, wafer structure, and chamber environment. This invention places the wafer above with the circuit structure facing down, fundamentally avoiding the flipping process, thereby reducing the contamination brought by this process.

[0038] 2. Particles fall under the influence of gravity: Wafer-to-wafer hybrid bonding requires aligning each wafer with the wafer one by one in the bonding process. The process time for aligning and bonding each wafer is relatively long. Usually, it takes dozens of minutes or even several hours to complete the bonding of all wafers on each wafer. During this process, since the wafer is facing up, the probability of particle falling is relatively high, which will contaminate the surface of the wafer and thus affect the bonding effect. At the same time, there are gaps between the wafers bonded to the wafer. There is also circuit design in this part. The circuits in this part are exposed in the cavity from the start to the end of the bonding and have a long standing time. The possibility of contamination caused by particle falling is even greater. At the same time, due to the large aspect ratio of the gap here, it is very difficult to clean the particle contamination completely, and abnormalities are likely to occur in this part of the circuit subsequently. In addition, during the original bonding process, the device for the wafer needs to repeatedly perform mechanical movement operations such as alignment and bonding above the wafer for piece-by-piece wafer-to-wafer bonding. During this process, a large amount of particle contamination will be generated. Under the action of gravity, it is easier to contaminate the surface of the wafer. In this invention, since the wafer is located above and facing down, particles will not fall on the wafer due to the action of gravity, thus minimizing the contamination of the wafer by particles to the greatest extent.

[0039] The way to reduce contamination in this invention can be to build an air flow system from top to bottom, blowing air from above and returning air from below, so as to better ensure that particles do not fall on the wafer. At the same time, since the wafer is blocked by the wafer, it will not be contaminated by particles affected by gravity either. The schematic diagram of the air flow system is as Figure 5 shown.

[0040] This invention is not limited to being applied to the process flow of wafer-to-wafer hybrid bonding. It can also be applied to optimization schemes for bonding equipment in other aspects such as chip-to-wafer and substrate, so as to reduce the contamination caused by chip flipping and particle falling under the influence of gravity.

[0041] In addition, after the wafer and the wafer are aligned, it is only pre-bonded, and there are not enough covalent bond connections between the dielectric film layers at the bonding interface, so the bonding strength is very weak. At this time, the back of the wafer has no support, and our bonding device will leave after bonding to perform the alignment and bonding process of the next wafer. The just-bonded wafer will be affected by gravity and may experience displacement or even fall. Therefore, we can make the following improvements:

[0042] We can integrate a heating function on the bonding device. While aligning and bonding, we also heat the back of the chip, which can increase some dangling bonds, enhance its bonding strength, and prevent it from experiencing displacement and falling.

[0043] We can also heat the wafer through a chuck behind the wafer. However, we need to precisely control the heating area and only heat the chip bonding positions on the wafer each time. If the entire wafer is heated each time, the wafer will be repeatedly heated, consuming a large amount of the wafer's thermal budget and affecting the chip's performance. We can design the electrostatic chuck (E Chuck) of the wafer accordingly. For example, multiple heating coils are equipped in different areas to achieve zonal heating. The schematic diagram is shown in Figure 6 as shown in (a) of

[0044] We can also deposit a material with good heat absorption for a certain wavelength band on the bonding interface. For example, we can deposit a certain thickness of TiN. TiN has obvious light absorption in the green wavelength band and generates heat, while other common semiconductor materials do not absorb light in this wavelength band and thus do not absorb heat. When heating the chip or wafer, we use green light. Therefore, we can deposit a certain thickness of film layer and then heat it by irradiating light with a specific wavelength to achieve precise heating of the bonding interface. The special film layer should be as close to the bonding interface as possible. However, to ensure the bonding effect, the introduced special film layer cannot be the bonding interface and only serves as a heating function. The schematic diagram is shown in Figure 6 as shown in (b) of

[0045] Since the bonding force mainly depends on the part of the dielectric layer at the bonding interface (because the area occupied by Cu is less than 10% and it mainly plays a role in electrical connection), annealing after bonding has two functions: the -OH active groups generated by the water coated on the surface react with the dangling bonds at the bonding interface to form Si-OH, and heating promotes the hydrophilic bonding reaction Si-OH + HO-Si → Si-O-Si + H2O during bonding, thereby enhancing the bonding strength. A temperature of 80°C - 150°C is sufficient here; the metal Cu grains expand when heated, and the copper on both sides comes into contact with each other to form electrical connection. Here, the internal stress of the metal is also pre-released to make the metal expand in advance to prevent the copper from continuing to expand and damaging the holes during subsequent thermal processes. The subsequent process temperature varies according to the process and is up to 350°C - 450°C at most. Therefore, to meet this requirement, the temperature needs to be 350°C - 450°C and cannot be lower than the subsequent process temperature to prevent the copper from continuing to expand and damaging the structure at a higher subsequent temperature. Therefore, the purpose of this step is to enhance the bonding strength rather than for electrical connection, so the temperature can be controlled at 80°C - 150°C, or even lower, as long as it can ensure that the chiplets do not move or fall off. After each chip is bonded to the wafer, a unified annealing is performed. In addition to enabling the expansion of the copper grains to achieve electrical connection, it can also further enhance the bonding strength.

[0046] In summary, the process features of the present invention are as follows:

[0047] (1) The overall process flow is as follows: Repeatedly perform bonding one by one at low temperature (80°C - 150°C). After all Dies are bonded, then perform a single high-temperature annealing step to complete the entire process.

[0048] (2) For each low-temperature heating step, only the area corresponding to the die bonding is heated for the wafer. Since there are Scribe Lanes isolating Dies from each other on the wafer, it will not be transferred to other positions of the wafer.

[0049] (3) During the low-temperature bonding process, the bonding device does not move away, and a certain pressure is applied to the chip to keep the positions of the chip and the wafer unchanged.

[0050] (4) For the final annealing, the chip and the wafer are flipped over, with the wafer below and the chip above. Such a relative position is more stable.

[0051] Therefore, in the present invention, the relative positions of the original wafer and the wafer are swapped up and down. The wafer is located above with the front circuit structure facing down; the wafer is located below with the front circuit structure facing up. The placement device realizes face-to-face bonding from the wafer to the wafer from bottom to top. Its advantages are as follows:

[0052] 1. After the die is picked up for bonding in this way, it does not need to be flipped, and face-to-face bonding with the wafer can be directly completed from bottom to top, avoiding particle contamination caused by die flipping.

[0053] 2. In this way, the circuit structure on the front of the wafer located above faces down, and particles will not fall on the wafer due to gravity like the existing machine structure (especially inside the gaps between the bonded wafers, which are difficult to remove), thus causing particle contamination.

[0054] In summary, this solution can be applied to chip-to-wafer hybrid bonding and other chip-to-panel packaging processes, eliminating the particle contamination introduced by the flip-chip process and avoiding the contamination caused by particles falling on the wafer and panel due to gravity, greatly improving the cleanliness of the overall process flow to meet the final packaging effect.

[0055] Advantages of the present invention:

[0056] 1. The overall orientation of bonding,

[0057] It should be noted that in this article, relational terms such as first and second, etc. The circuit structure of the wafer faces up and is located below; the circuit structure of the wafer faces down and is located above;

[0058] 2. The wafer suction device sucks the wafer from above, and then the bonding device is located on the back of the wafer, positioned below the wafer.

[0059] 3. The wafer-to-wafer bonding direction is from bottom to top.

[0060] 4. There is no flipping action of the wafer in the entire picking and bonding process flow.

[0061] 5. During the bonding process, it is necessary to pre-heat the chip and the wafer bonded to the chip to provide a certain bonding strength. At this time, the bonding device also provides a certain pressure. After the low-temperature heating is completed, the bonding device is withdrawn. When heating the wafer, only the Die part of the wafer bonded to the chip needs to be heated. Here, it is low-temperature heating (80°C - 150°C). Heating can be carried out by direct contact heating or by depositing a special film layer and irradiating with light of a special wavelength in a non-contact heating manner. After each chip is bonded to the wafer, we then flip the positions of the wafer and the chip so that the chip is on top and the wafer is below, and perform a unified annealing. The temperature is high-temperature annealing at 350°C - 450°C.

[0062] The terms are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0063] Each embodiment in this specification is described in a related manner. The same or similar parts between each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments.

[0064] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

[0065] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the claims of the present invention.

Claims

1. A method for stacking chips on a wafer, characterized in that: include: Step S1, placing the wafer in a bonding device with the side having the circuit pattern structure facing downward; Step S2, using a wafer suction device to suck the upper surface of the wafer from top to bottom, and placing the wafer into the bonding device with the side having the circuit pattern structure facing upward; Step S3, bonding is performed from bottom to top as the wafer-to-wafer bonding direction to complete the stacking of the core particles on the wafer, wherein: The step S3 includes: using the heating function component of the bonding device to pre-heat the chip where the chip is located and the wafer bonded to the chip before bonding, heating the back of the chip while aligning the chip and the wafer for bonding, and using a suction cup adsorbed on the back of the wafer to heat the wafer under conditions of 80°C-150°C for 10s-180s to achieve heating of only the chip bonding position.

2. The method for stacking chips on a wafer according to claim 1, characterized in that: The step S3 also includes: depositing a heat absorbing material of a specific wavelength range of 50A-10000A on the bonding interface, Wherein, the specific band heat absorption material is TiN or amorphous silicon.

3. The method for stacking chips on a wafer according to claim 1, characterized in that: After the bonding is completed, the positions of the wafer and the chip are flipped 180°, and high-temperature annealing is performed at 300° C.-500° C. for 30 min-180 min.

4. A semiconductor device, characterized in that: The semiconductor device is produced by obtaining the chip-on-wafer stacking method according to any one of claims 1 to 3 and completing wafer-level stacking through a hybrid bonding process.

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