Chip with top metal bonding pad spacing adjustment function

Abstract

Methods, systems, and apparatus are described for packages with top metal pad pitch adjustment. A first portion of the integrated circuit (e.g., including transistors and other devices) may have a first pitch associated with the internal connections. The first pitch may not be aligned with a desired pitch of the external connectors. Thus, a set of masks may be used to add a second portion of the integrated circuit (e.g., metal wiring) to the integrated circuit such that the integrated circuit obtains a second pitch different from the first pitch. The first portion of the integrated circuit may be consistent over one or more integrated circuits, while the second portion of the integrated circuit may be customized for desired external connections associated with the integrated circuit.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 539,327, filed on September 19, 2023, and the entire contents of that application are incorporated herein in their entirety for all purposes. Background Art

[0002] The chip must meet certain spacing requirements between its external contacts so that the chip is compatible with external systems, such as connectors on a printed circuit board to which the chip will be attached. In a typical system, the spacing of the chip's external contacts is too small for the external system to which it is connected; therefore, a substrate is placed between the chip's external contacts and the external system. The substrate has a set of contacts that is compatible with the chip, another set of contacts that is compatible with the external system, and a set of wires that connect the two sets of contacts.

[0003] When the pitch of the chip's external contacts is too small for the substrate to which it is attached, an interposer system may be introduced, such as an interposer having: a set of contacts compatible with the chip, another set of contacts compatible with the substrate, and a set of wires connecting the two sets of contacts.

[0004] Chiplets are small integrated circuits whose packages can have finer pitches than those of more traditional chips. The fine pitch of chiplets means that in addition to the substrate, they often require an interposer to interface with other external systems. This adds complexity to some packaging and assembly construction and can affect yields. Summary of the invention

[0005] The present invention relates to integrated circuit chips and packages with on-chip top metal pad spacing adjustment. Related methods are also disclosed. The spacing adjustment of the top metal pads can be formed by top metal wiring in the integrated circuit, which routes internal connectors to external chip connectors. The internal connectors can be pads in the metal layer of the integrated circuit. The external chip connectors can be pads, solder balls, bumps, pillars, leads or other conductive connectors. The internal connectors can have a finer pitch than the external chip connectors. The top metal wiring in the integrated circuit may be different between one production process of the chip and the next production process. Changes in the top metal wiring may affect the connection between the internal connectors and the external connectors, so that the same chip can be connected to a packaging substrate or interposer with different spacings. For example, one change in the top metal wiring can make each internal connector connected to an external connector with a first spacing, while a second change makes every other internal connector connected to an external connector with a spacing of twice the width. The top metal wiring can be defined by different mask sets, where different sets are selected as part of different production processes of the integrated circuit back-end process. The top metal wiring can be different on a single integrated circuit. Continuing with the above example, another variation could have each internal connector on one side of the chip connected to an external connector having a first pitch, while all other sides of the chip connected to external connectors having a pitch of twice the width.

[0006] A method for packaging an integrated circuit is disclosed herein. The method includes: forming a group of devices of the integrated circuit; forming a group of internal connectors of the integrated circuit connected to the group of devices of the integrated circuit; selecting a group of masks from a mask set library; using the group of masks to form a group of metal wiring layers of the integrated circuit; and connecting a group of external connectors of the integrated circuit to the group of internal connectors via the metal wiring layers; wherein: (i) multiple groups of masks in the mask set library are configured to form different groups of metal wiring layers; and (ii) different groups of metal wiring layers differ in the way in which the internal connectors of the integrated circuit are connected to the external connectors of the integrated circuit.

[0007] An integrated circuit is disclosed herein. The integrated circuit includes: a group of devices; a group of internal connections connected to the group of devices and having a first pitch, wherein the group of internal connections is a group of metal layer pads; a group of external connections connected to the group of internal connections and having a second pitch; and a group of metal wiring layers of the integrated circuit, wherein the group of internal connections is connected to the group of external connections; wherein a subcomponent of the group of internal connections is not connected to the group of external connections.

[0008] A method is disclosed herein. The method includes: forming a first set of devices of a first integrated circuit; forming a first set of internal connections of the first integrated circuit connected to the first set of devices of the first integrated circuit; selecting a first set of masks from a mask set library based at least in part on a first set of external connections; forming a first set of metal wiring layers of the first integrated circuit using the first set of masks; forming a second set of devices of a second integrated circuit, wherein the second set of devices has a configuration identical to that of the first set of devices; forming a second set of internal connections of the second integrated circuit connected to the second set of devices of the second integrated circuit; selecting a second set of masks from the mask set library based at least in part on a second set of external connections, wherein the second set of masks is different from the first set of masks, and the configuration of the second set of external connections is different from the configuration of the first set of external connections; and forming a second set of metal wiring layers of the second integrated circuit using the second set of masks, wherein the configuration of the second integrated circuit is different from the configuration of the first set of metal wiring layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings illustrate multiple embodiments of systems, methods, and multiple other aspects of the present invention. It will be appreciated by those skilled in the art that the element boundaries (e.g., boxes, box groups, or other shapes) shown in the figures represent an example of boundaries. In some examples, an element may be designed as multiple elements, or multiple elements may be designed as one element. In some examples, an element shown as an internal component of an element may be implemented as an external component in another element, and vice versa. In addition, these elements may not be drawn to scale. A non-restrictive and non-exhaustive description is described with reference to the following figures. The components in the figures are not necessarily drawn to scale, but emphasize the explanation principle.

[0010] Figure 1A and 1B According to certain embodiments of the invention disclosed herein, an integrated circuit is provided; Figure 2 A cross section of an integrated circuit on a substrate according to certain embodiments of the invention disclosed herein is provided; Figures 3 to 6 Provides a conceptual diagram of changing the spacing according to certain embodiments of the invention disclosed herein; Fig. 7A and 7B Intellectual property (IP) blocks according to certain embodiments of the invention disclosed herein are provided; Figure 8 Provided are die-to-die (D2D) connections according to certain embodiments of the invention disclosed herein; Fig. 9 and Fig.10 A method of packaging an integrated circuit according to certain embodiments of the invention disclosed herein is provided. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to implementations and examples of various aspects and variations of the systems and methods described herein. Although several exemplary variations of the systems and methods are described herein, other variations of the systems and methods may include aspects of the systems and methods described herein, combined in any suitable manner, with all or some of the described aspects combined.

[0012] Based on the above overview, an integrated circuit package with top metal pad spacing adjustment and related methods are disclosed in detail herein. The methods and systems disclosed herein are non-limiting embodiments of the present invention, are used for explanation purposes only, and should not be used to limit the full scope of the present invention. It should be understood that the disclosed embodiments may overlap with each other or may not overlap. Therefore, a portion of an embodiment or a specific embodiment thereof may or may not fall within the scope of another or a specific embodiment thereof, and vice versa. Different embodiments from different aspects may be implemented together or separately. Many different combinations and sub-combinations of the representative embodiments shown within the broad framework of the present invention may be obvious to those skilled in the art, but are not explicitly shown or described and should not be interpreted in an exclusive manner.

[0013] Figure 1 depicts a packaged integrated circuit. The packaged integrated circuit may be a die or a conventional chip. Figure 1A View 100-a1 of FIG. 100 includes a chip 101-a. View 100-a1 provides a top view of the packaged integrated circuit, while view 100-a2 is a side cross-sectional view of the packaged integrated circuit. The single chip 101-a is connected to an external system.

[0014] Figure 1B The view 100-b1 of FIG. 1 includes two core particles 101-b1 and 101-b2. The view 100-b1 is a top view of the packaged integrated circuit, and the view 100-b2 is a side cross-sectional view of the packaged integrated circuit. Figure 1B In FIG. 1 , two chiplets 101 - b 1 and 101 - b 2 are connected to the same external system as chip 101 - a through interposer 160 . The chiplets may be connected to (eg, may communicate with) each other via a die-to-die (D2D) connection 103 .

[0015] The external system or substrate 105 has a plurality of connectors 110 (e.g., copper pillar bump connectors) that are spaced apart from one another at a pitch 115. In some examples, the pitch 115 may be 110 microns. The chip 101-a has a plurality of external connectors 120 that are spaced apart from one another at a pitch 123. The core 101-b has a plurality of external connectors 125 (e.g., bump connectors). In some examples, the pitch 130 associated with the connectors 125 may be 55 microns. The interposer 160 has a plurality of connectors 135 that are spaced apart from one another at a pitch 140. In some examples, the pitch 140 may range between the pitch 130 (e.g., 55 microns) and the pitch 115 (e.g., 110 microns).

[0016] External connectors 120 may be coupled to external connectors 110 via conductors 145 (eg, metal wiring fabricated monolithically with internal connectors). In some examples, only a subset of internal connectors 120 may be coupled to a subset of external connectors 110.

[0017] External connector 125 may be coupled to connector 135 via conductor 150 (e.g., metal wiring fabricated monolithically with the internal connector). In some examples, only a subassembly of internal connector 125 may be coupled to a subassembly of connector 135. Connector 135 may be coupled to external connector 110 via conductor 155 (e.g., metal wiring fabricated monolithically with the internal connector). In some examples, only a subassembly of connector 135 may be coupled to a subassembly of external connector 110.

[0018] These external connections can be external contacts such as pads, solder balls, bumps, pillars, leads, or other conductive connections. As part of the integrated circuit packaging process, Figure 1A and Figure 1B The integrated circuits in the can be connected to one or more substrates. As part of the integrated circuit packaging process, these integrated circuits can be connected to the substrate along with other chips or die. The substrate can be an organic substrate. Substrate 105 can be a substrate of various packaging types. As part of the integrated circuit packaging process, these integrated circuits can be connected to an interposer. An interposer (such as interposer 160) can include multiple chips and auxiliary devices, which are connected to external systems and other devices on the interposer.

[0019] Figure 1A and Figure 1BAn integrated circuit in a chip may have multiple sets of internal connectors at different pitches. For example, two die may have similar basic circuits, but have different pitches of their external connectors. This may be referred to as the die-to-die pitch of the die. Different die-to-die pitches may be manufactured for similar die to meet different packaging constraints.

[0020] Some core particles require a large number of independent connectors between core particles. For example, the illustrated core particle 101-b may be a computing core particle that is constructed to perform parallel processing with other core particles to perform complex calculations. Core particle 101-b may include a large number of external connectors on the bottom side of core particle 101-b. However, since the communication speed between integrated circuits, especially the communication speed between core particles that perform parallel processing of complex calculations, is very important, core particle 101-b may be designed to have a large number of direct contacts on at least one side of the core particle and between adjacent core particles. One side of the core particle that includes this requirement may be referred to as a D2D interface and will provide multiple contacts for D2D connector 103.

[0021] According to certain embodiments of the present invention, the core particles and integrated circuits may generally have the same internal connectors and different external connector spacings. For example, in some examples, the core particles may have a spacing for their internal connectors (e.g., 65 microns). Then, for external connectors using a first top-level metal wiring pattern, the spacing may remain at 65 microns, or the spacing may be increased (e.g., to 130 microns) for external connectors using a second top-level metal wiring pattern that connects only one of each other internal connector to an external connector. For example, core particle 101-a may be substantially the same as core particle 101-b, except that core particle 101-a has different metal wiring layers between the internal connectors and the external connectors to the chip base layer. Therefore, core particle 101-b can be used in applications that require high density external connectors in a D2D interface. This same core particle can also be used as core particle 101-a with a simpler external system that does not require as many connections.

[0022] In a particular embodiment of the present invention, a method for packaging an integrated circuit 100 is provided. The method includes forming a group of devices for the integrated circuit. These devices may be passive devices or active devices, such as logic transistors used in a processor or capacitors or resistors used in analog circuits. The method may also include forming a group of internal connectors of the integrated circuit, the group of internal connectors being connected to the group of devices of the integrated circuit. The group of internal connectors may be pads of conductive material formed in a layer above the devices of the integrated circuit. The group of internal connectors may be connected to the devices through vias connected to highly doped regions of semiconductor material of the integrated circuit. The method may also include selecting a group of masks from a mask set library. The group of masks may define a top-level wiring pattern to be formed on the integrated circuit. The mask sets in the mask set library may be configured to form different groups of metal wiring layers. The mask set library may be configured to allow a designer to modify the integrated circuit during back-end processing to allow the integrated circuit to interoperate with packages having different configurations of external connectors for the integrated circuit. These different configurations may be set by wiring patterns of top-level metals. The method may continue to form a group of metal wiring layers for the integrated circuit using the group of masks. Different sets of metal wiring layers may differ in the manner in which they connect internal connectors of the integrated circuit 100 to external connectors of the integrated circuit 100. The set of metal wiring layers may vary the spacing between the internal connectors so that the device may interface with packages having different spacing between external connectors. The method may continue by coupling a set of external connectors of the integrated circuit 100 to the set of internal connectors via the metal wiring layers.

[0023] In a particular embodiment of the invention, the set of metal wiring layers causes subcomponents of the set of internal connectors to be uncoupled from the set of external connectors. The internal connectors can still be connected to internal circuit elements, but from the perspective of the external connectors, the pads are floating to which the external connectors would otherwise be connected. In these same embodiments, different sets of metal wiring layers applied to the same underlying integrated circuit 100 can use all of the internal connectors and couple them all to a set of external connectors. Thus, different sets of metal wiring layers that can be used with a given integrated circuit 100 and associated with different mask sets can differ in how many of the internal connectors in the set of internal connectors are uncoupled from the set of external connectors.

[0024] By changing the mask used to form conductors (e.g., metal wires) between internal and external connectors, the die can be more easily adapted to different packaging requirements. For example, the main circuit (e.g., including devices such as transistors) can be maintained while only the top layer of the die is adjusted for packaging purposes. Different wire stacks can be used. Post-tapeout changes can be achieved. Top layer changes can be relatively low cost and can reduce inventory to final processing time compared to traditional methods. Selecting masks for metal wiring based on packaging requirements enables a configurable package design.

[0025] Figure 2 A packaged device 200 is shown in the form of a core particle 205 disposed on a substrate 210. The substrate 210 may be an organic substrate. The substrate 210 may be a substrate of a package. The core particle 205 has a plurality of external connectors 215 that are spaced apart from each other by a spacing 220. In some examples, the spacing 220 may be 130 microns. The substrate 210 may include a plurality of connectors 225 that are spaced apart from each other by a spacing 230. The spacing 230 may be different from the spacing 220. The core particle 205 may be connected to the substrate 210 via a plurality of solder balls that cover the bottom surface of the core particle and have a spacing 220 of 130 microns. Shown here is one embodiment of how the core particle is connected to a substrate (e.g., an organic substrate). There are alternative methods of connecting the core particle to the substrate using different spacings or different connector types.

[0026] In a particular embodiment of the invention, the package device 200 may include internal connectors 215 of the integrated circuit, which are connected to a group of devices of the integrated circuit. The group of devices may be logic transistors. For example, in the case where the integrated circuit 200 is a processor, these devices may form a computing unit of the processor. These internal connectors may be pads in the integrated circuit within the core 205. For example, they may be flat metal areas that are formed to contact higher metal layers through vias or other conductive connectors during the manufacturing process of the integrated circuit.

[0027] These internal connectors (e.g., in an integrated circuit located within core particle 205) can have a variety of different configurations. For example, these internal connectors (e.g., connector 215) can be formed along the periphery of the integrated circuit in a band that frames the integrated circuit. Alternatively, these internal connectors can be found on the entire top surface or bottom surface of the integrated circuit. In the case where these internal connectors are formed on the bottom surface of the integrated circuit by a semiconductor, vias can be used to connect these devices to these internal connectors. The internal connectors (e.g., connector 215) can have a spacing (e.g., spacing 220) that is set according to the processing requirements of the integrated circuit and the size of the internal connectors required for the metal wiring layer disclosed herein. The spacing of the internal connectors can be referred to as the first spacing of the overall structure of the packaging device 200. The internal connectors can be arranged on one or more layers of the integrated circuit within the core particle 205 in a regular rectangular array, a checkerboard, or other pattern.

[0028] In a particular embodiment of the present invention, the integrated circuit may include a plurality of external connectors, which are connected to these internal connectors through a set of wiring layers. These external connectors may be formed by a higher level metal layer of the integrated circuit. The term "higher" is used herein to refer to a layer formed after other layers, regardless of the relative position of these layers to each other. For example, in the construction of a flip chip, from the perspective of the device initially manufactured, the metal wiring may be below the device of the original device. However, the metal wiring layer is still formed after the device layer, so it can be called a "higher" layer. These external connectors may have a second spacing different from the first spacing. The first spacing and the second spacing may differ by any factor, such as by two times or more. For example, the first spacing may be 65 microns and the second spacing may be 130 microns. In a particular embodiment of the present invention, in addition to the first set of external connectors, the integrated circuit may include a second set of external connectors, or the integrated circuit may be arranged in a package including a second set of external connectors in addition to the first set of external connectors. The second set of external connectors may have a third spacing. The metal wiring may connect the internal connector to the first set of external connectors and the second set of external connectors.

[0029] In certain embodiments, a given circuit design may be paired with different groups of metal wiring layers to form different finished chips. Different groups of metal wiring layers may be selected to connect the internal connectors of an integrated circuit to external connectors, which have different connections and different spacings. The spacing of these external connectors may be different from the spacing of the internal connectors, and may also be different on a given integrated circuit. Different groups of metal wiring layers allow a given integrated circuit design to be paired with different packages. When the top metal wiring layer of an integrated circuit is being formed, the pairing decision of the integrated circuit with a given package having a specific spacing may be determined during the back-end process of the integrated circuit. The term "group" of metal wiring layers is used here because the wiring may extend through multiple layers to allow for complex connection patterns to be wired, where one wiring may pass under or over another wiring. However, in certain embodiments of the present invention, multiple groups of metal wiring layers may be a layer group. Using standard photolithography or similar methods, these metal wiring layer groups may also be formed by multiple groups of masks, where in the case of single-layer wiring, the group of masks may include a single mask.

[0030] Figures 3 to 6 Conceptual diagram showing the changing pitch from the internal connector to the substrate ball grid array connection. Different mask sets can be used to construct Figures 3 to 6 . Figure 3 An example of a connection between an integrated circuit and an external connector is shown. Package device 300 includes silicon 305, a redistribution layer 310, and a substrate 320 (e.g., an organic substrate of a package). The silicon can accommodate internal connectors 325 and external connectors 330, which are connected together via multiple conductors 335 (e.g., metal wiring fabricated monolithically with the internal connectors). In some examples, a subassembly of connectors 325 can be connected to a subassembly of connectors 330. Connectors 325 can have a spacing 340, and connectors 330 can have a spacing 345. In some examples, spacing 340 can be the same as spacing 345. In other examples, spacing 340 can be different from spacing 345. Redistribution layer 310 can include multiple connectors 350, which are separated from each other by spacing 355. The distribution layer 310 can be an interposer. Spacing 355 can be different from spacing 345. The substrate 320 may include a plurality of connectors 360 spaced apart from each other by a pitch 365. The substrate 320 may be a substrate of a package. The pitch 365 may be different from the pitch 355.

[0031] exist Figure 3In the figure, the lowest level of the page is the internal connector 325 (e.g., pads spaced at 65 micron pitch in the metal layer), the next to the lowest level is the external connector 330 (e.g., bump metal spaced at 65 micron pitch of the integrated circuit), the next level is the connector 350 in the redistribution layer 310 (e.g., bump metal spaced at 150 micron pitch), and the highest level is the connector 360 of the substrate 320 (e.g., organic substrate) of the package (e.g., ball grid array contacts). These internal connectors can be connected to the semiconductor layer of the integrated circuit (e.g., to the terminals of passive devices or transistors formed in the semiconductor layer).

[0032] Figure 4 An example of a connection between an integrated circuit and an external connector is shown. Package device 400 includes silicon 405 of a package and a substrate 420 (e.g., an organic substrate). The silicon can accommodate internal connectors 425 and external connectors 430, which are connected together via multiple conductors 435 (e.g., metal wiring fabricated monolithically with the internal connectors). In some examples, a subassembly 427 of connector 425 can be connected to a subassembly of connector 430. Another subassembly 429 of connector 425 can avoid being connected to connector 430. Connector 425 can have a spacing 440, and connector 430 can have a spacing 445. Spacing 440 can be different from spacing 445. Substrate 420 can include multiple connectors 460, which are separated from each other by a spacing 465. Spacing 465 can be different from spacing 445.

[0033] exist Figure 4 In FIG. 4 , the external connector 430 has the same pitch as the external connector 350 described above (eg, the bump metal of the integrated circuit spaced at 130 micron pitch). Figure 3 and Figure 4 It can be seen from the comparison that by changing the top wiring layer of the integrated circuit, the same integrated circuit can be used with different external connections and can be compatible with different external systems. Figure 4 Also shown is how multiple internal connections 425 are coupled to the same external connection 430 (i.e., multiple metal layer pads spaced at 65 micron pitch are connected to the same multiple package bumps spaced at 130 micron pitch). For example, power or ground traces can be routed from a single external connection 430 to multiple internal connections 425.

[0034] The spacing 440 between the internal connectors 425 of different integrated circuits may be different. Figure 5 In the example, the internal connector is a metal layer pad, which is connected to the Figure 3 and Figure 4 Compared to the metal layer pads separated by 65 microns, Figure 5These metal layer pads are spaced apart from each other at a pitch of 45 microns.

[0035] Figure 5 An example of a connection between an integrated circuit and an external connector is shown. Package device 500 includes silicon 505 and substrate 520 (e.g., an organic substrate) of a package. Silicon can accommodate internal connectors 525 and external connectors 530, which are connected together via multiple conductors 535 (e.g., metal wiring monolithically manufactured with internal connectors). In some examples, a subassembly 527 of connector 525 can be connected to a subassembly of connector 530. Another subassembly 529 of connector 530 can avoid being connected to connector 530. Subassemblies 527 and subassemblies 529 can be organized so that when moving along a row of connectors 525, partial subassemblies 527 and partial subassemblies 529 are seen alternately. For example, every third connection 525 can belong to subassembly 527 (as shown). Alternatively, each other connector 525 can belong to subassembly 527. The number of connectors 525 in subassembly 527 can be the same as or different from the number of connectors 525 in subassembly 529. In some examples, there may be no particular pattern relationship between subassembly 527 and subassembly 529. Connectors 525 can have a pitch 540, and connectors 530 can have a pitch 545. Pitch 540 can be different from pitch 545. Substrate 520 can include a plurality of connectors 560, which are spaced apart from each other by a pitch 565. Pitch 565 can be different from pitch 545.

[0036] Figure 6 An example of a connection between an integrated circuit and an external connector is shown. Package device 600 includes silicon 605 of a package and a substrate 620 (e.g., an organic substrate). The silicon can accommodate internal connectors 625 and external connectors 630, which are connected together via multiple conductors 635 (e.g., metal wiring fabricated monolithically with the internal connectors). In some examples, a subassembly 627 of connector 625 can be connected to a subassembly of connector 630. Another subassembly 629 of connector 630 can avoid being connected to connector 630. Subassembly 627 and subassembly 629 can be organized so that when moving along a row of connectors 625, first the entire subassembly 627 is followed by the entire subassembly 629. Connector 625 can have a spacing 640, and connector 630 can have a spacing 645. Spacing 640 can be different from spacing 645. The substrate 620 may include a plurality of connectors 660 that are spaced apart from each other by a pitch 665. The pitch 665 may be different from the pitch 645.

[0037] In certain embodiments, a set of external connectors is provided to connect the integrated circuit to the package of the integrated circuit. Figure 3 and Figure 4 In the embodiment, these external connectors can be solder bumps formed on the die package. In a specific embodiment, the set of metal wiring layers forms a set of conductive paths connected to the external connectors, and the pitch of the set of conductive paths is equal to the pitch of the external connectors of the package. Figure 3 Consistent with these embodiments. In certain embodiments, the set of metal wiring layers forms a set of conductive paths connected to external connectors, and the pitch of the set of conductive paths is not equal to the pitch of external connectors on the package. Figure 4 According to these embodiments.

[0038] In a specific embodiment of the present invention, an integrated circuit is provided. The integrated circuit includes a set of devices and a set of internal connections, the set of internal connections being coupled to the set of devices and spaced apart from each other at a first spacing. The set of internal connections may be a set of metal layer pads. The integrated circuit also includes a set of external connections coupled to the set of internal connections, and a set of metal wiring layers of the integrated circuit coupling the set of internal connections to the set of external connections, wherein the set of external connections are spaced apart from each other at a second spacing. A subassembly of the set of internal connections is not connected to the set of external connections. Figure 4 According to these embodiments. In certain embodiments, a subassembly of the set of internal connectors is not connected to any metal wiring layer in the set of metal wiring layers. The set of external connectors may be package contacts formed on a package of the integrated circuit, such as solder balls, bumps, pillars, or leads.

[0039] In a particular embodiment, the integrated circuit may further include a second group of external connectors that are spaced apart from each other at a third spacing. The group of metal wiring layers of the integrated circuit may connect the group of internal connectors to the second group of external connectors. The spacing of different groups of external connectors may be different, and the same wiring layer may connect the internal connectors to both groups of external connectors. In a particular embodiment, the group of internal connectors covers the periphery of the integrated circuit. For example, a group of metal layer pads may be formed around all edges of the integrated circuit. Multiple groups of external connectors may be located on different sides of the integrated circuit. In these embodiments, the integrated circuit may be constructed to be connected to an external system having a first spacing on one side or a portion of one side, and to be connected to another external system having a different spacing on the other side.

[0040] In certain embodiments, the bottom layer circuitry (i.e., the circuitry below the internal connections and metal layers that allow for the pitch adjustment described herein) can be an IP block that is constructed using the methods described herein to interface with different bump pitches. In this way, when the bump pitch of the IP block changes, the single circuit design of the IP block can be tied together with the different bump pitches without requiring circuit redesign.

[0041] FIG7 shows an example of the method, which shows how to connect a single IP block to a package with three different bump pitches. Circuit system 700-a includes a side view (view 700-a1) and a top view (view 700-a2). Circuit system 700-b includes a side view (view 700-b1) and a top view (view 700-b2). IP block 715 accommodates circuit 705. Circuit 705 between two IP blocks 715-a and 715-b can be the same. Block 710 can be a substrate or an interposer. Connector 723 has a pitch 720, which can be the same between circuit systems 700-a and 700-b. Connectors 728-a and 728-b can have pitches 725-a and 725-b, respectively. The pitches 725-a and 725-b between circuit systems 700-a and 700-b can be different. These connectors 723 may be coupled to connector 728-a via conductor 730-a (eg, a set of metal wires). Connectors 723 may be coupled to connector 728-b via conductor 730-b (eg, a set of metal wires) having a different layout or configuration than conductor 730-a.

[0042] In one example, the pitch 720 and pitch 725-a of the connector (e.g., package) are 45 microns and the pitch 725-b is 110 microns, but different pitch values ​​are possible. In circuit systems 700-a and 700-b, top views are shown to illustrate how the same circuit 705 within IP block 715-a or 715-b can be utilized in any case, and only the distribution of conductors 730 (e.g., lines) from internal connectors to external connectors needs to be modified.

[0043] Figure 8An example of a D2D connector 800 according to a specific embodiment of the invention disclosed herein is provided. Core particles 805-a and 805-b include connectors 810-a and 810-b, respectively. Connections 810-a and 810-b are connected together via conductors 815 (e.g., metal traces on a substrate or interposer). These core particles can be produced using the methods disclosed herein or can include fine pitches for maximizing the number of connections available for chip-to-chip communication. Importantly, each core particle can be designed to communicate with an alternative core particle having a specific interconnect pitch without having to reserve space for alternative pitch connectors at the D2D interface. For example, in a method that does not utilize a specific embodiment of the invention disclosed herein, half of the D2D interface shown may need to be reserved for connection with a chip using a different contact pitch. Therefore, the specific embodiments of the invention disclosed herein allow the number of connections that can be provided in the D2D interface of the core particle system to be maximized by adjusting the top metal layer of the chip to obtain the desired pitch density across the D2D interface, which often has a high density of required connections.

[0044] Fig. 9 A method 900 for packaging an integrated circuit is provided. In step 905, a group of devices of the integrated circuit are formed. These devices can be transistors, capacitors, or other devices or combinations of devices. In step 910, a group of internal connectors of the integrated circuit are connected to the group of devices of the integrated circuit. In step 915, a group of masks are selected from a mask set library. The multiple groups of masks in the mask set library are configured to form different groups of metal wiring layers. In step 920, a group of metal wiring layers of the integrated circuit are formed using the group of masks selected in step 915. The different groups of metal wiring layers are different in the way they connect the internal connectors of the integrated circuit to the external connectors of the integrated circuit. In step 925, a group of external connectors of the integrated circuit are connected to the group of internal connectors via the metal wiring layers formed in step 920.

[0045] Fig.10A method 1000 for packaging an integrated circuit is provided. At step 1005, a first group of devices of an integrated circuit is formed. These devices may be transistors, capacitors, or other devices or combinations of devices. At step 1010, a first group of internal connectors of a first integrated circuit is formed. The first group of internal connectors are coupled to the first group of devices of the first integrated circuit. At step 1015, a first group of masks is selected from a mask set library based at least in part on the first group of external connectors. At step 1020, a first group of metal wiring layers of the first integrated circuit is formed using the first group of masks selected at step 1015. At step 1025, a second group of devices of a second integrated circuit is formed. The construction of the second group of devices may be the same as the construction of the first group of devices. At step 1030, a second group of internal connectors of a second integrated circuit is formed. The second group of internal connectors are coupled to the second group of devices of the second integrated circuit. At step 1035, a second group of masks is selected from a mask set library based at least in part on the second group of external connectors. The second group of masks may be different from the first group of masks. The second group of external connectors have a different construction than the first group of external connectors. At step 1040, a second set of metal wiring layers is formed for a second integrated circuit using a second set of masks, wherein the configuration of the second integrated circuit may be different from the configuration of the first set of metal wiring layers.

[0046] Although the specification has been described in detail with respect to specific embodiments of the present invention, it should be understood that modifications, variations, and equivalents of these embodiments can be easily conceived by those skilled in the art after understanding the foregoing. For example, although the specification mentions core particles, in accordance with the methods disclosed herein, in these examples, any form of integrated circuit can be used instead of the core particles. As another example, although the integrated circuit is referred to as being made of silicon in the examples herein, the technical enlightenment disclosed herein is more broadly applicable to any integrated circuit, including integrated circuits made of other semiconductor materials such as silicon carbide and gallium nitride. These and other modifications and variations of the present invention may be implemented by those skilled in the art without departing from the scope of the present invention, the scope of the present invention being more specifically set forth in the appended claims.

Claims

1. A method for packaging an integrated circuit, comprising: A group of devices forming an integrated circuit; forming a set of internal connections of the integrated circuit, the set of internal connections being coupled to a set of devices of the integrated circuit; Select a mask set from the mask set library; forming a metal wiring layer group of the integrated circuit using the mask group; and coupling a set of external connectors of the integrated circuit to the set of internal connectors via a metal wiring layer; Wherein: (i) the mask sets in the mask set library are constructed to form different metal wiring layer groups; and (ii) the different metal wiring layer groups differ in the manner in which they connect internal connectors of the integrated circuit to external connectors of the integrated circuit.

2. The method according to claim 1, wherein: The set of metal wiring layers decouples a subcomponent of the set of internal connectors from the set of external connectors; and Different metal wiring layer groups have different numbers of internal connectors in the internal connector groups that are not connected to the external connector group.

3. The method according to claim 1, wherein: The set of external connections is provided as part of a package of the integrated circuit.

4. The method according to claim 3, wherein: The metal wiring layer group forms a lead group, and the lead group is connected to the external connector group; The pitch in the lead set is equal to the pitch in the external connector set on the package.

5. An integrated circuit comprising: Device group; an internal connector group coupled to the device group and having a first pitch, wherein the internal connector group is a group of metal layer pads; an outer connector set coupled to the inner connector set and having a second spacing; and a set of metal wiring layers of the integrated circuit, the set of wiring layers coupling the set of internal connectors to the set of external connectors; Wherein, the subcomponents of the internal connector group are not connected to the external connector group.

6. The integrated circuit of claim 5, wherein: A subassembly of the set of internal connectors is not connected to any metal wiring layer in the set of metal wiring layers.

7. The integrated circuit of claim 5, wherein: The set of external connections are package contacts.

8. The integrated circuit of claim 5, wherein: The external connection member group is one of solder balls, bumps, pillars, or leads.

9. The method according to claim 5, further comprising: A second set of external connectors having a third pitch, wherein a set of metal wiring layers of the integrated circuit couples the set of internal connectors to the second set of external connectors.

10. The integrated circuit of claim 9, further comprising: The internal connection member group covers the periphery of the integrated circuit; The external connector set is located on a first side of the integrated circuit; and The second set of external connections is located on a second side of the integrated circuit.

11. The integrated circuit of claim 5, wherein: The integrated circuit is a chip; The device group is a transistor; and The first spacing and the second spacing differ by two times or more.

12. A method comprising: a first group of devices forming a first integrated circuit; forming a first set of internal connections of the first integrated circuit, the first set of internal connections coupled to a first set of devices of the first integrated circuit; selecting a first set of masks from a library of mask sets based at least in part on the first set of external connectors; forming a first set of metal wiring layers for the first integrated circuit using the first set of masks; forming a second group of devices of a second integrated circuit, wherein the second group of devices has a configuration identical to that of the first group of devices; forming a second set of internal connections of the second integrated circuit, the second set of internal connections coupled to a second set of devices of the second integrated circuit; selecting a second set of masks from the mask set library based at least in part on a second set of external connectors, wherein the second set of masks is different from the first set of masks and a configuration of the second set of external connectors is different from a configuration of the first set of external connectors; and A second set of metal wiring layers is formed for the second integrated circuit using the second set of masks, wherein the second integrated circuit has a configuration different from that of the first set of metal wiring layers.

13. The method according to claim 12, further comprising: coupling a first set of external connections of the first integrated circuit to the first set of internal connections via the first set of metal wiring layers; and A second set of external connections of the second integrated circuit are coupled to the second set of internal connections via the second set of metal wiring layers.

14. The method according to claim 13, wherein: Forming the first set of metal wiring layers includes decoupling a subassembly of the first set of internal connectors from the first set of external connectors in a first metal wiring configuration.

15. The method of claim 14, wherein forming a second set of metal wiring layers comprises: In the second metal wiring structure, the subcomponents of the second group of internal connectors are not connected to the second group of external connectors; and the number of subcomponents of the first group of internal connectors that are not connected to the first group of external connectors is different from the number of subcomponents of the second group of internal connectors that are not connected to the second group of external connectors.

16. The method of claim 12, wherein: The first set of external connections is associated with a first package; and The second set of external connections is associated with a second package.

17. The method of claim 16, wherein: The first package is different from the second package.

18. The method of claim 12, wherein: The first set of external connections is one of solder balls, bumps, pillars, and leads; and The second set of external connections is one of solder balls, bumps, pillars, and leads.

19. The method of claim 12, wherein: The first integrated circuit and the second integrated circuit are both chiplets; and The first group of devices and the second group of devices are both transistors.

20. The method of claim 12, wherein: The first set of internal connectors is associated with a first pitch, the second set of internal connectors is associated with a second pitch, the first set of external connectors is associated with a third pitch, and the second set of external connectors is associated with a fourth pitch; The first spacing is different from the third spacing; The second spacing is different from the fourth spacing; and The third interval is different from the fourth interval.

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