Method for preparing a semiconductor structure

Abstract

An embodiment of the present disclosure provides a method for preparing a semiconductor structure, characterized in that the method includes: providing a first wafer, the first wafer including a plurality of first chips, and a first cutting path is arranged between the plurality of first chips; forming a first dielectric layer and a first groove and a second groove located in the first dielectric layer on a first surface of the first wafer, forming a first alignment mark in the first groove, and forming a first contact pad in the second groove, the first contact pad being connected to the first chip; providing a plurality of second chip structures, and bonding the second chip structures to the first chips on a side of the first wafer provided with the first alignment mark to form the first semiconductor structure; forming a second alignment mark corresponding to the first alignment mark on the structure to be bonded; and bonding the first semiconductor structure to the structure to be bonded based on an alignment operation between the first alignment mark and the second alignment mark.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] As semiconductor devices develop towards miniaturization, high integration, and multifunctionality, the stability and reliability issues they present during use have also attracted widespread attention. The semiconductor device packaging process, as an essential stage in the formation of semiconductor devices, is directly related to the stability and reliability of the final semiconductor device during use.

[0003] However, in the current manufacturing process of semiconductor devices, the packaging stage still has relatively complex process. Summary of the Invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0005] A first semiconductor structure is provided, comprising:

[0006] Providing a first wafer, wherein the first wafer includes a plurality of first chips, and first dicing streets are provided between the plurality of first chips;

[0007] forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on the first surface of the first wafer, wherein an orthographic projection of the first groove on the first surface is within a range defined by an orthographic projection of the first cutting street on the first surface;

[0008] performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip;

[0009] Providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form the first semiconductor structure;

[0010] A structure to be bonded is provided, on which a second alignment mark corresponding to the first alignment mark is formed; and based on an alignment operation between the first alignment mark and the second alignment mark, the first semiconductor structure is bonded to the structure to be bonded.

[0011] In some embodiments, providing the first semiconductor structure further includes:

[0012] providing a carrier board, and forming a third alignment mark on the carrier board;

[0013] forming a fourth alignment mark corresponding to the third alignment mark on the second surface of the first wafer; wherein the first surface and the second surface are two surfaces of the first wafer disposed opposite to each other;

[0014] Based on an alignment operation between the third alignment mark and the fourth alignment mark, the carrier is bonded to a side of the first wafer away from the first alignment mark.

[0015] In some embodiments, providing the first semiconductor structure further includes:

[0016] providing a carrier board, and forming a third alignment mark on the carrier board;

[0017] Providing a second wafer, wherein the second wafer includes a plurality of third chips;

[0018] A fifth alignment mark and a sixth alignment mark are formed on two oppositely disposed surfaces of the second wafer; wherein the fifth alignment mark is disposed corresponding to the third alignment mark,

[0019] forming a fourth alignment mark on the second surface of the first wafer, wherein the sixth alignment mark is arranged corresponding to the fourth alignment mark;

[0020] The carrier is bonded to the second wafer based on an alignment operation between the third alignment mark and the fifth alignment mark, and the second wafer is bonded to the first wafer based on an alignment operation between the sixth alignment mark and the fourth alignment mark.

[0021] In some embodiments, providing a plurality of the second chip structures includes:

[0022] providing an initial structure comprising a plurality of second chips;

[0023] forming a second dielectric layer on the initial structure, wherein the second dielectric layer covers the surface of the initial structure;

[0024] forming a second contact pad in the second dielectric layer, wherein the second contact pad is connected to the second chip;

[0025] A sawing process is performed to separate the initial structure into a plurality of second chip structures.

[0026] In some embodiments, bonding the second chip structure to the side of the first wafer provided with the first alignment mark includes:

[0027] The first dielectric layer and the second dielectric layer are bonded correspondingly, and the first contact pad and the second contact pad are bonded correspondingly.

[0028] In some embodiments, after bonding the second chip structure to the side of the first wafer provided with the first alignment mark, the preparation method further includes:

[0029] A third dielectric layer is formed, wherein the third dielectric layer at least fills the gaps between adjacent second chip structures.

[0030] In some embodiments, the patterns of the first alignment mark, the second alignment mark, the third alignment mark, the fourth alignment mark, the fifth alignment mark, and the sixth alignment mark are formed using a same mask.

[0031] In some embodiments, the number of at least one of the patterns for forming the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark on the same mask may include plural numbers.

[0032] In some embodiments, after the structure to be bonded is bonded to the first semiconductor structure, the orthographic projection of the first alignment mark on the first surface falls within the range defined by the orthographic projection of the second alignment mark on the first surface, and the boundary of one coincides with the boundary of the other.

[0033] In some embodiments, a size of the first alignment mark ranges from 20 μm to 80 μm.

[0034] A method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes: providing a first semiconductor structure, including: providing a first wafer, the first wafer including a plurality of first chips, and a first cutting path being arranged between the plurality of first chips; forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on a first surface of the first wafer, the orthographic projection of the first groove on the first surface being located within a range defined by the orthographic projection of the first cutting path on the first surface; performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, the first contact pad being connected to the first chip; providing a plurality of second chip structures, and bonding the second chip structures to the first chip on the side of the first wafer where the first alignment mark is arranged to form the first semiconductor structure; providing a structure to be bonded, the structure to be bonded having a second alignment mark corresponding to the first alignment mark formed thereon; and bonding the first semiconductor structure to the structure to be bonded based on an alignment operation between the first alignment mark and the second alignment mark. Thus, in the embodiment of the present disclosure, in the same process of forming the first contact pad on the bonding surface of the first wafer for bonding with the second chip structure, a process step of forming the first alignment mark is also performed, that is, the formation of the first contact pad and the first alignment mark are combined into the same step, which helps to save multiple process steps and improve production efficiency. At the same time, in the embodiment of the present disclosure, the orthographic projection of the first alignment mark on the first surface of the first wafer falls within the orthographic projection range of the first cutting road on the first surface, so that the presence of the first alignment mark does not occupy the position of the first chip on the first wafer. At the same time, the setting of this position is also beneficial in the process of aligning and bonding the first semiconductor structure with the structure to be bonded. In the process of the bonding machine detecting whether the structures are effectively aligned, light can smoothly pass through the structure to be bonded and illuminate the first alignment mark, so that the first semiconductor structure can be well bonded to the first carrier.

[0035] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1A flowchart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figures 2 to 11 A process flow chart of the semiconductor structure during the preparation process provided by the embodiment of the present disclosure;

[0039] Figure 12 A partial perspective view of a semiconductor structure provided in accordance with an embodiment of the present disclosure;

[0040] Figure 13 A schematic structural diagram of a semiconductor structure during the manufacturing process provided by another embodiment of the present disclosure;

[0041] Figure 14 A schematic structural diagram of multiple alignment structures provided in an embodiment of the present disclosure;

[0042] Figure 15 A schematic structural diagram of a photomask provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0045] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0046] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0047] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] With the development of large-scale integrated circuits (ICs), circuit feature sizes continue to shrink, and chips are evolving in three dimensions, entering the post-Moore era. This approach meets the demands for high integration, fast transmission speeds, and low power consumption. Three-dimensional fabrication is primarily achieved through multi-wafer stacking. A carrier wafer is melt-bonded to the device wafer, and the backside of the device wafer is thinned and perforated to create new leads on the wiring layer. This allows for subsequent stacking of multiple wafers. This process is performed using a 3D mark (aligned with a bonding mark) to serve as a support.

[0050] However, in the above process, there is still the problem of complex preparation process.

[0051] Based on this, the following technical solutions are proposed in the embodiments of the present disclosure:

[0052] The present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the method includes the following steps:

[0053] A first semiconductor structure is provided, comprising:

[0054] Step S101: providing a first wafer, wherein the first wafer includes a plurality of first chips, and first dicing streets are provided between the plurality of first chips;

[0055] Step S102: forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on a first surface of a first wafer, wherein an orthographic projection of the first groove on the first surface is within a range defined by an orthographic projection of a first scribe line on the first surface;

[0056] Step S103: performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip;

[0057] Step S104: providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form a first semiconductor structure;

[0058] Step S105: providing a structure to be bonded, on which a second alignment mark corresponding to the first alignment mark is formed; and bonding the first semiconductor structure to the structure to be bonded based on an alignment operation between the first alignment mark and the second alignment mark.

[0059] Thus, in the embodiment of the present disclosure, during the same process of forming the first contact pad on the bonding surface of the first wafer for bonding with the second chip structure, a process step of forming the first alignment mark is also performed, that is, the formation of the first contact pad and the first alignment mark are combined into the same step, which helps to save multiple process steps and improve production efficiency. At the same time, in the embodiment of the present disclosure, the orthographic projection of the first alignment mark on the first surface of the first wafer falls within the orthographic projection range of the first cutting line on the first surface, so that the presence of the first alignment mark does not occupy the position of the first chip on the first wafer. At the same time, the setting of this position is also beneficial in the process of aligning and bonding the first semiconductor structure with the structure to be bonded. In the process of the bonding machine detecting whether the structures are effectively aligned, light can smoothly pass through the structure to be bonded and illuminate the first alignment mark, so that the first semiconductor structure can be well bonded to the first carrier.

[0060] It should be understood that although Figure 1 The steps in the diagram are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0061] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0062] Figures 2 to 11 A process flow chart of the semiconductor structure during the preparation process provided by the embodiment of the present disclosure; Figure 12 A partial perspective view of a semiconductor structure provided in accordance with an embodiment of the present disclosure; Figure 13 A schematic structural diagram of a semiconductor structure during the manufacturing process provided by another embodiment of the present disclosure; Figure 14 A schematic structural diagram of multiple alignment structures provided in an embodiment of the present disclosure; Figure 15 A schematic structural diagram of a photomask provided in an embodiment of the present disclosure.

[0063] The method for manufacturing a semiconductor device provided by an embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0064] The preparation method provided in the embodiment of the present disclosure involves a first semiconductor structure (for details, please refer to Figure 9 A1 in) and the structure to be bonded (for details, please refer to Figure 10 The bonding process of A2) in Figure 1 In the multiple steps shown, steps S101 to S104 are to provide a first semiconductor structure (for details, please refer to Figure 9 In the process of A1), step S105 is to provide a structure to be bonded (for details, please refer to Figure 10 A2) and the steps of bonding the two will be described below.

[0065] First, execute step S101: Figure 3 As shown, a first wafer W1 is provided. The first wafer W1 includes a plurality of first chips C1 , and a first dicing street Q1 is provided between the plurality of first chips C1 .

[0066] It can be understood that the first dicing lane Q1 is used to separate the multiple first chips C1 on the first wafer W1 after the packaging process is completed. The dicing process will cut the first wafer W1 at this position to achieve separation between the multiple first chips C1.

[0067] Furthermore, in some embodiments, the first cutting lane Q1 may also be used to place alignment marks to improve alignment accuracy during bonding between structures, thereby improving various aspects of performance of the bonded semiconductor structure.

[0068] Then, execute step S102, as shown in FIG. Figure 4 and Figure 5 As shown, a first dielectric layer L1 and a first groove T1 and a second groove T2 are formed in the first dielectric layer L1 on the first surface S1 of the first wafer W1. The orthographic projection of the first groove T1 on the first surface is within the range defined by the orthographic projection of the first cutting street Q1 on the first surface S1.

[0069] In some embodiments, the material of the first dielectric layer L1 may include but is not limited to oxide, nitride, oxynitride, and the like.

[0070] In some embodiments, after forming the first dielectric layer L1, a first sub-layer La may be formed. The material of La may include but is not limited to at least one of insulating materials such as silicon carbon nitride (SiCN), oxide or oxynitride, or a combination thereof.

[0071] However, it is not limited thereto. In some embodiments, the material (first sub-layer La) may not be formed. The material can be flexibly selected according to the actual situation and is not specifically limited here.

[0072] However, the present invention is not limited thereto. In some other embodiments, the material of the first dielectric layer L1 may also be any other suitable insulating material. In actual operation, the material can be flexibly selected according to the actual situation and is not specifically limited here.

[0073] It is understandable that in order to provide effective support for subsequent processes, a step of bonding the first wafer W1 to the carrier 10 will be pre-performed before performing the operation step S102 on the first wafer W1 .

[0074] Therefore, if Figures 2 to 4 As shown, in some embodiments, a first semiconductor structure A1 is provided, further comprising:

[0075] Providing a carrier board 10, and forming a third alignment mark M3 on the carrier board 10;

[0076] A fourth alignment mark M4 corresponding to the third alignment mark M3 is formed on the second surface S2 of the first wafer W1; wherein the first surface S1 and the second surface S2 are two surfaces opposite to each other of the first wafer W1;

[0077] Based on the alignment operation between the third alignment mark M3 and the fourth alignment mark M4 , the carrier 10 is bonded to a side of the first wafer W1 away from the first alignment mark M1 .

[0078] In some embodiments, the material of the carrier 10 may include but is not limited to waste wafers, glass substrates, semiconductor substrates, or ceramic substrates.

[0079] In some embodiments, the active surface of the first wafer W1 can be bonded to the carrier 10, but this is not limited to this. The inactive surface of the first wafer W1 can also be bonded to the carrier 10. The active surface is the side of the first wafer W1 on which the device structure is formed. Specifically, the active surface can be flexibly selected according to actual conditions and is not specifically limited here.

[0080] It is understandable that, considering the increasingly higher requirements of users for the integration of semiconductor structures, in some other embodiments, before the carrier 10 is bonded to the first wafer W1, the carrier 10 may be bonded to other wafers first, and then the bonding operation with the first wafer W1 is performed. For example:

[0081] In other embodiments, Figure 13 As shown, a first semiconductor structure A1 is provided, further comprising:

[0082] Providing a carrier board 10, and forming a third alignment mark M3 on the carrier board 10;

[0083] Providing a second wafer W2, wherein the second wafer W2 includes a plurality of third chips C3;

[0084] A fifth alignment mark M5 and a sixth alignment mark M6 are formed on two opposite surfaces of the second wafer W2; wherein the fifth alignment mark M5 is arranged corresponding to the third alignment mark M3.

[0085] A fourth alignment mark M4 is formed on the second surface S1 of the first wafer W1, and a sixth alignment mark M6 is provided corresponding to the fourth alignment mark M4;

[0086] Based on the alignment operation between the third alignment mark M3 and the fifth alignment mark M5 , the carrier 10 is bonded to the second wafer W2 . Based on the alignment operation between the sixth alignment mark M6 and the fourth alignment mark M4 , the second wafer W2 is bonded to the first wafer W1 .

[0087] In some embodiments, a second scribe line Q2 is provided between the plurality of third chips C3 . In some steps of the packaging process, the plurality of third chips C3 may be separated from each other based on the location of the second scribe line Q2 .

[0088] It should be noted that although Figure 13 In the embodiment in which two wafers are present before forming the first alignment mark M1 and the first contact pad D1, this is merely an exemplary description. In practice, the number of wafers may be greater, such as 3, 4, 5, 8, more than a dozen, dozens, or even more, and is not specifically limited here.

[0089] In some embodiments, the active surface of the second wafer W2 can be bonded to the carrier 10, but is not limited thereto. The inactive surface of the second wafer W2 can also be bonded to the carrier 10. The active surface is the side of the second wafer W2 on which the device structure is formed. Specifically, it can be flexibly selected according to actual conditions and is not specifically limited here. When the second wafer W2 is bonded to the first wafer W1, depending on whether the second wafer W2 and the carrier 10 are bonded with an active surface or an inactive surface, the second wafer W2 will be bonded with the active surface or the inactive surface of the first wafer W1 using the inactive surface or the active surface.

[0090] In some specific embodiments, one side of the first wafer W1 used for bonding with the carrier 10 or the second wafer W2 can be a non-active surface, which can reduce the communication distance between the first chip C1 contained in the first wafer and the second chip structure B2 bonded in the subsequent step S105, thereby improving communication efficiency.

[0091] However, the present invention is not limited thereto. The bonding surfaces of the first wafer W1 and the second chip structure B2 may also be in other situations. Specifically, whether the bonding surface between the two is an active surface can be flexibly selected based on the type of chip in the first semiconductor structure, and no specific limitation is made here.

[0092] In some embodiments, in order to make the final semiconductor structure have a smaller volume and a smaller weight, the back sides of the first wafer W1 and the second wafer W2 may be thinned before performing related bonding operations.

[0093] However, the present invention is not limited thereto. In some embodiments, when the first wafer W1 is directly bonded to the carrier 10 , a process of thinning the back side of the first wafer W1 may be performed after the first wafer W1 is bonded to the carrier 10 .

[0094] Alternatively, the backside thinning process of the second wafer W2 may be performed after the carrier 10 is bonded to the second wafer W2, or the backside thinning process of the first wafer W1 may be performed after the first wafer W1 is bonded to the second wafer W2. Specifically, the process can be flexibly selected according to actual conditions and is not specifically limited here.

[0095] Next, execute step S103, as shown in FIG. Figure 6 As shown, a filling process is performed on the first groove T1 and the second groove T2 in the same process step to form a first alignment mark M1 in the first groove T1 and a first contact pad D1 in the second groove T2. The first contact pad D1 is connected to the first chip C1.

[0096] Here, the material of the first contact pad D1 includes, but is not limited to, an alloy formed by one or more of copper, gold, silver, aluminum, nickel, tungsten, titanium, tin, conductive graphene, or carbon nanotubes.

[0097] In a conventional structure, in order to realize the alignment operation between the first semiconductor structure and the structure to be bonded in the subsequent step S105, a corresponding alignment mark is usually formed on the back side of the second chip structure (for example, the side of the second chip C2 close to the structure to be bonded A2). At this time, after the bonding operation between the second chip structure B2 and the first wafer W1 is completed, an additional series of process steps need to be performed, such as material deposition, photolithography, material etching and cleaning steps, before the first alignment mark can be obtained. The operation process is relatively complicated and the number of masks used will increase. In addition to the high process complexity, the production cost is also high.

[0098] It is understandable that if the first contact pad D1 and the first alignment mark M1 are not formed in the same step, that is, in Figure 9In the structure shown, when the first alignment mark M1 is not formed, after the first wafer W1 and the second chip structure B2 are bonded, not only a step similar to S102 of forming a dielectric material layer, but also a step similar to S103 of etching a first groove T1 for forming the first alignment mark M1 in the dielectric material layer and a step of filling the first groove T1 to form the first alignment mark M1 are required to be additionally performed at a position of the second chip structure B2 away from the first wafer W1. At the same time, in the above process, in order to form the first groove T1, a larger number of photomasks will be used, and further steps of forming a mask pattern on the photomask, as well as multiple steps such as exposure, development, and cleaning will be involved.

[0099] That is to say, compared with the case where the first contact pad D1 and the first alignment mark M1 are formed together in the same step, when the two are not formed in the same step, in addition to the need to increase the number of masks used, additional operation steps such as material deposition, photolithography, etching and cleaning will also be added. The process flow is more complicated, which can easily increase production costs and reduce production efficiency.

[0100] In some embodiments of the present disclosure, the mask pattern for forming the first contact pad D1 and the mask pattern for forming the first alignment mark can be designed on the same mask, which can save the number of masks.

[0101] Furthermore, compared to forming the first contact pad D1 and the first alignment mark M1 in separate steps, forming both in the same step not only reduces the number of photomasks used, but also eliminates the need for performing the aforementioned multiple additional steps. In other words, forming both in the same step not only reduces the number of photomasks used, but also helps simplify the overall process, eliminating a series of operational steps, including but not limited to material deposition, photolithography, etching, and cleaning, thereby streamlining the process and improving production efficiency.

[0102] Then, step S104 is executed. Figures 7 to 9 As shown, a plurality of second chip structures B2 are provided, and the second chip structures B2 are bonded to the first chips C1 on the side of the first wafer W1 where the first alignment mark M1 is provided, to form a first semiconductor structure A1.

[0103] In some embodiments, providing a plurality of second chip structures B2 includes:

[0104] Provide an initial structure B1 including a plurality of second chips C2 (for details, please refer to Figure 7 );

[0105] A second dielectric layer L2 is formed on the initial structure B1. The second dielectric layer L2 covers the surface of the initial structure B1 (see Figure 7 );

[0106] A second contact pad D2 is formed in the second dielectric layer L2, and the second contact pad D2 is connected to the second chip C2 (for details, please refer to Figure 7 );

[0107] Perform a cutting process to separate the initial structure B1 into a plurality of second chip structures B2 (for details, please refer to Figure 8 ).

[0108] In some embodiments, as Figure 9 As shown, after bonding the second chip structure B2 to the side of the first wafer W1 provided with the first alignment mark M1, the preparation method further includes:

[0109] A third dielectric layer L3 is formed, and the third dielectric layer L3 at least fills the gaps between adjacent second chip structures B2.

[0110] In some embodiments, the material of the third dielectric layer L3 may be the same as or different from the material of the first dielectric layer L1 or the second dielectric layer L2 , which is not specifically limited herein.

[0111] In some specific embodiments, the material of the third dielectric layer L3 may include oxide, such as silicon oxide.

[0112] In addition, in the subsequent bonding process, visible light needs to pass through the carrier 10 and the third dielectric layer L3 before irradiating the first alignment mark M1. Therefore, in the embodiment of the present disclosure, certain requirements are placed on the transmittance of the third dielectric layer L3.

[0113] It should be noted that, since during the subsequent step S105, the alignment operation between the bonded structure A2 and the first semiconductor structure A1 during bonding needs to use the first alignment mark M1 as one of the criteria for detecting whether the two structures are aligned, the third dielectric layer L3 needs to have a certain transmittance for visible light.

[0114] In some embodiments, the material included in the third dielectric layer L3 has a transmittance range of 75% to 100% for visible light (wavelength range: 380 nm to 780 nm).

[0115] In some embodiments, a through silicon via structure (not labeled in the figure) and a metal layer (not labeled in the figure) located on the through silicon via structure (not labeled in the figure) are further formed on the first chip C1 , the second chip C2 , and the third chip C3 .

[0116] In some embodiments, a third scribe line Q3 is provided between the plurality of second chips C2. When forming the second chip structure B2, the initial structure B1 is cut at the location of the third scribe line Q3 to form a plurality of separated second chip structures B2.

[0117] In some embodiments, the material of the second dielectric layer L2 located on the second chip structure B2 may be the same as or different from the material of the first dielectric layer L1 , which is not specifically limited herein.

[0118] In some embodiments, the material of the second contact pad D2 on the second chip structure B2 may be the same as or different from the material of the first contact pad D1 , which is not specifically limited herein.

[0119] Finally, step S105 is executed. Figure 10 and Figure 11 As shown, a structure A2 to be bonded is provided, on which a second alignment mark M2 corresponding to the first alignment mark M1 is formed; and based on an alignment operation between the first alignment mark M1 and the second alignment mark M2, the first semiconductor structure A1 is bonded to the structure A2 to be bonded.

[0120] In the structure obtained by bonding the first semiconductor structure A1 and the structure to be bonded A2, the side of the first semiconductor structure A1 where the second chip structure B2 is provided is bonded to the structure to be bonded A2.

[0121] It can be understood that in the process of bonding the first conductor structure A1 and the structure to be bonded A2 in this step, since the first alignment mark M1 is formed in advance in the same step of forming the first contact pad D1, there is no need to specially make an alignment mark on the side of the second chip structure B2 away from the first wafer W1. During the bonding process, the bonding machine can use visible light to illuminate the second alignment mark M2 and then pass through the structure to be bonded A2 and the third dielectric layer L3 to illuminate the first alignment mark M1. By detecting whether the two are aligned, the bonding accuracy can be improved and a good bonding effect can be obtained.

[0122] In some embodiments, the structure to be bonded A2 can be a carrier to provide effective support for the semiconductor structure during the process of packaging, protecting the semiconductor structure from damage or breakage due to stress generated during the process.

[0123] In some embodiments, the material of the structure A2 to be bonded, such as a carrier, may include but is not limited to a waste wafer, a glass substrate, a semiconductor substrate, or a ceramic substrate.

[0124] It is understandable that in order to achieve better alignment between the first semiconductor structure and the structure to be bonded, during the alignment detection operation performed by the bonding machine, visible light needs to pass through the structure to be bonded A2 and the interior of the third dielectric layer L3 at the same time. Therefore, there are certain requirements for the transmittance of visible light of the structure to be bonded. For example:

[0125] In some embodiments, the material of the to-be-bonded structure A2 has a transmittance of visible light ranging from 75% to 100%.

[0126] In some embodiments, the bonding between the first semiconductor structure A1 and the to-be-bonded structure A2 may be performed by at least one of a fusion bonding process and a hybrid bonding process.

[0127] In some specific embodiments, when a hybrid bonding process is adopted, bonding the second chip structure B2 to the side of the first wafer W1 provided with the first alignment mark M1 includes:

[0128] The first dielectric layer L1 and the second dielectric layer L2 are bonded correspondingly, and the first contact pad D1 and the second contact pad D2 are bonded correspondingly.

[0129] It can be understood that in the embodiment of the present disclosure, among the multiple alignment marks involved, in addition to the first alignment mark M1 being set on the same mask used to form the first contact pad D1, it can also be set on the same mask with other alignment marks. Specifically, it can be selected according to actual conditions and is not specifically limited here.

[0130] In some embodiments, as Figure 15 As shown, the same mask M is used to form the patterns of the first alignment mark M1 , the second alignment mark M2 , the third alignment mark M3 , the fourth alignment mark M4 , the fifth alignment mark M5 and the sixth alignment mark M6 as shown in the figure.

[0131] It is understandable that this processing method can effectively reduce the number of masks used in the entire semiconductor structure formation process, which is beneficial to saving costs. When forming the corresponding mark, it is only necessary to select the area where the corresponding pattern is located for normal process processing.

[0132] Continue to refer Figure 15 In some embodiments, the number of at least one of the patterns used to form the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark (the first group Z1, the second group Z2, the third group Z3, the fourth group Z4, and the fifth group Z5) located on the same mask M may include multiple ones.

[0133] It should be noted that the attached Figure 15The figure only schematically shows the case where a group of patterns contains multiple numbers. This is only for illustrative purposes. In fact, the number of any one can be set to multiple, which are not listed here one by one. The method of setting it to multiple is helpful in selecting a pattern structure with the required accuracy during the preparation process to meet the use requirements of the final mark.

[0134] In some embodiments, as Figure 14 and Figure 15 As shown, among the alignment marks obtained from the same set of patterns on the mask M, the marks used to achieve bonding alignment can be of complementary shapes, that is, the structure composed of the two has overlapping boundaries in the orthographic projection direction and no gaps within the edges. This helps to more efficiently detect whether the alignment is good.

[0135] The following will use the M1 and M2 alignment marks as an example to illustrate this situation. The same setting can also be used between other pairs of alignment marks used to detect whether two structures are effectively aligned:

[0136] In any of the above embodiments, if Figure 11 and Figure 12 As shown, after the bonded structure A2 is bonded to the first semiconductor structure A1, the orthographic projection of the first alignment mark M1 on the first surface S1 falls within the range defined by the orthographic projection of the second alignment mark M2 on the first surface S1, and the boundary of one coincides with the boundary of the other.

[0137] In some specific embodiments, Figure 14 As shown, the shapes of a pair of alignment marks used to detect whether the alignment is good during the bonding process may include but are not limited to Figure 14 For example, a pair of marks shown in Figures (a1) and (a2), a pair of marks shown in Figures (b1) and (b2), a pair of marks shown in Figures (c1) and (c2), a pair of marks shown in Figures (d1) and (d2), a pair of marks shown in Figures (e1) and (e2), etc. Any pair of alignment marks helps improve the efficiency of detecting whether the alignment is good.

[0138] In some embodiments, the size range of the first alignment mark M2 can be between 20μm and 80μm (including the endpoint values), for example, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, etc.

[0139] It is understandable that the size ranges of other alignment marks may also be within the above ranges, which will not be described in detail here.

[0140] It should be noted that the methods for fabricating the semiconductor structures provided in the embodiments of the present disclosure can be applied to any integrated circuit comprising the structure, including but not limited to vertical integration of processed integrated circuits for 3D SOCs, micro-pad packaging, low-cost and high-performance flip-chip replacement, wafer-level packaging, thermal management, and unique device structures (e.g., metal-based devices). Applications further include but are not limited to integrated circuits (e.g., backside-illuminated image sensors), RF front-ends, micro-electromechanical structures (MEMS) (e.g., pico-projectors and gyroscopes), 3D stacked memory (e.g., hybrid memory blocks), high-bandwidth memory, DIRAM, 2.5D (e.g., tilted FPGAs on an insert), and products incorporating these circuits (e.g., mobile phones and other mobile devices, laptops, and servers).

[0141] The various technical features in the technical solutions described in the various embodiments may be arbitrarily combined unless they conflict. Those skilled in the art will be able to change the order of the steps in the above-mentioned formation method without departing from the scope of protection of this disclosure. The various steps in the embodiments of this disclosure may be performed simultaneously or sequentially unless they conflict.

[0142] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: A first semiconductor structure is provided, comprising: Providing a first wafer, wherein the first wafer includes a plurality of first chips, and first dicing streets are provided between the plurality of first chips; forming a first dielectric layer and a first groove and a second groove in the first dielectric layer on the first surface of the first wafer, wherein an orthographic projection of the first groove on the first surface is within a range defined by an orthographic projection of the first dicing street on the first surface; performing a filling process on the first groove and the second groove in the same process step to form a first alignment mark in the first groove and a first contact pad in the second groove, wherein the first contact pad is connected to the first chip; Providing a plurality of second chip structures, and bonding the second chip structures to the first chips on the side of the first wafer provided with the first alignment mark to form the first semiconductor structure; A structure to be bonded is provided, on which a second alignment mark corresponding to the first alignment mark is formed; and based on an alignment operation between the first alignment mark and the second alignment mark, the first semiconductor structure is bonded to the structure to be bonded.

2. The method according to claim 1, characterized in that The first semiconductor structure is provided, further comprising: providing a carrier board, and forming a third alignment mark on the carrier board; forming a fourth alignment mark corresponding to the third alignment mark on the second surface of the first wafer; wherein the first surface and the second surface are two surfaces of the first wafer disposed opposite to each other; Based on an alignment operation between the third alignment mark and the fourth alignment mark, the carrier is bonded to a side of the first wafer away from the first alignment mark.

3. The method according to claim 1, characterized in that The first semiconductor structure is provided, further comprising: providing a carrier board, and forming a third alignment mark on the carrier board; Providing a second wafer, wherein the second wafer includes a plurality of third chips; A fifth alignment mark and a sixth alignment mark are formed on two oppositely disposed surfaces of the second wafer; wherein the fifth alignment mark is disposed corresponding to the third alignment mark, forming a fourth alignment mark on the second surface of the first wafer, wherein the sixth alignment mark is arranged corresponding to the fourth alignment mark; The carrier is bonded to the second wafer based on an alignment operation between the third alignment mark and the fifth alignment mark, and the second wafer is bonded to the first wafer based on an alignment operation between the sixth alignment mark and the fourth alignment mark.

4. The method according to claim 1, wherein Providing a plurality of the second chip structures includes: providing an initial structure comprising a plurality of second chips; forming a second dielectric layer on the initial structure, wherein the second dielectric layer covers the surface of the initial structure; forming a second contact pad in the second dielectric layer, wherein the second contact pad is connected to the second chip; A sawing process is performed to separate the initial structure into a plurality of second chip structures.

5. The method according to claim 4, characterized in that Bonding the second chip structure to a side of the first wafer provided with a first alignment mark includes: The first dielectric layer and the second dielectric layer are bonded correspondingly, and the first contact pad and the second contact pad are bonded correspondingly.

6. The method according to claim 1, wherein After bonding the second chip structure to the side of the first wafer provided with the first alignment mark, the preparation method further includes: A third dielectric layer is formed, wherein the third dielectric layer at least fills the gaps between adjacent second chip structures.

7. The method according to claim 3, characterized in that The patterns of the first alignment mark, the second alignment mark, the third alignment mark, the fourth alignment mark, the fifth alignment mark, and the sixth alignment mark are formed by using the same mask.

8. The method according to claim 7, characterized in that Among the patterns for forming the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark on the same mask, the number of at least one of them may include plural.

9. The method according to any one of claims 1 to 8, characterized in that: After bonding the structure to be bonded to the first semiconductor structure, the orthographic projection of the first alignment mark on the first surface falls within the range defined by the orthographic projection of the second alignment mark on the first surface, and the boundary of one coincides with the boundary of the other.

10. The method according to claim 8, characterized in that The size of the first alignment mark ranges from 20 μm to 80 μm.

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