Semiconductor device and method for manufacturing semiconductor device

Abstract

The embodiment provides a semiconductor device and a method for manufacturing the semiconductor device, wherein metal layers with different thicknesses can be formed at the final stage of a wiring process. According to one embodiment, a semiconductor device includes: a transistor; and a plurality of metal layers respectively disposed in the plurality of layers stacked above the transistor, the plurality of metal layers including: a first metal layer disposed in the lowermost layer among the plurality of layers; a second metal layer that is disposed on the uppermost layer among the plurality of layers and that is thicker than the first metal layer; and a third metal layer disposed on the uppermost layer body and thicker than the second metal layer.

Description

[0001] Reference to related applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-156365 (filing date: September 21, 2023) as a basic application. The present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] When manufacturing semiconductor devices, a thick metal layer is sometimes formed by electrolytic plating at the final stage of the wiring process. The thick metal layer can be used as a rewiring layer to change the lead position of the lower layer wiring or as an electrode pad to which a bonding wire can be connected.

[0005] However, since the rewiring layer for rewiring the lower-layer wiring also becomes thick, the wiring size increases, which sometimes hinders the miniaturization of the semiconductor device. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can form metal layers of different thicknesses in the final stage of a wiring process.

[0007] A semiconductor device of an embodiment comprises: a transistor; and a plurality of metal layers, respectively arranged in a plurality of layer bodies stacked above the transistor, the plurality of metal layers including: a first metal layer, arranged in a bottom layer body among the plurality of layer bodies; a second metal layer, arranged in an top layer body among the plurality of layer bodies and thicker than the first metal layer; and a third metal layer, arranged in the top layer body and thicker than the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic diagram showing an example of the structure of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a cross-sectional view showing an example of the structure of a layer body of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a cross-sectional view showing an example of the procedure of the method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 4 This is a cross-sectional view showing an example of the procedure of the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 5 It is a cross-sectional view showing an example of a method for forming a wiring layer of a semiconductor device according to a comparative example.

[0013] Figure 6 This is a diagram showing an example of the structure of a semiconductor device according to the second embodiment.

[0014] Figure 7 This is a diagram showing an example of the sequence of the method for manufacturing a semiconductor device according to the second embodiment.

[0015] Figure 8 This is a diagram showing an example of the sequence of the method for manufacturing a semiconductor device according to the second embodiment.

[0016] Fig. 9 This is a diagram showing an example of the sequence of the method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, referring to the attached Figure 1 The present invention is not limited to the following embodiments. The components in the following embodiments include components that can be easily conceived by a person skilled in the art or components that are substantially the same.

[0018] [Implementation Method 1]

[0019] Hereinafter, Embodiment 1 will be described in detail with reference to the drawings.

[0020] (Configuration Example of Semiconductor Device)

[0021] Figure 1 FIG. 1 is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a semiconductor substrate 10, a plurality of transistors TR, and a plurality of layer bodies M0 to M4, R0, R1, etc. However, these layer bodies M0 to M4, R0, R1, etc. are illustrative only, and the number of layer bodies included in the semiconductor device 1 is arbitrary.

[0022] The semiconductor substrate 10 is a silicon substrate or the like.

[0023] The plurality of transistors TR are provided on, for example, a semiconductor substrate 10. These transistors TR are field effect transistors (FET: Field-Effect Transistor) and the like, and may be configured as, for example, double-diffused Metal-Oxide-Semiconductor Field Effect Transistors (DMOS FET (Double-diffused Metal-Oxide-Semiconductor FET) and the like.

[0024] These transistors TR are covered by an insulating layer 20 such as a silicon oxide layer. Contacts 21 and wiring layers 22 connected to these transistors TR are arranged in the insulating layer 20. At least a portion of the insulating layer 20 and the contacts 21 and the wiring layer 22, at least the wiring layer 22 belongs to the layer body M0 above the transistor TR. The contacts 21 and the wiring layer 22 are, for example, metal layers including a tungsten layer or the like.

[0025] The above-mentioned multiple layers M0 to M4, R0, R1, etc. including the bottom layer M0 are sequentially arranged above the transistor TR, and have multiple vias 31, 33, 41, 43, VA and multiple wiring layers 22, 32, 34, 42, 44, WA, WB, etc. The design rule of these layers M0 to M4, R0, R1 is to gradually enlarge from the lower layer side close to the transistor TR to the upper layer side. As an example, the diameter, extension direction length and spacing of the contact 21 directly connected to the transistor TR and the vias 31, 33, 41, 43, VA, etc. on the upper layer become larger as they are closer to the upper layer side, and the width, thickness and spacing of the wiring layers 22, 32, 34, 42, 44, WA, WB, etc. become larger as they are closer to the upper layer side.

[0026] The layers M1 and M2 are sequentially arranged on the bottom layer M0. The layer M1 is provided with a via 31 and a wiring layer 32 connected to the wiring layer 22 of the layer M0, and an insulating layer 30a including these vias 31 and wiring layers 32. Similarly, the layer M2 is provided with a via 33 and a wiring layer 34 connected to the wiring layer 32 of the layer M1, and an insulating layer 30b including them.

[0027] The insulating layers 30a and 30b are, for example, silicon oxide layers. Hereinafter, these insulating layers 30a and 30b are sometimes collectively referred to as insulating layers 30, etc. The vias 31 and 33 and the wiring layers 32 and 34 are, for example, metal layers including a Cu layer, etc. In addition, these vias 31 and 33 and the wiring layers 32 and 34, etc., for example, electrically connect a plurality of transistors TR to each other, and are also referred to as local interconnects, etc.

[0028] Layers M3 and M4 are sequentially arranged on layer M2. Layer M3 is provided with vias 41 and wiring layers 42 connected to wiring layers 34 and the like of layer M2, and an insulating layer 40a including them, and layer M4 is provided with vias 43 and wiring layers 44 connected to wiring layers 42 and the like of layer M3, and an insulating layer 40b including them.

[0029] The insulating layers 40a and 40b are, for example, silicon oxide layers, etc. The vias 41 and 43 and the wiring layers 42 and 44 are, for example, metal layers including Cu layers, etc. In addition, these vias 41 and 43 and the wiring layers 42 and 44, for example, electrically connect circuits composed of a plurality of transistors TR to each other, and are also called global interconnects, etc.

[0030] Layer bodies R0 and R1 are sequentially arranged on layer body M4. Layer body R0 is provided with a via VA connected to wiring layer 44 of layer body M4 and the like and an insulating layer 40c including via VA and the like. Layer body R1 is the uppermost layer among multiple layer bodies M0 to M4, R0, R1, etc., and layer body R1 is provided with a wiring layer WA connected to via VA of layer body R0, a wiring layer WB thicker than wiring layer WA, and an insulating layer 50 including wiring layers WA, WB, etc. The insulating layer 50 has an opening, and the upper surface of wiring layer WB is exposed from the opening.

[0031] The insulating layer 40c is, for example, a silicon oxide layer, etc. Hereinafter, the insulating layers 40a to 40c may be collectively referred to as the insulating layer 40, etc. The insulating layer 50 is, for example, a polyimide layer, etc.

[0032] The via VA and the wiring layers WA and WB are metal layers including, for example, Cu layers, etc. The via VA and the wiring layers WA and WB are also called, for example, a re-distribution layer (RDL) formed using a re-distribution layer formation technology as described below.

[0033] However, in the semiconductor device 1 of the first embodiment, the wiring layer WB of the wiring layers WA and WB functions as an electrode pad that can be connected to an external device, etc. On the other hand, the wiring layer WA functions as a so-called rewiring layer in a narrow sense that changes the lead-out position of the wiring layer 44 of the underlying layer body M4, etc.

[0034] In addition, as mentioned above, Figure 1 The structure of the semiconductor device 1 shown is an example, and the number and combination of layers included in the semiconductor device 1 are not limited to the above. Figure 1 For example, the semiconductor device 1 may also include an intermediate wiring layer, a semi-global wiring layer, etc. between the local interconnection and the global interconnection. In this case, the design rules in the intermediate wiring layer and the semi-global wiring layer have values ​​between the design rules of the local interconnection and the global interconnection, and the intermediate wiring layer and the semi-global wiring layer may also have the same design rules.

[0035] In addition, Figure 1 In the example shown, vias 31, 33, 41, 43, VA, etc. and their corresponding wiring layers 32, 34, 42, 44, WA, WB, etc. are depicted as different structures, but as described later, these vias 31, 33, 41, 43, VA, etc. and their corresponding wiring layers 32, 34, 42, 44, WA, WB, etc. may be formed separately or together. When a predetermined via and its corresponding wiring layer are formed together, these vias and wiring layers can be observed as an integrated structure.

[0036] Figure 2 This is a cross-sectional view showing an example of the structure of layer bodies R0 and R1 of the semiconductor device 1 according to the first embodiment.

[0037] like Figure 2 As shown, a plurality of vias 43, a plurality of wiring layers 44, and a plurality of vias VA are sequentially provided in the insulating layer 40. Figure 2 The insulating layer 40 shown above Figure 1 At least a part of the insulating layers 40b and 40c is included therein. The plurality of vias 43 are connected to any one of the plurality of wiring layers 44, and the plurality of wiring layers 44 are connected to any one of the plurality of vias VA.

[0038] An insulating layer 50 is disposed on the insulating layer 40 . The insulating layer 50 is the uppermost layer of the semiconductor device 1 and has an opening 50 p . Each of the plurality of vias VA is connected to one of the wiring layers WA and WB included in the insulating layer 50 .

[0039] More specifically, the wiring layers WA and WB are arranged on the insulating layer 40, which belongs to the layer body M4 and R0 of the lower layer of the layer body R1 to which the wiring layers WA and WB belong. The wiring layer WA as the second metal layer is entirely buried in the insulating layer 50, and at least a portion of the upper surface of the wiring layer WB as the third metal layer is exposed from the opening 50p of the insulating layer 50. In addition, the insulating layer 50 may have unevenness on the upper surface along the unevenness of these wiring layers WA and WB.

[0040] The wiring layer WA is configured to be at least higher than the wiring layer 22 (see FIG. 1 ) which is the first metal layer in the lowermost layer body M0. Figure 1 ) and may be configured to be thicker than the wiring layer 44 included in the insulating layer 40. The wiring layer WB is thicker than the wiring layer WA and has a thickness of 40 times or more that of the wiring layer 22 in the lowermost layer body M0.

[0041] For example, even when the process node is reduced to 130nm, 90nm, 65nm, or 40nm, as an example, the wiring layer WA may have a thickness of about 5μm, and the wiring layer WB may have a thickness of more than 10μm. In addition, for example, when the process node is 130nm, it means that the gate length of the transistor TR is 130nm.

[0042] In this way, even when the process node is gradually reduced, the thickness of the wiring layers WA and WB can be maintained at about 5μm and more than 10μm, respectively. This is because the wiring layers WA and WB are formed using a different rewiring layer formation technology from the wiring layers 22, 32, 34, 42, 44, etc. of the lower layer bodies M0 to M4 as described later, so about 5μm as the thickness of the wiring layer WA becomes a thickness close to the minimum processing size. In addition, as described later, the wiring layer WB requires a predetermined strength, so it is preferable to maintain a thickness of more than 10μm.

[0043] On the other hand, as the process node is reduced to 130nm, 90nm, 65nm, and 40nm, and the thickness of the wiring layer 22 in the bottom layer M0 is gradually reduced, the wiring layer WB having a thickness of 10μm or more has a thickness of, for example, 50 to 77 times that of these wiring layers 22. In this way, the wiring layer WB can have a thickness of, for example, 40 times or more, and more preferably, a thickness of 40 times or more and 80 times or less, relative to the thickness of the wiring layer 22.

[0044] The wiring layers WA and WB and the vias VA connected to the wiring layers WA and WB have a plating layer 52 as a first layer and a barrier metal layer 51 as a second layer.

[0045] The plating layer 52 is, for example, a Cu layer formed by electrolytic plating using a seed layer (not shown) provided on the barrier metal layer 51 as an electrode, and corresponds to the core material of the via VA and the main body of the wiring layer WA. The plating layer 52 is continuously provided over the via VA and the wiring layer WA.

[0046] The barrier metal layer 51 is a layer containing a metal different from the plating layer 52, such as a Ti layer or a TiW layer, and is provided on the lower surface of the wiring layers WA and WB, except for the portion connected to the via VA, and the side and bottom surfaces of the via VA. The barrier metal layer 51 is continuously provided from the lower surface of the wiring layers WA and WB to the side and bottom surfaces of the via VA. Thus, the barrier metal layer 51 can suppress the barrier metal layer 51 and the plating layer 52, which are Cu layers, from diffusing into the insulating layer 40, etc. In addition, as described later, the barrier metal layer 51 can be processed, for example, by wet etching, and thus can also have a side etching shape with a narrower width than the plating layer 52 portion of the wiring layers WA and WB.

[0047] In addition, as described above, a seed layer (not shown) is arranged between the barrier metal layer 51 and the plating layer 52. That is, the seed layer is provided on the lower surface of the wiring layers WA and WB except for the portion connected to the via VA and the side and bottom surfaces of the via VA, that is, the inner side of the barrier metal layer 51. The seed layer is, for example, a Cu layer or the like, which is the same as the plating layer 52, and becomes an electrode when the plating layer 52, which is a Cu layer or the like, is formed by electrolytic plating.

[0048] In addition, the wiring layer WB further includes a cover layer 53 as a third layer on the surface exposed from the opening 50p of the insulating layer 50 on the plating layer 52. The cover layer 53 is composed of a metal different from the plating layer 52, for example, a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer. The outer edge of the cover layer 53 is covered and protected by the insulating layer 50.

[0049] In addition, the upper surface of the wiring layer WB including the cover layer 53 may not be flat, but may have an arc shape with an outer edge having an arc. In addition, the outer edge of the cover layer 53 may protrude from the outer edge of the plating layer 52. Even if the cover layer 53 has such a shape, the stress concentration at the end of the wiring layer WB of the insulating layer 50 protecting the outer edge of the wiring layer WB is also alleviated by the wiring layer WB becoming an arc shape, and the film peeling of the insulating layer 50 is suppressed.

[0050] Wiring layer WB functions as, for example, an electrode pad connected to an external device of semiconductor device 1. As described above, by providing cover layer 53 on the upper surface of wiring layer WB, for example, a bonding wire can be connected to wiring layer WB using cover layer 53 as a bonding layer.

[0051] In contrast, the wiring layer WA functions as a rewiring layer for changing the lead-out position of the lower wiring layer 44, etc., as described above. The wiring layer WA is configured to be thinner than the wiring layer WB, so a finer design rule than the wiring layer WB can be applied. That is, in addition to the thickness of the wiring layer WA, the width and pitch, etc. can also be configured to be finer than the wiring layer WB.

[0052] In addition, when the plating layer 52 of the wiring layer WA, WB is set as a Cu layer, Cu is an example of the first metal. In addition, when the cover layer 53 of the wiring layer WB is set as a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer, these metals used for the cover layer 53 are an example of the second metal.

[0053] (Method for manufacturing semiconductor device)

[0054] Next, use Figure 3 as well as Figure 4 , an example of a method for manufacturing the semiconductor device 1 according to the first embodiment is described. Figure 3 as well as Figure 4 This is a cross-sectional view showing an example of the procedure of the method for manufacturing the semiconductor device 1 according to the first embodiment.

[0055] in addition, Figure 3 as well as Figure 4 The following mainly describes a method for forming various structures in the layer bodies R0 and R1 of the semiconductor device 1. Various structures in the layer bodies M0 to M4 below the layer bodies R0 and R1 and the transistor TR can be formed by a general semiconductor process.

[0056] That is, refer to Figure 1 A gate insulating layer and a gate electrode are formed on the semiconductor substrate 10, and a predetermined conductive type impurity is diffused into the semiconductor substrate 10 to form a source / drain region, thereby forming a transistor TR. In addition, an insulating layer 20 is formed to cover the transistor TR.

[0057] The processes up to this point are also referred to as, for example, substrate processes (FEOL: Front End of Line), etc. On the other hand, the processes thereafter are also referred to as wiring processes (BEOL: Back End of Line), etc.

[0058] In the wiring process, when forming various structures on the layers M0 to M4, precision processing processes such as plasma etching and CVD (Chemical Vapor Deposition) are specifically used. That is, contact holes and wiring grooves are formed on the insulating layer 20 of the layer M0, and contacts 21 and wiring layers 22 are formed in these contact holes and wiring grooves. In addition, in the upper layers M1 to M4, while insulating layers 30a, 30b, 40a, 40b, etc. are formed, through holes and wiring grooves are formed in them in sequence, and passages 31, 33, 41, 43 and wiring layers 32, 34, 42, 44, etc. are gradually formed in the through holes and wiring grooves.

[0059] In addition, to explain in more detail, as a method of forming them, when a Cu layer is used as a metal layer, there are a single inlay method or a dual inlay method, and the single inlay method is to form vias 31, 33, 41, 43, etc. and their corresponding wiring layers 32, 34, 42, 44, etc. separately, and the dual inlay method is to form these vias 31, 33, 41, 43 and wiring layers 32, 34, 42, 44, etc. together.

[0060] For example, if a combination of via 31 and wiring layer 32 is taken as an example, in a single damascene method, a through hole is formed and a metal layer is filled in the through hole to form via 31, and then a wiring groove is formed on the formed via 31, and a metal layer is filled in the wiring groove to form wiring layer 32.

[0061] On the other hand, in the dual damascene method, after forming the through hole and the wiring groove, they are filled with a metal layer to form the via 31 and the wiring layer 32 at the same time.

[0062] In addition, when forming a through hole and a wiring groove by a dual inlay method, the main method used is to expand the upper end of the through hole to form a wiring groove after the through hole is formed (a hole first method), and to form a through hole extending from the bottom surface of the wiring groove in the depth direction after the wiring groove is formed (a trench first method).

[0063] In the semiconductor device 1 of embodiment 1, the vias 31, 33, 41, 43 and the wiring layers 32, 34, 42, 44, etc. can be formed, for example, by any of the above-mentioned methods. In addition, for example, different formation methods can be used in different layer bodies. In addition, Al layers, Al-Si-Cu layers, etc. can also be used as wiring materials.

[0064] The step of forming vias VA and wiring layers WA, WB in layer bodies R0, R1 corresponds to the final stage of the wiring step and is performed as follows using a low-load and inexpensive process such as lift-off using photolithography or electrolytic plating.

[0065] like Figure 3 As shown in (a), the via 43 and the wiring layer 44 are already formed in the insulating layer 40.

[0066] like Figure 3 As shown in (b), the insulating layer 40 is processed to form a plurality of through holes VH reaching the wiring layer 44.

[0067] like Figure 3 As shown in (c), a barrier metal layer 51b and a seed layer are sequentially formed on the surface of the insulating layer 40 and the side and bottom surfaces of the through hole VH. The barrier metal layer 51b is formed in the through hole VH by, for example, sputtering a target material such as Ti or TiW. The seed layer is formed on the barrier metal layer 51b by, for example, sputtering a target material such as Cu.

[0068] When the barrier metal layer 51b and the seed layer are formed by sputtering or the like, it is preferred that the barrier metal layer 51b and the seed layer be continuously formed while the semiconductor substrate 10 to be processed is kept under vacuum. In addition, as the barrier metal layer 51b, it is preferred that a material having a barrier property with respect to Cu or the like in the seed layer and the plating layer 52 to be formed later and having a high adhesion to the insulating layer 50 be used. The above-mentioned Ti or TiW or the like satisfies these conditions.

[0069] like Figure 3As shown in (d), a mask pattern 71 as a first mask pattern such as a photoresist layer is formed to cover the insulating layer 40 and the barrier metal layer 51b on the insulating layer 40. The mask pattern 71 has a plurality of openings OA and OBa as second and first openings at the formation position of the through hole VH.

[0070] like Figure 3 As shown in (e), the seed layer on the barrier metal layer 51b exposed at the openings OA and Oba of the mask pattern 71 is used as an electrode to form a plating layer 52 such as a Cu layer by electrolytic plating. The plating layer 52 as the first layer is formed to be thicker than at least the wiring layer 32 of the lowest layer body M0, and further, is formed to be thicker than the wiring layer 44 in the insulating layer 40 formed in the lower layer of the layer body R0.

[0071] In addition, the plating layer 52 and the like formed in the opening OA in the openings OA and OBa will later become the wiring layer WA functioning as a rewiring layer. Therefore, the opening OA of the mask pattern 71 is formed at a position where the lead-out position of the wiring layer 44 is changed, so that the wiring layer WA can rewire the wiring layer 44 of the lower layer.

[0072] like Figure 3 As shown in (f) , the mask pattern 71 is removed by ashing using oxygen plasma or the like.

[0073] In addition, as described above, the process of forming a wiring pattern or the like using the mask pattern 71 or the like as a mold is also referred to as lift-off or the like.

[0074] like Figure 3 As shown in (g), a mask pattern 72 as a second mask pattern such as a photoresist layer is formed in a manner covering the insulating layer 40 and the barrier metal layer 51b on the insulating layer 40 and a portion of the plating layer 52. The mask pattern 72 has an opening portion OBb as a third opening portion at a position overlapping with the opening portion OBa of the mask pattern 71 described above.

[0075] Thus, the plated layer 52 and the like formed in the opening OA of the mask pattern 71 are covered by the mask pattern 72. In addition, the plated layer 52 is exposed from the opening OBb. At this time, from the perspective of the alignment accuracy of the mask pattern 72 with respect to the plated layer 52, the opening OBb of the mask pattern 72 is preferably formed larger than the opening OBa of the mask pattern 71.

[0076] like Figure 4As shown in (a), the plated layer 52 exposed at the opening OB of the mask pattern 72 is used as an electrode, and the Cu layer is formed thicker by electrolytic plating. In the opening OBb, the thickened plated layer 52 has a thickness of more than 40 times that of the wiring layer 22 of the bottom layer body M0. In addition, the opening OBb of the mask pattern 72 is formed to be larger than the opening OBa of the mask pattern 71, and the plated layer 52 formed with a size smaller than the opening OBb is further electrolytically plated as a base. Therefore, the upper end of the thickened plated layer 52 can be made into an arc shape.

[0077] like Figure 4 As shown in (b), a cover layer 53 as a second layer such as a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer is formed on the thick film plating layer 52 formed in the opening portion OBb of the mask pattern 72 by, for example, electroless plating.

[0078] like Figure 4 As shown in (c), the mask pattern 72 is removed by ashing using oxygen plasma or the like.

[0079] like Figure 4 As shown in (d), the seed layer and barrier metal layer 51b (not shown) are removed from the surface of the insulating layer 40 that is not covered by the plating layer 52, etc. by wet etching, etc. Thus, the seed layer and barrier metal layer 51 having the pattern of the wiring layers WA and WB are formed, and the wiring layer WA having a thin layer without the covering layer 53 and the wiring layer WB having the covering layer 53 and being a thick film are formed.

[0080] Furthermore, when the barrier metal layer 51 and the like are wet-etched, in addition to side etching occurring in the seed layer and the barrier metal layer 51, a portion of the plating layer 52 on the barrier metal layer 51 is also etched. As a result, the width of the plating layer 52 is reduced, and the cover layer 53 on the plating layer 52 may be formed to protrude from the end of the plating layer 52 in an eave-like shape.

[0081] like Figure 4 As shown in (e), an opening 50p is provided at the formation position of the wiring layer WB, and an insulating layer 50 such as a polyimide layer is formed to cover the insulating layer 40 including the wiring layer WA. At this time, the upper surface of the insulating layer 50 may also be uneven depending on the wiring layers WA and WB.

[0082] As described above, the semiconductor device 1 according to the first embodiment is manufactured.

[0083] (Comparative Example)

[0084] Next, use Figure 5 , an example in which wiring layers WAx and WBx of a comparative example are formed will be described.

[0085] Figure 5 FIG. 1 is a cross-sectional view showing an example of a method for forming wiring layers WAx and WBx of a semiconductor device according to a comparative example. Figure 5 As shown, in the process of forming the rewiring layer by lift-off using photolithography or the like and electrolytic plating or the like, it is difficult to make the thicknesses of the wiring layers WAx and WBx different, and these wiring layers WAx and WBx are formed to have a single thickness.

[0086] That is, Figure 5 As shown in (a), a barrier metal layer 51xb is formed, as shown in Figure 5 As shown in (b), a mask pattern 77 covering the barrier metal layer 51xb is formed, and a plating layer 52x is formed at the openings OAx and OBx of the mask pattern 77. Figure 5 As shown in (c), a cover layer 53x is further formed. Figure 5 After removing the mask pattern 77 as shown in (d), Figure 5 As shown in (e), the exposed portion of the barrier metal layer 51xb and the like is removed, thereby forming wiring layers WAx and WBx having the same thickness. Figure 5 As shown in (f), the insulating layer 50x is formed by covering the wiring layer WAx and exposing the upper surface of the wiring layer WBx.

[0087] Thus, a wiring layer WAx functioning as a rewiring layer and a wiring layer WBx functioning as an electrode pad are formed.

[0088] Thus, in the semiconductor device of the comparative example, for example, a wiring layer WAx that functions as a rewiring layer is formed to match the thickness of the wiring layer WBx that functions as an electrode pad. Therefore, the enlarged design rule for thick film process is also applied to the wiring layer WAx, making it difficult to miniaturize the wiring layer WAx. This becomes a factor that hinders the miniaturization of semiconductor devices.

[0089] In addition, the cover layer 53x that becomes the bonding layer for bonding with the bonding wire is also formed on the wiring layer WAx that does not require a bonding layer, resulting in an increase in process cost. Moreover, for thick film wiring patterns, there is a risk of film peeling of the insulating layer 50x that becomes the protective layer of these. Therefore, in order to ensure the bonding reliability of the bonding and improve the yield rate, appearance inspection is indispensable. Since the wiring layers WAx and WBx are both formed as thick films, the total number of these inspections also increases, further increasing the process cost.

[0090] Therefore, it is considered to separately form a wiring layer WAx as a rewiring layer in a layer body below the wiring layer WBx as an electrode pad. However, the increase in the number of layers of the semiconductor device eventually leads to an increase in manufacturing load and process cost.

[0091] According to the semiconductor device 1 of embodiment 1, it includes: a wiring layer 22, which is arranged in the bottom layer M0 among multiple layer bodies M0~M4, R0, and R1; a wiring layer WA, which is arranged in the top layer R1 and is thicker than the wiring layer 22; and a wiring layer WB, which is arranged in the top layer R1 and is thicker than the wiring layer WA and has a thickness more than 40 times that of the wiring layer 22.

[0092] In this way, wiring layers WA and WB having different thicknesses can be formed at the final stage of the wiring process.

[0093] In addition, by setting the wiring layer WB to be, for example, 40 times thicker than the wiring layer 22, when the wiring layer WB functions as an electrode pad connected to the bonding wire, the on-resistance can be reduced and the output of the transistor TR can be improved. In addition, in addition to improving the heat dissipation characteristics of the wiring layer WB and improving the breakdown resistance, it is also possible to suppress damage to the underlying layer bodies M0 to M4 and the like due to the load when bonding with the bonding wire.

[0094] On the other hand, by making the wiring layer WA functioning as a rewiring layer thin, for example, more detailed design rules can be applied to the wiring layer WA without increasing the number of layers of the semiconductor device 1. This reduces process costs and facilitates miniaturization of the semiconductor device 1.

[0095] As described above, it is possible to achieve a balance between the two different requirements of improving device characteristics due to thickening of the film and reducing the design rule.

[0096] According to the semiconductor device 1 of the first embodiment, the wiring layer WB has the upper surface exposed from the opening 50p of the insulating layer 50. Thus, the wiring layer WB can function as an electrode pad.

[0097] According to the semiconductor device 1 of embodiment 1, the wiring layer WA includes: a plating layer 52 containing a metal such as Cu and a barrier metal layer 51 containing a metal different from the plating layer 52 and arranged on the lower side of the plating layer 52, and a covering layer 53 containing a metal such as Ti or TiW different from the metal of the plating layer 52 and arranged on the upper side of the plating layer 52 is selectively arranged on the plating layer 52 of the wiring layer WB.

[0098] In this way, the cover layer 53 is formed only on the wiring layer WB, and the wiring layer WA does not have an unnecessary cover layer 53 , thereby further reducing the process cost.

[0099] [Implementation Method 2]

[0100] Embodiment 2 will be described in detail below with reference to the drawings. The semiconductor device of Embodiment 2 is different from the above-described Embodiment 1 in that a part of the wiring layer is not formed in contact with the lower layer.

[0101] In the following drawings, the same components as those in the first embodiment are denoted by the same reference numerals and their description may be omitted.

[0102] (Configuration Example of Semiconductor Device)

[0103] Figure 6 FIG. 1 is a diagram showing an example of a configuration of a semiconductor device according to Embodiment 2. More specifically, Figure 6 (a) is a cross-sectional view showing a portion of a topmost layer body of a semiconductor device according to Embodiment 2. Figure 6 (b) is a top view of the uppermost layer of the semiconductor device of Embodiment 2. Figure 6 In (b), the structure covered by the insulating layer 50 is shown through the insulating layer 50.

[0104] like Figure 6 As shown, in the semiconductor device of Embodiment 2, the insulating layer 50 is arranged in the uppermost layer, and the insulating layer 40 is arranged in the lower layer of the uppermost layer. The insulating layer 40 includes a via 45 and a wiring layer 46 which are arranged in the lower layer of the uppermost layer.

[0105] In addition, a plurality of vias VB connected to the wiring layer 46 are arranged in the insulating layer 40, and these vias VB are connected to the wiring layer WD arranged in the insulating layer 50 which is the uppermost layer. The insulating layer 50 also has a wiring layer CB arranged therein.

[0106] The wiring layer CB as the second metal layer has, when viewed from the upper surface, a curved shape in which thin lines repeatedly meander, for example, and is arranged above the insulating layer 40 without being in contact with the lower insulating layer 40. Thus, the wiring layer CB is arranged inside the insulating layer 50 in a state separated from the insulating layer 40, for example. However, the wiring layer CB may also have a comb-tooth shape or a diaphragm shape. In either case, the wiring layer CB is configured with a dedicated intermediate layer 57.

[0107] Wiring layer WD as the third metal layer has, for example, a pad shape when viewed from the top surface, and a portion of the top surface is exposed from opening 50p of insulating layer 50. Wiring layer WD also has a thickness 40 times that of the wiring layer of the lowermost layer, more preferably 40 times or more and 80 times or less.

[0108] In addition, the wiring layer WD has a structure in which a barrier metal layer 55 as a second layer, a plating layer 56 as a first layer, and a cover layer 58 are stacked in this order. In addition, the wiring layer WD has an intermediate layer 57 as a third layer sandwiched in the plating layer 56, and a seed layer (not shown) sandwiched between the barrier metal layer 55 and the plating layer 56.

[0109] The barrier metal layer 55 is the same as the barrier metal layer 51 described above, for example, a Ti layer or a TiW layer. The seed layer and the plating layer 56 not shown are the same as the seed layer and the plating layer 52 described above, for example, a Cu layer, etc. In this case, Cu is an example of the first metal. The intermediate layer 57 is, for example, a Si layer or a Pd layer, etc. In this case, Si or Pd is an example of the second metal. The cover layer 58 is the same as the cover layer 53 described above, for example, a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer, etc.

[0110] The intermediate layer 57 of the wiring layer WD is connected to the intermediate layer 57 of the wiring layer CB, whereby the wiring layer WD functions as an anchor for supporting the wiring layer WA disposed above the insulating layer 40. The wiring layer WD may also function as an electrode pad.

[0111] The wiring layer WD is arranged on one side or both sides of the wiring layer CB to support the wiring layer CB, and the wiring layer CB has a cantilever beam structure or a beam structure with both ends fixed.

[0112] On the other hand, the thin wiring layer CB functions as an inductor, for example. Alternatively, the thin wiring layer CB may function as a sensor for sensing pressure, gas, or sound waves in the environment surrounding the semiconductor device of Embodiment 2, or may function as a movable spring or micromirror. In this case, a gap serving as a movable region of the wiring layer CB may be provided around the wiring layer CB, rather than burying the wiring layer CB in the insulating layer 50.

[0113] As described above, the uppermost layer body portion of the semiconductor device according to the second embodiment can be configured as, for example, an inductor or a MEMS (Micro Electro Mechanical System).

[0114] In addition, in the layer body portion lower than the top layer, the semiconductor device of the second embodiment can have transistors and contacts, vias, wiring layers, etc. connected to the transistors, similarly to the semiconductor device 1 of the above-mentioned embodiment. Such a lower layer portion of the semiconductor device is configured as, for example, a control circuit for controlling an inductor or MEMS of the top layer portion.

[0115] (Method for manufacturing semiconductor device)

[0116] Next, use Figure 7 to Figure 9 , an example of a method for manufacturing a semiconductor device according to embodiment 2 is described. Figure 7 to Figure 9 FIG. 1 is a diagram showing an example of the sequence of a method for manufacturing a semiconductor device according to Embodiment 2. Figure 7 to Figure 9 middle, Figure 7 (e) and Fig. 9 (c) is a top view of a semiconductor device in the process of being manufactured, and the others are cross-sectional views of a semiconductor device in the process of being manufactured.

[0117] in addition, Figure 7 to Figure 9 The following mainly describes a method for forming various structures in the uppermost layer of the semiconductor device according to the second embodiment.

[0118] like Figure 7 As shown in (a) of FIG. 1 , the via 45 and the wiring layer 46 are already formed in the insulating layer 40 .

[0119] like Figure 7 As shown in (b) , the insulating layer 40 is processed to form a plurality of via holes VH reaching the wiring layer 46 .

[0120] like Figure 7 As shown in (c), a barrier metal layer 55b and a seed layer are formed on the surface of the insulating layer 40 and the side and bottom surfaces of the through hole VH by, for example, sputtering. The barrier metal layer 55b and the seed layer are preferably formed continuously.

[0121] like Figure 7 As shown in (d), a mask pattern 73 of a photoresist layer or the like as a first mask pattern is formed in a manner covering the insulating layer 40 and the barrier metal layer 55b on the insulating layer 40. The mask pattern 73 has an opening portion ODa as a second opening portion at a position where the through hole VH is formed, and has an opening portion OC as a first opening portion at a position separated from the opening portion Oda.

[0122] like Figure 7 As shown in (e) of FIG. 7 , the opening OC of the mask pattern 73 has a curved shape in which the opening of the fine groove repeatedly meanders, and a part of the opening OC is connected to the opening ODa.

[0123] like Figure 8 As shown in (a), a plating layer 56 of a metal such as Cu as a first metal is formed by electrolytic plating, etc., using the seed layer on the barrier metal layer 55b exposed in the openings OC and ODa of the mask pattern 73 as an electrode. The plating layer 56 as the first metal layer is formed thicker than at least the wiring layer of the lowermost layer, and further thicker than the wiring layer 46 formed on the lower insulating layer 40.

[0124] like Figure 8As shown in (b), on the plating layer 56 of the openings OC and ODa of the mask pattern 73, for example, a Si layer or a Pd layer is formed as an intermediate layer 57 of the second layer. The Si layer can be formed, for example, by CVD, and the Pd layer can be formed, for example, by electrolytic plating or electroless plating. The metal such as Si or Pd constituting the intermediate layer 57 is an example of the second metal, and has a higher wet etching resistance than the metal constituting the barrier metal layer 55b and the plating layer 56, for example.

[0125] like Figure 8 As shown in (c), the mask pattern 73 is removed by ashing using oxygen plasma or the like.

[0126] like Figure 8 As shown in (d), a mask pattern 74 of a photoresist layer or the like as a second mask pattern is formed in a manner covering the insulating layer 40 and the barrier metal layer 51b on the insulating layer 40 and a portion of the plating layer 52 and the intermediate layer 57. The mask pattern 74 has an opening ODb as a third opening, which is larger than the opening ODa, at a position overlapping with the opening ODa of the mask pattern 73.

[0127] like Figure 8 As shown in (e), the intermediate layer 57 exposed in the opening ODb of the mask pattern 74 is used as an electrode, and a metal such as Cu as a third metal is formed thicker by electrolytic plating. As a result, the plated layer 56 having a smaller size and the intermediate layer 57 as a base is thickened and has an arc-shaped upper surface, and is formed to have a thickness of more than 40 times that of the wiring layer of the lowest layer.

[0128] like Figure 8 As shown in (f), a cover layer 58 such as a NiPd layer, a NiAu layer, a NiPdAu layer, or an Au layer is formed on the thick film plated layer 56 formed in the opening ODb of the mask pattern 74 by, for example, electrolytic plating or electroless plating.

[0129] like Fig. 9 As shown in (a), the mask pattern 74 is removed by ashing using oxygen plasma or the like.

[0130] like Fig. 9 As shown in (b), the barrier metal layer 55b and the seed layer are removed by wet etching or the like from the surface of the insulating layer 40 in the portion not covered by the intermediate layer 57 or the cover layer 58 or the like.

[0131] Thus, in the portion covered by the covering layer 58, a barrier metal layer 55 and a seed layer having a pattern of a wiring layer WD are formed having a side etching shape relative to the upper plating layer 56, and a portion of the plating layer 56 itself is also etched, thereby forming a wiring layer WD that is retreated in the width direction.

[0132] On the other hand, in the portion covered by the intermediate layer 57, the intermediate layer 57 and the plated layer 56 are in the form of thin lines, so the barrier metal layer 55 and the seed layer disappear together with the upper plated layer 56. At this time, the intermediate layer 57 containing a metal having a higher wet etching resistance than the seed layer and the plated layer 56 does not disappear but remains. Thus, a wiring layer CB having the intermediate layer 57 is formed, the intermediate layer 57 being separated upward from the insulating layer 40 and supported by the wiring layer WD. Fig. 9 (c) is shown in a top view.

[0133] like Fig. 9 As shown in (d), an opening 50p is provided at the formation position of the wiring layer WD, and an insulating layer 50 such as a polyimide layer is formed to cover the insulating layer 40 including the wiring layer CB.

[0134] As described above, the semiconductor device of the second embodiment is manufactured.

[0135] (Summary)

[0136] According to the semiconductor device of the second embodiment, the wiring layer CB is arranged above the lower layer body without being in contact with the lower layer body. By configuring the wiring layer CB in this way, a semiconductor device including an inductor or MEMS can be configured at low cost.

[0137] According to the semiconductor device of the second embodiment, the wiring layer CB is composed of a metal such as Si or Pd which is different from the metal of the plating layer 56, and the wiring layer WD includes an intermediate layer 57 in the plating layer 56 and at a height position equal to that of the wiring layer CB, and the intermediate layer 57 contains the above-mentioned metal which is different from the metal of the plating layer 56. By constructing the layers of the wiring layers WD and CB in this way, the wiring layer CB can be constructed in a manner that is not in contact with the layer body of the lower layer but is arranged above the layer body of the lower layer.

[0138] According to the semiconductor device of the second embodiment, the wiring layer WD is connected to the wiring layer CB to form an anchor for supporting the wiring layer CB, and the wiring layer CB has a cantilever beam structure or a fixed beam structure in a comb-shaped, curved, or diaphragm shape. Thus, the wiring layer CB can function as an inductor or a sensor.

[0139] In addition to this, the semiconductor device according to the second embodiment also achieves the same effects as the semiconductor device 1 according to the first embodiment described above.

[0140] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0141] Description of Reference Numerals

[0142] 1…Semiconductor devices

[0143] 10…Semiconductor substrate

[0144] 20, 30, 40, 50…Insulation layer

[0145] 21…Contact

[0146] 22, 32, 34, 42, 44…wiring layers

[0147] 31, 33, 41, 43…passage

[0148] 50p…Opening

[0149] 51, 55…Barrier metal layer

[0150] 52, 56…plating

[0151] 53, 58…covering layer

[0152] 57…Middle layer

[0153] CB, WA, WB, WD…wiring layer

[0154] M0~M4, R0, R1...layer body

[0155] TR…Transistor

[0156] VA, VB…channel

Claims

1. A semiconductor device, wherein: have: transistors; and A plurality of metal layers are respectively arranged on a plurality of layer bodies, and the plurality of layer bodies are stacked above the transistor. The plurality of metal layers comprises: A first metal layer is disposed on the bottommost layer of the plurality of layers; A second metal layer, disposed on the uppermost layer of the plurality of layers and thicker than the first metal layer; as well as The third metal layer is disposed on the uppermost layer and is thicker than the second metal layer.

2. The semiconductor device according to claim 1, wherein The third metal layer has a thickness greater than 40 times that of the first metal layer.

3. The semiconductor device according to claim 1, wherein The third metal layer has an arc shape with a curved outer edge.

4. The semiconductor device according to claim 1, wherein It also has an insulating layer disposed on the uppermost layer and having an opening, The second metal layer is covered by the insulating layer, The third metal layer has an upper surface exposed from the opening.

5. The semiconductor device according to claim 4, wherein: The third metal layer comprises: a first layer, comprising a first metal; a second layer containing a metal different from the first metal and disposed on a lower side of the first layer; and The third layer contains a second metal different from the first metal and is disposed on the first layer.

6. The semiconductor device according to claim 5, wherein: The second metal layer includes: the first layer and the second layer, The third layer is selectively configured on the first layer of the third metal layer among the second metal layer and the third metal layer.

7. The semiconductor device according to claim 4, wherein: At least a portion of a metal layer of a layer body disposed below the uppermost layer body among the plurality of metal layers is electrically connected to the transistor, The second metal layer is a rewiring layer for changing the lead-out position of at least a portion of the metal layer. The third metal layer is an electrode pad that can be connected to an external device.

8. The semiconductor device according to claim 1, wherein The third metal layer is disposed on a layer body below the uppermost layer body, The second metal layer is arranged above the lower layer body without being in contact with the lower layer body.

9. The semiconductor device according to claim 8, wherein: The third metal layer comprises: a first layer comprising a first metal; and The second layer contains a metal different from the first metal and is disposed under the first layer.

10. The semiconductor device according to claim 9, wherein: The second metal layer contains a second metal different from the first metal. The third metal layer further includes a third layer containing the second metal at the same height position in the first layer as that of the second metal layer.

11. The semiconductor device according to claim 8, wherein The third metal layer is connected to the second metal layer to form an anchor supporting the second metal layer. The second metal layer has a cantilever beam structure or a beam structure with fixed ends in a comb-tooth shape, a curved shape, or a diaphragm shape.

12. The semiconductor device according to claim 11, wherein The third metal layer is an electrode pad that can be connected to an external device.

13. A method for manufacturing a semiconductor device, wherein: A transistor is formed on a substrate. A plurality of layers each including a plurality of metal layers are stacked above the transistor. When forming the lowermost layer among the plurality of layers, forming a first metal layer, the first metal layer being a part of the plurality of metal layers and being electrically connected to the transistor, When forming the uppermost layer among the plurality of layers, forming a first mask pattern on a layer body below the uppermost layer body, wherein the first mask pattern has a first opening and a second opening, A second metal layer is formed in the first opening and the second opening by electrolytic plating, wherein the second metal layer is a part of the plurality of metal layers and is thicker than the first metal layer. forming a second mask pattern on the lower layer, wherein the second mask pattern has a third opening at a position overlapping the first opening, Electrolytic plating is further performed on the second metal layer exposed from the third opening to form a third metal layer in the third opening. The third metal layer is a part of the plurality of metal layers and is obtained after the second metal layer becomes a thick film.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The third metal layer has a thickness greater than 40 times that of the first metal layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: When forming the second metal layer, By the electrolytic plating, a first layer containing a first metal is formed in the first opening and the second opening.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: When forming the third metal layer, A second layer is formed on the first layer, the second layer containing a second metal different from the first metal.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: An insulating layer is further formed on the lower layer body, the insulating layer covering the second metal layer and having an opening portion through which the upper surface of the third metal layer is exposed.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: When forming the plurality of metal layers, At least a portion of a metal layer disposed in the lower layer among the plurality of metal layers is electrically connected to the transistor, When forming the first mask pattern, The second opening is formed at a position where the second metal layer becomes a layer for changing the extraction position of at least a part of the metal layer. The second opening is formed at a position where the third metal layer can be connected to an external device.

19. The method for manufacturing a semiconductor device according to claim 15, wherein: When forming the second metal layer, forming a second layer on the first layer, the second layer containing a second metal different from the first metal, After forming the third metal layer, the first layer of the second metal layer formed in the second opening is removed so that the second layer of the second metal layer is arranged above the lower layer body without contacting the lower layer body.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: When forming the third metal layer, connecting the third metal layer to a portion of the second metal layer formed in the second opening; When removing the first layer, The second layer is formed to have a cantilever beam structure or a beam structure with both ends fixed, in a comb-tooth shape, a curved shape, or a membrane shape.

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