A stacked silicon nitride ceramic silicon carbide chip module package

Abstract

The invention provides a stacked silicon nitride ceramic silicon carbide chip module package, which relates to the technical field of chip packaging; the stacked silicon nitride ceramic silicon carbide chip module package comprises two stacked substrates having an upper copper layer, a silicon nitride ceramic layer and a lower copper layer; wherein the upper copper layer included in the lower substrate comprises a lower substrate upper bridge copper layer and a lower substrate lower bridge copper layer, the upper substrate comprises an upper bridge upper substrate arranged on the lower substrate upper bridge copper layer, and a lower bridge upper substrate arranged on the lower substrate lower bridge copper layer; a plurality of silicon carbide chips are electrically connected and arranged on the lower substrate upper bridge copper and the lower substrate lower bridge copper layer; in this way, the circuit flow of current in space is realized, thereby offsetting stray inductance.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a stacked silicon nitride ceramic silicon carbide chip module package. Background Art

[0002] In power electronic devices, with the development of technology and the increase in demand, silicon carbide chip modules have gradually become mainstream in high-frequency, high-power density applications. However, traditional packaging technology faces multiple challenges, especially in terms of stray inductance and thermal management. Stray inductance can cause voltage spikes and electromagnetic interference in the circuit, affecting the efficiency and reliability of power devices. At the same time, as power density increases, thermal management becomes an important issue in packaging design. If heat dissipation is not sufficient, it may cause device overheating, accelerated aging, or even failure. Summary of the invention

[0003] The invention discloses a stacked silicon nitride ceramic silicon carbide chip module package to solve the above problems.

[0004] The present invention adopts the following scheme:

[0005] The present application provides a stacked silicon nitride ceramic silicon carbide chip module package, comprising two stacked substrates having an upper copper layer, a silicon nitride ceramic layer and a lower copper layer;

[0006] The upper copper layer of the lower substrate includes an upper bridge copper layer of the lower substrate and a lower bridge copper layer of the lower substrate, a first slot is provided on one side of the upper bridge copper layer of the lower substrate, and the lower bridge copper layer of the lower substrate is provided in the first slot; and the upper substrate includes an upper bridge upper substrate provided on the upper bridge copper layer of the lower substrate, and a lower bridge upper substrate provided on the lower bridge copper layer of the lower substrate;

[0007] The upper bridge substrate is provided with two second slots, and the lower bridge substrate is provided with two third slots; a plurality of silicon carbide chips electrically connected to the upper bridge copper layer of the lower substrate and the lower bridge copper layer of the lower substrate are arranged in the second slots and the third slots;

[0008] The silicon carbide chips placed in the second slots are electrically connected to the upper copper layer of the upper bridge substrate through bonding wires; the silicon carbide chips placed in the third slots are electrically connected to the upper copper layer of the lower bridge substrate through bonding wires;

[0009] Wherein, the upper copper layer of the upper bridge upper substrate is electrically connected to the lower bridge copper layer of the lower substrate through the bonding wire.

[0010] Furthermore, the upper bridge drain terminal is electrically connected to the upper bridge copper layer on the lower substrate; the lower bridge source terminal is electrically connected to the upper copper layer on the lower bridge substrate; and the upper bridge source and lower bridge drain terminals are electrically connected to the upper copper layer on the upper bridge substrate.

[0011] Furthermore, the lower copper layer of the upper substrate and the upper copper layer of the lower substrate are connected by welding.

[0012] Furthermore, the two second slots are symmetrically arranged; and the two third slots are symmetrically arranged.

[0013] Further, the current flows from left to right through the upper bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the second groove, flows from right to left to the upper copper layer of the upper substrate of the upper bridge, and then flows into the lower bridge copper layer of the lower substrate, and then passes through the silicon carbide chip placed in the third groove, and then flows from left to right to the upper copper layer of the upper substrate of the lower bridge; and when the current flows from right to left through the upper bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the second groove, flows from left to right to the upper copper layer of the upper substrate of the upper bridge, and then flows into the lower bridge copper layer of the lower substrate, and then passes through the silicon carbide chip placed in the third groove, and then flows from right to left to the upper copper layer of the upper substrate of the lower bridge.

[0014] Furthermore, the current flows into the upper copper layer of the lower substrate, flows into the upper copper layer of the upper substrate of the upper bridge through the silicon carbide chip of the upper bridge, then flows into the lower copper layer of the lower bridge of the lower substrate, flows into the upper copper layer of the upper substrate of the lower bridge through the silicon carbide chip of the lower bridge, and then flows out.

[0015] Furthermore, the lower copper layer of the lower substrate is attached to the heat-conducting bottom plate.

[0016] Furthermore, a plurality of heat-conducting columns are protruded and spaced below the heat-conducting bottom plate.

[0017] Furthermore, a shell is provided around the substrate.

[0018] By adopting the above technical solution, the present invention can achieve the following technical effects:

[0019] The present invention provides a stacked silicon nitride ceramic silicon carbide chip module package, which comprises two stacked substrates having an upper copper layer, a silicon nitride ceramic layer and a lower copper layer; wherein the upper copper layer included in the lower substrate comprises a lower substrate upper bridge copper layer and a lower substrate lower bridge copper layer, and the upper substrate comprises an upper bridge upper substrate arranged on the lower substrate upper bridge copper layer, and a lower bridge upper substrate arranged on the lower substrate lower bridge copper layer; a plurality of silicon carbide chips are electrically connected and arranged on the lower substrate upper bridge copper and the lower substrate lower bridge copper layer; thus, the circuit flow of current in space is realized, thereby offsetting stray inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of a stacked silicon nitride ceramic silicon carbide chip module packaging structure according to an embodiment of the present invention;

[0021] Figure 2 It is a schematic diagram of the exploded structure of a stacked silicon nitride ceramic silicon carbide chip module package according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of a partial structure of a stacked silicon nitride ceramic silicon carbide chip module package according to an embodiment of the present invention. Figure 1 ;

[0023] Figure 4 This is a schematic diagram of a partial structure of a stacked silicon nitride ceramic silicon carbide chip module package according to an embodiment of the present invention. Figure 2 ;

[0024] Figure 5 yes Figure 4 A schematic diagram of the structure of the assembly of the middle and lower substrates and the upper substrate;

[0025] Figure 6 yes Figure 5 Schematic diagram of the decomposition structure;

[0026] Figure 7 yes Figure 6 A schematic diagram of the structure is further decomposed;

[0027] Figure 8 This is a schematic diagram of the bottom structure of a thermally conductive base plate of a stacked silicon nitride ceramic silicon carbide chip module package according to an embodiment of the present invention;

[0028] Icons: lower substrate 1, copper layer on the bridge of lower substrate 2, copper layer on the lower bridge of lower substrate 3, first groove 4, upper substrate on the upper bridge 5, upper substrate on the lower bridge 6, second groove 7, third groove 8, silicon carbide chip 9, copper layer on the bridge of lower substrate 10, copper layer on the bridge of lower substrate 11, upper bridge drain terminal 12, lower bridge source terminal 13, first bonding wire 14, second bonding wire 15, thermal conductive base plate 16, thermal conductive column 17, outer shell 18. DETAILED DESCRIPTION

[0029] Example

[0030] Combination Figures 1 to 8 As shown, this embodiment provides a stacked silicon nitride ceramic silicon carbide chip module package, including two stacked substrates having an upper copper layer, a silicon nitride ceramic layer and a lower copper layer;

[0031] The upper copper layer of the lower substrate 1 includes a lower substrate upper bridge copper layer 10 and a lower substrate lower bridge copper layer 11, a first slot 4 is provided on one side of the lower substrate upper bridge copper layer 10, and the lower substrate lower bridge copper layer 11 is provided in the first slot 4; and the upper substrate includes an upper bridge upper substrate 5 provided on the lower substrate upper bridge copper layer 10, and a lower bridge upper substrate 6 provided on the lower substrate lower bridge copper layer 11;

[0032] The upper bridge upper substrate 5 is provided with two second slots 7, and the lower bridge upper substrate 6 is provided with two third slots 8; a plurality of silicon carbide chips 9 electrically connected to the upper bridge copper layer 10 of the lower substrate and the lower bridge copper layer 11 of the lower substrate are arranged in the second slots 7 and the third slots 8;

[0033] The silicon carbide chip 9 placed in the second slot 7 is electrically connected to the upper copper layer of the upper bridge substrate 5 through bonding wires; the silicon carbide chip 9 placed in the third slot 8 is electrically connected to the upper copper layer of the lower bridge substrate 6 through bonding wires;

[0034] The upper copper layer of the upper bridge upper substrate 5 is electrically connected to the lower bridge copper layer 11 of the lower substrate through the bonding wire.

[0035] Specifically, in this embodiment, Figures 5 to 7 As shown, the upper part of the bridge copper layer 10 of the lower substrate is provided with the first groove 4 similar to a convex shape, and the upper bridge drain terminal 12 is electrically connected to the two sides of the first groove 4. The lower bridge copper layer 11 of the lower substrate is also similar to a convex shape as a whole, and is arranged in the first groove 4. The lower copper layer of the upper bridge substrate 5 is welded on the upper bridge copper layer 10 of the lower substrate; the lower copper layer of the lower bridge substrate 6 is welded on the lower bridge copper layer 11 of the lower substrate. Two second grooves 7 are symmetrically arranged on the upper bridge substrate 5, and two third grooves 8 are symmetrically arranged on the lower bridge substrate 6; a plurality of silicon carbide chips 9 electrically connected to the upper bridge copper of the lower substrate 1 and the lower bridge copper layer 11 of the lower substrate are arranged in the second groove 7 and the third groove 8. In this embodiment, six silicon carbide chips 9 are symmetrically arranged in the second groove 7; and six silicon carbide chips 9 are also symmetrically arranged in the third groove 8. The upper copper layer of the upper bridge upper substrate 5 is electrically connected to the lower bridge copper layer 11 of the lower substrate through a second bonding wire 15 .

[0036] The upper copper layer of the lower bridge upper substrate 6 is electrically connected to the lower bridge source terminal 13; and the upper copper layer of the upper bridge upper substrate 5 is electrically connected to the upper bridge source and lower bridge drain terminals. The silicon carbide chip 9 placed in the second slot 7 and the third slot 8 is electrically connected to the upper copper layer 10 of the lower substrate and the lower copper layer 11 of the lower substrate through the first bonding wire 14, respectively.

[0037] The above stacked design realizes the flow of current in space. The chip package forms two left and right loops, wherein when the current flows from left to right through the upper bridge copper layer 2 of the lower substrate, after passing through the silicon carbide chip 9 placed in the second slot 7, it flows from right to left to the upper copper layer of the upper bridge substrate 5, then flows into the lower bridge copper layer 3 of the lower substrate, and then passes through the silicon carbide chip 9 placed in the third slot 8, and then flows from left to right to the upper copper layer of the lower bridge substrate 6; and when the current flows from right to left through the upper bridge copper layer 2 of the lower substrate, after passing through the silicon carbide chip 9 placed in the second slot 7, it flows from left to right to the upper copper layer of the upper bridge substrate 5, then flows into the lower bridge copper layer 3 of the lower substrate, and then passes through the silicon carbide chip 9 placed in the third slot 8, and then flows from right to left to the upper copper layer of the lower bridge substrate 6. Specifically, in this embodiment, the current loop on the left is: the current flows from the upper bridge drain terminal 12 into the upper bridge copper layer 10 of the lower substrate, flows through the silicon carbide chip 9 of the upper bridge (that is, the silicon carbide chip 9 placed in the second groove 7) through the first bonding wire 14 into the upper copper layer of the upper bridge substrate 5, and then flows through the second bonding wire 15 into the lower bridge copper layer 11 of the lower substrate, flows through the silicon carbide chip 9 of the lower bridge (that is, the silicon carbide chip 9 placed in the third groove 8) through the first bonding wire 14 into the upper copper layer of the lower bridge substrate 6, and then flows out from the lower bridge source terminal 13.

[0038] Most of the stray inductance comes from the interconnection between electrical components. If a single component is directly connected, the stray inductance will not be reduced. However, in the stacked spatial design of this solution, the two ends of a component are connected from an upper and lower angle respectively. The current flows from left to right in the lower layer, and from right to left in the upper layer; or the current flows from right to left in the lower layer, and from left to right in the upper layer. According to the electromagnetic principle, the stray inductance can be offset against each other.

[0039] Preferably, if Figure 2 and Figure 8 As shown, the lower copper layer of the lower substrate 1 is attached to the heat-conducting bottom plate 16, and a plurality of heat-conducting columns 17 are provided at intervals below the heat-conducting bottom plate 16, which can effectively dissipate heat from the chip and avoid local overheating caused by excessive local current. Heat can be conducted more evenly in the chip and the packaging structure, improving heat dissipation efficiency and helping to enhance high-frequency stability.

[0040] Of course, the outer periphery of the substrate is provided with a shell 18, and the shell 18 is filled with insulating glue to ensure that the internal components of the module are electrically insulated and physically sealed. In this embodiment, the entire module package includes a total of 36 silicon carbide chips 9. Of course, the chip model and quantity can be adjusted according to specific production requirements.

[0041] It should be understood that the above are only preferred implementations of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention.

[0042] The above description of the drawings used in the implementation manner only illustrates certain embodiments of the present invention and should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

Claims

1. A stacked silicon nitride ceramic silicon carbide chip module package, characterized in that: A substrate comprising two stacked layers having an upper copper layer, a silicon nitride ceramic layer and a lower copper layer; The upper copper layer of the lower substrate includes an upper bridge copper layer of the lower substrate and a lower bridge copper layer of the lower substrate, a first slot is provided on one side of the upper bridge copper layer of the lower substrate, and the lower bridge copper layer of the lower substrate is provided in the first slot; and the upper substrate includes an upper bridge upper substrate provided on the upper bridge copper layer of the lower substrate, and a lower bridge upper substrate provided on the lower bridge copper layer of the lower substrate; The upper bridge substrate is provided with two second slots, and the lower bridge substrate is provided with two third slots; a plurality of silicon carbide chips electrically connected to the upper bridge copper layer of the lower substrate and the lower bridge copper layer of the lower substrate are arranged in the second slots and the third slots; The silicon carbide chips placed in the second slots are electrically connected to the upper copper layer of the upper bridge substrate through bonding wires; the silicon carbide chips placed in the third slots are electrically connected to the upper copper layer of the lower bridge substrate through bonding wires; Wherein, the upper copper layer of the upper bridge upper substrate is electrically connected to the lower bridge copper layer of the lower substrate through the bonding wire; The current flows from left to right through the upper bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the second slot, flows from right to left to the upper copper layer of the upper substrate of the upper bridge, flows into the lower bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the third slot, and flows from left to right to the upper copper layer of the upper substrate of the lower bridge; and when the current flows from right to left through the upper bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the second slot, flows from left to right to the upper copper layer of the upper substrate of the upper bridge, flows into the lower bridge copper layer of the lower substrate, passes through the silicon carbide chip placed in the third slot, and flows from right to left to the upper copper layer of the upper substrate of the lower bridge; The current flows into the upper copper layer of the lower substrate, flows into the upper copper layer of the upper substrate of the upper bridge through the silicon carbide chip of the upper bridge, flows into the lower copper layer of the lower bridge of the lower substrate, flows into the upper copper layer of the upper substrate of the lower bridge through the silicon carbide chip of the lower bridge, and then flows out.

2. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 1, characterized in that: The upper bridge copper layer on the lower substrate is electrically connected to an upper bridge drain terminal; the upper copper layer on the lower bridge upper substrate is electrically connected to a lower bridge source terminal; and the upper copper layer on the upper bridge upper substrate is electrically connected to terminals of an upper bridge source and a lower bridge drain.

3. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 1, characterized in that: The lower copper layer of the upper substrate and the upper copper layer of the lower substrate are connected by welding.

4. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 1, characterized in that: The two second slots are symmetrically arranged; the two third slots are symmetrically arranged.

5. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 1, characterized in that: The lower copper layer of the lower substrate is attached to the heat-conducting bottom plate.

6. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 5, characterized in that: A plurality of heat-conducting columns are protruded and spaced below the heat-conducting bottom plate.

7. The stacked silicon nitride ceramic silicon carbide chip module package according to claim 6, characterized in that: A shell is arranged on the periphery of the substrate.

Images