Wave-by-wave current limiting method and system of cascaded H-bridge converter

Abstract

The invention provides a wave-by-wave current limiting method and system for a cascaded H-bridge converter, and the method comprises the steps: collecting the three-phase filtering inductive current of the AC side of the cascaded H-bridge converter, inputting the three-phase filtering inductive current into a hysteresis comparator, and comparing the three-phase filtering inductive current with a wave-by-wave current limiting threshold value, thereby obtaining a wave-by-wave current limiting signal; respectively inputting the wave-by-wave current-limiting signal to an RS latch module in each H bridge of the cascaded H-bridge converter, carrying out wave sealing processing when the RS latch module inputs the wave-by-wave current-limiting signal to a PWM signal processing module, controlling the cycle of the wave-by-wave current-limiting switch of the H bridge based on the cycle of a reset signal output by the RS latch module, and controlling the cycle of the pulse-by-wave current-limiting switch of the H bridge according to the number of cascaded H bridges. Setting an output phase staggered reset signal of the RS latch to control successive recovery of each H-bridge PWM (Pulse Width Modulation); and meanwhile, accumulating the number of times of wave sealing, and controlling the converter to be shut down when a threshold value is reached. According to the method, wave-by-wave current limiting can be performed on the cascaded H-bridge converter, and a relatively low current fluctuation amplitude is kept during the wave-by-wave current limiting period, so that the output performance of the converter is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of wave-by-wave current limiting control of electric power equipment, and in particular to a wave-by-wave current limiting method and system for a cascaded H-bridge converter. Background Art

[0002] At present, wave-by-wave current limiting has become one of the effective measures for current protection of power electronic equipment. Wave-by-wave current limiting ensures that the current of each waveform is within a safe range by monitoring and controlling the current wave by wave. It can effectively and quickly limit the current of the power switch tube in the converter and improve the reliability and anti-disturbance of the power converter.

[0003] In the related art, the wave-by-wave current limiting method is generally only for two-level or three-level inverters, and there is a lack of wave-by-wave current limiting control methods for multi-level inverters such as cascaded H-bridges. In addition, the wave-by-wave current limiting method in the related art usually uses the switching cycle of the power switch tube to block and recover the wave. Although the current fluctuation is not severe during the wave-by-wave current limiting at high switching frequencies, in multi-level circuits with low switching frequencies, this wave-by-wave current limiting method will cause severe current fluctuations, that is, the current ripple range is very large, which seriously affects the power quality and power supply performance of the converter output.

[0004] Therefore, how to perform wave-by-wave current limiting on the cascaded H-bridge converter with lower current fluctuation has become a problem that needs to be solved urgently. Summary of the invention

[0005] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0006] To this end, the first purpose of the present application is to propose a wave-by-wave current limiting method for a cascaded H-bridge converter, which can perform wave-by-wave current limiting on the cascaded H-bridge converter and maintain a low current fluctuation amplitude during the wave-by-wave current limiting period, thereby ensuring the output performance of the converter and solving the problem of lack of wave-by-wave current limiting for the cascaded H-bridge converter in the related art.

[0007] The second objective of the present application is to propose a wave-by-wave current limiting system for a cascaded H-bridge converter.

[0008] A third object of the present application is to provide a non-transitory computer-readable storage medium.

[0009] To achieve the above object, a first aspect of the present application is to propose a wave-by-wave current limiting method for a cascaded H-bridge converter, the method comprising the following steps:

[0010] The collected three-phase filter inductor current analog signal on the AC side of the cascaded H-bridge converter is input into the hysteresis comparator, and compared with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively, and the comparison signal obtained by the hysteresis comparison is used as the wave-by-wave current limiting signal;

[0011] The wave-by-wave current limiting signal is respectively input to the RS latch module preset in each H bridge of the cascaded H bridge converter, and the RS latch module performs wave sealing processing when inputting the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and based on the cycle of the reset signal output by the RS latch module, the wave-by-wave current limiting switching cycle of the H bridge is controlled, wherein the triggering moments of the reset signals of all H bridges in a single phase are distributed in one wave-by-wave current limiting switching cycle at the same interval time;

[0012] The number of times the PWM signal processing module performs wave sealing is accumulated, and when the number reaches a threshold of the wave-by-wave current limiting number, the cascaded H-bridge converter is controlled to shut down.

[0013] Optionally, in one embodiment of the present application, before the wave sealing processing is performed, it also includes: determining the wave-by-wave current limiting switching period of each H bridge based on the operating frequency and current ripple parameters of the power switch of the cascaded H-bridge converter; setting the period of the reset signal output by the RS latch module of each H bridge to be equal to the wave-by-wave current limiting switching period; determining the difference between the triggering times of the reset signals corresponding to two adjacent H bridges according to the wave-by-wave current limiting switching period and the number of H bridges cascaded in a single phase.

[0014] Optionally, in one embodiment of the present application, the S end of the RS latch module is used to receive the wave-by-wave current limiting signal, and the R end of the RS latch module is used to receive the reset signal; the output end of the RS latch module is connected to the input end of the corresponding PWM signal processing module, and the PWM signal processing module performs wave sealing processing when receiving the wave-by-wave current limiting signal; when the S end is in a valid state, the R end remains in an invalid state.

[0015] Optionally, in one embodiment of the present application, the triggering moment of the reset signal of each H-bridge is determined by the corresponding timer, and the wave-sealing processing is performed, and based on the cycle of the reset signal output by the RS latch module, the wave-by-wave current limiting switching cycle of the H-bridge is controlled, including: after the wave-by-wave current limiting signal is input to the RS latch module, the RS latch module is controlled to update the latched wave-by-wave current limiting signal and output it to the corresponding PWM signal processing module; while the PWM signal processing module performs the wave-sealing processing, the timer of each H-bridge is controlled to be reset to the corresponding initial value for counting, wherein the initial value corresponding to each timer is determined based on the triggering moment of the reset signal of the H-bridge; when any timer counts to the length of the reset signal cycle, the reset signal is generated and the state of the current wave-by-wave current limiting signal is judged; if the current wave-by-wave current limiting signal is in an invalid state, the wave-by-wave current limiting signal latched in the RS latch module is cleared by outputting the reset signal; if the current wave-by-wave current limiting signal is in a valid state, the generated reset signal is invalidated and any timer is controlled to be reset to 0 for cyclic counting until the wave-sealing ends.

[0016] Optionally, in one embodiment of the present application, the wave sealing processing is performed, and the wave-by-wave current limiting switching period of the H-bridge is controlled based on the period of the reset signal output by the RS latch module, and further includes: when the cascaded H-bridge converter is powered on, the timer of each H-bridge is controlled to be reset to the corresponding initial value for counting; when any timer counts to the duration of the reset signal period, the reset signal is generated and reset to 0 for cyclic counting; when the reset signal is generated, the state of the current wave-by-wave current limiting signal is judged; if the current wave-by-wave current limiting signal is in an invalid state, the wave-by-wave current limiting signal latched in the RS latch module is cleared by outputting the reset signal; if the current wave-by-wave current limiting signal is in a valid state, the generated reset signal is invalidated.

[0017] Optionally, in one embodiment of the present application, before inputting the current analog signal into the hysteresis comparator, the method further includes: setting a hysteresis parameter of the hysteresis comparator according to a current threshold range and anti-interference requirements of the cascaded H-bridge converter.

[0018] To achieve the above-mentioned purpose, the second aspect of the present application further proposes a wave-by-wave current limiting system of a cascaded H-bridge converter, comprising the following modules:

[0019] An acquisition module is used to acquire the three-phase filter inductor current outputted from the AC side of the cascaded H-bridge converter through a current sensor, and convert the three-phase filter inductor current into a current analog signal;

[0020] A comparison module, used for inputting the current analog signal into a hysteresis comparator, comparing it with a positive current wave-by-wave current limiting threshold and a negative current wave-by-wave current limiting threshold respectively, and using a comparison signal obtained by hysteresis comparison as a wave-by-wave current limiting signal;

[0021] A wave sealing module, used for inputting the wave-by-wave current limiting signal to the RS latch module preset in each H bridge of the cascaded H bridge converter respectively, performing wave sealing processing when the RS latch module inputs the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and controlling the wave-by-wave current limiting switching cycle of the H bridge based on the cycle of the reset signal output by the RS latch module, wherein the triggering moments of the reset signals of all H bridges in a single phase are distributed in one wave-by-wave current limiting switching cycle at the same interval time;

[0022] The accumulation module is used to accumulate the number of times the PWM signal processing module performs wave sealing, and when the number reaches a threshold of wave-by-wave current limiting times, control the cascaded H-bridge converter to shut down.

[0023] In order to implement the above-mentioned embodiments, the third aspect embodiment of the present application further proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the wave-by-wave current limiting method of the cascaded H-bridge converter in the above-mentioned first aspect is implemented.

[0024] The technical solution provided by the embodiment of the present application brings at least the following beneficial effects: the present application sets an RS latch module and a PWM signal processing module in each H bridge of the cascaded H bridge converter, controls the wave-closing period of the H bridge according to the interval time of the reset signal of the RS latch module, and then controls the switching frequency and current fluctuation degree of the power switch tube during the wave-by-wave current limiting period, and the RS latch module reset signals of all H bridges are distributed in a wave-by-wave current limiting switching period at the same interval time. Thus, based on the inherent topological characteristics of the cascaded H bridge, the present application can take into account the current fluctuation and the operating frequency range of the power switch to limit the current of the converter wave by wave. For the cascaded H bridge converter, the PWM of each H bridge recovers from the wave-closing state to the normal state at different times in the wave-by-wave current limiting state, and recovers at equal time intervals, so that the fluctuation amplitude of the output current of the converter can be effectively reduced, and the converter power switch tube can realize the wave-by-wave current limiting function at a lower operating frequency, and the equivalent switching frequency of the inverter is increased. In addition, the implementation method of the wave-by-wave current limiting function of the present application is relatively simple, the control cost is low, and it is easy to implement in practical applications. Therefore, the present application can perform wave-by-wave current limiting on the cascaded H-bridge converter and maintain a low current fluctuation amplitude during the wave-by-wave current limiting period, thereby improving the output performance of the cascaded H-bridge converter.

[0025] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 A flow chart of a wave-by-wave current limiting method for a cascaded H-bridge converter proposed in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a hysteresis comparator proposed in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the connection between an RS latch module and a PWM signal processing module proposed in an embodiment of the present application;

[0030] Figure 4 A flow chart of a wave-by-wave current limiting processing process proposed in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of a PWM timing sequence after a converter triggers wave-by-wave current limiting and a wave-by-wave current limiting reset signal timing sequence proposed in an embodiment of the present application;

[0032] Figure 6 A schematic diagram of a continuously triggered wave-by-wave current limiting timing sequence and a wave-closing timing sequence after exceeding the wave-by-wave current limiting times proposed in an embodiment of the present application;

[0033] Figure 7 A flowchart of another wave-by-wave current limiting processing process proposed in an embodiment of the present application;

[0034] Figure 8 A schematic diagram of another timing sequence of a wave-by-wave current limiting reset signal proposed in an embodiment of the present application;

[0035] Fig. 9 A schematic structural diagram of a wave-by-wave current limiting system of a cascaded H-bridge converter proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0036] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0037] It should be noted that for the cascaded H-bridge converter, each phase is composed of several H-bridge power circuits connected in cascade, and the pulse width modulation (PWM) triangular carrier of each H-bridge in each phase has different phase shift angles. The modulated PWM signal controls the corresponding power switch tube to output different high and low levels. Finally, the levels of all H-bridges are superimposed, thereby achieving multi-level output and equivalent switching frequency improvement. Therefore, compared with the ordinary two-level inverter, the cascaded H-bridge inverter using carrier phase shift modulation, at the same equivalent switching frequency, the switching frequency of each H-bridge in the converter with N H-bridges cascaded in each phase is reduced to 1 / 2N of the original, that is, the power switch in the cascaded H-bridge converter operates at a very low switching frequency.

[0038] However, if the actual switching cycle is maintained to uniformly block and restore all power switches when the wave-by-wave current limiting is triggered, the equivalent output switching frequency and the actual switching frequency will be consistent, which will cause the converter output current to fluctuate violently and seriously affect the output power quality. If the wave-by-wave current limiting is triggered according to the equivalent switching cycle of the converter, the operating frequency of the power switch will be many times higher than that of normal operation, and the thermal stress and risk of the power device will increase significantly.

[0039] To this end, the present application designs a wave-by-wave current limiting method based on the inherent topological characteristics of the cascaded H-bridge, which can take into account both current fluctuations and the operating frequency range of the power switch.

[0040] A wave-by-wave current limiting method and system for a cascaded H-bridge converter according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0041] Figure 1 Flow chart of a wave-by-wave current limiting method for a cascaded H-bridge converter proposed in an embodiment of the present application, such as Figure 1 As shown, the method comprises the following steps:

[0042] Step S101, input the collected three-phase filter inductor current analog signal on the AC side of the cascaded H-bridge converter into the hysteresis comparator, compare it with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively, and use the comparison signal obtained by hysteresis comparison as the wave-by-wave current limiting signal.

[0043] Specifically, various types of current sensors are first used to collect the current of the three-phase filter inductor output on the AC side of the cascaded H-bridge converter, and then the output value of the current sensor in each phase of the converter is adjusted and converted respectively, and the collected current is converted into a current analog signal that can represent the real-time current value.

[0044] As an example, various types of sensors capable of collecting the current on the AC side of the converter, such as current transformers, current Hall sensors and shunts, can be used as current sensors. The specific type and quantity of sensors used can be determined based on actual collection requirements, and this application does not impose any restrictions on this.

[0045] Furthermore, the converted current analog signal is compared with the preset positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold, respectively. The present application adopts a hysteresis comparison method for comparison, and the comparison signal output by the hysteresis comparator can be used as a wave-by-wave current limiting control signal.

[0046] As a possible implementation, Figure 2 As shown, the input end of the hysteresis comparator receives the current sensor value (i.e., the current analog signal). If the current analog signal representing the current size exceeds the range defined by the wave-by-wave current limiting threshold, the hysteresis comparator outputs a logic 1 signal, i.e., the wave-by-wave current limiting signal is valid. Otherwise, the hysteresis comparator outputs a logic 0 signal, i.e., the wave-by-wave current limiting signal is invalid. In the embodiment of the present application, it is equivalent to the hysteresis comparator outputting the wave-by-wave current limiting signal to the subsequent device when the comparison determines that the wave-by-wave current limiting signal is valid.

[0047] In one embodiment of the present application, before the current analog signal is input into the hysteresis comparator, the method further includes: setting a hysteresis parameter of the hysteresis comparator according to a current threshold range and an anti-interference requirement of the cascaded H-bridge converter.

[0048] Specifically, in this embodiment, in order to avoid the comparison signal from changing too frequently and improve the anti-interference ability of the cascaded H-bridge converter, the hysteresis parameters used by the hysteresis comparator can be determined by comprehensive consideration of various factors such as the actual current threshold range of the converter and the anti-interference performance of the system in which it is located. Among them, the hysteresis parameters include the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold, etc., and the anti-interference requirements include the requirements of the system in which the converter is located for the wave-by-wave current limiting operation to maintain a normal and stable working state.

[0049] Therefore, the present application can reasonably set the hysteresis parameters according to the actual working conditions of the converter, avoiding unnecessary frequent wave-by-wave current limiting operations due to unexpected factors and smaller fluctuations.

[0050] Step S102, respectively input the wave-by-wave current limiting signal to the RS latch module preset in each H bridge of the cascaded H bridge converter, perform wave sealing processing when the RS latch module inputs the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and control the wave-by-wave current limiting switching cycle of the H bridge based on the cycle of the reset signal output by the RS latch module, wherein the triggering moments of the reset signals of all H bridges in a single phase are distributed in one wave-by-wave current limiting switching cycle at the same interval time.

[0051] Specifically, the present application pre-sets an RS latch module and a PWM signal processing module in each H bridge of the cascaded H bridge converter. After the hysteresis comparator outputs the wave-by-wave current limiting signal, the wave-by-wave current limiting signal is first input to the RS latch module in each H bridge respectively, and the RS latch module then inputs the wave-by-wave current limiting signal to the corresponding PWM signal processing module. After receiving the wave-by-wave current limiting signal, the PWM signal processing module performs wave sealing processing. The reset signal input to the RS latch module can clear the wave-by-wave current limiting signal latched in the RS latch module, so the wave sealing time of the PWM signal processing module can be controlled by adjusting the interval time of the reset signal.

[0052] In one embodiment of the present application, the S end of the RS latch module is used to receive a wave-by-wave current limiting signal, and the R end of the RS latch module is used to receive a reset signal; the output end of the RS latch module is connected to the input end of the corresponding PWM signal processing module, and the PWM signal processing module performs wave sealing processing when receiving the wave-by-wave current limiting signal; when the S end is in a valid state, the R end remains in an invalid state.

[0053] Specifically, in this embodiment, Figure 3 As shown, the wave-by-wave current limiting signal is input to the S end of the RS latch, the reset signal is input to the R end of the RS latch, and the output end Q outputs the signal to the PWM processing module. When the output end Q outputs the wave-by-wave current limiting signal to the PWM processing module, the PWM module performs the wave sealing logic processing, otherwise the PWM module performs the normal wave sending logic.

[0054] Moreover, in order to avoid the R and S terminals of the RS latch being at 1 at the same time, in the present embodiment, a logic judgment element is added to the channel for inputting the reset signal to the RS latch. By performing logic judgment processing, it is ensured that when the wave-by-wave current limiting signal is 1, the reset signal always remains in the 0 state, that is, the reset signal is prohibited from being input to the R terminal of the latch.

[0055] As described above, in this step, the corresponding H-bridge sealing period can be controlled by adjusting the interval time of the reset signal of the RS latch module, and thus the present application can realize the control of the switching frequency and current fluctuation degree of the power switch tube during the wave-by-wave current limiting period. In addition, since each H-bridge in the present application has a RS latch module and a PWM signal processing module, for the reset signal received by the RS latch module, the reset signal corresponding to each H-bridge can be individually designed to be triggered at different times, thereby realizing the increase of the equivalent switching frequency of the inverter and reducing the current fluctuation degree during the wave-by-wave current limiting period.

[0056] In specific implementation, in one embodiment of the present application, before the wave sealing processing is performed, it also includes: determining the wave-by-wave current limiting switching period of each H bridge based on the operating frequency and current ripple parameters of the power switch of the cascaded H-bridge converter; setting the period of the reset signal output by the RS latch module of each H bridge to be equal to the wave-by-wave current limiting switching period; determining the difference between the triggering times of the reset signals corresponding to two adjacent H bridges according to the wave-by-wave current limiting switching period and the number of H bridges cascaded in a single phase.

[0057] Specifically, the wave-by-wave current limiting switching period T of the H-bridge is comprehensively determined based on the operating frequency and current ripple parameters of the power switch in the cascaded H-bridge converter. lock , then the reset signal period of the RS latch module of the H bridge is also T lock , that is, the duration of the two cycles is the same. In each phase of the converter, if there are N H bridges in cascade, the triggering time of the reset signal of the RS latch module of each H bridge differs by T lock / N, for example, if there are 4 H bridges in a single phase, the reset signal triggering time difference between the first H bridge and the second H bridge is T lock / 4. Thus, the reset signals of the RS latch modules of all H bridges in the phase of the wave-by-wave current limiting switching cycle can be evenly distributed in a wave-by-wave current limiting switching cycle at the same interval time. According to the number of cascaded H bridges, the output phase staggered reset signal of the RS latch is set to control the successive recovery of each H bridge PWM, thereby further reducing the current fluctuation degree during the wave-by-wave current limiting period.

[0058] It should be noted that the cascaded H-bridge converter can be set to single-phase or multi-phase (such as 3-phase) according to actual needs. The cascaded H-bridge in each phase is the same. This application describes the wave-by-wave current limiting process in a single phase, and the implementation process of the wave-by-wave current limiting in each phase is the same.

[0059] Step S103, accumulating the number of times the PWM signal processing module performs wave blocking, and when the number reaches a threshold of the wave-by-wave current limiting number, controlling the cascaded H-bridge converter to shut down.

[0060] Specifically, after the wave sealing process is started in the previous step, the number of times the PWM signal processing module continuously performs wave sealing during the wave-by-wave current limiting process is recorded, and it is determined whether the number of wave sealing times reaches the preset upper limit of the wave-by-wave current limiting times. If the upper limit is reached, the upper limit flag of the wave-by-wave current limiting times is set, and the shutdown logic is performed.

[0061] Therefore, the present application can prevent the power devices of the converter from operating in a wave-by-wave current limiting state for a long time, thereby exceeding the upper limit of the working stress of the power switch tube and damaging the switch tube.

[0062] In summary, the wave-by-wave current limiting method of the cascaded H-bridge converter of the embodiment of the present application is to set an RS latch module and a PWM signal processing module in each H-bridge of the cascaded H-bridge converter, and control the wave-closing period of the H-bridge according to the interval time of the reset signal of the RS latch module, thereby controlling the switching frequency and current fluctuation degree of the power switch tube during the wave-by-wave current limiting period, and the RS latch module reset signals of all H-bridges are distributed in a wave-by-wave current limiting switching cycle at the same interval time. Therefore, the method is based on the inherent topological characteristics of the cascaded H-bridge, and can take into account the current fluctuation and the operating frequency range of the power switch to perform wave-by-wave current limiting on the converter. For the cascaded H-bridge converter, in the wave-by-wave current limiting state, the PWM of each H-bridge recovers from the wave-closing state to the normal state at different times, and recovers at equal time intervals, thereby effectively reducing the fluctuation amplitude of the converter output current, and the converter power switch tube can realize the wave-by-wave current limiting function at a lower operating frequency, and improve the equivalent switching frequency of the inverter. Moreover, the wave-by-wave current limiting function of the method is relatively simple to implement, with low control cost and easy implementation in practical applications. Therefore, the method can perform wave-by-wave current limiting on the cascaded H-bridge converter and maintain a low current fluctuation amplitude during the wave-by-wave current limiting period, thereby improving the output performance of the cascaded H-bridge converter.

[0063] Based on the above embodiments, in order to more clearly illustrate the specific implementation process of the present application in which the RS latch module and the PWM signal processing module perform wave-by-wave current limiting, and control the H-bridge sealing period according to the interval time of the reset signal, two specific embodiments are used for illustrative explanation below.

[0064] In the first specific embodiment, a cascaded H-bridge inverter consisting of four H-bridges in a single phase is used as an example for explanation. The switching frequency PWM modulation method of the converter adopts carrier phase shift modulation, and the PWM carrier period is T s The wave-by-wave current limiting PWM wave-closing time length determined comprehensively according to the above embodiment is T lock In this embodiment, a timing counter is pre-set for each H bridge, and the reset signal triggering time of the RS latch module of each H bridge is obtained by its timing counter.

[0065] In this embodiment, in the first step, the current sensor converts the three-phase filter inductor current of the cascaded H-bridge converter into a corresponding real-time analog signal.

[0066] In the second step, the signal is input into the hysteresis comparator and compared with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively. When the signal representing the current exceeds the wave-by-wave current limiting threshold, the comparator outputs logic 1, that is, the wave-by-wave current limiting signal is valid; otherwise, the comparator outputs logic 0, that is, the wave-by-wave current limiting signal is invalid.

[0067] In the third step, the RS latch module and PWM signal processing module of each H bridge perform wave-by-wave current limiting processing and reset based on the reset signal raised by the corresponding timing counter. In order to more clearly describe the wave-by-wave current limiting processing process in this step, the following is combined with Figure 4 For detailed description. Figure 4 As shown, the wave-by-wave current limiting process includes the following steps:

[0068] Step S401, after the wave-by-wave current limiting signal is input to the RS latch module, the RS latch module is controlled to update the latched wave-by-wave current limiting signal and output it to the corresponding PWM signal processing module.

[0069] Specifically, the wave-by-wave current limiting signal generated in the second step is input into each H-bridge RS latch module respectively. When the wave-by-wave current limiting signal changes from invalid to valid, the RS latch module updates the internally latched wave-by-wave current limiting signal and outputs it. When the PWM signal processing module receives the valid wave-by-wave current limiting signal, it performs the wave sealing logic processing.

[0070] Step S402: while the PWM signal processing module performs the wave sealing process, the timer of each H bridge is controlled to be reset to the corresponding initial value for counting.

[0071] The initial value corresponding to each timer is determined based on the triggering moment of the reset signal of the H-bridge, that is, in order to achieve that the triggering moments of the reset signals of all H-bridges in a single phase in the above embodiment are distributed at the same interval in a wave-by-wave current limiting switching cycle, the initial value of each timer is set. According to the method of setting the triggering moment of the reset signal in the above embodiment, the initial values ​​of the timing counters corresponding to H-bridge No. 1 to H-bridge No. 4 in this embodiment should be 0, T lock / 4、T lock / 2 and 3T lock / 4.

[0072] Specifically, when the PWM signal processing module starts to perform the wave sealing process, the reset signal timing counters of all H bridges are reset to the initial value and start counting.

[0073] Step S403, when any timer counts to the duration of the reset signal cycle, a reset signal is generated and the state of the current wave-by-wave current limiting signal is determined.

[0074] Specifically, when a certain H-bridge timing counter counts to the set PWM wave blocking time T lock When the reset signal is generated, it is input to the RS latch module of the H bridge. In addition, the state of the current wave-by-wave current limiting signal is determined, and the state of the previous wave-by-wave current limiting signal is determined. Figure 3 On the receiving channel of the reset signal shown, it is determined whether the reset signal is input to the R end of the RS latch module.

[0075] Step S404, if the current wave-by-wave current limiting signal is in an invalid state, the wave-by-wave current limiting signal latched in the RS latch module is cleared by outputting a reset signal; if the current wave-by-wave current limiting signal is in a valid state, the generated reset signal is invalidated and any timer is controlled to reset to 0 for cyclic counting until the wave-sealing is ended.

[0076] Specifically, when judging whether to reset on the receiving channel of the above-mentioned reset signal, if the current wave-by-wave current limiting signal is in an invalid state, that is, set to 0, the reset signal is input to the R end of the RS latch module, and then the latch value is cleared by the reset signal, the PWM signal processing module ends the wave limiting, the converter returns to a normal working state, and controls the timing counter to stop counting.

[0077] If the current wave-by-wave current limiting signal is in a valid state, that is, the wave-by-wave current limiting signal is still set to 1, the reset signal is determined to be invalid, and the signal is blocked from being input to the R end of the RS latch module. Then, the PWM signal processing module continues to block the wave, and controls the timing counter to reset to 0 and restart counting, and counts to the wave blocking time length T in the next calculation cycle. lock When the PWM signal processing module is in operation, the judgment is made again in the above manner and the process is repeated in sequence until the PWM signal processing module finishes sealing the wave and returns to the normal working state.

[0078] It can be understood that since the timing counters corresponding to the above four H bridges start counting from different initial values, when the reset signal cycle T lock For example, the timing counter corresponding to the No. 4 H bridge counts T lock / 4 first reaches the duration of the reset signal cycle for judgment, and the remaining H bridges make judgments in turn at the corresponding time, and in the next round, they can also make judgments in this time sequence. In this way, the triggering moments of the reset signals of all H bridges in a single phase can be distributed in a wave-by-wave current limiting switching cycle at the same interval time.

[0079] The fourth step is to accumulate the number of times the wave-by-wave current limiting signal triggers the PWM module to perform wave blocking, and continuously determine whether the number of wave blocking times reaches the set upper limit of the wave-by-wave current limiting times. If the upper limit is reached, the upper limit flag of the wave-by-wave current limiting times is set, and the converter shutdown logic is performed.

[0080] When the wave-by-wave current limiting is performed according to the method of this embodiment, the PWM timing after the converter triggers the wave-by-wave current limiting and the timing of the wave-by-wave current limiting reset signal are as follows: Figure 5 The timing of continuous triggering of the wave-by-wave current limiting and the timing of closing the wave after exceeding the wave-by-wave current limiting times are shown as follows. Figure 6 shown.

[0081] In the second specific embodiment, a cascaded H-bridge inverter composed of four H-bridges in a single phase is also used as an example for explanation. The switching frequency PWM modulation method of the converter adopts carrier phase shift modulation, and the PWM carrier period is T s The wave-by-wave current limiting PWM wave-closing time length determined comprehensively according to the above embodiment is T lock In this embodiment, a timing counter is pre-set for each H bridge, and the reset signal triggering time of the RS latch module of each H bridge is obtained by its timing counter.

[0082] In this embodiment, in the first step, the current sensor converts the three-phase filter inductor current of the cascaded H-bridge converter into a corresponding real-time analog signal.

[0083] In the second step, the signal is input into the hysteresis comparator and compared with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively. When the signal representing the current exceeds the wave-by-wave current limiting threshold, the comparator outputs logic 1, that is, the wave-by-wave current limiting signal is valid; otherwise, the comparator outputs logic 0, that is, the wave-by-wave current limiting signal is invalid.

[0084] In the third step, the RS latch module, PWM signal processing module and timing counter of each H bridge perform wave-by-wave current limiting processing in a manner different from the first specific embodiment described above and reset based on the reset signal raised by the corresponding timing counter. Figure 7 For detailed description. Figure 7 As shown, the wave-by-wave current limiting process includes the following steps:

[0085] Step S701 : when the cascaded H-bridge converter is powered on, the timer of each H-bridge is controlled to be reset to the corresponding initial value for counting.

[0086] Specifically, when the converter system starts to power on, the timing counter corresponding to each H-bridge of the converter starts counting from the corresponding initial value. Similarly, the initial value corresponding to each timer is determined based on the triggering moment of the reset signal of the H-bridge. In order to achieve that the triggering moment of the reset signal of all H-bridges in a single phase in the above embodiment is distributed at the same interval in a wave-by-wave current limiting switching cycle, the initial value of each timer is set. According to the method of setting the triggering moment of the reset signal in the above embodiment, in this embodiment, the initial values ​​of the timing counters corresponding to H-bridge No. 1 to H-bridge No. 4 should be 0, T, and T, respectively. lock / 4, T lock / 2 and 3T lock / 4.

[0087] Step S702: When any timer counts to the duration of the reset signal cycle, a reset signal is generated and reset to 0 for cyclic counting.

[0088] Specifically, when a certain H-bridge timing counter counts to the set PWM wave blocking time T lock When the reset signal is generated, the reset signal is input to the RS latch module of the H bridge. The timing counter is controlled to reset to 0 and restart the next round of counting, and the cycle continues.

[0089] Step S703, after the wave-by-wave current limiting signal is input to the RS latch module, the RS latch module is controlled to update the latched wave-by-wave current limiting signal and output it to the corresponding PWM signal processing module.

[0090] Specifically, when the converter system starts to power on, according to the actual working situation, the generated wave-by-wave current limiting signal is subjected to wave sealing processing, and the wave sealing processing process is the same as the above embodiment. This step determines the order according to the time when the actual wave-by-wave current limiting signal is generated.

[0091] Step S704, when generating a reset signal, determine the state of the current wave-by-wave current limiting signal. If the current wave-by-wave current limiting signal is in an invalid state, clear the wave-by-wave current limiting signal latched in the RS latch module by outputting a reset signal. If the current wave-by-wave current limiting signal is in a valid state, invalidate the generated reset signal.

[0092] Specifically, when the reset signal is generated in step S702, the state of the current wave-by-wave current limiting signal is determined, and the state of the previous wave-by-wave current limiting signal is determined as follows: Figure 3 On the receiving channel of the reset signal shown, it is determined whether the reset signal is input to the R end of the RS latch module.

[0093] If the wave-by-wave current limiting signal is set to 0 before the reset signal is output to the R terminal of the RS latch module, the PWM signal processing module ends the blocking of the wave by resetting the signal and clearing the latch value through the reset signal, and returns to normal working state. If the current wave-by-wave current limiting signal is in a valid state, that is, the wave-by-wave current limiting signal is still set to 1, then the reset signal is determined to be invalid, and the signal is blocked from being input to the R terminal of the RS latch module. Then, the PWM signal processing module continues to block the wave until the next reset signal cycle T lock When the reset signal is valid, it is judged again according to the state of the wave-by-wave current limiting signal, and the cycle is repeated until the PWM signal stops blocking and returns to normal working state.

[0094] The fourth step is to accumulate the number of times the wave-by-wave current limiting signal triggers the PWM module to perform wave blocking, and continuously determine whether the number of wave blocking times reaches the set upper limit of the wave-by-wave current limiting times. If the upper limit is reached, the upper limit flag of the wave-by-wave current limiting times is set, and the converter shutdown logic is performed.

[0095] When the method of this embodiment is used to perform the wave-by-wave current limiting, the reset signal timing in the wave-by-wave current limiting process is as follows: Figure 8 shown.

[0096] In order to implement the above embodiment, the present application also proposes a wave-by-wave current limiting system of a cascaded H-bridge converter. Fig. 9 A schematic diagram of a wave-by-wave current limiting system of a cascaded H-bridge converter proposed in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the system includes: a collection module 100 , a comparison module 200 , a wave envelope module 300 and an accumulation module 400 .

[0097] The acquisition module 100 is used to acquire the three-phase filter inductor current outputted from the AC side of the cascaded H-bridge converter through a current sensor, and convert the three-phase filter inductor current into a current analog signal.

[0098] The comparison module 200 is used to input the current analog signal into the hysteresis comparator, compare it with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively, and use the comparison signal obtained by the hysteresis comparison as the wave-by-wave current limiting signal.

[0099] The wave sealing module 300 is used to input the wave-by-wave current limiting signal to the RS latch module preset in each H bridge of the cascaded H-bridge converter respectively, and perform wave sealing processing when the RS latch module inputs the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and control the wave-by-wave current limiting switching period of the H bridge based on the period of the reset signal output by the RS latch module, wherein the triggering time of the reset signal of all H bridges in a single phase is distributed in a wave-by-wave current limiting switching period at the same interval time.

[0100] The accumulation module 400 is used to accumulate the number of times the PWM signal processing module performs wave sealing, and when the number reaches the wave-by-wave current limiting number threshold, control the cascaded H-bridge converter to shut down.

[0101] Optionally, in one embodiment of the present application, the wave sealing module 300 is specifically used to: determine the wave-by-wave current limiting switching period of each H-bridge based on the operating frequency and current ripple parameters of the power switch of the cascaded H-bridge converter; set the period of the reset signal output by the RS latch module of each H-bridge to be equal to the wave-by-wave current limiting switching period; determine the difference between the triggering times of the reset signals corresponding to two adjacent H-bridges according to the wave-by-wave current limiting switching period and the number of H-bridges cascaded in a single phase.

[0102] Optionally, in one embodiment of the present application, the wave-sealing module 300 is specifically used to: after the wave-by-wave current limiting signal is input to the RS latch module, control the RS latch module to update the latched wave-by-wave current limiting signal and output it to the corresponding PWM signal processing module; while the PWM signal processing module performs wave-sealing processing, control the timer of each H-bridge to reset to the corresponding initial value for counting, wherein the initial value corresponding to each timer is determined based on the triggering moment of the reset signal of the H-bridge; when any timer counts to the duration of the reset signal cycle, generate a reset signal and judge the state of the current wave-by-wave current limiting signal; if the current wave-by-wave current limiting signal is in an invalid state, clear the latched wave-by-wave current limiting signal in the RS latch module by outputting a reset signal; if the current wave-by-wave current limiting signal is in a valid state, invalidate the generated reset signal and control any timer to reset to 0 for cyclic counting until the wave-sealing ends.

[0103] Optionally, in one embodiment of the present application, the wave sealing module 300 is specifically used to: when the cascaded H-bridge converter is powered on, control the timer of each H-bridge to reset to the corresponding initial value for counting; when any timer counts to the duration of the reset signal cycle, generate a reset signal and reset to 0 for cyclic counting; when generating the reset signal, judge the state of the current wave-by-wave current limiting signal, if the current wave-by-wave current limiting signal is in an invalid state, clear the wave-by-wave current limiting signal latched in the RS latch module by outputting the reset signal, and if the current wave-by-wave current limiting signal is in a valid state, invalidate the generated reset signal.

[0104] Optionally, in one embodiment of the present application, the comparison module 200 is specifically used to set the hysteresis parameter of the hysteresis comparator according to the current threshold range and anti-interference requirements of the cascaded H-bridge converter.

[0105] It should be noted that the above explanation of the embodiment of the wave-by-wave current limiting method for the cascaded H-bridge converter is also applicable to the system of this embodiment, and will not be repeated here.

[0106] In summary, the wave-by-wave current limiting method system of the cascaded H-bridge converter of the embodiment of the present application, based on the topological characteristics of the cascaded H-bridge itself, can take into account the current fluctuation and the operating frequency range of the power switch to perform wave-by-wave current limiting on the converter. For the cascaded H-bridge converter, in the wave-by-wave current limiting state, the PWM of each H-bridge recovers from the closed wave state to the normal state at different times, and recovers at equal time intervals, thereby effectively reducing the fluctuation amplitude of the converter output current, and the converter power switch tube can realize the wave-by-wave current limiting function at a lower operating frequency, and improve the equivalent switching frequency of the inverter, thereby improving the output performance of the cascaded H-bridge converter.

[0107] In order to implement the above-mentioned embodiments, the present application also proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the wave-by-wave current limiting method of the cascaded H-bridge converter as described in any one of the above-mentioned first aspect embodiments is implemented.

[0108] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0109] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0110] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0112] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0113] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0114] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0115] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A wave-by-wave current limiting method for a cascaded H-bridge converter, characterized in that: The following steps are involved: The collected three-phase filter inductor current analog signal on the AC side of the cascaded H-bridge converter is input into the hysteresis comparator, and compared with the positive current wave-by-wave current limiting threshold and the negative current wave-by-wave current limiting threshold respectively, and the comparison signal obtained by the hysteresis comparison is used as the wave-by-wave current limiting signal; The wave-by-wave current limiting signal is respectively input to the RS latch module preset in each H bridge of the cascaded H bridge converter, and the RS latch module performs wave sealing processing when inputting the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and based on the cycle of the reset signal output by the RS latch module, the wave-by-wave current limiting switching cycle of the H bridge is controlled, wherein the triggering moments of the reset signals of all H bridges in a single phase are distributed in one wave-by-wave current limiting switching cycle at the same interval time; The number of times the PWM signal processing module performs wave sealing is accumulated, and when the number reaches a threshold of the wave-by-wave current limiting number, the cascaded H-bridge converter is controlled to shut down.

2. The wave-by-wave current limiting method according to claim 1, characterized in that: Before the wave-enclosing process is performed, the method further includes: Determining the wave-by-wave current limiting switching period of each H-bridge based on the operating frequency and current ripple parameters of the power switch of the cascaded H-bridge converter; Setting the period of the reset signal output by the RS latch module of each H-bridge to be equal to the period of the wave-by-wave current limiting switch; The difference between the triggering moments of the reset signals corresponding to two adjacent H bridges is determined according to the wave-by-wave current limiting switching cycle and the number of H bridges cascaded in a single phase.

3. The wave-by-wave current limiting method according to claim 1, characterized in that: The S terminal of the RS latch module is used to receive the wave-by-wave current limiting signal, and the R terminal of the RS latch module is used to receive the reset signal; The output end of the RS latch module is connected to the input end of the corresponding PWM signal processing module, and the PWM signal processing module performs wave sealing processing when receiving the wave-by-wave current limiting signal; When the S terminal is in a valid state, the R terminal remains in an invalid state.

4. The wave-by-wave current limiting method according to claim 1, characterized in that: The triggering moment of the reset signal of each H-bridge is determined by the corresponding timer, and the wave-sealing processing is performed, and based on the cycle of the reset signal output by the RS latch module, the wave-by-wave current limiting switching cycle of the H-bridge is controlled, including: After the wave-by-wave current limiting signal is input to the RS latch module, the RS latch module is controlled to update the latched wave-by-wave current limiting signal and output it to the corresponding PWM signal processing module; While the PWM signal processing module performs the wave sealing processing, the timer of each H-bridge is controlled to be reset to a corresponding initial value for counting, wherein the initial value corresponding to each timer is determined based on the triggering moment of the reset signal of the H-bridge; When any timer counts to the length of the reset signal cycle, the reset signal is generated and the state of the current wave-by-wave current limiting signal is determined; If the current wave-by-wave current limiting signal is in an invalid state, the wave-by-wave current limiting signal latched in the RS latch module is cleared by outputting the reset signal; if the current wave-by-wave current limiting signal is in a valid state, the generated reset signal is invalidated and any timer is controlled to reset to 0 for cyclic counting until the wave sealing is ended.

5. The wave-by-wave current limiting method according to claim 4, characterized in that: The method of performing the wave sealing process and controlling the wave-by-wave current limiting switching cycle of the H bridge based on the cycle of the reset signal output by the RS latch module also includes: When the cascaded H-bridge converter is powered on, the timer of each H-bridge is controlled to be reset to the corresponding initial value for counting; When any timer counts to the duration of the reset signal cycle, the reset signal is generated and reset to 0 for cyclic counting; When generating the reset signal, the state of the current wave-by-wave current limiting signal is determined. If the current wave-by-wave current limiting signal is in an invalid state, the wave-by-wave current limiting signal latched in the RS latch module is cleared by outputting the reset signal. If the current wave-by-wave current limiting signal is in a valid state, the generated reset signal is invalidated.

6. The wave-by-wave current limiting method according to claim 1, characterized in that: Before inputting the current analog signal into the hysteresis comparator, the method further includes: The hysteresis parameter of the hysteresis comparator is set according to the current threshold range and anti-interference requirement of the cascaded H-bridge converter.

7. A wave-by-wave current limiting system for a cascaded H-bridge converter, characterized in that: include: An acquisition module is used to acquire the three-phase filter inductor current outputted from the AC side of the cascaded H-bridge converter through a current sensor, and convert the three-phase filter inductor current into a current analog signal; A comparison module, used for inputting the current analog signal into a hysteresis comparator, comparing it with a positive current wave-by-wave current limiting threshold and a negative current wave-by-wave current limiting threshold, and using a comparison signal obtained by hysteresis comparison as a wave-by-wave current limiting signal; A wave sealing module, used for inputting the wave-by-wave current limiting signal to the RS latch module preset in each H bridge of the cascaded H bridge converter respectively, performing wave sealing processing when the RS latch module inputs the wave-by-wave current limiting signal to the corresponding PWM signal processing module, and controlling the wave-by-wave current limiting switching cycle of the H bridge based on the cycle of the reset signal output by the RS latch module, wherein the triggering moments of the reset signals of all H bridges in a single phase are distributed in one wave-by-wave current limiting switching cycle at the same interval time; The accumulation module is used to accumulate the number of times the PWM signal processing module performs wave sealing, and when the number reaches a threshold of wave-by-wave current limiting times, control the cascaded H-bridge converter to shut down.

8. The wave-by-wave current limiting system according to claim 7, characterized in that: The wave-sealing module is specifically used for: Determining the wave-by-wave current limiting switching period of each H-bridge based on the operating frequency and current ripple parameters of the power switch of the cascaded H-bridge converter; Setting the period of the reset signal output by the RS latch module of each H-bridge to be equal to the period of the wave-by-wave current limiting switch; The difference between the triggering moments of the reset signals corresponding to two adjacent H bridges is determined according to the wave-by-wave current limiting switching cycle and the number of H bridges cascaded in a single phase.

9. The wave-by-wave current limiting system according to claim 7, characterized in that: The comparison module is specifically used for: The hysteresis parameter of the hysteresis comparator is set according to the current threshold range and anti-interference requirement of the cascaded H-bridge converter.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the wave-by-wave current limiting method for the cascaded H-bridge converter according to any one of claims 1 to 6 is implemented.

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