Driver circuit controlled by cross-coupling dead time

Abstract

The invention discloses a driver circuit controlled by cross-coupling dead time. The driver circuit comprises a signal input end VIN, an upper arm driving unit, a lower arm driving unit, a first dead time controller, a second dead time controller and a signal output end VOUT, the signal input end VIN is connected with the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected with the signal output end VOUT, the first dead time controller is connected with the upper arm driving unit and the lower arm driving unit, and the second dead time controller is connected with the upper arm driving unit and the lower arm driving unit; each of the upper arm driving unit and the lower arm driving unit comprises a logic module for sequential control; a control signal of the upper arm driving unit controls the conduction or cut-off of the lower arm driving unit through cross coupling of a first dead zone time controller, and meanwhile, a control signal after the conduction or cut-off of the lower arm driving unit controls the conduction or cut-off of the upper arm driving unit through cross coupling; the first dead time controller and the second dead time controller control the dead time by controlling the conduction time difference between the upper arm driving unit and the lower arm driving unit.

Description

Technical Field

[0001] The present application belongs to the technical field of drivers, and specifically refers to a driver circuit with cross-coupling dead time control. Background Art

[0002] Dead time refers to the time difference between the two tubes being turned off when the switch tube is switched in the switching power supply. Its purpose is to avoid short circuit caused by the upper and lower tubes being turned on at the same time, so as to prevent the power components from burning out. The dead time control between the upper arm drive unit and the lower arm drive unit in the high-voltage gate driver is very important. If the dead time is too short, the upper arm drive unit and the lower arm drive unit will be penetrated, resulting in large current and high voltage on the power device at the same time, and the power consumption will increase sharply, damaging the device; if the dead time is too long, the upper arm drive unit and the lower arm drive unit will be cut off for a long time at the same time, which is easy to be interfered by external signals, and may also cause increased power consumption, and serious functional errors will cause irreversible damage to the entire system. Therefore, the dead time control of the high-voltage gate driver is very important.

[0003] The dead time control in the prior art is usually achieved by delaying resistors and capacitors, that is, a power device is turned off by a short delay, and another power device is turned on by a long delay, and the time difference between the long delay and the short delay is used to control the dead time. The disadvantage of this solution is that during the manufacturing process of semiconductor devices, the actual values ​​of resistors and capacitors deviate greatly from the designed values, which may cause the long delay and the short delay to be far from the designed values, resulting in a smaller dead time, a pass-through between the upper arm drive unit and the lower arm drive unit, and a large current and high voltage on the power device at the same time, which increases power consumption sharply, damages the device and then damages the system. That is, the delay scheme of resistors and capacitors used in the prior art has poor stability and is prone to large errors. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present application provides a driver circuit with cross-coupling dead time control, which adopts logic timing control and performs cross-coupling control according to the conduction relationship between the upper arm driving unit and the lower arm driving unit, thereby realizing dead time control.

[0005] The present invention provides a driver circuit for cross-coupling dead time control, the driver circuit comprising: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead time controller, a second dead time controller and a signal output terminal VOUT; the signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT, the first dead time controller is connected to the upper arm driving unit and the lower arm driving unit, the second dead time controller is connected to the upper arm driving unit and the lower arm driving unit; the upper arm driving unit and the lower arm driving unit both comprise a logic module for timing control;

[0006] The control signal of the upper arm driving unit is cross-coupled through the first dead time controller to control the on or off of the lower arm driving unit, and the control signal after the on or off of the lower arm driving unit is cross-coupled to control the on or off of the upper arm driving unit; the first dead time controller and the second dead time controller control the dead time by controlling the on time difference between the upper arm driving unit and the lower arm driving unit.

[0007] According to the driver circuit for cross-coupling dead time control provided by the present application, the upper arm driving unit includes a first level shifter, a first logic circuit module and a first transistor; the control input end of the first level shifter is connected to the signal input end VIN, the control output end of the first level shifter is connected to the first input end of the first logic circuit module, and the output end of the first logic circuit module is connected to the control input end of the first dead time controller and the gate of the first transistor; the source of the first transistor is connected to the level input end of the upper arm driving unit, and the drain of the first transistor is connected to the signal output end VOUT;

[0008] Wherein, the first transistor is a PMOS transistor.

[0009] According to the driver circuit for cross-coupling dead time control provided by the present application, the lower arm driving unit includes a second level shifter, a second logic circuit module and a second transistor; the control input end of the second level shifter is connected to the signal input end VIN, the control output end of the second level shifter is connected to the first input end of the second logic circuit module, and the output end of the second logic circuit module is connected to the control input end of the second dead time controller and the gate of the second transistor; the source of the second transistor is connected to the ground end of the lower arm driving unit, and the drain of the second transistor is connected to the signal output end VOUT;

[0010] Wherein, the second transistor is an NMOS transistor.

[0011] According to the cross-coupled dead time controlled driver circuit provided by the present application, the upper arm driving unit is a high voltage domain driving unit, and the lower arm driving unit is a low voltage domain driving unit;

[0012] The first level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage power supply VDD_HIGH of a high voltage domain and a ground GND_HIGH of a high voltage domain, and the control output terminal of the first level shifter outputs an output signal VIN_HIGH of the high voltage domain;

[0013] The second level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage supply VDD_LOW in the low voltage domain and a ground GND in the low voltage domain, and the control output terminal of the second level shifter outputs an output signal VIN_LOW in the low voltage domain.

[0014] According to the cross-coupled dead time controlled driver circuit provided by the present application, the output signal VIN_HIGH of the high voltage domain and the output signal VIN_LOW of the low voltage domain have the same phase.

[0015] According to the cross-coupled dead time controlled driver circuit provided by the present application, the first logic circuit module includes a NAND gate, a first inverter, a second inverter, a third inverter and a fourth inverter, the first input end of the NAND gate is connected to the output signal VIN_HIGH of the high voltage domain, the second input end of the NAND gate is connected to the control output end of the second dead time controller, and the output end of the NAND gate is connected to the input end of the first inverter; the first inverter, the second inverter, the third inverter and the fourth inverter are connected in series in sequence, and the output end of the fourth inverter is connected to the gate of the first transistor; the NAND gate, the first inverter, the second inverter, the third inverter and the fourth inverter are all connected to the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

[0016] According to the cross-coupled dead time controlled driver circuit provided by the present application, the second logic circuit module includes an NOR gate, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter, the first input end of the NOR gate is connected to the output signal VIN_LOW of the low voltage domain, the second input end of the NOR gate is connected to the control output end of the first dead time controller, and the output end of the NOR gate is connected to the input end of the fifth inverter; the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are connected in series in sequence, and the output end of the eighth inverter is connected to the gate of the second transistor; the NOR gate, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are all connected to the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain.

[0017] According to the cross-coupled dead time controlled driver circuit provided by the present application, the first dead time controller is a third level shifter, and the second dead time controller is a fourth level shifter;

[0018] The control input end of the third level shifter is connected to the output end of the third inverter, the control output end of the third level shifter is connected to the second input end of the NOR gate, and the third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain;

[0019] The control input end of the fourth level shifter is connected to the output end of the seventh inverter, the control output end of the fourth level shifter is connected to the second input end of the NAND gate, and the fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

[0020] According to the cross-coupled dead time controlled driver circuit provided in the present application, when the signal input terminal VIN changes from a low level to a high level, the output signal VIN_LOW of the low voltage domain makes the same jump, the second transistor is turned off, the fourth level shifter converts the high level of the low voltage domain input at the control input terminal into the high level of the high voltage domain and outputs it to the NAND gate, the first transistor is turned on, and the signal output terminal VOUT outputs a high level.

[0021] According to the cross-coupled dead time controlled driver circuit provided in the present application, when the signal input terminal VIN changes from a high level to a low level, the output signal VIN_LOW of the low voltage domain and the output signal VIN_HIGH of the high voltage domain make the same jump, the first transistor is turned off, the third level shifter converts the low level of the high voltage domain input at the control input terminal into the low level of the low voltage domain and outputs it to the NOR gate, the second transistor is turned on, and the signal output terminal VOUT outputs a low level.

[0022] The beneficial effects of the present invention are as follows: the present application provides a driver circuit with cross-coupling dead time control, wherein both the upper arm driving unit and the lower arm driving unit include logic modules for timing control, and cross-coupling control is performed according to the conduction relationship between the upper arm driving unit and the lower arm driving unit. The upper arm driving unit will be turned on only after the lower arm driving unit is turned off and after the conversion of the second dead time controller; or the lower arm driving unit will be turned on only after the upper arm driving unit is turned off and after the conversion of the first dead time controller. Therefore, it can be effectively ensured that the upper arm driving unit and the lower arm driving unit will not be turned on at the same time, avoiding the occurrence of the upper arm driving unit and the lower arm driving unit being through, and realizing the dead time control of the driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0024] Figure 1 This is a schematic diagram of the structure of a driver circuit with cross-coupling dead time control provided in this embodiment. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0028] The embodiments of the present application are now further described in conjunction with the accompanying drawings and specific implementation methods.

[0029] Figure 1 A schematic diagram of the structure of a driver circuit with cross-coupling dead time control provided in an embodiment of the present application.

[0030] like Figure 1As shown, the driver circuit provided in this embodiment mainly includes: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead time controller, a second dead time controller and a signal output terminal VOUT; the signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT, the first dead time controller is connected to the upper arm driving unit and the lower arm driving unit, and the second dead time controller is connected to the upper arm driving unit and the lower arm driving unit; the upper arm driving unit and the lower arm driving unit both include a logic module for timing control; only one of the upper arm driving unit and the lower arm driving unit is turned on and outputs a signal from the signal output terminal VOUT.

[0031] The control signal of the upper arm driving unit is cross-coupled through the first dead time controller to control the on or off of the lower arm driving unit, and the control signal after the on or off of the lower arm driving unit is cross-coupled to control the on or off of the upper arm driving unit; only when the upper arm driving unit is cut off and a corresponding control signal is sent, and transmitted to the lower arm driving unit through the first dead time controller, can the lower arm driving unit be controlled to be turned on; or only when the lower arm driving unit is cut off and a corresponding control signal is sent, and transmitted to the upper arm driving unit through the second dead time controller, can the upper arm driving unit be controlled to be turned on. The first dead time controller and the second dead time controller control the dead time by controlling the on time difference between the upper arm driving unit and the lower arm driving unit.

[0032] like Figure 1 As shown, the upper arm driving unit includes a first level shifter, a first logic circuit module and a first transistor PM1; the control input end of the first level shifter is connected to the signal input end VIN, the control output end of the first level shifter is connected to the first input end of the first logic circuit module, and the output end of the first logic circuit module is connected to the control input end of the first dead time controller and the gate of the first transistor PM1; the source of the first transistor PM1 is connected to the level input end of the upper arm driving unit, and the drain of the first transistor PM1 is connected to the signal output end VOUT; wherein the first transistor PM1 is a PMOS transistor. When the first transistor PM1 is turned on, the signal output end VOUT outputs a high level.

[0033] The lower arm driving unit includes a second level shifter, a second logic circuit module and a second transistor NM1; the control input end of the second level shifter is connected to the signal input end VIN, the control output end of the second level shifter is connected to the first input end of the second logic circuit module, and the output end of the second logic circuit module is connected to the control input end of the second dead time controller and the gate of the second transistor NM1; the source of the second transistor NM1 is connected to the ground end of the lower arm driving unit, and the drain of the second transistor NM1 is connected to the signal output end VOUT; wherein the second transistor NM1 is an NMOS transistor. When the second transistor NM1 is turned on, the signal output end VOUT outputs a low level.

[0034] Specifically, in this embodiment, the upper arm driving unit is a high voltage domain driving unit, and the lower arm driving unit is a low voltage domain driving unit;

[0035] The first level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage power supply VDD_HIGH of a high voltage domain and a ground GND_HIGH of a high voltage domain, and the control output terminal of the first level shifter outputs an output signal VIN_HIGH of the high voltage domain;

[0036] The second level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage supply VDD_LOW in the low voltage domain and a ground GND in the low voltage domain, and the control output terminal of the second level shifter outputs an output signal VIN_LOW in the low voltage domain.

[0037] The output signal VIN_HIGH of the high voltage domain and the output signal VIN_LOW of the low voltage domain have the same phase.

[0038] The first level shifter converts the input signal VIN of the signal input terminal VIN into an output signal VIN_HIGH of the high voltage domain among a voltage power supply VDD_HIGH of the high voltage domain and a ground GND_HIGH of the high voltage domain. Meanwhile, the second level shifter converts the input signal VIN of the signal input terminal VIN into an output signal VIN_LOW of the low voltage domain among a voltage power supply VDD_LOW of the low voltage domain and a ground GND of the low voltage domain.

[0039] In another embodiment, the upper arm driving unit may be a low voltage domain driving unit, and the lower arm driving unit may be a high voltage domain driving unit, which will not be described in detail here.

[0040] like Figure 1As shown, in the first logic circuit module, the first logic circuit module includes a NAND gate NAND1, a first inverter INV1, a second inverter INV2, a third inverter INV3 and a fourth inverter INV4, the first input end of the NAND gate NAND1 is connected to the output signal VIN_HIGH of the high voltage domain, the second input end of the NAND gate NAND1 is connected to the control output end of the second dead time controller, and the output end of the NAND gate NAND1 is connected to the input end of the first inverter INV1; the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 are connected in series in sequence, and the output end of the fourth inverter INV4 is connected to the gate of the first transistor PM1; the NAND gate NAND1, the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 are all connected to the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain. The first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 invert the level signal of the input end in turn, converting the high level of the input end into a low level, or converting the low level of the input end into a high level. When the gate of the first transistor PM1 is at a high level, the first transistor PM1 is turned off.

[0041] In the second logic circuit module, the second logic circuit module includes a NOR gate NOR1, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7 and an eighth inverter INV8, the first input end of the NOR gate NOR1 is connected to the output signal VIN_LOW of the low voltage domain, the second input end of the NOR gate NOR1 is connected to the control output end of the first dead time controller, and the output end of the NOR gate NOR1 is connected to the input end of the fifth inverter INV5; the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 are connected in series in sequence, and the output end of the eighth inverter INV8 is connected to the gate of the second transistor NM1; the NOR gate NOR1, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 are all connected to the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain. The fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 invert the level signal of the input end in turn, converting the high level of the input end into a low level, or converting the low level of the input end into a high level. When the gate of the second transistor NM1 is at a low level, the second transistor NM1 is turned off.

[0042] like Figure 1 As shown, in this embodiment, the first dead time controller is a third level shifter, and the second dead time controller is a fourth level shifter.

[0043] The control input end of the third level shifter is connected to the output end of the third inverter INV3, the control output end of the third level shifter is connected to the second input end of the NOR gate NOR1, and the third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain;

[0044] The control input end of the fourth level shifter is connected to the output end of the seventh inverter INV7, the control output end of the fourth level shifter is connected to the second input end of the NAND gate NAND1, and the fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

[0045] In this embodiment, when the signal input terminal VIN changes from a low level to a high level, the output signal VIN_LOW of the low voltage domain makes the same jump, the second transistor NM1 is turned off, the fourth level shifter converts the high level of the low voltage domain input at the control input terminal into a high level of the high voltage domain and outputs it to the NAND gate NAND1, the first transistor PM1 is turned on, and the signal output terminal VOUT outputs a high level.

[0046] When the signal input terminal VIN changes from a high level to a low level, the output signal VIN_LOW of the low voltage domain and the output signal VIN_HIGH of the high voltage domain make the same jump, the first transistor NM1 is turned off, the third level shifter converts the low level of the high voltage domain input at the control input terminal into the low level of the low voltage domain and outputs it to the NOR gate NOR1, the second transistor NM1 is turned on, and the signal output terminal VOUT outputs a low level.

[0047] The working principle of the driver circuit for cross-coupling dead time control provided in this embodiment is as follows:

[0048] When the input signal VIN of the signal input terminal VIN changes from a low level to a high level, the output signal VIN_LOW of the low voltage domain outputted by the control output terminal of the second level shifter also makes the same jump, that is, the output signal VIN_LOW of the low voltage domain changes to a high level. The high-level output signal VIN_LOW of the low voltage domain sequentially passes through the NOR gate NOR1, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 in the second logic circuit module, so that the output terminal of the eighth inverter INV8 outputs a low level, that is, the gate input of the second transistor NM1 is a low level, and the second transistor NM1 becomes cut-off state. At the same time, the output end of the seventh inverter INV7 becomes a high-level signal, and the high-level signal output by the seventh inverter INV7 is input into the fourth level shifter. The fourth level shifter converts the high-level signal of the low-voltage domain input into a high-level signal of the high-voltage domain and outputs it to the NAND gate NAND1. At this time, both input ends of the NAND gate NAND1 input high-level signals, and the output end of the NAND gate NAND1 outputs a low-level signal. The low-level signal output by the NAND gate NAND1 passes through the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 in sequence, so that the output end of the fourth inverter INV4 outputs a low-level signal, that is, the gate input of the first transistor PM1 is low-level, the first transistor PM1 becomes conductive, and at the same time, the signal output end VOUT outputs a high-level signal.

[0049] When the input signal VIN of the signal input terminal VIN changes from a high level to a low level, the output signal VIN_HIGH of the high voltage domain outputted by the control output terminal of the first level shifter and the output signal VIN_LOW of the low voltage domain outputted by the control output terminal of the second level shifter also make the same jump, except that the voltage domains of the output signals are different, that is, the output signal VIN_HIGH of the high voltage domain changes to a low level. The output signal VIN_HIGH of the high voltage domain of the low level sequentially passes through the NAND gate NAND1, the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fourth inverter INV4 in the first logic circuit module, so that the output terminal of the fourth inverter INV4 outputs a high level, that is, the gate input of the first transistor PM1 is a high level, and the first transistor PM1 becomes a cut-off state. At the same time, the output end of the third inverter INV3 becomes a low-level signal, and the low-level signal output by the third inverter INV3 is input into the third level shifter, and the third level shifter converts the low level of the high-voltage domain input at the control input end into the low level of the low-voltage domain and outputs it to the NOR gate NOR1. At this time, both input ends of the NOR gate NOR1 input low-level signals, and the output end of the NOR gate NOR1 outputs a high-level signal. The high-level signal output by the NOR gate NOR1 passes through the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7 and the eighth inverter INV8 in sequence, so that the output end of the eighth inverter INV8 outputs a high-level signal, that is, the gate input of the second transistor NM1 is high, the second transistor becomes conductive, and at the same time, the signal output end VOUT outputs a low-level signal.

[0050] In this embodiment, when the input signal VIN of the signal input terminal VIN changes from a low level to a high level, the second transistor NM1 is first turned into a cut-off state through the second logic circuit module, and then the high-level signal output by the seventh inverter INV7 is used to turn the first transistor PM1 into a conducting state through the second dead time controller and the first logic circuit module, so that a dead time can be formed when the input signal VIN changes from a low level to a high level, thereby avoiding the first transistor PM1 and the second transistor NM1 being turned on at the same time.

[0051] Similarly, when the input signal VIN of the signal input terminal VIN changes from a high level to a low level, the first transistor PM1 is first turned into a cut-off state through the first logic circuit module, and then the second transistor NM1 is turned into a conducting state through the first dead time controller and the second logic circuit module using the low level signal output by the third inverter INV3, thereby forming a dead time when the input signal VIN changes from a high level to a low level, thereby avoiding the first transistor PM1 and the second transistor NM1 being turned on at the same time.

[0052] The present application provides a driver circuit with cross-coupling dead time control, wherein both the upper arm driving unit and the lower arm driving unit include logic modules for timing control, and cross-coupling control is performed according to the conduction relationship between the upper arm driving unit and the lower arm driving unit. The upper arm driving unit will be turned on only after the lower arm driving unit is turned off and after the conversion of the second dead time controller; or the lower arm driving unit will be turned on only after the upper arm driving unit is turned off and after the conversion of the first dead time controller. Therefore, it can be effectively ensured that the upper arm driving unit and the lower arm driving unit will not be turned on at the same time, avoiding the occurrence of the upper arm driving unit and the lower arm driving unit being through, and realizing the dead time control of the driver.

[0053] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the attached claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention. Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0054] The above is a detailed introduction to a driver circuit with cross-coupled dead time control provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A driver circuit with cross-coupling dead time control, characterized in that: The driver circuit comprises: a signal input terminal VIN, an upper arm driving unit, a lower arm driving unit, a first dead time controller, a second dead time controller and a signal output terminal VOUT; the signal input terminal VIN is connected to the upper arm driving unit and the lower arm driving unit, the upper arm driving unit and the lower arm driving unit are connected to the signal output terminal VOUT, the first dead time controller is connected to the upper arm driving unit and the lower arm driving unit, and the second dead time controller is connected to the upper arm driving unit and the lower arm driving unit; the upper arm driving unit and the lower arm driving unit both comprise a logic module for timing control; The control signal of the upper arm driving unit is cross-coupled through the first dead time controller to control the on or off of the lower arm driving unit, and the control signal after the on or off of the lower arm driving unit is cross-coupled to control the on or off of the upper arm driving unit; the first dead time controller and the second dead time controller control the dead time by controlling the on time difference between the upper arm driving unit and the lower arm driving unit.

2. The cross-coupled dead time controlled driver circuit according to claim 1, characterized in that: The upper arm driving unit includes a first level shifter, a first logic circuit module and a first transistor; the control input end of the first level shifter is connected to the signal input end VIN, the control output end of the first level shifter is connected to the first input end of the first logic circuit module, and the output end of the first logic circuit module is connected to the control input end of the first dead time controller and the gate of the first transistor; the source of the first transistor is connected to the level input end of the upper arm driving unit, and the drain of the first transistor is connected to the signal output end VOUT; Wherein, the first transistor is a PMOS transistor.

3. The cross-coupled dead time controlled driver circuit according to claim 2, characterized in that: The lower arm driving unit includes a second level shifter, a second logic circuit module and a second transistor; the control input end of the second level shifter is connected to the signal input end VIN, the control output end of the second level shifter is connected to the first input end of the second logic circuit module, and the output end of the second logic circuit module is connected to the control input end of the second dead time controller and the gate of the second transistor; the source of the second transistor is connected to the ground end of the lower arm driving unit, and the drain of the second transistor is connected to the signal output end VOUT; Wherein, the second transistor is an NMOS transistor.

4. The cross-coupled dead time controlled driver circuit according to claim 3, characterized in that: The upper arm driving unit is a high voltage domain driving unit, and the lower arm driving unit is a low voltage domain driving unit; The first level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage power supply VDD_HIGH of a high voltage domain and a ground GND_HIGH of a high voltage domain, and the control output terminal of the first level shifter outputs an output signal VIN_HIGH of the high voltage domain; The second level shifter converts the input power supply voltage VDD and the ground GND of the driving circuit into a voltage supply VDD_LOW in the low voltage domain and a ground GND in the low voltage domain, and the control output terminal of the second level shifter outputs an output signal VIN_LOW in the low voltage domain.

5. The cross-coupled dead time controlled driver circuit according to claim 4, characterized in that: The output signal VIN_HIGH of the high voltage domain and the output signal VIN_LOW of the low voltage domain have the same phase.

6. The cross-coupled dead time controlled driver circuit according to claim 4, characterized in that: The first logic circuit module includes a NAND gate, a first inverter, a second inverter, a third inverter and a fourth inverter, the first input end of the NAND gate is connected to the output signal VIN_HIGH of the high voltage domain, the second input end of the NAND gate is connected to the control output end of the second dead time controller, and the output end of the NAND gate is connected to the input end of the first inverter; the first inverter, the second inverter, the third inverter and the fourth inverter are connected in series in sequence, and the output end of the fourth inverter is connected to the gate of the first transistor; the NAND gate, the first inverter, the second inverter, the third inverter and the fourth inverter are all connected to the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

7. The cross-coupled dead time controlled driver circuit according to claim 6, characterized in that: The second logic circuit module includes a NOR gate, a fifth inverter, a sixth inverter, a seventh inverter and an eighth inverter, wherein the first input end of the NOR gate is connected to the output signal VIN_LOW of the low voltage domain, the second input end of the NOR gate is connected to the control output end of the first dead time controller, and the output end of the NOR gate is connected to the input end of the fifth inverter; the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are connected in series in sequence, and the output end of the eighth inverter is connected to the gate of the second transistor; the NOR gate, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are all connected to the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain.

8. The cross-coupled dead time controlled driver circuit according to claim 7, characterized in that: The first dead time controller is a third level shifter, and the second dead time controller is a fourth level shifter; The control input end of the third level shifter is connected to the output end of the third inverter, the control output end of the third level shifter is connected to the second input end of the NOR gate, and the third level shifter converts the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain into the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain; The control input end of the fourth level shifter is connected to the output end of the seventh inverter, the control output end of the fourth level shifter is connected to the second input end of the NAND gate, and the fourth level shifter converts the voltage power supply VDD_LOW of the low voltage domain and the ground GND of the low voltage domain into the voltage power supply VDD_HIGH of the high voltage domain and the ground GND_HIGH of the high voltage domain.

9. The cross-coupled dead time controlled driver circuit according to claim 8, characterized in that: When the signal input terminal VIN changes from a low level to a high level, the output signal VIN_LOW of the low voltage domain makes the same jump, the second transistor is turned off, the fourth level shifter converts the high level of the low voltage domain input at the control input terminal into the high level of the high voltage domain and outputs it to the NAND gate, the first transistor is turned on, and the signal output terminal VOUT outputs a high level.

10. The cross-coupled dead time controlled driver circuit according to claim 8, characterized in that: When the signal input terminal VIN changes from a high level to a low level, the output signal VIN_LOW of the low voltage domain and the output signal VIN_HIGH of the high voltage domain make the same jump, the first transistor is turned off, the third level shifter converts the low level of the high voltage domain input at the control input terminal into the low level of the low voltage domain and outputs it to the NOR gate, the second transistor is turned on, and the signal output terminal VOUT outputs a low level.

Images