A control circuit, switching power supply, power supply system and power distribution system

Abstract

The present invention discloses a control circuit, a switching power supply, a power supply system, and a power distribution system. The control circuit includes: a first bias circuit for controlling a field-effect transistor to remain on; a shutdown circuit for controlling the field-effect transistor to shut down when current flows from the drain to the source; a second bias circuit, a first bipolar transistor, and a compensation circuit. A second bias voltage is input to one end of the second bias circuit; the other end of the second bias circuit, the base of the first bipolar transistor, and the first and second ends of the compensation circuit are connected to a first node; the collector of the first bipolar transistor is connected to the gate of the field-effect transistor, the emitter is connected to the source of the field-effect transistor, and the third end of the compensation circuit is connected to the drain of the field-effect transistor; the compensation circuit is used to compensate for the voltage between the source and drain of the field-effect transistor and the voltage between the base and emitter of the first bipolar transistor. The field-effect transistor of the present invention has a low on-state voltage drop and a fast shutdown speed, which is conducive to improving the efficiency and applicability of the switching power supply and power distribution system.

Description

Technical Field

[0001] The present invention belongs to the field of switching power supplies, and in particular relates to a control method of an ORing circuit and a circuit thereof, a switching power supply, and a power distribution system having the switching power supply. Background Art

[0002] The application of ORing circuits (automatic switching circuits to prevent backflow) in switching power supplies is currently very widespread, especially in the need for parallel operation and multi-channel redundant power supplies. When multiple low-current power supplies are connected in parallel, diodes are usually used directly to prevent backflow. However, in high-current applications, such as power distribution systems such as new energy vehicle charging stations, diodes will cause significant losses and heat problems. Therefore, MOSFET-based ORing circuits have become the most popular demand in the power supply industry. To prevent a single power supply output short-circuit fault from degrading the bus voltage, it is necessary to quickly shut down the MOSFET by detecting the voltage across its two ends and prevent current backflow by reverse-biasing the MOSFET body diode. It is also necessary to ensure output voltage accuracy and low cost. Summary of the Invention

[0003] In view of this, the technical problem to be solved by the present invention is to provide a control circuit, a switching power supply, a power supply system and a power distribution system, which at least to a certain extent solve one of the technical problems existing in the prior art.

[0004] As a first aspect of the present invention, the technical solution of the control circuit embodiment provided is as follows:

[0005] A control circuit for controlling the on and off of a field effect transistor, wherein the source of the field effect transistor is connected to the output of a power supply, and the drain of the field effect transistor is connected to a bus, wherein the control circuit comprises:

[0006] a first bias circuit, used for controlling the field effect transistor to remain conductive, wherein one end of the first bias circuit is used for inputting a first bias voltage, and the other end is used for connecting to the gate of the field effect transistor;

[0007] a shutdown circuit, configured to control the field-effect transistor to shut down when current in the field-effect transistor flows from the drain to the source, the shutdown circuit comprising a second bias circuit, a first bipolar transistor, and a compensation circuit, wherein one end of the second bias circuit is configured to input a second bias voltage, the other end of the second bias circuit, the base of the first bipolar transistor, the first end of the compensation circuit, and the second end of the compensation circuit are connected to a first node, the collector of the first bipolar transistor is configured to connect to the gate of the field-effect transistor, the emitter of the first bipolar transistor is configured to connect to the source of the field-effect transistor, and the third end of the compensation circuit is configured to connect to the drain of the field-effect transistor;

[0008] The compensation circuit is used to compensate for the voltage between the source and drain of the field-effect transistor and the voltage between the base and emitter of the first bipolar transistor, thereby reducing the conduction voltage drop of the field-effect transistor when the current in the field-effect transistor flows from the source to the drain, and increasing the turn-off speed of the field-effect transistor when the current in the field-effect transistor flows from the drain to the source.

[0009] Preferably, the compensation circuit includes a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together to form a first end of the compensation circuit, the collector of the second bipolar transistor is the second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is the third end of the compensation circuit;

[0010] The voltage between the collector and the emitter of the second bipolar transistor is a first compensation voltage, compensating for the voltage between the base and the emitter of the first bipolar transistor;

[0011] The voltage between the emitter and the collector of the third bipolar transistor is a second compensation voltage, which compensates the voltage between the source and the drain of the field effect transistor.

[0012] Furthermore, the second bipolar transistor and the first bipolar transistor have the same specifications.

[0013] Furthermore, the third bipolar transistor is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop of the field effect transistor.

[0014] Furthermore, the first bipolar transistor, the second bipolar transistor and the third bipolar transistor are each packaged separately, or two of them are packaged together, or all three are packaged together.

[0015] Preferably, the first bias circuit is a resistor R1 and / or the second bias circuit is a resistor R2.

[0016] Furthermore, the first bias voltage and the second bias voltage are the same.

[0017] Preferably, the compensation circuit includes a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together to form a first end of the compensation circuit, the collector of the second bipolar transistor is the second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is the third end of the compensation circuit;

[0018] The first bias circuit is a resistor R1;

[0019] The second bias circuit is a resistor R2;

[0020] The first bias voltage and the second bias voltage are the same.

[0021] As a first aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows:

[0022] A switching power supply, comprising a field effect transistor, wherein the field effect transistor is arranged in an output circuit inside the switching power supply, and the switching power supply further comprises a control circuit according to any of the above solutions.

[0023] As a third aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows:

[0024] A power supply system, wherein: the power supply system includes N switching power supplies and N field-effect transistors, N is a natural number greater than or equal to 2, the source of each field-effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, the power supply system also includes N control circuits according to any one of claims 1 to 7, each of the control circuits is used to control the conduction and shutdown of one of the N field-effect transistors.

[0025] As a fourth aspect of the present invention, a power distribution system is provided, which includes the above-mentioned switching power supply.

[0026] The beneficial effects of the present invention are:

[0027] 1. The control circuit of the embodiment of the present invention is provided with a compensation circuit that can compensate for the voltage between the source and drain of the field-effect transistor, thereby reducing the forward voltage drop of the field-effect transistor when the current in the field-effect transistor flows from the source to the drain, so that the forward voltage of the field-effect transistor is reduced to about 30mV, thereby improving power supply efficiency;

[0028] 2. The compensation circuit provided in the control circuit of the embodiment of the present invention can also compensate for the voltage between the base and the emitter of the bipolar transistor, thereby increasing the turn-off speed of the field-effect transistor when the current in the field-effect transistor flows from the drain to the source, making the backflow current of the field-effect transistor smaller, improving the power supply reliability, and further improving the applicability of the power supply system and the power distribution system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a circuit schematic diagram of the first existing ORing circuit;

[0030] Figure 2 is a circuit schematic diagram of a second conventional ORing circuit;

[0031] Figure 3 is a circuit schematic diagram of a third existing ORing circuit;

[0032] Figure 4 It is a structural diagram of an existing NPN bipolar transistor;

[0033] Figure 5 is a circuit schematic diagram of a fourth conventional ORing circuit;

[0034] Figure 6 A specific circuit schematic diagram of the control circuit of the first embodiment of the present invention;

[0035] Figure 7 for Figure 6 The circuit's working waveform simulation diagram;

[0036] Figure 8 for Figure 6 Schematic diagram of the application of the circuit in the current-sharing parallel power supply system;

[0037] Figure 9 for Figure 8 The circuit's working waveform simulation diagram. DETAILED DESCRIPTION

[0038] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0039] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0040] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate to describe the embodiments of the present application here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] It should be understood that in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.

[0042] In addition, the figures of this disclosure are merely schematic diagrams of the present disclosure and are not necessarily drawn to scale. Identical reference numbers in the figures denote identical or similar parts, and therefore repeated descriptions thereof will be omitted. Some of the blocks shown in the figures are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented using software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontrollers.

[0043] MOSFET-based ORing circuits are a hot topic in the power supply industry. The inventors of this application have conducted in-depth research on existing technologies and found that although MOSFET on- and off-control can be achieved with only a few components, the results are unsatisfactory. This is because the circuit design of existing technologies mainly stays at the application layer, ignoring the physical layer working mechanism of components and the impact of manufacturing process deviations on circuit implementation performance. Therefore, the inventors of this application have conducted in-depth analysis and verification of typical ORing circuits in existing technologies and found that they all have certain defects, as follows:

[0044] Patent No. US6060943 discloses an ORing circuit, such as Figure 1 、 Figure 2 As shown (from the patent appendix Figure 7 , Attachment Figure 8 ). Among them, Figure 1 The ORing circuit solution mentioned above has the disadvantages of poor accuracy of the power supply output voltage under different loads and large reverse current due to the different production processes of the bipolar transistor 56 and the diode 59, which leads to a large difference between the voltage VBE between the base and emitter of the bipolar transistor 56 and the forward conduction voltage drop VF of the diode 59. Figure 2 In the ORing circuit solution, the reverse bias voltage VEB between the emitter and base of bipolar transistor 69 is generally only about 6 to 7V in the industry. When a single power supply fails, the bus voltage is applied to the series branch between the emitter and base of bipolar transistor 69 and the base and emitter of bipolar transistor 68, which will cause voltage stress breakdown damage to bipolar transistors 68 and 69.

[0045] Patent No. US7636011B2 also discloses an ORing circuit, such as Figure 3 As shown (from the patent appendix Figure 1 ). Among them, Figure 3 The ORing circuit solution is to short-circuit the emitter and base of the bipolar transistor 106 to obtain a diode structure formed by the base and the collector to reduce the voltage between the base and the emitter of the bipolar transistor and the voltage between the base and the collector of the bipolar transistor to solve the problem. Figure 1 Program and Figure 2 The inventors of this application have found that Figure 4 As shown in the structural diagram of the NPN bipolar transistor shown in the figure, after the base and emitter of the bipolar transistor are short-circuited, the PN junction between the base and emitter is essentially short-circuited, so that the PN junction (diode) between the base and collector is used to work. However, due to the difference in the bipolar transistor structure itself, VEB and VEC still have a large deviation, resulting in significant defects in power supply accuracy and reverse current.

[0046] Patent No. US8207779B2 also discloses an ORing circuit, such as Figure 5 As shown (from the patent appendix Figure 4 ). Among them, the added diodes D1 and D2 can effectively solve the problem. Figure 2 The pressure resistance problem can also be solved Figure 1 The aforementioned issue of on-state voltage drop deviation is addressed, but the number of components is inevitably large, resulting in a large board area. Furthermore, the inventors of this application noted that the MOSFET gate-source turn-off voltage is equal to the VF of diode D1 plus the collector-emitter voltage VCE of bipolar transistor Q1. This increase in the MOSFET turn-off voltage is detrimental to the application of low-drive-voltage MOSFETs.

[0047] It should be noted that the above analysis content is only intended to deepen the understanding of the overall background technology of this application, and should not be regarded as an admission or in any form of implication that the content constitutes prior art already known to those skilled in the art. In particular, the discovery of the above-mentioned prior art problems should not be regarded as an admission or in any form of implication that the content constitutes prior art already known to those skilled in the art.

[0048] The disclosure of the above content is only used to assist in understanding the concept and technical solution of this application. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of this patent application, the above content should not be used to evaluate the novelty and creativity of this application.

[0049] Based on the analysis of the above-mentioned prior art, the inventor of this application proposed the inventive concept of this application, which is specifically: a bias circuit is used to control the field effect tube to remain on, and when the current in the field effect tube is reversed, the driving voltage of the gate and source of the field effect tube is pulled down by the conduction of the bipolar transistor to control the field effect tube to be turned off. The driving circuit of the bipolar transistor includes a field effect tube, and a compensation circuit is set in the driving circuit of the bipolar transistor to compensate for the voltage between the source and drain of the field effect tube and the voltage between the base and emitter of the bipolar transistor, thereby reducing the conduction voltage drop of the field effect tube when the current in the field effect tube flows from the source to the drain, and improving the turn-off speed of the field effect tube when the current in the field effect tube flows from the drain to the source.

[0050] First embodiment

[0051] Figure 6 This is a specific circuit schematic diagram of the control circuit of the first embodiment of the present invention. This embodiment provides a control circuit for controlling the on and off of the field effect transistor FET1. The source of the field effect transistor FET1 is used to connect to the output Vout of the power supply, and the drain of the field effect transistor FET1 is used to connect to the bus Vbus. The control circuit includes:

[0052] A first bias circuit R1 is used to control the field effect transistor FET1 to remain on, one end of the first bias circuit R1 is used to input a first bias voltage BIAS, and the other end is used to connect to the gate of the field effect transistor FET1;

[0053] a shutdown circuit for controlling the field-effect transistor FET1 to shut down when the current in the field-effect transistor FET1 flows from the drain to the source, the shutdown circuit comprising a second bias circuit R2, a first bipolar transistor Q1, and a compensation circuit E1, one end of the second bias circuit R2 being used to input a second bias voltage, the other end of the second bias circuit R2, the base of the first bipolar transistor Q1, a first end of the compensation circuit E1, and a second end of the compensation circuit E1 being connected to a first node A, the collector of the first bipolar transistor Q1 being used to connect to the gate of the field-effect transistor FET1, the emitter of the first bipolar transistor Q1 being used to connect to the source of the field-effect transistor FET1, and the third end of the compensation circuit E1 being used to connect to the drain of the field-effect transistor FET1;

[0054] The compensation circuit E1 is used to compensate for the voltage between the source and drain of the field-effect transistor FET1 and the voltage between the base and emitter of the first bipolar transistor Q1, thereby reducing the on-state voltage drop of the field-effect transistor FET1 when the current in the field-effect transistor FET1 flows from the source to the drain, and increasing the turn-off speed of the field-effect transistor FET1 when the current in the field-effect transistor FET1 flows from the drain to the source.

[0055] The control circuit of this embodiment is provided with a compensation circuit E1, which can compensate for the voltage between the source and drain of the field-effect transistor FET1, thereby reducing the on-state voltage drop of the field-effect transistor FET1 when the current in the field-effect transistor FET1 flows from the source to the drain, so that the on-state voltage of the field-effect transistor FET1 is reduced to approximately 30mV, thereby improving power supply efficiency; the compensation circuit E1 provided in the control circuit of this embodiment can also compensate for the voltage between the base and emitter of the first bipolar transistor Q1, thereby increasing the turn-off speed of the field-effect transistor FET1 when the current in the field-effect transistor FET1 flows from the drain to the source, reducing the backflow current of the field-effect transistor FET1, and improving power supply reliability.

[0056] Compensation circuit E1 includes a second bipolar transistor Q2 and a third bipolar transistor Q3. The bases of the second bipolar transistor Q2 and the third bipolar transistor Q3 are connected together to form a first terminal of compensation circuit E1. The collector of the second bipolar transistor Q2 forms a second terminal of compensation circuit E1. The emitter of the second bipolar transistor Q2 is connected to the emitter of the third bipolar transistor Q3, and the collector of the third bipolar transistor Q3 forms a third terminal of compensation circuit E1. Both the first bias voltage and the second bias voltage are BIAS. Typically, the ground level of BIAS is the power supply output Vout. The bipolar transistor of the present invention is a triode.

[0057] Figure 6 The circuit only requires three bipolar transistors and two resistors to realize the control of the ORing circuit, which occupies a small board area, is low in cost and simple to control.

[0058] The working principle of the control circuit of this embodiment to control the conduction of the field effect tube FET1 is combined with Figure 6 The circuit shown is analyzed as follows:

[0059] When the current in the field effect transistor FET1 flows from the source to the drain, by properly setting the bias resistors R1 and R2, the bipolar transistors Q1 and Q2 work in the amplification state, and the bipolar transistor Q3 works in the saturation state. The voltage between the base and emitter of the bipolar transistor Q2 compensates the voltage between the base and emitter of the bipolar transistor Q1, and the voltage between the emitter and collector of the bipolar transistor Q3 compensates the voltage between the source and drain of the field effect transistor FET1. This achieves that when the load current changes, the driving voltage of the field effect transistor FET1 changes accordingly, but the optimal efficiency can be achieved. The detailed working waveform simulation diagram is as follows. Figure 7 shown.

[0060] Where: Vout is the output voltage of the power supply, Io is the current flowing from the source to the drain of the field effect transistor FET1, Vgs is the driving voltage from the gate to the source of the field effect transistor FET1, and Vds is the conduction voltage drop from the drain to the source of the field effect transistor FET1 (also called the drain-source voltage of the field effect transistor FET1).

[0061] The detailed analysis of the working waveform simulation diagram is as follows:

[0062] Because transistors Q1 and Q2 are both operating in the amplification state, the base and emitter are turned on, and the conduction voltage drop remains basically unchanged. Therefore, the voltage VQ1_be between the base and emitter of transistor Q1 is approximately equal to the voltage VQ2_be between the base and emitter of transistor Q2, that is, VQ1_be≈VQ2_be, and remains basically unchanged. Because the base and collector of transistor Q2 are connected, the amplification operating characteristics of transistor Q2 show that VQ2_be≈VQ2_ce, that is, VQ1_be≈VQ2_ce, and remain basically unchanged. Transistor Q3 operates in the saturation state, and the voltage VQ3_ec between the emitter and collector of transistor Q3 is ≈30mV.

[0063] There are two paths for the current flowing through the bias resistor R2 from node A to the output Vout: Path one is from node A → base of transistor Q1 → emitter of transistor Q1 → output Vout, where the current flowing is recorded as I1; Path two is from node A → collector of transistor Q2 → emitter of transistor Q2 → emitter of transistor Q3 → collector of transistor Q3 → drain of field effect transistor FET1 → source of field effect transistor FET1 → output Vout, where the current flowing is recorded as I2;

[0064] Correspondingly, the voltage (VA-Vout) between node A and output Vout can be calculated through the above two current paths: Path one is equal to the voltage VQ1_be between the base and emitter of transistor Q1, that is, (VA-Vout)=VQ1_be; Path two is equal to the sum of the voltage VQ2_ce between the collector and emitter of transistor Q2, the voltage VQ3_ec between the emitter and collector of transistor Q3, and the drain-source voltage Vds of field-effect transistor FET1, that is, (VA-Vout)=(VQ2_ce+VQ3_ec+Vds). Therefore, (VA-Vout)=VQ1_be=(VQ2_ce+VQ3_ec+Vds) and is basically unchanged.

[0065] When the switching power supply is operating normally, the current Io flows from the source to the drain of the field-effect transistor FET1, so the drain-source voltage Vds of the field-effect transistor FET1 is negative. When the current Io gradually increases, the negative voltage on the drain-source voltage Vds of the field-effect transistor FET1 will be forced to gradually increase, which will cause the voltage across the two ends of the above-mentioned path (VQ2_ce+VQ3_ec+Vds) to decrease. In order to maintain the voltage across the two ends of path two unchanged, the current I2 flowing into path two from the bias resistor R2 will be forced to gradually increase, thereby increasing the voltage between point A in path two and the collector of the transistor Q3 (VQ2_ce+VQ3_ec) to offset the increase in the negative voltage of the drain-source voltage Vds of the field-effect transistor FET1.

[0066] The current I2 flowing through bias resistor R2 in path two increases, causing the current I1 flowing through path one to gradually decrease. Since transistor Q1 operates in an amplifying state, the current flowing through bias resistor R1 between the collector and emitter of transistor Q1 is forced to gradually decrease. The on-resistance of the transistor operating in the amplifying state changes in the opposite direction to the current flowing through the collector and emitter. Therefore, the impedance between the collector and emitter of transistor Q1 increases, and the driving voltage Vgs from the gate to the source of field-effect transistor FET1 gradually increases. The increase in driving voltage Vgs can further reduce the negative voltage on the drain-source voltage Vds of field-effect transistor FET1, thereby improving power supply efficiency.

[0067] See also Figure 7 In the simulated waveform, the driving voltage Vgs also increases as the current Io gradually increases, proving that the above theoretical analysis is consistent with the actual working mechanism of the circuit.

[0068] On the contrary, when the current Io gradually decreases, those skilled in the art can understand from the above analysis when the current Io gradually increases that the negative voltage on the drain-source voltage Vds of the field-effect transistor FET1 will gradually decrease, and the current flowing from the bias resistor R2 into path two will gradually decrease, so that the current flowing into path one will gradually increase, and the current flowing from the bias resistor R1 between the collector and emitter of the transistor Q1 will also gradually increase, and the impedance between the collector and emitter of the transistor Q1 will decrease, so the driving voltage Vgs from the gate to the source of the field-effect transistor FET1 will gradually decrease, preparing for the rapid shutdown of the field-effect transistor FET1.

[0069] Furthermore, Figure 6 The second bipolar transistor Q2 and the first bipolar transistor Q1 have the same specifications, so that the first compensation voltage is as consistent as possible with the voltage between the collector and the emitter of the first bipolar transistor Q1.

[0070] Furthermore, Figure 6The third bipolar transistor Q3 is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop between the drain and the source of the field effect transistor FET1, thereby ensuring the output voltage accuracy of the batch power supply.

[0071] Furthermore, the first bipolar transistor Q1 , the second bipolar transistor Q2 , and the third bipolar transistor Q3 are each packaged separately, or two of them are packaged together, or all three are packaged together.

[0072] It should be noted that Figure 6 The circuit also has the following two beneficial effects:

[0073] (1) The problem of voltage stress damage when Vbus>Vout is solved by the high voltage withstand characteristic between the collector and base of transistor Q3.

[0074] (2) Due to the low saturation voltage (about 0.1V) of the transistor Q1, it can be applied to both low-driving-voltage field-effect transistors and high-driving-voltage field-effect transistors, and has a wider range of applications.

[0075] Second embodiment

[0076] This embodiment provides a switching power supply, which includes a field effect transistor, which is arranged in an output circuit inside the switching power supply. The switching power supply also includes any control circuit in the first embodiment.

[0077] Since the switching power supply of this embodiment includes any one of the control circuits in the first embodiment, the on-state voltage drop of the field-effect transistor can be reduced when the current in the field-effect transistor flows from the source to the drain, so that the on-state voltage of the field-effect transistor is reduced to about 30 mV, thereby improving power supply efficiency. In addition, when the current in the field-effect transistor flows from the drain to the source, the turn-off speed of the field-effect transistor can be increased, so that the reverse current of the field-effect transistor is smaller, thereby improving power supply reliability.

[0078] Third embodiment

[0079] This embodiment provides a power supply system, wherein: the power supply system includes N switching power supplies and N field-effect transistors, N is a natural number greater than or equal to 2, the source of each field-effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, and the power supply system also includes N control circuits of any one of the first embodiments, each control circuit is used to control the conduction and shutdown of one of the N field-effect transistors.

[0080] Since the power supply system of this embodiment includes any one of the control circuits in the first embodiment, the on-state voltage drop of the field-effect transistor can be reduced when the current in the field-effect transistor flows from the source to the drain, so that the on-state voltage of the field-effect transistor is reduced to about 30mV, thereby improving the power supply efficiency. In addition, when the current in the field-effect transistor flows from the drain to the source, the turn-off speed of the field-effect transistor can be increased, so that the backflow current of the field-effect transistor is smaller, thereby improving the power supply reliability.

[0081] Figure 8 for Figure 6 The circuit is used in the current-sharing parallel power supply system. Figure 8 , which includes two power supplies. The anti-backflow field-effect transistor of the second power supply (referred to as power supply 2) is FET2. The control circuit of the field-effect transistor FET2 includes resistor R3, resistor R4, transistor Q4, transistor Q5 and transistor Q6. The specific connection method corresponds to the connection method of each component in the control circuit of the anti-backflow field-effect transistor FET1 of the first power supply (referred to as power supply 1). Figure 8 The working principle of turning off the control field effect tube FET1 is analyzed as follows:

[0082] When the output of power supply 1 is short-circuited, the current originally flowing from the source to the drain in the field effect transistor FET1 in power supply 1 drops rapidly to 0A, and the current then flows from the drain to the source and increases rapidly. At this time, by properly setting the bias resistors R1, R2, R3 and R4, the bipolar transistors Q1, Q2, Q4 and Q5 are all working in the amplification state, and the bipolar transistors Q3 and Q6 are working in the saturation state. The voltage between the base and emitter of the transistor Q2 is used to compensate the voltage between the base and emitter of the transistor Q1, and the voltage between the source and drain of the FET1 is compensated by the voltage between the emitter and collector of the transistor Q3, so that the field effect transistor FET1 is quickly turned off when the current flows from the drain to the source, so that the reverse current of the field effect transistor FET1 is small, thereby improving the reliability of the power supply. The detailed working waveform simulation diagram is shown in the figure below. Figure 9 As shown:

[0083] Where: Vout1 is the output voltage of power supply 1, Vout2 is the output voltage of power supply 2, Vbus is the output voltage of the bus, Vgs1 is the driving voltage from the gate to the source of the field effect transistor FET1, Vgs2 is the driving voltage from the gate to the source of the field effect transistor FET2, Io1 is the current flowing from the source to the drain of the field effect transistor FET1, Io2 is the current flowing from the source to the drain of the field effect transistor FET2, and Ibus is the total current on the bus.

[0084] The detailed analysis of the working waveform simulation diagram is as follows:

[0085] When the output of power supply 1 is short-circuited and the current originally flowing from source to drain in field effect transistor FET1 in power supply 1 is rapidly reduced to 0A, the working principle is as described above. Figure 7 The analysis of a single power supply has been described and will not be repeated here. The control circuit of this embodiment can be implemented to prepare for the rapid shutdown of the field effect transistor FET1; when the output of the power supply 1 is short-circuited and the current flows from the drain to the source and increases rapidly, the drain-source voltage Vds of the field effect transistor FET1 becomes positive and increases rapidly. Those skilled in the art can know from the analysis of the first embodiment above that the current flowing from the bias resistor R2 into the second path quickly decreases to 0A, so that the current flowing into the first path quickly increases, and the current flowing from the bias resistor R1 between the collector and emitter of the transistor Q1 also quickly increases, and the impedance between the collector and emitter of the transistor Q1 quickly decreases, so the driving voltage Vgs from the gate to the source of the field effect transistor FET1 quickly decreases until the field effect transistor FET1 is turned off.

[0086] After the field effect transistor FET1 is turned off, Vout1 maintains 0V output, the collector and base of the transistor Q3 are subjected to reverse voltage and are cut off, the transistor Q2 is in a non-working state, and the current of the second bias circuit R2 flows entirely between the base and emitter of the transistor Q1. The transistor Q1 is saturated and turned on, and the voltage between its collector and emitter is about 0.1V, so that the field effect transistor FET1 remains reliably turned off.

[0087] Figure 8 When the output of power supply 1 is short-circuited, the working principle of the ORing circuit in power supply 2 is the same as Figure 6 The same as in , I will not repeat them here.

[0088] The switching power supply described in the present invention is specifically applied to power distribution systems and can be widely used in industrial control, intelligent transportation, smart grid, smart medical care, new energy, Internet of Things, communications and other fields to meet the power distribution requirements necessary for system operation.

[0089] The above are merely preferred embodiments of the present invention. The above preferred embodiments should not be construed as limiting the present invention. A person skilled in the art would be able to make a number of equivalent transformations, improvements, and modifications without departing from the spirit and scope of the present invention. These equivalent transformations, improvements, and modifications should also be considered within the scope of protection of the present invention. Examples will not be used here to further describe the scope of protection of the present invention. The scope of protection of the present invention should be based on the scope defined in the claims.

Claims

1. A control circuit for controlling the on and off of a field effect tube, wherein the source of the field effect tube is The output of the field effect tube is connected to the power supply, and the drain of the field effect tube is used to connect to the bus, characterized in that: The control circuit comprises: The first bias circuit is used to control the field effect tube to remain conductive, and one end of the first bias circuit is used For inputting a first bias voltage, the other end is used to connect to the gate of the field effect transistor; a shutdown circuit, configured to control the field-effect transistor to shut down when current in the field-effect transistor flows from the drain to the source, the shutdown circuit comprising a second bias circuit, a first bipolar transistor, and a compensation circuit, wherein one end of the second bias circuit is configured to input a second bias voltage, the other end of the second bias circuit, the base of the first bipolar transistor, the first end of the compensation circuit, and the second end of the compensation circuit are connected to a first node, the collector of the first bipolar transistor is configured to connect to the gate of the field-effect transistor, the emitter of the first bipolar transistor is configured to connect to the source of the field-effect transistor, and the third end of the compensation circuit is configured to connect to the drain of the field-effect transistor; The compensation circuit is used to compensate for the voltage between the source and drain of the field effect transistor and the voltage between the base and emitter of the first bipolar transistor, thereby reducing the on-state voltage drop of the field effect transistor when the current in the field effect transistor flows from the source to the drain, and increasing the turn-off speed of the field effect transistor when the current in the field effect transistor flows from the drain to the source; The compensation circuit includes a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together to form a first end of the compensation circuit, the collector of the second bipolar transistor is the second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is the third end of the compensation circuit; The voltage between the collector and the emitter of the second bipolar transistor is a first compensation voltage, compensating for the voltage between the base and the emitter of the first bipolar transistor; The voltage between the emitter and the collector of the third bipolar transistor is a second compensation voltage, which compensates the voltage between the source and the drain of the field effect transistor.

2. The control circuit according to claim 1, wherein: The second bipolar transistor and the first bipolar transistor have the same specifications.

3. The control circuit according to claim 1, wherein: The third bipolar transistor is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop of the field effect transistor.

4. The control circuit according to claim 1, wherein: The first bipolar transistor, the second bipolar transistor and the third bipolar transistor are each packaged separately, or two of them are packaged together, or all three of them are packaged together.

5. The control circuit according to claim 1, wherein: The first bias circuit is a resistor R1 and / or the second bias circuit is a resistor R2.

6. The control circuit according to claim 1, wherein: The first bias voltage and the The second bias voltage is the same.

7. A switching power supply, characterized in that: It includes a field effect tube, which is arranged on the switch In the output circuit inside the switching power supply, the switching power supply further includes the control circuit according to any one of claims 1 to 6.

8. A power supply system, characterized in that: The power supply system includes N switching power supplies and N Field effect transistor, N is a natural number greater than or equal to 2, the source of each field effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, the power supply system further includes N control circuits according to any one of claims 1 to 6, each of the control circuits is used to control the conduction and shutdown of one of the N field effect transistors.

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