Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises a slew rate control circuit. The slew rate control circuit includes a first transistor, a second transistor, an input terminal, and an output terminal. The slew rate control circuit is configured to receive a scan signal switched between a first high voltage level and a first low voltage level, and output an adjusted scan signal switched between a second high voltage level and a second low voltage level. The first transistor and the second transistor are transistors of the same type and respectively form a diode or a source follower amplifier. The electronic device can effectively drive the adjustable element through the pixel circuit.

Description

Technical Field

[0001] The present invention relates to a device, and in particular to an electronic device. Background Art

[0002] An active matrix device (e.g., a varactor antenna) consists of multiple tunable components (e.g., varactors) and multiple pixel circuits, each of which has a scan transistor and a storage capacitor. Generally speaking, using a large storage capacitor and a large transistor in the pixel circuit is essential to reduce the control voltage drop caused by the varactor leakage and achieve fast scanning operation. However, the fast rise and fall of the scan signal is conducive to fast scanning operation, but it will cause drain avalanche hot-carrier (DAHC) stress and severe kickback effect of the scan transistor. In addition, the input impedance of the large scan transistor is small (i.e., the gate terminal capacitance becomes larger), which will cause the scan signal to be distorted, and slowing down the rise and fall speed of the far end of the scan driver will make the uniformity worse (i.e., the signal difference between the near end and the far end). Summary of the invention

[0003] The electronic device disclosed herein includes a conversion rate control circuit. The conversion rate control circuit includes a first transistor, a second transistor, an input terminal and an output terminal. The conversion rate control circuit is used to receive a scan signal switched between a first high voltage level and a first low voltage level, and output an adjusted scan signal switched between a second high voltage level and a second low voltage level. The first transistor and the second transistor are transistors of the same type and form a diode or a source follower amplifier respectively.

[0004] The electronic device disclosed herein includes a conversion rate control circuit. The conversion rate control circuit includes a first transistor, a second transistor, an input terminal and an output terminal. The conversion rate control circuit is used to receive a scan signal switched between a first high voltage level and a first low voltage level, and output an adjusted scan signal switched between a second high voltage level and a second low voltage level. The first transistor is an n-type transistor, and the second transistor is a p-type transistor. The first transistor and the second transistor respectively form a diode or a source-follower amplifier.

[0005] Based on the above, according to the electronic device disclosed herein, the electronic device can adjust the scan signal through the conversion rate control circuit to effectively drive the adjustable element through the pixel circuit.

[0006] In order to make the above content clearer and easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2 A schematic diagram of a conversion rate control circuit and a pixel according to an embodiment of the present disclosure;

[0009] Figure 3 A schematic diagram of the waveforms of a scanning signal and an adjusted scanning signal according to an embodiment of the present disclosure;

[0010] Figure 4A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0011] Figure 4B For the purpose of disclosure Figure 4A A schematic equivalent circuit diagram of an embodiment of the invention;

[0012] Figure 5A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0013] Figure 5B For the purpose of disclosure Figure 5A A schematic equivalent circuit diagram of an embodiment of the invention;

[0014] Fig. 6A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0015] Figure 6B For the purpose of disclosure Fig. 6A A schematic equivalent circuit diagram of an embodiment of the invention;

[0016] Fig. 7A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0017] Figure 7B For the purpose of disclosure Fig. 7A A schematic equivalent circuit diagram of an embodiment of the invention;

[0018] Fig. 8A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0019] Figure 8B For the purpose of disclosure Fig. 8A A schematic equivalent circuit diagram of an embodiment of the invention;

[0020] Fig. 9A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0021] Fig. 9B For the purpose of disclosure Fig. 9A A schematic equivalent circuit diagram of an embodiment of the invention;

[0022] Fig. 10A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0023] Fig. 10B For the purpose of disclosure Fig. 10A A schematic equivalent circuit diagram of an embodiment of the invention;

[0024] Fig.11A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0025] Fig. 11B For the purpose of disclosure Fig.11A A schematic equivalent circuit diagram of an embodiment of the invention;

[0026] Fig. 12A A schematic diagram of a conversion rate control circuit according to an embodiment of the present disclosure;

[0027] Fig. 12B For the purpose of disclosure Fig. 12A A schematic equivalent circuit diagram of an embodiment of the invention;

[0028] Fig.13 A schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure;

[0029] Fig.14 A schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure;

[0030] Fig.15 FIG. 1 is a schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure.

[0031] Description of Reference Numerals

[0032] 100: electronic device;

[0033] 110: active matrix element;

[0034] 111, 211: pixel circuit;

[0035] 112, 212: adjustable element;

[0036] 220, 420, 520, 620, 720, 820, 920, 1020, 1120, 1220, 1520, 1320_1~1320_m, 1420_1~1420_k: conversion rate control circuit;

[0037] 1301, 1401, 1501: scanning driver;

[0038] D1, D2: diodes;

[0039] DL: data signal line;

[0040] DS: data signal;

[0041] P(1,1)~P(m,n):pixel;

[0042] SL, SL_n: scanning signal lines;

[0043] SP: scanning period;

[0044] SS, SS_n: scanning signal;

[0045] SS_n', SS': adjusted scanning signals;

[0046] T1: first transistor;

[0047] T2: second transistor;

[0048] V1, V2, V3: DC voltage;

[0049] VGH1: first high voltage level;

[0050] VGH2: second high voltage level;

[0051] VGL1: first low voltage level;

[0052] VGL2: second low voltage level;

[0053] Vls1, Vls2: voltage loss;

[0054] t1, t2: time. DETAILED DESCRIPTION

[0055] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0056] Certain terms are used in the specification and claims of this disclosure to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same parts by different names. It is not intended to distinguish between components that have the same function but different names. In the following description and claims, words such as "include" and "comprising" are open-ended terms and should be interpreted as "including but not limited to..."

[0057] The term "coupled (or connected)" used in the specification (including claims) of this disclosure may refer to any direct or indirect connection mode. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly coupled to the second device, or the first device can be indirectly coupled through other devices or coupled to the second device through some connecting device. The terms "first", "second" and similar terms mentioned in the entire specification (including claims) of this application are only used to name discrete elements or to distinguish different embodiments or scopes. Therefore, these terms should not be regarded as limiting the upper or lower limits of the number of elements, and should not be used to limit the order of arrangement of elements. In addition, whenever possible, the elements / components / steps with the same figure numbers in the drawings and embodiments represent the same or similar parts. The same figure numbers can be used or the same terms can be used to refer to the relevant descriptions of elements / components / steps in different embodiments.

[0058] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1 , the electronic device 100 includes an active matrix device 110, and the active matrix device 110 includes a plurality of pixels P(1,1)-P(m,n), where m and n are positive integers. The pixels P(1,1)-P(m,n) can be arranged as follows Figure 1 Array shown. In one embodiment of the present disclosure, each pixel P(1,1)~P(m,n) includes a pixel circuit 111 and an adjustable element 112, and the pixel circuit 111 is coupled to the adjustable element 112. In one embodiment of the present disclosure, the adjustable element 112 may be a voltage-controlled element (such as a variable capacitor, a varactor diode, or a micro-electromechanical system (MEMS)), but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the electronic device 100 may be a display device or an antenna device, but the present disclosure is not limited thereto.

[0059] Figure 2 FIG. 1 is a schematic diagram of a conversion rate control circuit and a pixel according to an embodiment of the present disclosure. Figure 2, the electronic device 100 also includes a conversion rate control circuit 220. The conversion rate control circuit 220 includes an input terminal Pin and an output terminal Pout. The input terminal Pin of the conversion rate control circuit 220 is coupled to the scan signal line SL to receive the scan signal SS switched between the first high voltage level and the first low voltage level, and the output terminal Pout of the conversion rate control circuit 220 is coupled to the pixel including the pixel circuit 211 and the adjustable element 212 to output the adjusted scan signal SS' switched between the second high voltage level and the second low voltage level. The output terminal Pout of the conversion rate control circuit 220 is coupled to the pixel circuit 211, and the pixel circuit 211 is also coupled to the adjustable element 212.

[0060] In one embodiment of the present disclosure, the pixel circuit 211 includes a scanning transistor Ts and a storage capacitor Cst. The control end of the scanning transistor Ts is coupled to the output end Pout of the conversion rate control circuit 220. The first end of the scanning transistor Ts is coupled to the data signal line DL to receive the data signal DS. The second end of the scanning transistor Ts is coupled to the adjustable element 212 and the storage capacitor Cst. In one embodiment of the present disclosure, the gate voltage Vg of the control end of the scanning transistor Ts is determined by the adjusted scanning signal SS'. In one embodiment of the present disclosure, the scanning transistor Ts can be an n-type transistor, but the present disclosure is not limited to this. When the adjusted scanning signal SS' provides a low voltage level, the scanning transistor Ts is turned off. When the adjusted scanning signal SS' provides a high voltage level, the scanning transistor Ts is turned on. The scanning transistor Ts provides a data signal DS to the storage capacitor Cst to provide a data voltage Vdata to the adjustable element 212 according to the data signal DS.

[0061] Figure 3 FIG. 1 is a waveform diagram of a scanning signal and an adjusted scanning signal according to an embodiment of the present disclosure. Figure 2 and Figure 3 , the scanning waveform of the scanning signal SS can be as follows Figure 3 As shown. During the scanning period SP, the scanning signal SS may change from the first low voltage level VGL1 to the first high voltage level VGH1. Specifically, after time t1, the voltage level of the scanning signal SS may rise from the first low voltage level VGL1 to the first high voltage level VGH1. After time t2, the voltage level of the scanning signal SS may drop from the first high voltage level VGH1 to the first low voltage level VGL1.

[0062] In one embodiment of the present disclosure, the slew rate control circuit 220 can adjust at least one of the rising slew rate and the falling slew rate of the scan signal SS, and output the following: Figure 3The adjusted scan signal SS' shown. That is, at least one of the rise time and the fall time of the adjusted scan signal SS' is longer than the rise time and the fall time of the scan signal SS, respectively. During the scan period SP, the adjusted scan signal SS' can be changed from the second low voltage level VGL2 to the second high voltage level VGH2. Specifically, after time t1, the voltage level of the adjusted scan signal SS' can rise from the second low voltage level VGL2 to the second high voltage level VGH2. After time t2, the voltage level of the adjusted scan signal SS' can fall from the second high voltage level VGH2 to the second low voltage level VGL2. In one embodiment of the present disclosure, the rise time and the fall time of the adjusted scan signal SS' can be longer than the rise time and the fall time of the scan signal SS, respectively. Therefore, the drain avalanche hot carrier (DAHC) stress of the scan transistor Ts can be effectively reduced. In one embodiment of the present disclosure, the falling conversion rate of the adjusted scan signal SS' can be lower than the rising conversion rate of the adjusted scan signal SS'. Therefore, fast charging can be achieved, and the kickback effect of the scan transistor Ts can be effectively reduced.

[0063] Figure 4A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Figure 4B For the purpose of disclosure Figure 4A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Figure 4A The conversion rate control circuit 420. Figure 4A The conversion rate control circuit 420 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the input terminal Pin. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the output terminal Pout. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout.

[0064] refer to Figure 4A and Figure 4B , the first transistor T1 can be equivalent to the diode D1, and the second transistor T2 can be equivalent to the diode D2. The anode of the diode D1 is coupled to the input terminal Pin and the cathode of the diode D2. The cathode of the diode D1 is coupled to the output terminal Pout and the anode of the diode D2. The first transistor T1 and the second transistor T2 can be n-type transistors (i.e. transistors of the same type). Figure 3 and Figure 4BDuring the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D1 to the cathode of the diode D1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D2 to the cathode of the diode D2. Therefore, the output terminal Pout of the conversion rate control circuit 420 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0065] In addition, refer to Figure 3 and Figure 4A , the voltage loss Vls1 between the first high voltage level VGH1 of the scan signal SS and the second high voltage level VGH2 of the adjusted scan signal SS' is caused by the threshold voltage of the first scan signal SS. In one embodiment of the present disclosure, the rising transition rate of the adjusted scan signal SS' is determined by the aspect ratio of the first transistor T1 (i.e., the aspect ratio (W / L)), and the falling transition rate of the adjusted scan signal SS' is determined by the aspect ratio of the first transistor T1 (i.e., the aspect ratio (W / L)).

[0066] Figure 5A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Figure 5B For the purpose of disclosure Figure 5A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Figure 5A The conversion rate control circuit 520. Figure 5A , the conversion rate control circuit 520 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the DC voltage V1. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the output terminal Pout. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 and the second transistor T2 can be n-type transistors.

[0067] See also Figure 5A and Figure 5B , the first transistor T1 can be equivalent to a source follower amplifier, and the second transistor T2 can be equivalent to a diode D2. The cathode of the diode D2 is coupled to the input terminal Pin and the control terminal of the first transistor T1. The anode of the diode D2 is coupled to the output terminal Pout and the second terminal of the second transistor T2. Figure 3and Figure 5B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the first terminal of the first transistor T1 to the second terminal of the first transistor T1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D2 to the cathode of the diode D2. Therefore, the output terminal Pout of the conversion rate control circuit 520 can output the following Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0068] Also, please refer to Figure 3 and Figure 5A In one embodiment of the present disclosure, the voltage level of the DC voltage V1 may be higher than the first low voltage level VGL1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V1 may be equal to the first high voltage level VGH1.

[0069] Fig. 6A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Figure 6B For the purpose of disclosure Fig. 6A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 6A The conversion rate control circuit 620. Fig. 6A , the conversion rate control circuit 620 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the input terminal Pin. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the output terminal Pout. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 and the second transistor T2 may be p-type transistors.

[0070] refer to Fig. 6A and Figure 6B , the first transistor T1 can be equivalent to a diode D1, and the second transistor T2 can be equivalent to a diode D2. The cathode of the diode D1 is coupled to the input terminal Pin and the anode of the diode D2. The anode of the diode D1 is coupled to the output terminal Pout and the cathode of the diode D2. The anode of the diode D2 is coupled to the input terminal Pin. The cathode of the diode D2 is coupled to the output terminal Pout. Figure 3 and Figure 6BDuring the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D2 to the cathode of the diode D2. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D1 to the cathode of the diode D1. Therefore, the output terminal Pout of the conversion rate control circuit 620 can output the following Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0071] Fig. 7A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Figure 7B For the purpose of disclosure Fig. 7A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 7A The conversion rate control circuit 720. Fig. 7A , the conversion rate control circuit 720 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the DC voltage V1. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the output terminal Pout. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 and the second transistor T2 can be p-type transistors.

[0072] See also Fig. 7A and Figure 7B , the first transistor T1 can be equivalent to a source follower amplifier, and the second transistor T2 can be equivalent to a diode D2. The anode of the diode D2 is coupled to the input terminal Pin and the control terminal of the first transistor T1. The cathode of the diode D2 is coupled to the output terminal Pout and the second terminal of the first transistor T1. Figure 3 and Figure 7B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D2 to the cathode of the diode D2. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the second end of the first transistor T1 to the first end of the first transistor T1. Therefore, the output terminal Pout of the conversion rate control circuit 720 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0073] Also, please refer to Figure 3 and Fig. 7A In one embodiment of the present disclosure, the voltage level of the DC voltage V1 may be lower than the first high voltage level VGH1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V1 may be equal to the first low voltage level VGL1.

[0074] Fig. 8A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Figure 8B For the purpose of disclosure Fig. 8A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 8A The conversion rate control circuit 820. Fig. 8A , the conversion rate control circuit 820 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the input terminal Pin. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the input terminal Pin. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 can be an n-type transistor, and the second transistor T2 can be a p-type transistor.

[0075] refer to Fig. 8A and Figure 8B , the first transistor T1 can be equivalent to a diode D1, and the second transistor T2 can be equivalent to a diode D2. The anode of the diode D1 is coupled to the input terminal Pin and the cathode of the diode D2. The cathode of the diode D1 is coupled to the output terminal Pout and the anode of the diode D2. The cathode of the diode D2 is coupled to the input terminal Pin. The anode of the diode D2 is coupled to the output terminal Pout. Figure 3 and Figure 8B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D1 to the cathode of the diode D1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D2 to the cathode of the diode D2. Therefore, the output terminal Pout of the conversion rate control circuit 820 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0076] Fig. 9A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Fig. 9B For the purpose of disclosure Fig. 9A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 9A The conversion rate control circuit 920. Fig. 9A , the conversion rate control circuit 920 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the output terminal Pout. The first terminal of the first transistor T1 is coupled to the input terminal Pin. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the output terminal Pout. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 can be an n-type transistor, and the second transistor T2 can be a p-type transistor.

[0077] refer to Fig. 9A and Fig. 9B , the first transistor T1 can be equivalent to a diode D1, and the second transistor T2 can be equivalent to a diode D2. The cathode of the diode D1 is coupled to the input terminal Pin and the anode of the diode D2. The anode of the diode D1 is coupled to the output terminal Pout and the cathode of the diode D2. The anode of the diode D2 is coupled to the input terminal Pin. The cathode of the diode D2 is coupled to the output terminal Pout. Figure 3 and Fig. 9B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D2 to the cathode of the diode D2. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D1 to the cathode of the diode D1. Therefore, the output terminal Pout of the conversion rate control circuit 920 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0078] Fig. 10A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Fig. 10B For the purpose of disclosure Fig. 10A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 10A The conversion rate control circuit 1020. Fig. 10A, the conversion rate control circuit 1020 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the DC voltage V2. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the input terminal Pin. The first terminal of the second transistor T2 is coupled to the input terminal Pin. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 can be an n-type transistor, and the second transistor T2 can be a p-type transistor.

[0079] See also Fig. 10A and Fig. 10B , the first transistor T1 can be equivalent to a source follower amplifier, and the second transistor T2 can be equivalent to a diode D2. The cathode of the diode D2 is coupled to the input terminal Pin and the control terminal of the first transistor T1. The anode of the diode D2 is coupled to the output terminal Pout and the second terminal of the first transistor T1. Figure 3 and Fig. 10B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the first end of the first transistor T1 to the second end of the first transistor T1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the anode of the diode D2 to the cathode of the diode D2. Therefore, the output terminal Pout of the conversion rate control circuit 1020 can output the following Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0080] Also, please refer to Figure 3 and Fig. 10A In one embodiment of the present disclosure, the voltage level of the DC voltage V2 may be higher than the first low voltage level VGL1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V2 may be equal to the first high voltage level VGH1.

[0081] Fig.11A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Fig. 11B For the purpose of disclosure Fig.11A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig.11A The conversion rate control circuit 1120. Fig.11A, the conversion rate control circuit 1120 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to the input terminal Pin. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the input terminal Pin. The first terminal of the second transistor T2 is coupled to the DC voltage V3. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 can be an n-type transistor, and the second transistor T2 can be a p-type transistor.

[0082] See also Fig.11A and Fig. 11B , the first transistor T1 can be equivalent to the diode D1, and the second transistor T2 can be equivalent to the source follower amplifier. The anode of the diode D1 is coupled to the input terminal Pin and the control terminal of the second transistor T2. The cathode of the diode D1 is coupled to the output terminal Pout and the second terminal of the second transistor T2. Figure 3 and Fig. 11B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the anode of the diode D1 to the cathode of the diode D1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the second end of the second transistor T2 to the first end of the second transistor T2. Therefore, the output terminal Pout of the conversion rate control circuit 1120 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0083] Also, please refer to Figure 3 and Fig.11A In one embodiment of the present disclosure, the voltage level of the DC voltage V3 may be lower than the first high voltage level VGH1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V3 may be equal to the first low voltage level VGL1.

[0084] Fig. 12A FIG. 4 is a schematic diagram of a slew rate control circuit according to an embodiment of the present disclosure. Fig. 12B For the purpose of disclosure Fig. 12A A schematic equivalent circuit diagram of an embodiment of the present disclosure. In one embodiment of the present disclosure, Figure 2 The conversion rate control circuit 220 can be implemented as Fig. 12A The conversion rate control circuit 1220. Fig. 12A, the conversion rate control circuit 1220 includes a first transistor T1, a second transistor T2, an input terminal Pin and an output terminal Pout. The control terminal of the first transistor T1 is coupled to the input terminal Pin. The first terminal of the first transistor T1 is coupled to a DC voltage V2. The second terminal of the first transistor T1 is coupled to the output terminal Pout. The control terminal of the second transistor T2 is coupled to the input terminal Pin. The first terminal of the second transistor T2 is coupled to a DC voltage V3. The second terminal of the second transistor T2 is coupled to the output terminal Pout. The first transistor T1 can be an n-type transistor, and the second transistor T2 can be a p-type transistor.

[0085] See also Fig. 12A and Fig. 12B , the first transistor T1 can be equivalent to a source follower amplifier, and the second transistor T2 can be equivalent to another source follower amplifier. Figure 3 and Fig. 12B During the rising period of the voltage level of the scanning signal SS, the charging current Ic flows from the first end of the first transistor T1 to the second end of the first transistor T1. During the falling period of the voltage level of the scanning signal SS, the discharging current Id flows from the second end of the second transistor T2 to the first end of the second transistor T2. Therefore, the output terminal Pout of the conversion rate control circuit 1220 can output the following: Figure 3 The adjusted scan signal SS′ is shown, and the adjusted scan signal SS′ can enable the scan transistor to achieve a fast charging effect with low DAHC stress and low kickback effect.

[0086] Also, please refer to Figure 3 and Fig. 12A In one embodiment of the present disclosure, the voltage level of the DC voltage V2 may be higher than the first low voltage level VGL1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V2 may be equal to the first high voltage level VGH1. In one embodiment of the present disclosure, the voltage level of the DC voltage V3 may be lower than the first high voltage level VGH1, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the DC voltage V3 may be equal to the first low voltage level VGL1.

[0087] Fig.13 FIG. 1 is a schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure. Figure 1 In one embodiment of the present disclosure, each pixel P(1,1)-P(m,n) includes a pixel circuit 111 and an adjustable element 112, and each pixel P(1,1)-P(m,n) includes a pixel circuit 111 and an adjustable element 112. Fig.13Taking a row of pixels P(1,1) to P(m,n) in the active matrix device 110 as an example, the electronic device 100 may further include a scan driver 1301, and the pixels P(1,n) to P(m,n) may further include a plurality of conversion rate control circuits 1320_1 to 1320_m. The scan driver 1301 is connected to the input terminals of the conversion rate control circuits 1320_1 to 1320_m of the pixels P(1,n) to P(m,n) through scan lines SL_n. The scan driver 1301 may output a scan signal SS_n to the pixels P(1,n) to P(m,n), and the conversion rate control circuits 1320_1 to 1320_m may respectively adjust the scan signal SS_n to provide the corresponding adjusted scan signal to the pixels P(1,n) to P(m,n). Therefore, by having an input impedance of the slew rate control circuit greater than the scan transistor of the pixel P, signal distortion of the scan signal SS_n for driving the pixels P(1,n) to P(m,n) can be effectively mitigated.

[0088] Fig.14 FIG. 1 is a schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure. Figure 1 In one embodiment of the present disclosure, each pixel P(1,1)-P(m,n) includes a pixel circuit 111 and an adjustable element 112, and each pixel P(,1)-P(m,n) may also include a conversion rate control circuit. Fig.14 Taking a row of pixels P(1,1)-P(m,n) in the active matrix device 110 as an example, the electronic device 100 may further include a scan driver 1401, and the pixels P(1,n)-P(k,n) may further include a plurality of conversion rate control circuits 1420_1-1420_k, where k is between 1 and m. The scan driver 1401 is coupled to the input terminals of the conversion rate control circuits 1420_1-1420_k of the pixels P(1,n)-P(k,n) via the scan lines SL_n, and is directly coupled to the pixels P(1,n)-P(k,n), where k is a positive integer. The pixels P(1,n)-P(k,n) are close to the scan driver 1401 (near side). The scan driver 1401 can output a scan signal SS_n to the pixels P(1,n)~P(m,n), and the conversion rate control circuits 1420_1~1420_k can adjust the scan signal SS_n respectively to provide the corresponding adjusted scan signal to the pixels P(1,n)~P(m,n). Therefore, the signal distortion of the scan signal SS_n used to drive the pixels P(1,n)~P(m,n) can be effectively reduced by the input impedance of the conversion rate control circuit being larger than the scan transistor of the pixel.

[0089] Fig.15 FIG. 1 is a schematic diagram of a row of pixels in an active matrix device according to an embodiment of the present disclosure. Figure 1 In one embodiment of the present disclosure, each pixel P(1,1)-P(m,n) includes a pixel circuit 111 and an adjustable element 112, and each row of pixels P(1,1)-P(m,n) may correspond to a conversion rate control circuit. Fig.15 Taking a row of pixels P(1,1) to P(m,n) in the active matrix device 110 as an example, the electronic device 100 may further include a scan driver 1501 and a conversion rate control circuit 1520, and the scan driver 1501 is coupled to the input end of the conversion rate control circuit 1520. The conversion rate control circuit 1520 is also coupled to the pixels P(1,n) to P(m,n) through the scan line SL_n. The scan driver 1501 may output a scan signal to the conversion rate control circuit 1520. The conversion rate control circuit 1520 may adjust the scan signal to provide the corresponding adjusted scan signal SS_n' to the pixels P(1,n) to P(m,n), while optimizing the rise and fall times of the adjusted scan signal SS_n' to reduce the signal distortion of the adjusted scan signal SS_n. Therefore, the signal distortion of the adjusted scan signal SS_n' used to drive the pixels P(1,n) to P(m,n) may have lower signal distortion.

[0090] In summary, according to the electronic device disclosed herein, the conversion rate control circuit includes two transistors, and each transistor forms a diode or a source follower amplifier. The conversion rate control circuit disclosed herein is set between the scan driver and the scan transistor in the pixel of the active matrix device, and achieves independent conversion rate control (i.e., optimizing the rise and fall time of the scan signal) by adjusting the length and width of the transistor. The conversion rate control circuit disclosed herein can reduce the pulse feedthrough (i.e., kickback) and DAHC stress on the scan transistor. In addition, the conversion rate control circuit disclosed herein suppresses the distortion of the scan signal by a larger input impedance than the scan transistor. Therefore, the conversion rate control circuit disclosed herein improves the reliability and uniformity of the active matrix device.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, characterized in that: include: A slew rate control circuit includes a first transistor, a second transistor, an input terminal, and an output terminal, for receiving a scan signal switched between a first high voltage level and a first low voltage level, and outputting an adjusted scan signal switched between a second high voltage level and a second low voltage level, The first transistor and the second transistor are transistors of the same type and respectively form a diode or a source follower amplifier.

2. The electronic device according to claim 1, characterized in that: The control terminal of the first transistor is coupled to the input terminal, and one terminal of the first transistor is coupled to the output terminal. The control terminal and the terminal of the second transistor are coupled to the output terminal.

3. The electronic device according to claim 2, characterized in that: The other end of the first transistor is coupled to the input end.

4. The electronic device according to claim 2, characterized in that: The other end of the first transistor is coupled to a direct current voltage.

5. The electronic device according to claim 4, characterized in that: The voltage level of the DC voltage is higher than the first low voltage level.

6. The electronic device according to claim 4, characterized in that: The voltage level of the DC voltage is lower than the first high voltage level.

7. The electronic device according to claim 2, characterized in that: The other end of the second transistor is coupled to the input end.

8. The electronic device according to claim 1, characterized in that: At least one of the rising time and the falling time of the adjusted scanning signal is longer than the rising time and the falling time of the scanning signal.

9. The electronic device according to claim 1, characterized in that: The input end is coupled to a scan driver, and the output end is coupled to at least one pixel of an active matrix device.

10. The electronic device according to claim 1, characterized in that: The first transistor and the second transistor are n-type transistors or p-type transistors.

11. An electronic device, characterized in that: include: A slew rate control circuit includes a first transistor, a second transistor, an input terminal, and an output terminal, for receiving a scan signal switched between a first high voltage level and a first low voltage level, and outputting an adjusted scan signal switched between a second high voltage level and a second low voltage level, The first transistor is an n-type transistor, and the second transistor is a p-type transistor. The first transistors and the second transistors respectively form diodes or source-follower amplifiers.

12. The electronic device according to claim 11, characterized in that: A control terminal of the first transistor is coupled to a control terminal of the second transistor, and the first transistor and the second transistor are coupled to the output terminal.

13. The electronic device according to claim 12, characterized in that: The control terminals of the first transistor and the second transistor are coupled to the input terminal.

14. The electronic device according to claim 12, characterized in that: The control terminals of the first transistor and the second transistor are coupled to the output terminal.

15. The electronic device according to claim 12, characterized in that: The other end of the first transistor is coupled to the input end.

16. The electronic device according to claim 12, characterized in that: The other end of the first transistor is coupled to a direct current voltage.

17. The electronic device according to claim 12, characterized in that: The other end of the second transistor is coupled to the input end.

18. The electronic device according to claim 12, characterized in that: The other end of the second transistor is coupled to a direct current voltage.

19. The electronic device according to claim 11, characterized in that: At least one of the rising time and the falling time of the adjusted scanning signal is longer than the rising time and the falling time of the scanning signal.

20. The electronic device according to claim 11, characterized in that: The input end is coupled to a scan driver, and the output end is coupled to at least one pixel of an active matrix device.

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