IQ channel calibration method of radio frequency receiver, radio frequency receiver and electronic equipment

Abstract

The embodiment of the invention discloses an IQ channel calibration method of a radio frequency receiver, the radio frequency receiver and electronic equipment, and relates to the field of communication. Excitation signals are generated through the signal generator, and I-path and Q-path digital signals are generated through processing of modules such as the signal selector, the low-noise amplifier, the multiplier, the filter amplifier and the ADC. A notch module is introduced to remove interference of excitation signal frequency, and an interference detection module is used for judging whether obvious external interference exists or not. The IQ amplitude and phase mismatch calibration module determines whether to execute a calibration action according to the interference detection result. If the interference is smaller than the threshold value, amplitude and phase calibration is carried out on the I-path and Q-path alternating current signals; and if the interference is greater than or equal to the threshold value, stopping calibration. According to the scheme, through dynamic configuration and real-time monitoring, the calibration process is ensured to be carried out under the condition of no obvious interference, and the calibration accuracy and the system performance are improved.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to an IQ channel calibration method of a radio frequency receiver, an electronic device, and a computer storage medium. Background Art

[0002] In wireless communication systems, IQ RF receivers play a vital role, and their performance directly affects communication quality and system stability. In order to ensure the normal operation of IQ RF receivers, it is necessary to calibrate their IQ channels. Traditional calibration methods usually use excitation signals as calibration sources, input known signals into the IQ channels, and measure the characteristics of the output signals to achieve IQ channel calibration.

[0003] However, the existing IQ calibration method based on the excitation signal has significant disadvantages. Since the RF receiver is usually in an open environment, when the excitation signal is input into the RF receiver, it is easy to couple with the wireless signals in the surrounding environment. In particular, when these wireless signals are in the same or similar frequency band as the excitation signal used for calibration, such as common WIFI signals, they will overlap with the excitation signal and cause interference.

[0004] The presence of such interference signals will seriously affect the accuracy of IQ calibration. On the one hand, the interference signal will change the actual input signal of the IQ channel, causing the signal characteristics measured during the calibration process to deviate from the actual situation. On the other hand, the interference signal may also introduce additional amplitude and phase distortion, further exacerbating the calibration error. Therefore, performing IQ calibration in the presence of interference signals is likely to result in abnormal calibration results that cannot accurately reflect the actual performance of the IQ channel. Summary of the invention

[0005] The embodiments of the present application provide an IQ channel calibration method, an electronic device, and a computer storage medium for a radio frequency receiver, which can solve the problem of large interference in IQ channel calibration in the prior art. The technical solution is as follows:

[0006] In a first aspect, the present application provides an IQ channel calibration method for a radio frequency receiver, comprising:

[0007] The processor obtains the current gear gain, configures the frequency f and power for the signal generating module according to the current gear gain, and instructs the signal selector to open the test channel and close the antenna channel;

[0008] The signal generator outputs an excitation signal to the signal selector according to the frequency f and the power;

[0009] The signal selector sends the excitation signal to the low noise amplifier through the test channel;

[0010] The low noise amplifier performs amplification and power division processing on the excitation signal, and generates two identical I-channel test signals and Q-channel test signals, and sends the I-channel test signal to the I-channel multiplier, and sends the Q-channel test signal to the Q-channel multiplier;

[0011] The processor instructs the local oscillator to generate Q local oscillator signals according to the frequency f of the excitation signal; the frequency of the Q local oscillator signals is f+△f, where f is the frequency of the excitation signal and △f is a preset frequency offset;

[0012] The phase shifter performs a 90-degree phase shift on the Q-channel local oscillator signal and then outputs an I-channel local oscillator signal;

[0013] The I-channel multiplier multiplies the I-channel test signal and the I-channel local oscillator signal and then outputs an I-channel analog signal;

[0014] The Q-channel multiplier multiplies the Q-channel test signal and the Q-channel local oscillator signal and then outputs a Q-channel analog signal;

[0015] The I-channel filter amplifier performs filtering and amplifying processing on the I-channel analog signal, and the Q-channel filter amplifier performs filtering and amplifying processing on the Q-channel analog signal;

[0016] The I-channel ADC performs analog-to-digital conversion on the signal output by the I-channel filter amplifier and then outputs an I-channel digital signal; the Q-channel ADC performs analog-to-digital conversion on the signal output by the Q-channel filter amplifier and then outputs a Q-channel digital signal;

[0017] The DC component elimination module performs DC elimination processing on the I-channel digital signal and the Q-channel digital signal to obtain an I-channel AC signal and a Q-channel AC signal;

[0018] The processor configures the notch frequency of the notch module to be a preset frequency offset Δf, and configures a power threshold for the interference detection module;

[0019] The notch module performs notch processing on the I-channel AC signal and the Q-channel AC signal according to a preset frequency offset Δf, and then outputs an I-channel band-stop signal and a Q-channel band-stop signal;

[0020] The interference detection module calculates the power sum of the I-path band-stop signal and the Q-path band-stop signal, and if the power sum is less than the power threshold, sends a calibration permission indication signal to the IQ amplitude and phase mismatch calibration module; if the power sum is greater than or equal to the power threshold, sends a calibration termination indication signal to the IQ amplitude and phase mismatch calibration module;

[0021] When the IQ amplitude and phase mismatch calibration module receives the calibration permission indication signal from the interference detection module, it compares the I-channel AC signal and the Q-channel AC signal output by the DC component elimination module to obtain the amplitude calibration amount and the phase calibration amount of the current gear gain, and performs amplitude calibration and phase calibration on the input I-channel AC signal and the Q-channel AC signal according to the amplitude calibration amount and the phase calibration amount; when receiving the calibration termination indication signal from the interference detection module, it stops executing the calibration action;

[0022] The demodulation module performs demodulation processing on the calibrated I-path signal and the calibrated Q-path signal.

[0023] In a second aspect, an embodiment of the present application provides a radio frequency receiver, which is applied to the IQ channel calibration method of the present application, and includes:

[0024] Signal selector, low noise amplifier, I-channel multiplier, Q-channel multiplier, I-channel filter amplifier, Q-channel filter amplifier, I-channel ADC, Q-channel ADC, DC component elimination module, IQ amplitude and phase mismatch calibration module, demodulation module, phase shifter, local oscillator, signal generator, processor, notch module and interference detection module;

[0025] Wherein, the processor is respectively connected to the control end of the signal generator, the local oscillator, the trap module and the interference detection module;

[0026] The RF antenna is connected to the first input end of the signal selector, the output end of the signal generating module is connected to the second input end of the signal selector, the output end of the signal selector is connected to the input end of the low noise amplifier, and the output end of the low noise amplifier is respectively connected to the first input end of the I-way multiplier and the second input end of the Q-way multiplier; the output end of the local oscillator is connected to the I-way input end of the I-way multiplier through the phase shifter, and the output end of the local oscillator is connected to the Q-way input end of the Q-way multiplier;

[0027] The output end of the I-way multiplier is connected to the I-way input end of the DC component elimination module through the I-way filter amplifier and the I-way ADC;

[0028] The output end of the Q-path multiplier is connected to the Q-path input end of the DC component elimination module through the Q-path filter amplifier and the Q-path ADC;

[0029] The I-way output end of the DC component elimination module is connected to the I-way input end of the IQ amplitude and phase mismatch calibration module, and the Q-way output end of the DC component elimination module is connected to the Q-way input end of the IQ amplitude and phase mismatch calibration module;

[0030] The I-way output end of the DC component elimination module is connected to the I-way input end of the notch module, the Q-way output end of the DC component elimination module is connected to the Q-way input end of the notch module, the I-way output end of the notch module is connected to the I-way input end of the interference detection module, the Q-way output end of the notch module is connected to the Q-way input end of the interference detection module, and the output end of the interference detection module is connected to the control end of the IQ amplitude and phase mismatch calibration module;

[0031] The I-channel output end of the IQ amplitude and phase mismatch calibration module is connected to the I-channel input end of the demodulation module, and the Q-channel output end of the IQ amplitude and phase mismatch calibration module is connected to the Q-channel input end of the demodulation module.

[0032] In a third aspect, an embodiment of the present application provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the above-mentioned method steps.

[0033] In a fourth aspect, an embodiment of the present application provides an electronic device, which may include: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and executing the above-mentioned method steps.

[0034] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0035] By introducing the notch module and the interference detection module, the interference signals with the same or similar frequency band as the excitation signal can be effectively removed or reduced during the calibration process. The notch module performs band-stop processing on the preset frequency offset △f signal to ensure that the I-channel AC signal and the Q-channel AC signal do not contain the interference component of this frequency. The interference detection module calculates the power sum of the band-stop signal and compares it with the preset power threshold to determine whether there is significant external interference. This mechanism avoids calibration in the presence of interference, thereby greatly improving the accuracy of calibration. By dynamically configuring the frequency f and power of the signal generator, the frequency (f+△f) of the local oscillator, and adjusting the calibration parameters according to the current gear gain, accurate calibration of the IQ channels under different gain gears is achieved. At the same time, by real-time monitoring of interference signals and terminating calibration when interference exists, the robustness and adaptability of the calibration process are enhanced, making the calibration results more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 is a schematic diagram of the structure of a radio frequency receiver provided in an embodiment of the present application;

[0038] Figure 2 It is a flowchart of an IQ channel calibration method for a radio frequency receiver provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] Figure 1 A schematic structural diagram of a radio frequency receiver that can be applied to the present application is shown.

[0041] like Figure 1 As shown, the RF receiver may include: a signal selector, a low noise amplifier, an I-channel multiplier, a Q-channel multiplier, an I-channel filter amplifier, a Q-channel filter amplifier, an I-channel ADC, a Q-channel ADC, a DC component elimination module, an IQ amplitude and phase mismatch calibration module, a demodulation module, a phase shifter, a local oscillator, a signal generator, a processor, a notch module and an interference detection module.

[0042] Among them, the connection relationship between the above components is:

[0043] The processor is connected to the control end of the signal generator, the local oscillator, the notch module and the interference detection module respectively. The processor configures the frequency and power for the signal generator, the local oscillator frequency and frequency offset for the local oscillator, the notch frequency for the notch module, and the power threshold for the interference detection module through the control end. The RF antenna is connected to the first input end of the signal selector, the output end of the signal generation module is connected to the second input end of the signal selector, the output end of the signal selector is connected to the input end of the low noise amplifier, and the output end of the low noise amplifier is respectively connected to the first input end of the I multiplier and the second input end of the Q multiplier. The output end of the local oscillator is connected to the I input end of the I multiplier through the phase shifter, and the output end of the local oscillator is connected to the Q input end of the Q multiplier. The output end of the I-channel multiplier is connected to the I-channel input end of the DC component elimination module through the I-channel filter amplifier and the I-channel ADC; the output end of the Q-channel multiplier is connected to the Q-channel input end of the DC component elimination module through the Q-channel filter amplifier and the Q-channel ADC; the I-channel output end of the DC component elimination module is connected to the I-channel input end of the IQ amplitude and phase mismatch calibration module, and the Q-channel output end of the DC component elimination module is connected to the Q-channel input end of the IQ amplitude and phase mismatch calibration module; the I-channel output end of the DC component elimination module is connected to the I-channel input end of the notch module. The Q-path output end of the DC component elimination module is connected to the Q-path input end of the notch module, the I-path output end of the notch module is connected to the I-path input end of the interference detection module, the Q-path output end of the notch module is connected to the Q-path input end of the interference detection module, and the output end of the interference detection module is connected to the control end of the IQ amplitude and phase mismatch calibration module; the I-path output end of the IQ amplitude and phase mismatch calibration module is connected to the I-path input end of the demodulation module, and the Q-path output end of the IQ amplitude and phase mismatch calibration module is connected to the Q-path input end of the demodulation module.

[0044] In some embodiments of the present application, a low noise amplifier, an I-channel multiplier, a Q-channel multiplier, an I-channel filter amplifier, a Q-channel filter amplifier, an I-channel ADC, a Q-channel ADC, a DC component elimination module, an IQ amplitude and phase mismatch calibration module, a demodulation module, a phase shifter, a local oscillator, a processor, a notch module and an interference detection module are integrated into the same chip, and the advantage is that the integrated design reduces the connection loss and interference between modules and improves the efficiency and accuracy of signal processing. The signal transmission between the modules is more direct and fast, which helps to improve the performance and stability of the entire system. The modules integrated in the same chip can share power and ground, reducing the complexity of power management and reducing power consumption. This is of great significance for improving the endurance of the device and reducing energy waste. The integrated design reduces the number of external components and the packaging cost, making the cost of the entire system more controllable. In addition, due to the closer interconnection between the modules inside the chip, the production cost and manufacturing cycle can be further reduced. Integrating multiple modules into the same chip greatly saves space on the circuit board, making the design of the device more compact and flexible. This is of great significance for the design of miniaturized and lightweight devices. The integrated design reduces external connection points and interfaces, reducing the risk of failure due to poor connection or loose interface. At the same time, the protection mechanism and redundancy design inside the chip can further improve the reliability and stability of the system.

[0045] Among them, the processor may include one or more processing cores. The processor uses various interfaces and lines to connect the various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory. Optionally, the processor can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU) and a modem.

[0046] The following will be combined with the attached Figure 2 , the IQ channel calibration method of the radio frequency receiver provided in the embodiment of the present application is described in detail. Among them, the IQ channel calibration device in the embodiment of the present application can be Figure 1 RF receiver shown.

[0047] See also Figure 2 , is a flow chart of an IQ channel calibration method for a radio frequency receiver provided in an embodiment of the present application. Figure 2 As shown, the method of the embodiment of the present application may include the following steps:

[0048] S201. The processor obtains the current gear gain, configures the frequency f and power for the signal generating module according to the current gear gain, and instructs the signal selector to open the test channel and close the antenna channel.

[0049] The processor first reads the currently set gear gain value, which determines the output characteristics of the signal generation module. Based on this gear gain, the processor configures the output frequency f and power of the signal generation module. At the same time, the processor controls the signal selector to open the channel for testing and close the antenna channel to ensure the independence of the test environment. Figure 1 As shown, the antenna channel refers to a signal channel formed between a first input terminal and an output terminal of the signal selector, and the test channel refers to a signal channel formed between a second input terminal and an output terminal of the signal selector.

[0050] S202: The signal generator outputs an excitation signal to the signal selector according to the frequency f and the power.

[0051] The signal generator generates an excitation signal according to the frequency f and power set by the processor, and outputs the signal to the signal selector.

[0052] S203: The signal selector sends the excitation signal to the low noise amplifier through the test channel.

[0053] The signal selector, under the control of the processor, sends the excitation signal to the low noise amplifier (LNA) through the test channel.

[0054] S204, the low noise amplifier amplifies and power divides the excitation signal, generates two identical I-channel test signals and Q-channel test signals, sends the I-channel test signal to the I-channel multiplier, and sends the Q-channel test signal to the Q-channel multiplier.

[0055] The low noise amplifier amplifies the received excitation signal and generates two identical signals through a built-in power divider, which are marked as I-channel test signal and Q-channel test signal. The two signals are sent to the I-channel multiplier and the Q-channel multiplier respectively.

[0056] S205: The processor instructs the local oscillator to generate Q local oscillation signals according to the frequency f of the excitation signal.

[0057] The processor instructs the local oscillator (LO) to generate a Q-channel local oscillator signal according to the frequency f of the excitation signal, whose frequency is f+△f, wherein △f is a preset frequency offset, and IQ amplitude and phase mismatch calibration is performed based on the △f signal.

[0058] S206 , the phase shifter performs a 90-degree phase shift on the Q-channel local oscillator signal and outputs an I-channel local oscillator signal.

[0059] The phase shifter receives the Q-channel local oscillator signal and shifts its phase by 90 degrees to generate the I-channel local oscillator signal. In this way, the I-channel and Q-channel local oscillator signals form an orthogonal relationship.

[0060] S207, the I-channel multiplier multiplies the I-channel test signal and the I-channel local oscillator signal and outputs an I-channel analog signal.

[0061] The I-channel multiplier multiplies the I-channel test signal with the I-channel local oscillator signal to generate an I-channel analog signal.

[0062] S208, the Q-channel multiplier multiplies the Q-channel test signal and the Q-channel local oscillator signal and outputs a Q-channel analog signal.

[0063] The Q-channel multiplier multiplies the Q-channel test signal with the Q-channel local oscillator signal to generate a Q-channel analog signal.

[0064] S209 , the I-channel filter amplifier performs filtering and amplifying processing on the I-channel analog signal, and the Q-channel filter amplifier performs filtering and amplifying processing on the Q-channel analog signal.

[0065] The I-channel and Q-channel filter amplifiers filter and amplify their respective analog signals to remove unnecessary frequency components and enhance signal strength.

[0066] S210, the I-channel ADC performs analog-to-digital conversion on the signal output by the I-channel filter amplifier and outputs an I-channel digital signal, and the Q-channel ADC performs analog-to-digital conversion on the signal output by the Q-channel filter amplifier and outputs a Q-channel digital signal.

[0067] Among them, the I-channel ADC (analog-to-digital converter) and the Q-channel ADC convert the filtered and amplified analog signals into digital signals for subsequent digital signal processing.

[0068] S211 , a DC component elimination module performs DC elimination processing on an I-channel digital signal and a Q-channel digital signal to obtain an I-channel AC signal and a Q-channel AC signal.

[0069] The DC component elimination module performs DC elimination processing on the I-channel and Q-channel digital signals to remove the DC offset introduced by the non-ideal factors of the system, and obtains the I-channel AC signal and the Q-channel AC signal.

[0070] S212: The processor configures the notch frequency of the notch module to be a preset frequency offset Δf, and configures a power threshold for the interference detection module.

[0071] The processor configures a notch module to perform band-stop processing on the signal with a frequency offset of △f, in order to remove the component with a frequency offset of △f in the signal. At the same time, the processor also configures a power threshold for the interference detection module, which is used to subsequently determine whether there is an external interference signal.

[0072] S213 , the notch module performs notch processing on the I-channel AC signal and the Q-channel AC signal according to a preset frequency offset △f, and then outputs an I-channel band-stop signal and a Q-channel band-stop signal.

[0073] The notch module performs band-stop processing on the components of the preset frequency offset △f in the I-channel AC signal and the Q-channel AC signal according to the parameters set by the processor. This means that the notch module removes or significantly reduces the signal components with a frequency of △f in the two signals, thereby generating an I-channel band-stop signal and a Q-channel band-stop signal. These band-stop signals are then sent to the interference detection module for further analysis.

[0074] S214, the interference detection module calculates the power sum of the I-path band-stop signal and the Q-path band-stop signal. If the power sum is less than the power threshold, a calibration permission indication signal is sent to the IQ amplitude and phase mismatch calibration module; if the power sum is greater than or equal to the power threshold, a calibration termination indication signal is sent to the IQ amplitude and phase mismatch calibration module.

[0075] The interference detection module calculates the power sum of the I-channel band-stop signal and the Q-channel band-stop signal. If the power sum is less than the set power threshold, it is considered that there is no external interference, and a calibration permission indication signal is sent to the IQ amplitude and phase mismatch calibration module; if the power sum is greater than or equal to the power threshold, it is considered that there is external interference, and a calibration termination indication signal is sent.

[0076] Further, in some embodiments of the present application, the interference detection module first calculates the square of the amplitude of the I-path band-stop signal and the Q-path band-stop signal respectively. The square of the amplitude is obtained by multiplying the real part of the signal by itself (for a real signal) or by squaring the real part and the imaginary part of the complex form of the signal and then adding them (for a complex signal). Then, the interference detection module sums the two squared amplitude values ​​to obtain the power sum of the I-path band-stop signal and the Q-path band-stop signal.

[0077] This power sum represents the power sum of all signal components in the I and Q signals except the component with frequency △f after notch processing. The interference detection module then compares this power sum with the power threshold previously configured by the processor.

[0078] If the power sum is less than the power threshold, the interference detection module considers that there is no significant external interference in the current environment, and thus sends a calibration permission indication signal to the IQ amplitude and phase mismatch calibration module.

[0079] If the power sum is greater than or equal to the power threshold, the interference detection module considers that external interference exists, which may affect the accuracy of IQ calibration, and therefore sends a calibration termination indication signal to the IQ amplitude and phase mismatch calibration module.

[0080] This step is a critical step in ensuring that the IQ calibration process can be performed without significant external interference, thereby improving the accuracy and reliability of the calibration.

[0081] Furthermore, the interference detection module believes that there is no significant external interference in the current environment, so it sends a bit 1 signal as a calibration indication signal to the IQ amplitude and phase mismatch calibration module. This bit 1 signal indicates that the calibration process can continue. If the power sum is greater than or equal to the power threshold, the interference detection module believes that there is external interference, which may affect the accuracy of the IQ calibration, so it sends a bit 0 signal as a calibration termination indication signal to the IQ amplitude and phase mismatch calibration module. This bit 0 signal indicates that the calibration process should be terminated to avoid calibration errors caused by interference. In this way, the interference detection module can effectively control the calibration process of the IQ amplitude and phase mismatch calibration module, ensuring that calibration is performed only under the condition of no significant external interference, thereby improving the accuracy and reliability of the calibration. At the same time, using bit 1 and bit 0 as indication signals also simplifies the complexity of signal transmission and processing.

[0082] S215. When the IQ amplitude and phase mismatch calibration module receives a calibration permission indication signal from the interference detection module, it compares the I-channel AC signal and the Q-channel AC signal output by the DC component elimination module to obtain the amplitude calibration amount and the phase calibration amount of the current gear gain, and performs amplitude calibration and phase calibration on the input I-channel AC signal and the Q-channel AC signal according to the amplitude calibration amount and the phase calibration amount; when it receives a calibration termination indication signal from the interference detection module, it stops executing the calibration action.

[0083] When the IQ amplitude and phase mismatch calibration module receives the calibration permission indication signal, it compares and analyzes the I and Q AC signals output by the DC component elimination module, and calculates the amplitude calibration amount and phase calibration amount under the current gear gain. Then, the input I and Q AC signals are calibrated for amplitude and phase according to these calibration amounts. If the calibration termination indication signal is received, the calibration action is stopped.

[0084] S216: The demodulation module demodulates the calibrated I-path signal and the calibrated Q-path signal.

[0085] The demodulation module demodulates the calibrated I-channel and Q-channel signals to restore the original information signals.

[0086] The embodiment of the present application, by introducing a notch module and an interference detection module, can effectively remove or reduce interference signals with the same frequency or a similar frequency band as the excitation signal during the calibration process. The notch module performs band-stop processing for the preset frequency offset △f to ensure that the I-channel AC signal and the Q-channel AC signal do not contain interference components of this frequency. The interference detection module calculates the power sum of the band-stop signal and compares it with the preset power threshold to determine whether there is significant external interference. This mechanism avoids calibration in the presence of interference, thereby greatly improving the accuracy of calibration. By dynamically configuring the frequency f and power of the signal generator, the frequency (f+△f) of the local oscillator, and adjusting the calibration parameters according to the current gear gain, accurate calibration of the IQ channels under different gain gears is achieved. At the same time, by real-time monitoring of interference signals and terminating calibration when interference exists, the robustness and adaptability of the calibration process are enhanced, making the calibration results more reliable.

[0087] The present application also provides a computer storage medium, which can store multiple instructions, and the instructions are suitable for being loaded and executed by a processor as described above. Figure 2 The method steps of the embodiment shown in the figure can be found in the specific implementation process. Figure 2 The specific description of the illustrated embodiment will not be repeated here.

[0088] The present application also provides a computer program product, which stores at least one instruction, and the at least one instruction is loaded and executed by the processor to implement the IQ channel calibration method of the radio frequency receiver as described in the above embodiments.

[0089] Furthermore, an electronic device is provided for an embodiment of the present application, the electronic device comprising a radio frequency receiver, a radio frequency transmitter, at least one processor, at least one network interface, a user interface, a memory, and at least one communication bus, wherein the processor, the memory, and the at least one communication bus are located in a calibration device.

[0090] The communication bus is used to realize the connection and communication between these components.

[0091] Optionally, the electronic device further includes a user interface, which may include a display screen (Display) and a camera (Camera). The optional user interface may also include a standard wired interface and a wireless interface.

[0092] The network interface includes the radio frequency transmitter and radio frequency receiver of the present application.

[0093] Among them, the processor may include one or more processing cores. The processor uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory. Optionally, the processor can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor can integrate one or more combinations of central processing unit (Central Processing Unit, CPU), image processor (Graphics Processing Unit, GPU) and modem. Among them, the CPU mainly processes the operating system, user interface and application program; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor, but implemented by a single chip.

[0094] Among them, the memory may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory includes a non-transitory computer-readable storage medium. The memory can be used to store instructions, programs, codes, code sets or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory may also be optionally at least one storage device located away from the aforementioned processor. The memory as a computer storage medium may include an operating system, a network communication module, a user interface module and an application.

[0095] The user interface in the electronic device is mainly used to provide an input interface for the user and obtain the data input by the user; the processor can be used to call the application stored in the memory and specifically execute the following Figure 2 The specific process can be referred to Figure 2 As shown, no further description is given here.

[0096] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0097] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A method for calibrating an IQ channel of a radio frequency receiver, characterized in that: The method comprises: The processor obtains the current gear gain, configures the frequency f and power for the signal generator according to the current gear gain, and instructs the signal selector to open the test channel and close the antenna channel; The signal generator outputs an excitation signal to the signal selector according to the frequency f and the power; The signal selector sends the excitation signal to the low noise amplifier through the test channel; The low noise amplifier performs amplification and power division processing on the excitation signal, and generates two identical I-channel test signals and Q-channel test signals, and sends the I-channel test signal to the I-channel multiplier, and sends the Q-channel test signal to the Q-channel multiplier; The processor instructs the local oscillator to generate Q local oscillator signals according to the frequency f of the excitation signal; the frequency of the Q local oscillator signals is f+△f, where f is the frequency of the excitation signal and △f is a preset frequency offset; The phase shifter performs a 90-degree phase shift on the Q-channel local oscillator signal and then outputs an I-channel local oscillator signal; The I-channel multiplier multiplies the I-channel test signal and the I-channel local oscillator signal and then outputs an I-channel analog signal; The Q-channel multiplier multiplies the Q-channel test signal and the Q-channel local oscillator signal and then outputs a Q-channel analog signal; The I-channel filter amplifier performs filtering and amplifying processing on the I-channel analog signal, and the Q-channel filter amplifier performs filtering and amplifying processing on the Q-channel analog signal; The I-channel ADC performs analog-to-digital conversion on the signal output by the I-channel filter amplifier and then outputs an I-channel digital signal; the Q-channel ADC performs analog-to-digital conversion on the signal output by the Q-channel filter amplifier and then outputs a Q-channel digital signal; The DC component elimination module performs DC elimination processing on the I-channel digital signal and the Q-channel digital signal to obtain an I-channel AC signal and a Q-channel AC signal; The processor configures the notch frequency of the notch module to be a preset frequency offset Δf, and configures a power threshold for the interference detection module; The notch module performs notch processing on the I-channel AC signal and the Q-channel AC signal according to the preset frequency offset Δf, and then outputs an I-channel band-stop signal and a Q-channel band-stop signal; The interference detection module calculates the power sum of the I-path band-stop signal and the Q-path band-stop signal, and if the power sum is less than the power threshold, sends a calibration permission indication signal to the IQ amplitude and phase mismatch calibration module; if the power sum is greater than or equal to the power threshold, sends a calibration termination indication signal to the IQ amplitude and phase mismatch calibration module; When the IQ amplitude and phase mismatch calibration module receives the calibration permission indication signal from the interference detection module, it compares the I-channel AC signal and the Q-channel AC signal output by the DC component elimination module to obtain the amplitude calibration amount and the phase calibration amount of the current gear gain, and performs amplitude calibration and phase calibration on the input I-channel AC signal and the Q-channel AC signal according to the amplitude calibration amount and the phase calibration amount; when receiving the calibration termination indication signal from the interference detection module, it stops executing the calibration action; The demodulation module performs demodulation processing on the calibrated I-path signal and the calibrated Q-path signal.

2. The method according to claim 1, characterized in that: The interference detection module calculates the power sum of the I-path band-stop signal and the Q-path band-stop signal, including: The square of the amplitude of the I-path band-stop signal and the square of the amplitude of the Q-path band-stop signal are summed to obtain a power sum.

3. The method according to claim 2, characterized in that The calibration permission indication signal is a bit 1 signal, and the calibration termination indication signal is a bit 0 signal.

4. A radio frequency receiver, characterized in that: include: Signal selector, low noise amplifier, I-channel multiplier, Q-channel multiplier, I-channel filter amplifier, Q-channel filter amplifier, I-channel ADC, Q-channel ADC, DC component elimination module, IQ amplitude and phase mismatch calibration module, demodulation module, phase shifter, local oscillator, signal generator, processor, notch module and interference detection module; Wherein, the processor is respectively connected to the control end of the signal generator, the local oscillator, the trap module and the interference detection module; The RF antenna is connected to the first input end of the signal selector, the output end of the signal generating module is connected to the second input end of the signal selector, the output end of the signal selector is connected to the input end of the low noise amplifier, and the output end of the low noise amplifier is respectively connected to the first input end of the I-way multiplier and the second input end of the Q-way multiplier; the output end of the local oscillator is connected to the I-way input end of the I-way multiplier through the phase shifter, and the output end of the local oscillator is connected to the Q-way input end of the Q-way multiplier; The output end of the I-way multiplier is connected to the I-way input end of the DC component elimination module through the I-way filter amplifier and the I-way ADC; The output end of the Q-path multiplier is connected to the Q-path input end of the DC component elimination module through the Q-path filter amplifier and the Q-path ADC; The I-way output end of the DC component elimination module is connected to the I-way input end of the IQ amplitude and phase mismatch calibration module, and the Q-way output end of the DC component elimination module is connected to the Q-way input end of the IQ amplitude and phase mismatch calibration module; The I-way output end of the DC component elimination module is connected to the I-way input end of the notch module, the Q-way output end of the DC component elimination module is connected to the Q-way input end of the notch module, the I-way output end of the notch module is connected to the I-way input end of the interference detection module, the Q-way output end of the notch module is connected to the Q-way input end of the interference detection module, and the output end of the interference detection module is connected to the control end of the IQ amplitude and phase mismatch calibration module; The I-channel output end of the IQ amplitude and phase mismatch calibration module is connected to the I-channel input end of the demodulation module, and the Q-channel output end of the IQ amplitude and phase mismatch calibration module is connected to the Q-channel input end of the demodulation module.

5. The radio frequency receiver according to claim 4, characterized in that: A low noise amplifier, an I-channel multiplier, a Q-channel multiplier, an I-channel filter amplifier, a Q-channel filter amplifier, an I-channel ADC, a Q-channel ADC, a DC component elimination module, an IQ amplitude and phase mismatch calibration module, a demodulation module, a phase shifter, a local oscillator, a processor, a notch module and an interference detection module are integrated in the same chip.

6. An electronic device, characterized in that: include: A radio frequency receiver as claimed in claim 4 or 5.

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