A method and apparatus for managing logical ports of an intelligent network card, and a medium

Abstract

The application discloses a logic port management method and device of an intelligent network card, equipment and medium, applied to the technical field of computers, and used for improving the management efficiency of ports. The method comprises the following steps: a first chip in the intelligent network card acquires port management information, and configures the logic port of the first chip; meanwhile, a network card event with an event type of port configuration is triggered; then, the first chip listens to the network card event, and when the event type of the network card event is port configuration, the first chip sends port management information corresponding to the network card event to a second chip; and the second chip configures the logic port of the second chip according to the port management information corresponding to the network card event. According to the scheme, the first chip listens to the network card event and sends the port management information to the second chip, so that the second chip can directly configure the logic port, thereby avoiding the need to configure the port by means of the DPDK driver and the need to develop an operation and maintenance tool, and the efficiency of port management is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device and medium for managing the logical ports of a smart network interface card (NIC). Background Technology

[0002] A Smart Network Interface Card (SNIC) is a flexible, programmable network interface card with computing capabilities, enabling it to perform various functions such as storage acceleration, data encryption, deep packet inspection, and complex routing. SNICs typically have two or more physical ports for external data transmission. To achieve load balancing across these multiple physical ports, bonding technology is used to abstract and bind multiple physical ports into a single logical port.

[0003] Logical port management primarily relies on the Data Plane Development Kit (DPDK), which resides in user space. In practice, technicians need to develop an operations and maintenance tool to connect to the DPDK and manage the logical ports within the SNIC. Different operations and maintenance tools are required for different SNICs, leading to inefficient port management and high management costs.

[0004] In summary, there is an urgent need for a logical port management method for smart network interface cards (NICs) to improve port management efficiency and reduce port management costs. Summary of the Invention

[0005] This application provides a logical port management method, apparatus, device, and medium for a smart network interface card (NIC), which improves port management efficiency and reduces port management costs.

[0006] Firstly, this application provides a logical port management method for a smart network interface card (NIC). The method includes: a first chip in the smart NIC acquires port management information and configures the logical ports of the first chip according to the port management information; simultaneously, a NIC event of type port configuration is triggered; then, the first chip listens for NIC events, and when the event type of the NIC event is port configuration, sends the port management information corresponding to the NIC event to a second chip. The second chip configures its logical ports according to the port management information corresponding to the NIC event. The logical ports of the first chip are obtained by binding multiple mapped ports of the first chip. The mapped ports of the first chip refer to virtual interfaces that have a mapping relationship with the second chip in the smart NIC. The logical ports of the second chip are obtained by binding multiple external ports of the second chip. The external ports of the second chip are the physical ports of the smart NIC for external data transmission, and the external ports of the second chip are mutually mapped to the mapped ports of the first chip.

[0007] When configuring the logical ports of a smart network interface card (NIC), without using DPDK, the port management information received by the first chip cannot be transmitted and configured to the logical ports of the second chip. To solve this problem, in this solution, since the logical ports of the first chip are configured in the kernel space of the first chip, a NIC event of type port configuration is triggered. Subsequently, the first chip listens for NIC events. When it detects a NIC event of type port configuration, it can send the corresponding port management information to the second chip. This allows the second chip to receive the port management information and configure its logical ports accordingly, eliminating the need for DPDK driver-based port configuration. Therefore, no further development of maintenance tools is required, thus improving port management efficiency and reducing port management costs.

[0008] Optionally, the method further includes: the first chip obtaining the port status of the logical port of the second chip; the first chip comparing whether the port status of the logical port of the second chip is consistent with the port status of the logical port of the first chip; if they are inconsistent, the first chip configuring the logical port of the first chip according to the port status of the logical port of the second chip.

[0009] Using the above method, the port status of the logic port of the first chip is kept consistent with the port status of the logic port of the second chip, so that the first chip can determine the port status of the logic port of the second chip in real time and realize port status management of the logic port.

[0010] Optionally, the first chip has multiple mapped ports including a first mapped port and a second mapped port, and the second chip has multiple external ports including a first external port and a second external port; the first mapped port is mapped to the first external port, and the second mapped port is mapped to the second external port; the first chip compares whether the port state of the second chip's logical port is consistent with the port state of the first chip's logical port, including: the first chip compares whether the port state of the first mapped port is consistent with the port state of the first external port; the first chip compares whether the port state of the second mapped port is consistent with the port state of the second external port; if they are inconsistent, the first chip configures the logical port of the first chip according to the port state of the second chip's logical port, including: if the port state of the first mapped port is inconsistent with the port state of the first external port, the first chip configures the port state of the first mapped port according to the port state of the first external port; if the port state of the second mapped port is inconsistent with the port state of the second external port, the first chip configures the port state of the second mapped port according to the port state of the second external port.

[0011] In this solution, a logical port is a logical concept that aggregates the capabilities of multiple physical ports, enabling them to work together as a single network port to provide services externally. In other words, the logical port does not carry specific functions; those functions are carried by the physical ports it corresponds to. Therefore, port status tracking actually tracks the port status of the physical ports corresponding to the logical ports. Thus, this solution tracks the port status of the first external port and the second external port, and configures the port status of the first and second mapped ports based on these port statuses.

[0012] Optionally, the second chip further includes a logic port status register; the logic port status register is used to track the port status of the logic ports of the second chip; the first chip obtains the port status of the logic ports of the second chip by: the first chip obtaining the port status of the logic ports of the second chip through the logic port status register.

[0013] This solution sets a logic port status register in the second chip. The logic port status register can track the port status of the logic ports of the second chip in real time. The first chip can determine the port status of the logic ports of the second chip in real time by polling the logic port status register.

[0014] Optionally, the second chip further includes a binding management register; sending port management information corresponding to the network card event to the second chip in the smart network card includes: sending the port management information corresponding to the network card event to the binding management register; the second chip configures the logical port of the second chip according to the port management information corresponding to the network card event, including: configuring the logical port of the second chip according to the port management information corresponding to the network card event through the binding management register.

[0015] In the above method, by setting a binding management register in the second chip, the second chip can obtain the port management information corresponding to the network card event through the binding management register, and can configure the logical port of the second chip according to the port management information corresponding to the network card event.

[0016] Optionally, the first chip in the smart network card acquires port management information, including: the first chip acquires port management information input by the user, and / or, the first chip acquires port management information transmitted by the second chip.

[0017] In the above method, the first chip can directly receive port management information input by the user, or it can receive port management information transmitted by the second chip. For example, in dynamic link binding mode, the first chip receives LACP messages transmitted by the switch through the second chip as port management information, thereby realizing logical port management in dynamic link binding mode.

[0018] Optionally, the first chip obtains port management information transmitted by the second chip, including: the first chip receiving Link Convergence Control Protocol (LACP) messages forwarded by the second chip; and the first chip parsing the LACP messages to obtain the port management information corresponding to the LACP messages.

[0019] In the above method, under dynamic link binding mode, the first chip receives LACP messages transmitted by the switch through the second chip as port management information. By parsing the LACP messages and based on the parsed information, the management of logical ports can be realized.

[0020] Optionally, the method further includes: the first chip receiving the Address Resolution Protocol (ARP) packet forwarded by the second chip; the first chip parsing the ARP packet to obtain the address corresponding to the ARP packet; and the first chip storing the address corresponding to the ARP packet.

[0021] In the above method, the address corresponding to the ARP packet needs to be learned first during ARP packet transmission. In this solution, the Bonding module of the first chip can directly parse and learn the address corresponding to the ARP packet without relying on the DPDK driver, thus improving the efficiency of port management.

[0022] Secondly, this application provides a logical port management device for a smart network interface card (NIC), comprising: a first acquisition unit for acquiring port management information; a first processing unit for configuring a logical port of a first chip according to the port management information and triggering a NIC event of type port configuration; the logical port of the first chip is obtained by binding multiple mapped ports of the first chip; the mapped port of the first chip refers to a virtual interface that has a mapping relationship with a second chip in the smart NIC; listening to NIC events and sending the port management information corresponding to the NIC event to the second chip when the event type of the NIC event is port configuration; a second processing unit for configuring a logical port of the second chip according to the port management information corresponding to the NIC event; the logical port of the second chip is obtained by binding multiple external ports of the second chip; the external ports of the second chip are the physical ports for the smart NIC to transmit data externally; the external ports of the second chip are mapped to the mapped ports of the first chip.

[0023] Thirdly, this application provides a smart network interface card (NIC), including a first chip and a second chip connected together. The first chip is used to acquire port management information; configure the logical ports of the first chip according to the port management information, and trigger a NIC event of type port configuration. The logical ports of the first chip are obtained by binding multiple mapped ports of the first chip. The mapped ports of the first chip refer to virtual interfaces that have a mapping relationship with the second chip in the smart NIC. The first chip listens for NIC events and, when the event type of the NIC event is port configuration, sends the port management information corresponding to the NIC event to the second chip. The second chip is used to configure the logical ports of the second chip according to the port management information corresponding to the NIC event. The logical ports of the second chip are obtained by binding multiple external ports of the second chip. The external ports of the second chip are the physical ports for the smart NIC to transmit data externally. The external ports of the second chip are mapped to the mapped ports of the first chip.

[0024] Fourthly, this application provides a computing device, including at least one processor and at least one memory, wherein the memory stores a computer program, and when the program is executed by the processor, the processor performs the logical port management method of the smart network card described in any of the first aspects.

[0025] Fifthly, this application also provides a computer-readable storage medium storing a program that, when run on a computer, causes the computer to implement the logical port management method of any of the smart network cards described in the first aspect.

[0026] For details of the beneficial effects of the second to fifth aspects mentioned above, please refer to the technical effects that can be achieved by the corresponding design in the first aspect mentioned above, which will not be repeated here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of a smart network interface card provided in an embodiment of this application;

[0029] Figure 2 A flowchart illustrating a logical port management method for a smart network interface card (NIC) provided in this application embodiment;

[0030] Figure 3 A flowchart illustrating a method for obtaining port management information transmitted by a second chip, provided in an embodiment of this application;

[0031] Figure 4 A flowchart illustrating a logical port management method for a smart network interface card (NIC) provided in this application embodiment;

[0032] Figure 5 This application provides a flowchart illustrating a method for parsing ARP packets.

[0033] Figure 6 A schematic diagram illustrating the parsing of ARP packets by a smart network interface card (NIC) as provided in an embodiment of this application;

[0034] Figure 7 A structural diagram of a logical port management device for a smart network interface card (NIC) provided in this application embodiment;

[0035] Figure 8 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] It should be noted that in the description of this application, "multiple" is understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. A connected to B can represent: A and B directly connected, or A and B connected through C. Furthermore, in the description of this application, terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0038] Bonding technology refers to virtualizing multiple physical ports of a smart network interface card (NIC) into a single logical port, thereby improving network throughput and availability for hosts connected to the smart NIC. Physical ports correspond to physical layer hardware, responsible for actual data transmission and physical link connections; each physical port has a unique MAC address. Correspondingly, the logical port is visible to external applications and the network protocol stack as if it were a separate physical port, and all physical ports corresponding to a logical port share the same Internet Protocol (IP) address. Through load balancing and failover of multiple physical ports, logical ports can provide higher bandwidth and redundancy.

[0039] Typically, logical ports include seven bonding modes. The industry standard stipulates that smart network interface cards (NICs) must support at least three of these seven modes: primary / standby mode (mode=1), load balancing mode (mode=2), and dynamic link bonding mode (mode=4). Primary / standby mode means that only one physical port is available and allows network traffic to pass through at any given time, while the remaining physical ports act as backup ports and do not transmit data. Load balancing mode uses a specified hash policy to transmit data packets, providing load balancing and fault tolerance. Dynamic link bonding mode means that the logical port supports the 802.3ad protocol and can recognize Link Aggregation Control Protocol (LACP) messages transmitted by the switch. In this mode, all physical ports corresponding to the logical port maintain the same speed and duplex mode.

[0040] In practice, logical ports need to be managed according to the binding mode. However, a logical port is a virtual concept and does not carry specific functions. Therefore, configuring a logical port actually refers to configuring the physical port corresponding to the logical port to ensure that it operates as required. As introduced in the background, traditional technology typically uses DPDK to manage logical ports. This method requires the development of corresponding operation and maintenance tools, resulting in low management efficiency. In view of this, this application provides a logical port management method for smart network interface cards (NICs).

[0041] like Figure 1The diagram shown is a structural schematic of a smart network interface card (NIC) provided in an embodiment of this application. The operating system of the smart NIC can be Linux or other operating systems, and is not specifically limited. The smart NIC includes a first chip 100 and a second chip 200. The first chip 100 and the second chip 200 can exchange information. The communication method can be wired communication, for example, through the Peripheral Component Interconnect Express (PCIe) bus.

[0042] The first chip 100 and the second chip 200 will be described in detail below.

[0043] The first chip 100 can be a System on Chip (SOC). An SOC is an integrated circuit chip that integrates multiple functional modules (such as processors, memory controllers, I / O ports, etc.). The first chip can be divided into user space and kernel space. Kernel space is the area accessed by the operating system kernel, independent of ordinary applications, and is a protected memory space. User space is the space accessible to ordinary applications. When a process runs in kernel space, it is in kernel mode; when a process runs in user space, it is in user mode. In user mode, the program runs on top of the operating system but is subject to certain restrictions, unable to directly access underlying hardware resources or perform privileged operations. This is to ensure the stability and security of the operating system. In user mode, programs can perform ordinary application tasks, such as opening files and performing calculations, but cannot directly manipulate memory or other system resources. In kernel mode, programs have higher privileges and can directly access underlying hardware resources and perform privileged operations, such as memory management and hardware drivers. Traditional technologies typically manage logical ports through DPDK in user space. This method has low management efficiency and requires technicians to develop an operation and maintenance tool to connect to DPDK, resulting in high management costs. However, this solution manages logical ports based on kernel space, which has relatively high management efficiency.

[0044] The first chip 100 includes a user input module 101. The user input module 101 resides in the user space of the first chip 100 and is used to receive port management information input by the user. In the Linux operating system, the user input module 101 can refer to the software package iproute2 or the software package net-tools. The software package iproute2 is a new generation toolkit for managing and controlling TCP / IP networks and flow control under Linux. It uses the tools "ip" and "sysfs" to receive port management information input by the user. This port management information includes, but is not limited to: creating a logical port, adding member ports to a logical port (for the first chip, this means adding a mapped port to the logical ports of the first chip; for the second chip, this means adding an external port to the logical ports of the second chip), querying the aggregation information of a logical port, deleting member ports of a logical port, disabling a logical port (i.e., suspending the use of a logical port), enabling a logical port (i.e., enabling a logical port), and deleting a logical port.

[0045] The first chip 100 also includes a bonding module 102. The bonding module 102 resides in the kernel space of the first chip 100 and is used to configure the bonding ports of the first chip 100, implementing the port bonding function. It should be noted that since performing operations in the kernel space triggers a network interface card (NIC) generation event, when the bonding module 102 performs operations, it will trigger a NIC generation event in the kernel space. When the bonding module 102 configures the bonding ports of the first chip 100, the event type of the triggered NIC event is port configuration. In this embodiment, the bonding module can be a kernel module natively supported by the Linux operating system. The first chip 100 can manually load this kernel module by performing the "modprobe bonding" operation, and by default, it will compile and output the bonding.ko module file.

[0046] / usr / lib / modules / $(uname-r) / kernel / drivers / net / bonding / bonding.ko

[0047] The first chip 100 also includes a monitoring module 103. The monitoring module 103 resides in the kernel space of the first chip 100 and is used to monitor network interface card (NIC) events in the internal control space of the first chip 100, filter out NIC events of interest, parse and synchronize configuration parameters to the second chip 200 or its relevant registers. Furthermore, the monitoring module 103 can poll the port status of the logical ports on the second chip 200, compare the port status of the logical ports on the second chip 200 with that of the first chip 100, and if they are inconsistent, configure the logical ports of the first chip 100 according to the port status of the logical ports on the second chip 200. Optionally, a high-precision timer (hrtimer) can be configured for the monitoring module 103, allowing it to periodically query the second chip 200 for the port status of the logical ports on the second chip 200. Those skilled in the art can set the access time interval of the high-precision timer based on experience; for example, the monitoring module 103 may query the second chip 200 every second.

[0048] The first chip 100 also includes multiple mapped ports. A mapped port is a virtual interface that has a mapping relationship with the second chip in the smart network card. Binding the multiple mapped ports of the first chip 100 can obtain the logical ports of the first chip 100. This application embodiment does not limit the number of mapped ports. Figure 1 The example illustrates two mapped ports, namely the first mapped port 104 and the second mapped port 105. Using a binding technique, the first mapped port 104 and the second mapped port 105 are abstractly bound into a single logical port, referred to as the logical port 106 of the first chip. Specifically, the process of binding the logical port can be as follows: first, create the logical port 106 of the first chip; add the first mapped port 104 to the member port of the logical port 106 of the first chip, denoted as member port 1; then add the second mapped port 105 to the member port of the logical port 106 of the first chip, denoted as member port 2.

[0049] In this embodiment of the application, since a logical port is a logical concept and does not carry a specific function, configuring the logical port 106 of the first chip 100 actually refers to configuring the mapped port 104 and the mapped port 105.

[0050] In one possible implementation, the first chip 100 also includes a management port 107, which is the management port of the second chip 200, used to transmit data related to the second chip 200. For example, port management information is transmitted from the first chip 100 to the second chip 200 through the management port 107, or the port status of the logical port of the second chip 200 is transmitted from the second chip 200 to the first chip 100 through the management port 107.

[0051] In one possible implementation, the first chip 100 further includes at least one network packet forwarding port 108. Figure 1 The example shows three network packet forwarding ports. Network packet forwarding port 108 is used for forwarding network packets between the first chip and the second chip.

[0052] In one possible implementation, the first chip 100 further includes at least one block storage message forwarding port 109. Figure 1 The example shows a block storage message forwarding port 109, which is used for forwarding network messages between the first chip and the second chip.

[0053] Furthermore, the first chip 100 may also include a software data plane (OVS) module 110. The OVS module 110 is located in the user space of the first chip 100 and is responsible for slow path forwarding and flow table offloading with the help of the IFC module 111, ultimately enabling fast path forwarding of the second chip 200.

[0054] Furthermore, the first chip 100 may also include a user space driver (IFC) module 111. The IFC module 111 is located in the user space of the first chip 100 and is used to establish data and control paths between the first chip 100 and the second chip 200.

[0055] The second chip 200 is a programmable chip, such as a field programmable gate array (FPFA) or an application specific integrated circuit (ASIC).

[0056] The second chip 200 includes at least one external port, which is the physical port for the smart network card to transmit data externally. The external ports of the second chip 200 are mapped to the mapped ports of the first chip 100. Logical ports of the second chip 200 are obtained by binding the external ports of the second chip 200. Figure 1The example illustrates a second chip comprising two external ports: a first external port 201 (denoted as MAC0) and a second external port 202 (denoted as MAC1). To achieve load balancing across multiple physical ports, the first external port 201 and the second external port 202 are bound together to obtain a logical port 203 for the second chip. In this embodiment, since a logical port is a logical concept and does not carry a specific function, configuring the logical port 203 of the second chip essentially refers to configuring the first external port 201 and the second external port 202. Furthermore, to enable the first chip 100 to determine the port status of the logical ports of the second chip in real time, the port status of the logical ports of the first chip is kept consistent with the port status of the logical ports of the second chip. Figure 1 In this configuration, the first external port 201 is mapped to the first mapped port 104, and the second external port 202 is mapped to the second mapped port 105.

[0057] The second chip 200 also includes a binding management register 204, which is a configuration register used to manage the logic port 203 of the second chip 200.

[0058] The second chip 200 also includes a logic port status register 205, used to track the port status of the logic port 203 of the second chip 200. Figure 1 In the example, the logical port status register 205 actually tracks the port status of the first external port 201 and the second external port 202.

[0059] The second chip 200 also includes a hardware flow table register 206 for storing hardware flow tables used to unload software forwarding rules.

[0060] The second chip 200 also includes a virtio-net backend 207, which is used to work with the virtio-net driver in the host system.

[0061] Based on the above introduction to smart network interface cards, Figure 2 A flowchart illustrating a logical port management method for a smart network interface card (NIC) provided in this application embodiment is shown. The method includes the following steps:

[0062] Step 201: The first chip 100 obtains port management information.

[0063] In one possible implementation, the method of obtaining port management information includes: the first chip 100 obtaining port management information input by the user, and / or the first chip 100 obtaining port management information transmitted by the second chip 200.

[0064] In this embodiment, port management information can come from user input or from input from an external device (such as a switch) connected to the smart network card. For user input, the Bonding module 102 in the first chip 100 can obtain the user-inputted port management information through the user input module 101. A detailed description of the user-inputted port management information can be found above and will not be repeated here. For input from external components, the external port of the second chip 200 obtains the input from the external component and transmits it to the Bonding module 102 through the corresponding mapped port of the first chip 100. The Bonding module 102 then obtains the port management information transmitted by the second chip 200.

[0065] In one possible implementation, when the binding mode of the logical port is set to dynamic link binding mode, the external port of the second chip 200 obtains the LACP message transmitted by the switch and transmits it to the Bonding module 102 through the corresponding mapped port of the first chip 100. The Bonding module 102 then obtains the LACP message.

[0066] Figure 3 An exemplary flowchart illustrates a method for obtaining port management information transmitted by a second chip, the method comprising the following steps:

[0067] Step 301: The first chip 100 receives the LACP message forwarded by the second chip.

[0068] Specifically, the Bonding module 102 in the first chip 100 obtains the LACP message forwarded by the second chip 200.

[0069] Step 302: The first chip 100 parses the LACP message to obtain the port management information corresponding to the LACP message.

[0070] Specifically, the Bonding module 102 in the first chip 100 parses the LACP message to obtain the port management information corresponding to the LACP message.

[0071] Through steps 301 to 302 above, the first chip obtains the port management information transmitted by the switch in the dynamic link binding mode.

[0072] Step 202: The first chip 100 configures the logical port of the first chip 100 according to the port management information and triggers a network card event of the event type of port configuration.

[0073] Specifically, the first chip 100 configures its logical ports in its kernel space according to port management information and triggers a network card event of type port configuration.

[0074] In one possible implementation, the Bonding module 102 in the first chip 100 configures the logical ports of the first chip 100 according to port management information. Taking the port management information as setting the logical ports to primary / backup mode, where the first external port 201 is set as the primary port and the second external port 202 is set as the backup port, after receiving the port management information, the Bonding module 102 will configure the first mapped port 104 corresponding to the first external port 201 as the primary port and the second mapped port 105 corresponding to the second external port 202 as the backup port. During configuration, the Bonding module 102 will simultaneously trigger a network interface card event of type port configuration in the kernel space.

[0075] Step 203: The first chip 100 listens for network card events, and when the event type of the network card event is port configuration, it sends the port management information corresponding to the network card event to the second chip 200.

[0076] Specifically, the listening module 103 in the kernel space of the first chip 100 listens for network card events in the kernel space, and when it detects that the event type of the network card event is port configuration, it sends the port management information corresponding to the network card event to the second chip 200.

[0077] Optionally, when the listening module 103 detects that the event type of the network card event is port configuration, the listening module 103 will parse the network card event, obtain the port management information corresponding to the network card event, and send it to the second chip 200.

[0078] Optionally, after parsing and obtaining the port management information corresponding to the network card event, the listening module 103 will determine the execution type of the port management information. If the execution type of the port management information is to add a member port to the logical port, the listening module 103 will also cache the information of the added member port in the system memory of the first chip. If the execution type of the port management information is to enable the logical port, that is, to enable the logical port, the listening module 103 will first read the configuration parameters of the logical port (e.g., the enable bit) and the configuration parameters of the member port corresponding to the logical port. Then, it will send the port management information to the second chip 200, enabling the second chip 200 to enable its logical port and setting the enable bit of the logical port of the second chip 200 to 1. In addition, the listening module 103 will also start a timer function to periodically poll the status of the logical port on the second chip. If the execution type of the port management information is to disable the logical port, that is, to stop the logical port, the listening module 103 will send the port management information to the second chip 200, causing the second chip 200 to disable the logical port of the second chip 200 and set the enable bit of the logical port of the second chip 200 to 0. If the execution type of the port management information is to delete the logical port, the listening module 103 will send the port management information to the second chip 200, causing the second chip 200 to delete its logical port.

[0079] Alternatively, the first chip 100 may send the port management information corresponding to the network card event to the binding management register 204 of the second chip 200.

[0080] Step 204: The second chip 200 configures the logical port of the second chip 200 according to the port management information corresponding to the network card event.

[0081] Optionally, by binding the management register 204, the second chip 200 can configure the logical port of the second chip according to the port management information corresponding to the network card event.

[0082] Taking the port management information mentioned above as setting the logical port to primary / backup mode, with the first external port 201 set as the primary port and the second external port 202 set as the backup port, after receiving the port management information, the second chip 200 sets the first external port 201 as the primary port and the second external port 202 as the backup port, thereby setting the logical port 203 of the second chip 200 to primary / backup mode.

[0083] Through steps 201 to 204 above, when the first chip listens to a network card event of type port configuration, it can send the port management information corresponding to the network card event to the second chip, so that the second chip receives the port management information and can configure the logical port of the second chip according to the port management information. There is no need to use the DPDK driver for port configuration or to develop operation and maintenance tools, thus improving the efficiency of port management.

[0084] In order for the first chip 100 to determine the port status of the logic port of the second chip 200 in real time, the port status of the logic port of the first chip needs to be consistent with the port status of the logic port of the second chip. That is, the port status of the mapped port of the first chip needs to be consistent with the port status of the corresponding external port of the second chip.

[0085] Figure 4 A flowchart illustrating a logical port management method for a smart network interface card (NIC) provided in this application embodiment is shown. The method includes the following steps:

[0086] Step 401: The first chip 100 obtains the port status of the logic port of the second chip 200.

[0087] Optionally, the first chip 100 can obtain the port status of the logical port of the second chip 200 through the logical port status register 205. Specifically, the first chip 100 can obtain relevant information from the logical port status register 205 through periodic polling. The polling interval can be set according to specific business scenarios; for example, it can query the logical port status register 205 once every 100 milliseconds.

[0088] Step 402: The first chip compares the port status of the logic port of the second chip with the port status of the logic port of the first chip. If they do not match, proceed to step 403; if they match, proceed to step 404.

[0089] Here, port status refers to whether a port is in an open or closed state. In this embodiment, since a logical port is an abstract concept and does not carry a specific function, the actual comparison is whether the port status of the external port of the second chip is consistent with the port status of the mapped port of the first chip.

[0090] exist Figure 1In the example, the mapped ports of the first chip 100 include a first mapped port 104 and a second mapped port 105, and the external ports of the second chip 200 include a first external port 201 and a second external port 202. The first mapped port 104 is mapped to the first external port 201, and the second mapped port 105 is mapped to the second external port 202. Therefore, the first chip 200 compares whether the port status of the first mapped port 104 is consistent with the port status of the first external port 201, and the first chip 200 compares whether the port status of the second mapped port 105 is consistent with the port status of the second external port 202.

[0091] Step 403: The first chip configures the logic port of the first chip according to the port status of the logic port of the second chip.

[0092] Specifically, if the port status of the logic port of the second chip 200 is inconsistent with the port status of the logic port of the first chip 100, then the logic port of the first chip 100 is configured according to the port status of the logic port of the second chip 200. That is, the port status of the mapped port of the first chip is configured according to the port status of the external port of the second chip.

[0093] exist Figure 1 In the example, if the port status of the first mapped port 104 is inconsistent with the port status of the first external port 201, the first chip 100 configures the port status of the first mapped port 104 according to the port status of the first external port 201; if the port status of the second mapped port 105 is inconsistent with the port status of the second external port 202, the first chip 100 configures the port status of the second mapped port 105 according to the port status of the second external port 202.

[0094] Step 404: Do not perform any operation.

[0095] Specifically, if the port state of the logic port of the second chip 200 is consistent with the port state of the logic port of the first chip 100, then the second chip 200 will not perform any operation.

[0096] Through steps 401 to 404 above, the port status of the logic port of the first chip is kept consistent with the port status of the logic port of the second chip, so that the first chip can determine the port status of the logic port of the second chip in real time and realize port status management of the logic port.

[0097] For Address Resolution Protocol (ARP) packets, the external port of the second chip receives ARP packets from external devices and sends them back to the first chip through the mapped port of the first chip 100. The first chip then parses and learns the ARP packet. For example, Figure 1 After receiving an ARP packet, the first external port 201 will forward the packet to the first chip 100 through the first mapping port 104. Correspondingly, after receiving an ARP packet, the second external port 202 will forward the packet to the first chip 100 through the second mapping port 105.

[0098] Figure 5 This application provides a flowchart illustrating a method for parsing ARP packets, which includes the following steps:

[0099] Step 501: The first chip 100 receives the ARP message forwarded by the second chip 200.

[0100] Specifically, the Bonding module 102 in the first chip 100 receives the Address Resolution Protocol (ARP) packets forwarded by the second chip 200.

[0101] Step 502: The first chip 100 parses the ARP packet to obtain the address corresponding to the ARP packet.

[0102] Specifically, the Bonding module 102 in the first chip 100 can parse ARP packets and obtain the address corresponding to the ARP packets according to its own function.

[0103] Step 503: The first chip 100 stores the address corresponding to the ARP packet.

[0104] Specifically, the Bonding module 102 in the first chip 100 stores the address corresponding to the parsed ARP packet, so that the smart network card obtains the address corresponding to the ARP packet sent by the external device, and can then transmit data with the external device.

[0105] It should be noted that, as Figure 6 As shown, for ARP packets, the external port of the second chip sends them to the Bonding module 102 of the first chip through the mapping port of the first chip 100. At the same time, it also sends them to the IFC module 111 of the user space of the first chip through the network packet forwarding port of the first chip 100, and then transmits them to the OVS module 110 for address resolution through the IFC module 111.

[0106] Based on the same inventive concept described above, this application also provides a smart network interface card (NIC), including a first chip and a second chip connected together. The first chip and the second chip are described below:

[0107] The first chip is used to acquire port management information; configure the logical ports of the first chip according to the port management information, and trigger network card events with the event type of port configuration; the logical ports of the first chip are obtained by binding multiple mapped ports of the first chip; the mapped ports of the first chip refer to the virtual interfaces that have a mapping relationship with the second chip in the smart network card; listen for network card events, and when the event type of the network card event is port configuration, send the port management information corresponding to the network card event to the second chip;

[0108] The second chip is used to configure the logical ports of the second chip according to the port management information corresponding to the network card event; the logical ports of the second chip are obtained by binding multiple external ports of the second chip; the external ports of the second chip are the physical ports for the smart network card to transmit data to the outside; the external ports of the second chip are mapped to the mapping ports of the first chip.

[0109] Optionally, the first chip is further configured to obtain the port status of the logic port of the second chip; compare whether the port status of the logic port of the second chip is consistent with the port status of the logic port of the first chip; if they are inconsistent, configure the logic port of the first chip according to the port status of the logic port of the second chip.

[0110] Optionally, the first chip is specifically used to compare whether the port status of the first mapped port is consistent with the port status of the first external port; compare whether the port status of the second mapped port is consistent with the port status of the second external port; if the port status of the first mapped port is inconsistent with the port status of the first external port, then configure the port status of the first mapped port according to the port status of the first external port; if the port status of the second mapped port is inconsistent with the port status of the second external port, then configure the port status of the second mapped port according to the port status of the second external port.

[0111] Optionally, the first chip is specifically used to obtain the port status of the logic port of the second chip through the logic port status register.

[0112] Optionally, the first chip is specifically used to send the port management information corresponding to the network card event to the binding management register; the second chip is specifically used to configure the logical port of the second chip according to the port management information corresponding to the network card event through the binding management register.

[0113] Based on the same inventive concept described above, this application also provides a logical port management device for a smart network interface card (NIC), which can execute the methods described in the above-described embodiments. The structure of the logical port management device for a smart NIC provided in this application can be found in [reference needed]. Figure 7The logical port management device 700 for a smart network interface card (NIC) includes an acquisition unit 701, a first processing unit 702, and a second processing unit 703. The acquisition unit 701 acquires port management information. The first processing unit 702 configures the logical ports of a first chip according to the port management information and triggers a NIC event of type port configuration. The logical ports of the first chip are obtained by binding multiple mapped ports of the first chip. The mapped ports of the first chip refer to physical ports that have a mapping relationship with the second chip in the smart NIC. The unit listens for NIC events and, when the event type of the NIC event is port configuration, sends the port management information corresponding to the NIC event to the second chip. The second processing unit 703 configures the logical ports of the second chip according to the port management information corresponding to the NIC event. The logical ports of the second chip are obtained by binding multiple external ports of the second chip. The external ports of the second chip are the physical ports for the smart NIC to transmit data externally. The external ports of the second chip are mapped to the mapped ports of the first chip.

[0114] Optionally, the first processing unit 702 is specifically used to obtain the port status of the logic port of the second chip; compare whether the port status of the logic port of the second chip is consistent with the port status of the logic port of the first chip; if they are inconsistent, configure the logic port of the first chip according to the port status of the logic port of the second chip.

[0115] Optionally, the mapped ports of the first chip include a first mapped port and a second mapped port, and the external ports of the second chip include a first external port and a second external port; the first mapped port is mapped to the first external port, and the second mapped port is mapped to the second external port; the first processing unit 702 is specifically used to compare whether the port state of the first mapped port is consistent with the port state of the first external port; compare whether the port state of the second mapped port is consistent with the port state of the second external port; if the port state of the first mapped port is inconsistent with the port state of the first external port, then configure the port state of the first mapped port according to the port state of the first external port; if the port state of the second mapped port is inconsistent with the port state of the second external port, then configure the port state of the second mapped port according to the port state of the second external port.

[0116] Optionally, the second chip further includes a logic port status register; the logic port status register is used to track the port status of the logic ports of the second chip; the first processing unit 702 is specifically used for the first chip to obtain the port status of the logic ports of the second chip through the logic port status register.

[0117] Optionally, the second chip further includes a binding management register; the first processing unit 702 is specifically used to send the port management information corresponding to the network card event to the binding management register; the second processing unit 703 is specifically used to configure the logical port of the second chip according to the port management information corresponding to the network card event through the binding management register.

[0118] Optionally, the first processing unit 702 is specifically used to obtain port management information input by the user, and / or to obtain port management information transmitted by the second chip.

[0119] Optionally, the first processing unit 702 is specifically used to receive LACP messages forwarded by the second chip; parse the LACP messages to obtain the port management information corresponding to the LACP messages.

[0120] Optionally, the first processing unit 702 is specifically used to receive the ARP packets forwarded by the second chip; parse the ARP packets to obtain the address corresponding to the ARP packets; and store the address corresponding to the ARP packets.

[0121] Based on the same technical concept, this application also provides a computing device, such as Figure 8 As shown, the computing device 800 includes at least one processor 801 and a memory 802 connected to the at least one processor. This application does not limit the specific connection medium between the processor 801 and the memory 802. Figure 8 Taking the connection between the processor 801 and the memory 802 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0122] In this application, the memory 802 stores instructions that can be executed by at least one processor 801. By executing the instructions stored in the memory 802, at least one processor 801 can perform the steps included in the aforementioned logical port management method of the smart network card.

[0123] The processor 801 serves as the control center of the computing device, connecting various parts of the device via various interfaces and lines. It manages the logical ports of the smart network interface card (NIC) by running or executing instructions stored in the memory 802 and accessing data stored in the memory 802. Optionally, the processor 801 may include one or more processing units. The processor 801 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles issuing instructions. It is understood that the modem processor may not be integrated into the processor 801. In some embodiments, the processor 801 and the memory 802 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0124] The processor 801 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the logical port management method for smart network interface cards can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0125] Memory 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 802 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 802 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. Memory 802 in this application can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0126] Based on the same technical concept, this application also provides a computer-readable storage medium storing a computer program executable by a computing device, which, when run on the computing device, causes the computing device to perform the steps of the above-described logical port management method for a smart network interface card.

[0127] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0129] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0131] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A logical port management method for a smart network interface card (NIC), characterized in that, The method includes: The first chip in the smart network card acquires port management information; The first chip configures its logical ports according to the port management information and triggers a network interface card (NIC) event of type port configuration; the logical ports of the first chip are obtained by binding multiple mapped ports of the first chip; the mapped ports of the first chip refer to virtual interfaces that have a mapping relationship with the second chip in the smart NIC. The first chip listens for network interface card (NIC) events, and when the event type of the NIC event is port configuration, it sends the port management information corresponding to the NIC event to the second chip. The second chip configures its logical ports according to the port management information corresponding to the network card event; the logical ports of the second chip are obtained by binding multiple external ports of the second chip; the external ports of the second chip are the physical ports for the smart network card to transmit data externally; the external ports of the second chip are mapped to the mapping ports of the first chip.

2. The method as described in claim 1, characterized in that, The method further includes: The first chip obtains the port status of the logic port of the second chip; The first chip compares the port status of the logic port of the second chip with the port status of the logic port of the first chip to see if they are consistent. If they are inconsistent, the first chip configures the logical port of the first chip according to the port status of the logical port of the second chip.

3. The method as described in claim 2, characterized in that, The first chip has multiple mapped ports, including a first mapped port and a second mapped port, and the second chip has multiple external ports, including a first external port and a second external port; the first mapped port is mapped to the first external port, and the second mapped port is mapped to the second external port. The first chip compares the port state of the logic port of the second chip with the port state of the logic port of the first chip to see if they are consistent, including: The first chip compares whether the port status of the first mapped port is consistent with the port status of the first external port; the first chip compares whether the port status of the second mapped port is consistent with the port status of the second external port. If there is a discrepancy, the first chip configures the logical ports of the first chip according to the port status of the logical ports of the second chip, including: If the port status of the first mapped port is inconsistent with the port status of the first external port, the first chip configures the port status of the first mapped port according to the port status of the first external port; if the port status of the second mapped port is inconsistent with the port status of the second external port, the first chip configures the port status of the second mapped port according to the port status of the second external port.

4. The method as described in claim 2, characterized in that, The second chip also includes a logic port status register; the logic port status register is used to track the port status of the logic ports of the second chip; The first chip obtains the port status of the logic port of the second chip, including: The first chip obtains the port status of the logic port of the second chip through the logic port status register.

5. The method as described in claim 1, characterized in that, The second chip also includes a binding management register; Sending the port management information corresponding to the network card event to the second chip in the smart network card includes: Send the port management information corresponding to the network card event to the binding management register; The second chip configures its logical ports according to the port management information corresponding to the network card event, including: Through the binding management register, the second chip configures the logical port of the second chip according to the port management information corresponding to the network card event.

6. The method as described in claim 1, characterized in that, The first chip in the smart network interface card (NIC) acquires port management information, including: The first chip acquires port management information input by the user, and / or the first chip acquires port management information transmitted by the second chip.

7. The method as described in claim 6, characterized in that, The first chip acquires the port management information transmitted by the second chip, including: The first chip receives Link Convergence Control Protocol (LACP) messages forwarded by the second chip; The first chip parses the LACP message to obtain the port management information corresponding to the LACP message.

8. The method as described in claim 1, characterized in that, The method further includes: The first chip receives the Address Resolution Protocol (ARP) packets forwarded by the second chip; The first chip parses the ARP packet to obtain the address corresponding to the ARP packet; The first chip stores the address corresponding to the ARP packet.

9. A logical port management device for a smart network interface card (NIC), characterized in that, include: The first acquisition unit is used to acquire port management information; The first processing unit is configured to configure the logical ports of the first chip according to the port management information and trigger a network interface card event of type port configuration; the logical ports of the first chip are obtained by binding multiple mapped ports of the first chip. The mapped port of the first chip refers to a virtual interface that has a mapping relationship with the second chip in the smart network card; Listen for network interface card (NIC) events, and when the event type of the NIC event is port configuration, send the port management information corresponding to the NIC event to the second chip; The second processing unit is used to configure the logical port of the second chip according to the port management information corresponding to the network card event; the logical port of the second chip is obtained by binding multiple external ports of the second chip; the external port of the second chip is the physical port for the smart network card to transmit data externally; the external port of the second chip is mapped to the mapping port of the first chip.

10. A smart network interface card, characterized in that, Including the first and second chips that are connected; The first chip is used to acquire port management information; configure the logical ports of the first chip according to the port management information, and trigger a network interface card event of type port configuration; the logical ports of the first chip are obtained by binding multiple mapped ports of the first chip. The mapped port of the first chip refers to a virtual interface that has a mapping relationship with the second chip in the smart network card; Listen for network interface card (NIC) events, and when the event type of the NIC event is port configuration, send the port management information corresponding to the NIC event to the second chip; The second chip is used to configure the logical port of the second chip according to the port management information corresponding to the network card event; the logical port of the second chip is obtained by binding multiple external ports of the second chip; the external port of the second chip is the physical port for the smart network card to transmit data externally; the external port of the second chip is mapped to the mapping port of the first chip.

11. A computing device, characterized in that, It includes at least one processor and at least one memory, wherein the memory stores a computer program that, when executed by the processor, causes the processor to perform the method as claimed in any one of claims 1 to 8.

12. A computer-readable storage medium, characterized in that, The storage medium stores a program that, when run on a computer, causes the computer to perform the method as described in any one of claims 1 to 8.

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