A communication timeout processing method and apparatus, and an electronic device and a storage medium

Abstract

The application relates to a communication timeout processing method and device, electronic equipment and a storage medium. The method comprises the following steps: a control processor sends an access request to a PCIE device and records a first communication start time; a first current communication time and an initial timeout time threshold value are obtained, and whether the PCIE device is in communication timeout is determined according to the first communication start time, the first current communication time and the initial timeout time threshold value; in response to the communication timeout of the PCIE device, the initial timeout time threshold value is increased according to a timeout time increasing rule until the communication of the PCIE device is normal, and an intermediate timeout time threshold value is recorded; based on the intermediate timeout time threshold value, the control processor sends access requests to the PCIE device multiple times, and records corresponding multiple communication durations; and a final timeout time threshold value is determined according to the multiple communication durations. The method can reduce the communication timeout caused by external reasons and ensure the continuity and accuracy of communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and in particular to a communication timeout processing method and device, electronic equipment and storage medium. BACKGROUND

[0002] With the continuous development of science and technology, servers are used more and more commonly, and the number of PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) devices accessed also gradually increases. Since the external devices in the server are mostly PCIE devices except for the central processor and the memory, such as ordinary network cards, smart network cards, sound cards, and graphics cards, etc., PCIE device applications almost cover all fields of server applications, so the running status of PCIE devices is particularly important.

[0003] At present, in the case of accessing different PCIE devices, the communication scenarios of the server CPU (Central Processing Unit) and the PCIE device are various, and the communication requirements of each PCIE device and the CPU are not the same. Some PCIE devices and CPUs have large data transmission volume, so the communication time is long; some PCIE devices and CPUs have small data transmission volume, so the communication time is short, and thus the maximum timeout time of communication between the PCIE device and the CPU is different in the case of using different PCIE devices.

[0004] At present, there is a situation that the central processor and the newly introduced PCIE device are mis-triggered to alarm because of long single communication time. This situation may be caused by the actual interaction time of the newly introduced PCIE device on the one hand, and may be caused by external reasons such as electromagnetic interference and poor link signals on the other hand, resulting in the extension of the interaction time.

[0005] Therefore, it is necessary to provide a communication timeout processing method, device, electronic equipment and storage medium which can reduce the communication timeout situation caused by external reasons and ensure the continuity and accuracy of communication. SUMMARY

[0006] Therefore, it is necessary to provide a communication timeout processing method, device, electronic equipment and storage medium which can reduce the communication timeout situation caused by external reasons and ensure the continuity and accuracy of communication.

[0007] In a first aspect, a communication timeout processing method is provided, the method comprising:

[0008] The control processor sends an access request to the PCIE device and records a first communication start time, wherein the first communication start time is the sending time of the access request;

[0009] The first current communication time and the initial timeout time threshold are obtained, and whether the PCIE device is in communication timeout is determined according to the first communication start time, the first current communication time and the initial timeout time threshold;

[0010] In response to the PCIE device being in communication timeout, the initial timeout time threshold is increased according to a timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout time threshold at this time is recorded;

[0011] Based on the intermediate timeout time threshold, the control processor sends access requests to the PCIE device multiple times, and records corresponding multiple communication durations;

[0012] The final timeout time threshold of the PCIE device is determined according to the multiple communication durations.

[0013] In one of the embodiments, the first current communication time and the initial timeout time threshold are obtained, and whether the PCIE device is in communication timeout is determined according to the first communication start time, the first current communication time and the initial timeout time threshold, including:

[0014] The initial timeout time threshold is obtained, and a first communication time maximum value is calculated according to the initial timeout time threshold and the first communication start time;

[0015] The first current communication time is obtained, and the first current communication time is compared with the first communication time maximum value to obtain a time comparison result;

[0016] In response to the time comparison result indicating that the first current communication time exceeds the first communication time maximum value and the processor does not receive feedback information of the PCIE device, it is determined that the PCIE device is in communication timeout;

[0017] In response to the time comparison result indicating that the first current communication time does not exceed the first communication time maximum value and the processor receives the feedback information of the PCIE device, it is determined that the PCIE device is in normal communication.

[0018] In one of the embodiments, in response to the PCIE device being in communication timeout, the initial timeout time threshold is increased according to a timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout time threshold at this time is recorded, including:

[0019] In response to the PCIE device being in communication timeout, a first preset time period is added to the initial timeout time threshold to obtain a first timeout time threshold, wherein the value of the first preset time period is greater than 0;

[0020] the control processor re-sends the access request to the PCIE device, and records a second communication start time;

[0021] a second current communication time is obtained, and it is determined whether the PCIE device is in communication timeout according to the second communication start time, the second current communication time, and a first timeout time threshold value;

[0022] in response to the PCIE device being in normal communication, the increase of the first timeout time threshold value is stopped, and the first timeout time threshold value is recorded as an intermediate timeout time threshold value;

[0023] in response to the PCIE device being in communication timeout, a second timeout time threshold value is obtained by adding a first preset time period to the first timeout time threshold value;

[0024] the control processor re-sends the access request to the PCIE device, and records a third communication start time;

[0025] a third current communication time is obtained, and it is determined whether the PCIE device is in communication timeout according to the third communication start time, the third current communication time, and the second timeout time threshold value;

[0026] in response to the PCIE device being in normal communication, the increase of the second timeout time threshold value is stopped, and the second timeout time threshold value is recorded as the intermediate timeout time threshold value;

[0027] in response to the PCIE device being in communication timeout, the second timeout time threshold value is increased according to a timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout time threshold value at this time is recorded.

[0028] in one of the embodiments, in response to the PCIE device being in communication timeout, the initial timeout time threshold value is increased according to the timeout time increasing rule until the PCIE device is in normal communication, including:

[0029] a current cycle number and a cycle number threshold value are obtained, and the current cycle number is compared with the cycle number threshold value to obtain a number comparison result;

[0030] in response to the number comparison result indicating that the current cycle number reaches the cycle number threshold value and the PCIE device being in communication timeout, the increase of the corresponding timeout time threshold value is stopped, and a fault information of the PCIE device is returned, wherein the fault information includes location information of the PCIE device;

[0031] in response to the number comparison result indicating that the current cycle number is less than the cycle number threshold value, the corresponding timeout time threshold value is increased according to the timeout time increasing rule until the PCIE device is in normal communication.

[0032] In one of the embodiments, the final timeout threshold of the PCIE device is determined according to a plurality of communication durations, comprising:

[0033] An average value of the communication durations is calculated according to the plurality of communication durations;

[0034] The average value of the communication durations is compared with the initial timeout threshold;

[0035] In response to the average value of the communication durations being greater than the initial timeout threshold, the final timeout threshold = the average value of the communication durations + a second preset time period, wherein the value of the second preset time period is greater than 0.

[0036] In one of the embodiments, the average value of the communication durations is calculated according to a plurality of communication durations, comprising:

[0037] A first average value of the communication durations is calculated according to the plurality of communication durations;

[0038] A plurality of deviation values of the communication durations is obtained by subtracting the first average value of the communication durations from the plurality of communication durations;

[0039] A standard deviation of the communication durations is calculated according to the plurality of deviation values of the communication durations and the number of the plurality of communication durations;

[0040] The plurality of deviation values of the communication durations are compared with a preset multiple of the standard deviation of the communication durations respectively;

[0041] In response to a deviation value of the communication durations being greater than the preset multiple of the standard deviation of the communication durations, the communication duration corresponding to the deviation value is determined as abnormal data and is excluded from the plurality of communication durations;

[0042] A second average value of the communication durations is recalculated according to the plurality of communication durations after the abnormal data is excluded.

[0043] In one of the embodiments, the method further comprises:

[0044] In response to a change in the device type of the PCIE device, the processor is controlled to send an access request to the changed PCIE device and record the communication duration of the changed PCIE device;

[0045] A time difference value is obtained by subtracting the communication duration of the changed PCIE device from the final timeout threshold of the PCIE device before the change;

[0046] A time difference threshold value is obtained and the time difference value before and after the change is compared with the time difference threshold value;

[0047] In response to the time difference value before and after the change being less than or equal to the time difference threshold value, the final timeout threshold of the PCIE device before the change is determined as the final timeout threshold of the PCIE device after the change.

[0048] In a second aspect, a communication timeout processing apparatus is provided, the apparatus comprising a PCIE device information reading module, a PCIE device analyzing module, and a PCIE device processing module,

[0049] The PCIE device information reading module is configured to monitor access requests of a processor to a PCIE device, and generate access records based on request information in the access requests and save the access records to a PCIE communication information table, and place the access records to a first processing queue of the PCIE device analyzing module;

[0050] The PCIE device analyzing module is configured to read the access records in the first processing queue, and when a PCIE device communication timeout occurs, obtain communication timeout information of the PCIE device, and place the communication timeout information to a second processing queue of the PCIE device processing module, otherwise, update a communication duration of the PCIE device to the PCIE communication information table;

[0051] The PCIE device processing module is configured to read the communication timeout information in the second processing queue, and adjust an initial timeout threshold until the PCIE device communication is normal, and record the communication duration of the PCIE device at this time to the PCIE communication information table.

[0052] In a third aspect, an electronic device is provided, the electronic device comprising one or more processors; and a memory associated with the one or more processors, the memory configured to store program instructions that, when executed by the one or more processors, perform the steps of any one of the methods of the first aspect.

[0053] In a fourth aspect, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, the computer program being executed by a processor to perform the steps of any one of the methods of the first aspect.

[0054] In a fifth aspect, a computer program product is provided, the computer program product comprising a computer program, the computer program being executed by a processor to implement the steps of any one of the methods of the first aspect.

[0055] The communication timeout processing method, apparatus, electronic device, and storage medium described above reduce communication timeout situations caused by external reasons by increasing a request retransmission mechanism and dynamically adjusting a timeout threshold of a PCIE device according to a timeout time increase rule, and ensure communication continuity and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 A flowchart of a communication timeout processing method in an embodiment;

[0057] Figure 2A structural block diagram of a communication timeout processing device in an embodiment;

[0058] Figure 3 An internal structural diagram of an electronic device in an embodiment. DETAILED DESCRIPTION

[0059] For the purpose, technical solutions and advantages of the present application to be more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0060] Embodiment One

[0061] In an embodiment, as shown in Figure 1 A communication timeout processing method is provided, and the method comprises:

[0062] The control processor sends an access request to the PCIE device and records a first communication start time, wherein the first communication start time is the sending time of the access request;

[0063] The first current communication time and the initial timeout time threshold are obtained, and it is determined whether the PCIE device is in communication timeout according to the first communication start time, the first current communication time and the initial timeout time threshold;

[0064] In response to the PCIE device being in communication timeout, the initial timeout time threshold is increased according to a timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout time threshold at this time is recorded;

[0065] Based on the intermediate timeout time threshold, the control processor sends access requests to the PCIE device multiple times, and records a plurality of communication durations corresponding thereto;

[0066] The final timeout time threshold of the PCIE device is determined according to the plurality of communication durations.

[0067] Specifically, the execution subject of the control processor sending the access request to the PCIE device is a common superior system of the processor and the PCIE device, which can be a communication timeout processing system for implementing the communication timeout processing method. By increasing the request retransmission mechanism and dynamically adjusting the timeout time threshold of the PCIE device according to the timeout time increasing rule, the communication timeout situation caused by external reasons is reduced, and the communication continuity and accuracy are ensured.

[0068] In an embodiment, the first current communication time and the initial timeout time threshold are obtained, and it is determined whether the PCIE device is in communication timeout according to the first communication start time, the first current communication time and the initial timeout time threshold, which comprises:

[0069] an initial timeout threshold is obtained, and a first communication time maximum value is calculated according to the initial timeout threshold and a first communication start time;

[0070] a first current communication time is obtained, and the first current communication time is compared with the first communication time maximum value to obtain a time comparison result;

[0071] in response to the time comparison result indicating that the first current communication time exceeds the first communication time maximum value and that the processor does not receive feedback information of the PCIE device, it is determined that the PCIE device communication is timed out;

[0072] in response to the time comparison result indicating that the first current communication time does not exceed the first communication time maximum value and that the processor receives the feedback information of the PCIE device, it is determined that the PCIE device communication is normal.

[0073] Specifically, according to the time comparison result of the first current communication time and the first communication time maximum value, and whether the processor receives the feedback information of the PCIE device, it is determined whether the PCIE device communication is normal, so as to subsequently resend the access request and adjust the timeout threshold.

[0074] In one embodiment, in response to the PCIE device communication being timed out, the initial timeout threshold is increased according to a timeout time increasing rule until the PCIE device communication is normal, and an intermediate timeout threshold at this time is recorded, including:

[0075] in response to the PCIE device communication being timed out, a first preset time period is added to the initial timeout threshold to obtain a first timeout threshold, wherein a value of the first preset time period is greater than 0;

[0076] the processor is controlled to resend the access request to the PCIE device, and a second communication start time is recorded;

[0077] a second current communication time is obtained, and whether the PCIE device communication is timed out is determined according to the second communication start time, the second current communication time and the first timeout threshold;

[0078] in response to the PCIE device communication being normal, the increase of the first timeout threshold is stopped, and the first timeout threshold is recorded as the intermediate timeout threshold;

[0079] in response to the PCIE device communication being timed out, a first preset time period is added to the first timeout threshold to obtain a second timeout threshold;

[0080] the processor is controlled to resend the access request to the PCIE device, and a third communication start time is recorded;

[0081] acquire a third current communication time, and determine whether the PCIE device is in communication timeout according to the third communication start time, the third current communication time and the second timeout time threshold;

[0082] in response to the PCIE device being in normal communication, stop increasing the second timeout time threshold, and record the second timeout time threshold as an intermediate timeout time threshold;

[0083] in response to the PCIE device being in communication timeout, increase the second timeout time threshold according to the timeout time increasing rule until the PCIE device is in normal communication, and record the intermediate timeout time threshold at this time.

[0084] Specifically, the first preset time period can be set to 100 ms, or can be set according to actual conditions. By way of example of the first timeout time threshold and the second timeout time threshold, the specific content of the timeout time increasing rule is explained, which reduces the communication timeout caused by external reasons, and guarantees the continuity and accuracy of communication.

[0085] In one embodiment, in response to the PCIE device being in communication timeout, the initial timeout time threshold is increased according to the timeout time increasing rule until the PCIE device is in normal communication, including:

[0086] acquire a current cycle number and a cycle number threshold, and compare the current cycle number with the cycle number threshold to obtain a number comparison result;

[0087] in response to the number comparison result indicating that the current cycle number reaches the cycle number threshold and the PCIE device is in communication timeout, stop increasing the corresponding timeout time threshold, and return a fault information of the PCIE device, wherein the fault information includes location information of the PCIE device;

[0088] in response to the number comparison result indicating that the current cycle number is less than the cycle number threshold, increase the corresponding timeout time threshold according to the timeout time increasing rule until the PCIE device is in normal communication.

[0089] Specifically, the cycle number threshold can be set to 5 times, or can be set to an option for adjustment. By comparing the current cycle number with the cycle number threshold, it is determined whether to increase the corresponding timeout time threshold, which avoids over-adjusting the timeout time threshold to cause the communication timeout caused by external reasons to be ignored.

[0090] In one embodiment, the final timeout time threshold of the PCIE device is determined according to a plurality of communication durations, including:

[0091] calculate a communication duration average according to the plurality of communication durations;

[0092] compare the communication duration average with the initial timeout time threshold;

[0093] In response to the average of the communication durations being greater than the initial timeout time threshold, the final timeout time threshold = the average of the communication durations + a second preset time period, wherein the value of the second preset time period is greater than 0.

[0094] Specifically, the second preset time period can be set to 100 ms, or can be set according to actual conditions. By comparing the average of the communication durations with the initial timeout time threshold, the final timeout time threshold is determined, thereby improving the accuracy of determining communication timeout.

[0095] In one embodiment, the average of the communication durations is calculated according to a plurality of communication durations, comprising:

[0096] The first average of the communication durations is calculated according to a plurality of communication durations;

[0097] The plurality of communication durations is subtracted by the first average of the communication durations to obtain a plurality of communication duration deviation values corresponding thereto;

[0098] The communication duration standard deviation is calculated according to the plurality of communication duration deviation values and the number of the plurality of communication durations;

[0099] The plurality of communication duration deviation values are compared with the communication duration standard deviation multiplied by a preset multiple, respectively;

[0100] In response to the communication duration deviation value being greater than the communication duration standard deviation multiplied by the preset multiple, the communication duration corresponding to the communication duration deviation value is determined as abnormal data, and is excluded from the plurality of communication durations;

[0101] The second average of the communication durations is recalculated according to the plurality of communication durations after the abnormal data is excluded.

[0102] Specifically, the preset multiple can be set to 3, or can be set according to actual conditions. The abnormal data in the plurality of communication durations is identified and excluded, thereby ensuring the accuracy and representativeness of the second average of the communication durations.

[0103] In one embodiment, the method further comprises:

[0104] In response to the device type of the PCIE device changing, the processor is controlled to send an access request to the changed PCIE device, and the communication duration of the changed PCIE device is recorded;

[0105] The final timeout time threshold of the PCIE device before the change is subtracted by the communication duration of the PCIE device after the change to obtain a time difference value before and after the change;

[0106] The time difference value threshold is obtained, and the time difference value before and after the change is compared with the time difference value threshold;

[0107] In response to the time difference value before and after the change being less than or equal to the time difference value threshold, the final timeout time threshold of the PCIE device before the change is determined as the final timeout time threshold of the PCIE device after the change.

[0108] Specifically, the time difference value threshold can be set to 100 ms, or can be specifically set according to actual conditions. If the PCIE device is replaced after the current position, the communication duration is filled into the PCIE communication information table every fixed time (default 1 s, which can be adjusted and set), and the average value of the communication time in a period of time (default every day, which can be set and adjusted) is compared with the final timeout time threshold before the change.

[0109] In one embodiment, the method further comprises:

[0110] In response to the time difference value before and after the change being greater than the time difference value threshold, the final timeout time threshold of the PCIE device before the change is increased according to a timeout time increasing rule in a loop until the PCIE device after the change communicates normally, and an intermediate timeout time threshold of the PCIE device after the change is recorded.

[0111] Based on the intermediate timeout time threshold of the PCIE device after the change, the processor controls to send access requests to the PCIE device after the change multiple times, and records a plurality of changed communication durations corresponding thereto.

[0112] The average value of the changed communication durations is calculated according to the plurality of changed communication durations.

[0113] The average value of the changed communication durations is compared with the final timeout time threshold of the PCIE device before the change.

[0114] In response to the average value of the changed communication durations being greater than the final timeout time threshold of the PCIE device before the change, the final timeout time threshold of the PCIE device after the change = the average value of the communication durations of the PCIE device after the change + a third preset time period, wherein the value of the third preset time period is greater than 0.

[0115] Specifically, the third preset time period can be the same as the second preset time period, or can be specifically set according to actual conditions. If the PCIE device is replaced at the current position, and the time difference value before and after the change is greater than the time difference value threshold, the final timeout time threshold of the PCIE device before the change is increased according to a timeout time increasing rule in a loop until the PCIE device after the change communicates normally, and the final timeout time threshold of the PCIE device after the change is determined, thereby avoiding communication timeout caused by different communication duration requirements of the PCIE devices and the CPU.

[0116] It should be understood that, although Figure 1The steps in the flowchart are shown in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, Figure 1 At least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the sub-steps or stages is not necessarily sequential, but can be alternately executed with other steps or at least part of the sub-steps or stages of other steps.

[0117] Embodiment Two

[0118] In one embodiment, as shown in Figure 2 A communication timeout processing apparatus is provided, which includes a PCIE device information reading module, a PCIE device analysis module, and a PCIE device processing module,

[0119] The PCIE device information reading module is configured to monitor access requests of a processor to a PCIE device, and generate access records saved to a PCIE communication information table according to request information in the access requests, and place the access records into a first processing queue of the PCIE device analysis module;

[0120] The PCIE device analysis module is configured to read the access records in the first processing queue, and when the PCIE device communication is timed out, obtain communication timeout information of the PCIE device, and place the communication timeout information into a second processing queue of the PCIE device processing module, otherwise, update a communication duration of the PCIE device into the PCIE communication information table;

[0121] The PCIE device processing module is configured to read the communication timeout information in the second processing queue, and adjust an initial timeout threshold until the PCIE device communication is normal, and record the communication duration of the PCIE device at this time into the PCIE communication information table.

[0122] Specifically, (1) the PCIE device information reading module has two working scenes.

[0123] Scenario one: daily detection. After the BIOS (Basic Input Output System) boot, the CPU0, CPU1, …, on the server are traversed in turn every fixed time, and then the PCIE device information of the PE port (PE0, PE1, PE2, …) on the CPU is traversed in turn. The PCIE device information includes device identification (manufacturer number, device number), device type, and performance information (bandwidth and processing speed), etc. According to different device types, the CPU sends an access request to each PCIE device, and records the location information of the PCIE device, the request type (daily detection), and the request time in the PCIE communication information table, and places the record in the processing queue of the PCIE device analysis module.

[0124] Scenario two: PCIE device business application. When there is a business under the operating system that accesses the PCIE device (for example, application software accesses the PCIE network card and sends data to the application software on other host servers), the function module will monitor the access request of the CPU to the PCIE device (the CPU generates a signal interrupt, and the module will monitor it), and record the PCIE location information, request type (PCIE device business application), and request time in the PCIE communication information table, and place the record in the processing queue of the PCIE device analysis module.

[0125] (2) The PCIE device analysis module reads the device information in the processing queue of the module (in order to improve processing efficiency, multiple processing threads can be started, and the number of threads is 5 by default and can be adjusted). If the CPU has not received the feedback information of the PCIE device when the maximum communication time of the access request is reached, it is determined that the communication is timed out, and the communication timeout information (PCIE location information, request type, request time, and corresponding timeout time threshold) is placed in the processing queue of the PCIE device processing module. Otherwise, the communication duration of this time is updated in the PCIE communication information table.

[0126] (3) The PCIE device information processing module reads the communication timeout information in the module queue (in order to improve processing efficiency, multiple processing threads can be started, and the number of threads is 5 by default and can be adjusted). According to the timeout time increase rule, the initial timeout time threshold is increased until the PCIE device communication is normal, and the communication duration of the PCIE device at this time is recorded in the PCIE communication information table.

[0127] In addition, another function of the PCIE device information processing module is that when the current position is replaced by a PCIE device, the communication time in each record of the PCIE communication information table is compared with the final timeout threshold value at a fixed time (default every day, the time can be set) or the average value of the communication time is compared with the final timeout threshold value, whether the comparison result is within the time difference threshold value (reasonable time deviation, default 100 milliseconds, can be set) is judged, if it does not meet the requirements, the final timeout threshold value before replacement is adjusted again according to the timeout time increase rule, and after the adjustment is completed, the information in the PCIE communication information table before the change is deleted.

[0128] The specific limitations of the communication timeout processing device can be referred to the limitations of the communication timeout processing method in the foregoing, which will not be repeated here. Each module in the above communication timeout processing device can be realized by software, hardware and their combination in whole or in part. The above modules can be embedded in or independent of the processor in the electronic device in hardware form, or can be stored in the memory in the electronic device in software form, so as to be called and executed by the processor to perform the operations corresponding to each of the above modules.

[0129] Embodiment three

[0130] In one embodiment, an electronic device is provided, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0131] The processor is controlled to send an access request to the PCIE device, and a first communication start time is recorded, wherein the first communication start time is the sending time of the access request;

[0132] The first current communication time and the initial timeout threshold value are obtained, and whether the PCIE device is in communication timeout is determined according to the first communication start time, the first current communication time and the initial timeout threshold value;

[0133] In response to the communication timeout of the PCIE device, the initial timeout threshold value is increased according to the timeout time increase rule until the PCIE device communicates normally, and the intermediate timeout threshold value at this time is recorded;

[0134] Based on the intermediate timeout threshold value, the processor is controlled to send access requests to the PCIE device multiple times, and a plurality of communication durations corresponding thereto are recorded;

[0135] The final timeout threshold value of the PCIE device is determined according to the plurality of communication durations.

[0136] The program instructions, when read and executed by one or more processors, can also perform operations corresponding to each step in the above method embodiments, which can be referred to the description in the foregoing, which will not be repeated here.Figure 3 An exemplary architecture of the electronic device is shown, which can specifically include a processor 310, a video display adapter 311, a disk drive 312, an input / output interface 313, a network interface 314, and a memory 320. The processor 310, the video display adapter 311, the disk drive 312, the input / output interface 313, the network interface 314, and the memory 320 can be communicatively connected through a communication bus 330.

[0137] The processor 310 can be implemented in a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided in the present application.

[0138] The memory 320 can be implemented in a read only memory (ROM), a random access memory (RAM), a static storage device, a dynamic storage device, etc. The memory 320 can store an operating system 321 for controlling the operation of the electronic device 300, a basic input / output system (BIOS) 322 for controlling the low-level operation of the electronic device 300. In addition, a web browser 323, a data storage management 324, and an icon font processing system 325, etc. can also be stored. The icon font processing system 325 can be an application program for implementing the above-mentioned steps in the embodiments of the present application. In summary, when the technical solutions provided in the present application are implemented by software or firmware, the related program codes are stored in the memory 320 and executed by the processor 310.

[0139] The input / output interface 313 is configured to connect an input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0140] The network interface 314 is configured to connect a communication module (not shown in the figure) to realize the communication interaction between the device and other devices. The communication module can realize communication through wired means (such as USB, network cable, etc.) or through wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0141] The bus 330 includes a path that transmits information between various components of the device (e.g., the processor 310, the video display adapter 311, the disk drive 312, the input / output interface 313, the network interface 314, and the memory 320).

[0142] In addition, the electronic device 300 can also obtain information of the specific obtaining condition from the virtual resource object obtaining condition information database 341, for use in condition judgment, etc.

[0143] It should be noted that although the above electronic device 300 only shows the processor 310, the video display adapter 311, the disk drive 312, the input / output interface 313, the network interface 314, the memory 320, the bus 330, etc., in the specific implementation process, the electronic device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain the components necessary to implement the scheme of the present application, and does not have to contain all the components shown in the figure.

[0144] From the above description of the embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software and the necessary general hardware platform. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for causing an electronic device (which can be a personal computer, a cloud server, or a network device, etc.) to execute the method of each embodiment or some part of the embodiment of the present application.

[0145] Embodiment Four

[0146] In one embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0147] The control processor sends an access request to the PCIE device and records a first communication start time, wherein the first communication start time is the sending time of the access request;

[0148] The first current communication time and the initial timeout threshold are obtained, and it is determined whether the PCIE device is in communication timeout according to the first communication start time, the first current communication time, and the initial timeout threshold;

[0149] In response to the PCIE device being in communication timeout, the initial timeout threshold is increased according to the timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout threshold at this time is recorded;

[0150] Based on the intermediate timeout threshold, the control processor sends access requests to the PCIE device multiple times and records a plurality of communication durations corresponding to the access requests;

[0151] The final timeout threshold of the PCIE device is determined according to the plurality of communication durations.

[0152] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the computer program can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM) and memory bus dynamic RAM (RDRAM) and the like.

[0153] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0154] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

[0155] Embodiment five

[0156] In one embodiment, a computer program product is provided, and a computer program is stored on the computer program product. The computer program is executed by a processor to implement the following steps:

[0157] The control processor sends an access request to the PCIE device and records a first communication start time, wherein the first communication start time is the sending time of the access request;

[0158] The first current communication time and the initial timeout threshold are obtained, and it is determined whether the PCIE device is in communication timeout according to the first communication start time, the first current communication time and the initial timeout threshold;

[0159] In response to the PCIE device being in communication timeout, the initial timeout threshold is increased according to a timeout time increasing rule until the PCIE device is in normal communication, and an intermediate timeout threshold at this time is recorded;

[0160] Based on the intermediate timeout threshold, the control processor sends access requests to the PCIE device multiple times, and records corresponding multiple communication durations;

[0161] The final timeout threshold of the PCIE device is determined according to the multiple communication durations.

[0162] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the computer program can be stored in a computer program product. When the computer program is executed, it can include the processes of the above-mentioned embodiment methods.

[0163] The technical features of the above-mentioned embodiments can be combined in any way. In order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.

[0164] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A communication timeout processing method, characterized in that: The method comprises: Control the processor to send an access request to the PCIE device and record a first communication start time, wherein the first communication start time is the sending time of the access request; Obtaining a first current communication time and an initial timeout threshold, and determining whether the PCIE device has timed out of communication according to the first communication start time, the first current communication time, and the initial timeout threshold; In response to the PCIE device communication timeout, cyclically increasing the initial timeout threshold according to a timeout increase rule until the PCIE device communicates normally, and recording the intermediate timeout threshold at this time; Based on the intermediate timeout threshold, controlling the processor to send access requests to the PCIE device multiple times, and recording corresponding multiple communication durations; A final timeout threshold of the PCIE device is determined according to the multiple communication durations.

2. The method according to claim 1, characterized in that Obtaining a first current communication time and an initial timeout threshold, and determining whether the PCIE device has timed out of communication according to the first communication start time, the first current communication time, and the initial timeout threshold, including: Obtaining the initial timeout threshold, and calculating a first communication time maximum value based on the initial timeout threshold and the first communication start time; Obtaining a first current communication time, and comparing the first current communication time with a first communication time maximum value to obtain a time comparison result; In response to the time comparison result indicating that the first current communication time exceeds a first communication time maximum value, and the processor does not receive feedback information from the PCIE device, determining that the PCIE device communication has timed out; In response to the time comparison result indicating that the first current communication time does not exceed the first maximum communication time, and the processor receiving feedback information from the PCIE device, it is determined that the PCIE device is communicating normally.

3. The method according to claim 1, characterized in that In response to the PCIE device communication timeout, cyclically increasing the initial timeout threshold according to the timeout increase rule until the PCIE device communication is normal, and recording the intermediate timeout threshold at this time, including: In response to the PCIE device communication timeout, adding a first preset time period to the initial timeout threshold to obtain a first timeout threshold, wherein the value of the first preset time period is greater than 0; Control the processor to resend the access request to the PCIE device and record the second communication start time; Obtain a second current communication time, and determine whether the PCIE device has timed out according to the second communication start time, the second current communication time, and the first timeout threshold; In response to the PCIE device communicating normally, stopping increasing the first timeout threshold, and recording the first timeout threshold as the intermediate timeout threshold; In response to a communication timeout of the PCIE device, adding the first preset time period to the first timeout threshold to obtain a second timeout threshold; Control the processor to resend the access request to the PCIE device and record the start time of the third communication; Obtain a third current communication time, and determine whether the PCIE device has timed out in communication according to the third communication start time, the third current communication time, and a second timeout threshold; In response to the PCIE device communicating normally, stopping increasing the second timeout threshold, and recording the second timeout threshold as the intermediate timeout threshold; In response to the PCIE device communication timeout, the second timeout threshold is cyclically increased according to the timeout increase rule until the PCIE device communicates normally, and the intermediate timeout threshold at this time is recorded.

4. The method according to claim 1, characterized in that In response to the PCIE device communication timeout, cyclically increasing the initial timeout threshold according to a timeout increase rule until the PCIE device communicates normally, including: Obtaining a current cycle number and a cycle number threshold, and comparing the current cycle number with the cycle number threshold to obtain a number comparison result; In response to the comparison result indicating that the current cycle count reaches the cycle count threshold and the communication of the PCIE device times out, stopping increasing the corresponding timeout threshold and returning fault information of the PCIE device, wherein the fault information includes location information of the PCIE device; In response to the comparison result indicating that the current cycle number is less than the cycle number threshold, the corresponding timeout threshold is cyclically increased according to a timeout increase rule until the PCIE device communicates normally.

5. The method according to claim 1, characterized in that: Determining a final timeout threshold of the PCIE device according to the multiple communication durations includes: Calculating an average communication duration based on the multiple communication durations; Comparing the average communication duration with an initial timeout threshold; In response to the average communication duration being greater than the initial timeout threshold, the final timeout threshold=the average communication duration+a second preset time period, wherein the value of the second preset time period is greater than 0.

6. The method according to claim 5, characterized in that Calculating an average communication duration based on the multiple communication durations includes: Calculating a first communication duration average value based on the multiple communication durations; Subtracting the first communication duration average from the multiple communication durations to obtain corresponding multiple communication duration deviation values; Calculating a communication duration standard deviation based on the multiple communication duration deviation values ​​and the number of communication durations; Comparing the plurality of communication duration deviation values ​​with a preset multiple of the communication duration standard deviation respectively; In response to the communication duration deviation value being greater than a preset multiple of the communication duration standard deviation, determining the communication duration corresponding to the communication duration deviation value as abnormal data and removing it from the plurality of communication durations; The second communication duration average is recalculated based on the multiple communication durations after the abnormal data are removed.

7. The method according to claim 1, characterized in that The method further comprises: In response to a change in the device type of the PCIE device, controlling the processor to send an access request to the changed PCIE device and recording a communication duration of the changed PCIE device; Subtract the communication duration of the PCIE device after the change from the final timeout threshold of the PCIE device before the change to obtain the time difference before and after the change; Obtaining a time difference threshold, and comparing the time difference before and after the change with the time difference threshold; In response to the time difference before and after the change being less than or equal to the time difference threshold, the final timeout threshold of the PCIE device before the change is determined as the final timeout threshold of the PCIE device after the change.

8. A communication timeout processing device, characterized in that: The device includes a PCIE device information reading module, a PCIE device analysis module and a PCIE device processing module. The PCIE device information reading module is used to monitor the processor's access request to the PCIE device, generate an access record stored in the PCIE communication information table according to the request information in the access request, and place the access record in the first processing queue of the PCIE device analysis module; The PCIE device analysis module is configured to read the access records in the first processing queue, and when the communication of the PCIE device times out, obtain the communication timeout information of the PCIE device, and place the communication timeout information into the second processing queue of the PCIE device processing module; otherwise, update the communication duration of the PCIE device into the PCIE communication information table; The PCIE device processing module is used to read the communication timeout information in the second processing queue, adjust the initial timeout threshold until the PCIE device communicates normally, and record the communication duration of the PCIE device at this time in the PCIE communication information table.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images