Semiconductor structure and method of manufacturing the same, memory

Abstract

The application provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a lower group of conductive layers and an upper group of conductive layers located above the lower group of conductive layers, the two groups of conductive layers have the same number of layers, each conductive layer has a common connection region and a memory cell region located at least one side of the common connection region; a plurality of through holes arranged in the common connection region and spaced along the extension direction of the common connection region, the through holes penetrate the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers; a plurality of conductive columns, each conductive column is arranged in each through hole one by one, each conductive column comprises a lower conductive segment and an upper conductive segment separated by an insulating segment, each lower conductive segment is electrically connected to the lower group of conductive layers one by one, and each upper conductive segment is electrically connected to the upper group of conductive layers one by one. The application realizes that the shared bit line or the shared word line can be connected to the devices located below and above the memory cell array at the same time.

Description

Technical Field

[0001] This application relates to, but is not limited to, semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] As 3D memory increases storage density through multi-layer stacking, the number of sense amplifiers (SAs) and sub-word line drivers (SWDs) in the peripheral circuitry also increases accordingly. Currently, in co-line memory device structures, a large number of SAs need to be placed on bonding chips. However, with the increase in the number of 3D stacking layers, the number of SAs also increases, placing higher demands on the placement and integration density of SAs and SWDs on the bonding chips. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] In one aspect, an exemplary embodiment of this application provides a semiconductor structure, including:

[0005] The lower conductive layer comprises a plurality of conductive layers stacked at vertical intervals;

[0006] An upper conductive layer is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals. The upper conductive layer and the lower conductive layer have the same number of layers. Each conductive layer has a common connection area and a memory cell area located on at least one side of the common connection area.

[0007] Multiple through holes are disposed in the common connection area and spaced apart along the extension direction of the common connection area. The through holes penetrate the upper conductive layer and the lower conductive layer, and the number of through holes is equal to the number of layers in the lower conductive layer.

[0008] Multiple conductive pillars are disposed in each of the through holes. Each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment. Each lower conductive segment is electrically connected to each conductive layer in the lower group of conductive layers, and each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers.

[0009] In an exemplary embodiment, the system further includes a plurality of lower insulating rings and a plurality of upper insulating rings. Each of the lower insulating rings is disposed in a corresponding via and surrounds a corresponding lower conductive segment. The height of each lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment. Each of the upper insulating rings is disposed in a corresponding via and surrounds a corresponding upper conductive segment. The end of each upper insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

[0010] In an exemplary embodiment, along the extension direction of the common connection area, the height of the lower conductive segment in each of the through holes gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in each of the through holes gradually decreases, while the height of the upper conductive segment gradually increases.

[0011] In an exemplary embodiment, the distance between adjacent vias is the same along the extension direction of the common connection area.

[0012] On the other hand, exemplary embodiments of this application provide a memory comprising:

[0013] A substrate on which multiple first devices are disposed;

[0014] The lower conductive layer is located above the substrate and includes a plurality of conductive layers stacked at vertical intervals.

[0015] An upper conductive layer is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals. The upper conductive layer and the lower conductive layer have the same number of conductive layers. Each conductive layer has a common connection area and a memory cell area located on at least one side of the common connection area.

[0016] A bonding chip is located above the upper conductive layer and has multiple second devices disposed thereon;

[0017] Multiple through holes are disposed in the common connection area and spaced apart along the extension direction of the common connection area. The through holes penetrate the multiple conductive layers, and the number of through holes is equal to the number of layers in the lower group of conductive layers.

[0018] Multiple conductive pillars are disposed one-to-one within each of the vias. Each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment. The end of each lower conductive segment away from the substrate is electrically connected to each conductive layer in the lower conductive layer group, and the end closer to the substrate is electrically connected to each of the first devices. The end of each upper conductive segment away from the bonding chip is electrically connected to each conductive layer in the upper conductive layer group, and the end closer to the bonding chip is electrically connected to each of the second devices.

[0019] In an exemplary embodiment, the common connection area is a shared bit line area and both the first device and the second device are sense amplifiers, or the common connection area is a shared word line area and both the first device and the second device are sub-word line drivers.

[0020] In an exemplary embodiment, the system further includes a plurality of lower insulating rings and a plurality of upper insulating rings. Each lower insulating ring is disposed in a corresponding via and surrounds a corresponding lower conductive segment. The height of each lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment. Each upper insulating ring is disposed in a corresponding via and surrounds a corresponding upper conductive segment. The end of each upper insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer. The height of the lower conductive segment is greater than the height of the conductive layer it is electrically connected to and less than the height of the next conductive layer adjacent to the electrically connected conductive layer. The end of the upper conductive segment near the substrate is located between the conductive layer it is electrically connected to and the adjacent next conductive layer.

[0021] In another aspect, exemplary embodiments of this application provide a method for manufacturing a semiconductor structure, comprising:

[0022] A stacked structure is formed on a substrate, the stacked structure including a lower sacrificial layer and an upper sacrificial layer above the lower sacrificial layer. The lower sacrificial layer includes a plurality of sacrificial layers stacked vertically at intervals, and the upper sacrificial layer includes a plurality of sacrificial layers stacked vertically at intervals. The upper sacrificial layer and the lower sacrificial layer have the same number of layers. Each sacrificial layer has a preset common connection area and a preset memory cell area located on at least one side of the preset common connection area.

[0023] Multiple through holes are formed at intervals in the preset common connection area and along the extension direction of the preset common connection area. The through holes penetrate the stacked structure, and the number of through holes is equal to the number of layers of the lower sacrificial layer.

[0024] Conductive pillars and insulating rings surrounding the conductive pillars are formed within each through hole;

[0025] The stacked structure is patterned such that the preset common connection area forms a common connection area and the preset storage unit area forms a storage unit area.

[0026] The material of each of the sacrificial layers is replaced with a conductive material to form the corresponding lower conductive layer and upper conductive layer;

[0027] Conductive pillars and insulating rings of different heights are formed in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers.

[0028] The insulating segment is formed above each of the lower conductive segments;

[0029] Conductive pillars and insulating rings of different heights are formed on the insulating segment to form each upper conductive segment and each upper insulating ring, and each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers.

[0030] In an exemplary implementation,

[0031] The method of forming conductive pillars and insulating rings of different heights within each through-hole to form lower conductive segments and lower insulating rings, wherein each lower conductive segment is electrically connected to each conductive layer in the lower group of conductive layers in a one-to-one correspondence, includes:

[0032] An insulating thin film is deposited on the inner sidewall and bottom surface of each of the through holes;

[0033] Remove the insulating film from the bottom surface of the through hole to form an insulating ring located on the inner sidewall of the through hole;

[0034] Conductive material is deposited within each of the aforementioned through-holes to form conductive pillars;

[0035] Remove part of the material of the insulating ring and the conductive post in the through hole to the same height, so that the height of the insulating ring and the conductive post in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and higher than the height of the next layer of conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form a groove of different height in each through hole;

[0036] Deposit conductive material into each empty slot until each slot is filled;

[0037] Remove a portion of the conductive material from each of the empty slots, such that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers.

[0038] In an exemplary implementation,

[0039] The process of forming conductive pillars and insulating rings of different heights on the insulating segment to form upper conductive segments and upper insulating rings, wherein each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers in a one-to-one correspondence, includes:

[0040] An insulating film is deposited above the insulating segment within each of the vias, and the insulating film at the top of each of the insulating segments is removed to form each of the upper insulating rings; wherein the end of each insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

[0041] Remove a portion of the insulating segment within each of the vias, such that the end of each insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0042] Conductive material is deposited in each of the empty slots to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers.

[0043] This application forms lower conductive segment structures of different heights on the substrate side near the bottom of the memory array within a via structure located in the common connection area of ​​the memory array. Each lower conductive segment structure is electrically connected to a corresponding lower conductive layer of the memory array. Simultaneously, upper conductive segment structures of different heights are formed on the chip side near the top of the memory array. Each upper conductive segment structure is electrically connected to a corresponding upper conductive layer of the memory array. This allows for downward connection to devices located on the substrate below the memory array (such as a sense amplifier SA or a sub-word line driver SWD) and upward connection to devices on the bonded chip above the memory array (such as a sensor). The measurement amplifier (SA) or sub-word line driver (SWD) can also connect memory cells located on both sides of the common connection area, thereby enabling multiple SA and SWD devices to be placed in a distributed manner and allowing these devices to be placed more evenly on the chip below the memory array or on the bonding chip above the memory array, relieving the pressure on the bonding chip and significantly reducing the manufacturing difficulty and process cost of 3D devices; or it can also rationally allocate the number of peripheral devices placed on the chip below the memory array or on the bonding chip above the memory array as needed, making the manufacturing process more flexible and enhancing the design flexibility and adaptability of 3D device products.

[0044] The semiconductor structure provided in this application is particularly suitable for the device structure of planar channel ring (PCAA) DRAM.

[0045] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0046] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0047] Figure 1A A three-dimensional schematic diagram of a semiconductor structure provided for an exemplary embodiment of this application;

[0048] Figure 1B for Figure 1A A schematic diagram of a vertical cross-section of the structure shown, taken along a plane parallel to the first direction;

[0049] Figure 2 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0050] Figure 3AA schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a sacrificial layer.

[0051] Figure 3B for Figure 3A The diagram shows a vertical cross-section of the intermediate product taken along a plane parallel to the first direction.

[0052] Figure 4 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0053] Figure 5 A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a sacrificial layer.

[0054] Figure 6A A schematic diagram of a horizontal cross-section along a conductive layer of an intermediate product obtained from an intermediate step in a method for manufacturing a semiconductor structure, as provided in an exemplary embodiment of this application.

[0055] Figure 6B for Figure 6A The diagram shows a vertical cross-section of the intermediate product taken along a plane parallel to the first direction.

[0056] Figure 7 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0057] Figure 8 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0058] Figure 9 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0059] Figure 10 A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0060] Figure 11A schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0061] Figure 12 A schematic diagram of a vertical cross-section taken along a plane parallel to a first direction, representing an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method according to an exemplary embodiment of this application; and

[0062] Figure 13 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0064] The embodiments described herein can be implemented in many different forms. Those skilled in the art will readily understand that the implementation methods and content can be varied in many ways without departing from the spirit and scope of this application. Therefore, this application should not be construed as limited to the contents described in the following embodiments. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

[0065] The scale of the figures in this application can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The figures described in this application are only schematic diagrams of the structure, and the approach of this application is not limited to the shapes or values ​​shown in the figures.

[0066] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as needed.

[0067] In this specification, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0068] In the description of this application, ordinal numbers such as "first" and "second" are used to avoid confusion of constituent elements, rather than to limit the quantity.

[0069] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may sometimes be replaced with "metal film".

[0070] Sensing amplifiers (SAs) are typically coupled to columns of memory cells (e.g., bit lines) to detect the current or voltage flowing through the memory cells as part of a read operation. A large number of SAs are placed on bonding chips, and the number of SAs increases with the number of stacked layers, placing higher demands on the placement and integration density of SAs and SWDs on the bonding chips. However, the inventors of this application discovered that shunting the SAs to increase the integration density of memory cells, i.e., placing the SAs below the transistor array, would place the bit lines above the SAs, thus making it impossible to connect the SAs to the bit lines.

[0071] Therefore, this application provides a semiconductor structure including a lower conductive layer comprising a plurality of vertically spaced conductive layers; an upper conductive layer located above the lower conductive layer and comprising a plurality of vertically spaced conductive layers, wherein the upper conductive layer and the lower conductive layer have the same number of layers, each conductive layer having a common connection region and a memory cell region located on at least one side of the common connection region; a plurality of vias disposed in the common connection region and spaced apart along the extension direction of the common connection region, the vias penetrating the upper conductive layer and the lower conductive layer, the number of vias being equal to the number of layers in the lower conductive layer; and a plurality of conductive pillars, each conductive pillar being disposed one-to-one in each of the vias, each conductive pillar comprising a lower conductive segment and an upper conductive segment separated by an insulating segment, each lower conductive segment being electrically connected to each conductive layer in the lower conductive layer, and each upper conductive segment being electrically connected to each conductive layer in the upper conductive layer.

[0072] The semiconductor structure provided by the exemplary embodiments of this application may include a lower conductive layer and an upper conductive layer located above the lower conductive layer. Each conductive layer may include a plurality of conductive layers stacked vertically at intervals, and the upper conductive layer and the lower conductive layer have the same number of layers.

[0073] As used in this application, the term "first direction" X is defined as a direction parallel to the via arrangement direction; the term "second direction" Y is defined as intersecting the first direction X; and the term "third direction" Z is defined as a direction perpendicular to the plane containing the substrate. The plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, "second direction" Y, and "third direction" Z can be defined as follows: Figure 1A As shown in the figure.

[0074] Figure 1A A three-dimensional schematic diagram of a semiconductor structure provided for an exemplary embodiment of this application; Figure 1B for Figure 1A The diagram shows a vertical cross-section of the structure taken along a plane parallel to the first direction. (See diagram below.) Figure 1A and 1B As shown, the lower conductive layer may include a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64, and a fifth lower conductive layer 65, for a total of 5 layers. The upper conductive layer may include a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74, and a fifth upper conductive layer 75, for a total of 5 layers. That is, the lower conductive layer and the upper conductive layer have the same number of layers.

[0075] Each conductive layer may have a common bit line extending along a first direction X and at least two memory cells located on both sides of the common bit line and extending along a second direction Y. For 1T1C and 2T0C memory cells, the drain of each memory cell may be connected to the common bit line.

[0076] Continue to refer to Figure 1B The semiconductor structure provided in this application may include five vias arranged sequentially in a common bit line region along the extension direction of the common connection region, each via penetrating the lower conductive layer and the upper conductive layer. The number of vias is the same as the number of the lower conductive layer and the upper conductive layer.

[0077] Each through-hole may include a conductive post and an insulating ring. Figure 1B The diagram shows that the first through hole may include a first lower conductive segment 21, a first insulating segment 31, and a first upper conductive segment 41; the second through hole may include a second lower conductive segment 22, a second insulating segment 32, and a second upper conductive segment 42; the third through hole may include a third lower conductive segment 23, a third insulating segment 33, and a third upper conductive segment 43; the fourth through hole may include a fourth lower conductive segment 24, a fourth insulating segment 34, and a fourth upper conductive segment 44; and the fifth through hole may include a fifth lower conductive segment 25, a fifth insulating segment 35, and a fifth upper conductive segment 45.

[0078] Figure 1BIt is also shown that the first lower conductive segment 21 is electrically connected only to the first lower conductive layer 61; the second lower conductive segment 22 is electrically connected only to the second lower conductive layer 62; the third lower conductive segment 23 is electrically connected only to the third lower conductive layer 63; the fourth lower conductive segment 24 is electrically connected only to the fourth lower conductive layer 64; and the fifth lower conductive segment 25 is electrically connected only to the fifth lower conductive layer 65. That is, the lower conductive segment in each through hole is electrically connected only to one lower conductive layer and electrically insulated from other lower conductive layers through their respective lower insulating rings.

[0079] Figure 1B It is also shown that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71, the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72, the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73, the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74, and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75. That is, the upper conductive segment in each through hole is electrically connected only to one upper conductive layer and electrically insulated from other upper conductive layers through their respective upper insulating rings.

[0080] Figure 1B It is also shown that the height of the first lower conductive segment 21 is greater than the height of the first conductive layer 61 to which it is electrically connected and less than the height of the upper conductive layer 62 adjacent to the electrically connected conductive layer 61; the height of the second lower conductive segment 22 is greater than the height of the second conductive layer 62 to which it is electrically connected and less than the height of the upper conductive layer 63 adjacent to the electrically connected conductive layer 62; the height of the third lower conductive segment 23 is greater than the height of the third conductive layer 63 to which it is electrically connected and less than the height of the upper conductive layer 64 adjacent to the electrically connected conductive layer 63; the height of the fourth lower conductive segment 24 is greater than the height of the fourth conductive layer 64 to which it is electrically connected and less than the height of the upper conductive layer 65 adjacent to the electrically connected conductive layer 64; and the height of the fifth lower conductive segment 25 is greater than the height of the fifth conductive layer 65 to which it is electrically connected and greater than the height of the first upper conductive layer 71.

[0081] Using the bonded chip as the height reference plane, Figure 1BIt also shows that the height of the first upper conductive segment 41 is greater than the height of the upper conductive layer 71 to which it is electrically connected and less than the height of the next lower conductive layer 65 adjacent to the upper conductive layer 71 to which it is electrically connected; the height of the second upper conductive segment 42 is greater than the height of the upper conductive layer 72 to which it is electrically connected and less than the height of the next upper conductive layer 71 adjacent to the upper conductive layer 72 to which it is electrically connected; the height of the third upper conductive segment 43 is greater than the height of the upper conductive layer 73 to which it is electrically connected and less than the height of the next upper conductive layer 72 adjacent to the upper conductive layer 73 to which it is electrically connected; the height of the fourth upper conductive segment 44 is greater than the height of the upper conductive layer 74 to which it is electrically connected and less than the height of the next upper conductive layer 73 adjacent to the upper conductive layer 74 to which it is electrically connected; and the height of the fifth upper conductive segment 45 is greater than the height of the upper conductive layer 75 to which it is electrically connected and less than the height of the next upper conductive layer 74 adjacent to the upper conductive layer 75 to which it is electrically connected.

[0082] As used in this application, when referring to lower conductive segments and lower insulating rings, the term "height" refers to the distance from the upper surface of the substrate to the side of each lower conductive segment away from the substrate and the side of each lower insulating ring away from the substrate. When referring to upper conductive segments and upper insulating rings, the term "height" refers to the distance from the upper surface of the stacked structure (i.e., the side where the bonding chip is located) to the side of each upper conductive segment and the side of each upper insulating ring near the substrate.

[0083] Figure 1B It is also shown that, along the first direction X, the height of the first lower conductive segment to the fifth lower conductive segment gradually increases, while the height of the first upper conductive segment to the fifth upper conductive segment gradually decreases. However, in other exemplary embodiments, along the first direction X, the height of the first lower conductive segment to the fifth lower conductive segment may gradually decrease, while the height of the first upper conductive segment to the fifth upper conductive segment may gradually increase.

[0084] In an exemplary embodiment, the common connection area may be a shared bit line area or a shared word line area.

[0085] In an exemplary embodiment, the storage unit may be a 1T1C storage unit, a 2T0C storage unit, or a 2T1C storage unit.

[0086] Therefore, this application is particularly suitable for connecting the common bit lines of each layer of a three-dimensional memory to both the device below the three-dimensional memory (such as a memory chip) and the corresponding sensing amplifier in the device above the three-dimensional memory (such as a bonding chip).

[0087] The technical solution of this application will be further described below through the manufacturing process of a semiconductor structure according to an exemplary embodiment of this application. The "patterning process" mentioned in this exemplary embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this exemplary embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film made by depositing or coating a certain material on a substrate. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0088] The manufacturing method of this application will be illustrated below by taking the manufacturing process of a semiconductor structure for connecting the bit lines of a three-dimensional memory to a sense amplifier (SA) disposed below and above the bit lines as an example.

[0089] This exemplary manufacturing method may include the following steps:

[0090] S100: A stacked structure is formed on a substrate, the stacked structure comprising, from bottom to top, a first lower insulating layer and a first lower sacrificial layer; a second lower insulating layer and a second lower sacrificial layer; ...; an nth lower insulating layer and an nth lower sacrificial layer; an isolation insulating layer; a first upper insulating layer and a first upper sacrificial layer; a second upper insulating layer and a second upper sacrificial layer; ...; and an nth upper insulating layer and an nth upper sacrificial layer, where n is a positive integer; the stacked structure has a preset common connection region and a preset memory cell region located on at least one side of the preset common connection region.

[0091] An exemplary step may include: alternately depositing insulating layer films and sacrificial layer films on a substrate 2 to form a stacked structure 1, the stacked structure 1 comprising, from bottom to top, a first lower insulating layer 101 and a first lower sacrificial layer 121, a second lower insulating layer 102 and a second lower sacrificial layer 122, a third lower insulating layer 103 and a third lower sacrificial layer 123, a fourth lower insulating layer 104 and a fourth lower sacrificial layer 124, a fifth lower insulating layer 105 and a fifth lower sacrificial layer 125, and an isolation layer... The stacked structure 1 comprises an upper insulating layer 106, a first upper insulating layer 107 and a first upper sacrificial layer 126, a second upper insulating layer 108 and a second upper sacrificial layer 127, a third upper insulating layer 109 and a third upper sacrificial layer 128, a fourth upper insulating layer 110 and a fourth upper sacrificial layer 129, and a fifth upper insulating layer 111 and a fifth upper sacrificial layer 130; the stacked structure 1 has a preset common bit line region 100 and preset memory cell regions 200 and 300 located on both sides of the preset common bit line region 100, such as... Figure 2 As shown. Figure 2 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0092] In an exemplary embodiment, methods such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, and atomic layer deposition (ALD) can be used to deposit the insulating layer film and the sacrificial layer film.

[0093] In an exemplary embodiment, each insulating layer may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO2), which facilitates large-area deposition.

[0094] In an exemplary embodiment, each sacrificial layer may be made of a nitride material, such as silicon nitride (SiN).

[0095] S200: Forms a through hole.

[0096] An exemplary step may include: forming five equally spaced vias, namely via K1, via K2, via K3, via K4, and via K5, along the extension direction Y of the preset common bit line region 100 by photolithography etching. The number of vias is the same as the number of layers in the subsequently formed upper or lower conductive layer. Figure 3A and 3B As shown. Figure 3A A schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a sacrificial layer. Figure 3B for Figure 3A The diagram shows a vertical cross-section of the intermediate product taken along a plane parallel to the first direction.

[0097] In an exemplary embodiment, the orthographic projection of each through hole onto a plane parallel to the substrate 2 can be circular, elliptical, square, rectangular, or other shapes.

[0098] S300: Forms conductive pillars and insulating rings.

[0099] Exemplary steps may include: depositing an insulating film around the inner wall and bottom of each via using atomic layer deposition (ALD); anisotropically etching the insulating layer at the bottom while retaining only the insulating layer on the inner wall of the via; continuing to deposit metal within each via using ALD; and finally flushing the upper surface of the stacked structure using CMP to form five conductive pillars 10 and five insulating rings 20, as shown. Figure 4 As shown. Figure 4 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0100] In an exemplary embodiment, each conductive post may be made of a metallic material such as tungsten.

[0101] In an exemplary embodiment, each insulating ring may be made of materials such as HfO2 or Al2O3.

[0102] S400: A patterned stacked structure is formed in the preset common bit line region, with one second sub-stacked structure extending along a second direction, and multiple first sub-stacked structures extending along a first direction and terminating at the second sub-stacked structure are formed in the preset memory cell region, wherein the multiple first sub-stacked structures are spaced apart in the second direction.

[0103] An exemplary step may include: forming a second sub-stacked structure 1000 extending along a second direction Y in the preset common bit line region 100 by photolithography etching of the stacked structure; and forming a plurality of first sub-stacked structures 2000 and 3000 extending along a first direction X and terminating at the second sub-stacked structure 1000 in the preset memory cell regions 200 and 300, wherein the plurality of first sub-stacked structures 2000 and 3000 are spaced apart in the second direction Y, as shown below. Figure 5 As shown. Figure 5 This is a schematic diagram of a horizontal cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided as an exemplary embodiment of this application, taken along a sacrificial layer.

[0104] S500: Replace the material of each sacrificial layer in the stacked structure with a conductive material to form n conductive layers, so as to form the memory cell area of ​​each layer in the first sub-stacked structure and the common bit line area of ​​each layer in the second sub-stacked structure;

[0105] Exemplary steps may include: forming multiple grooves by etching away each sacrificial layer; depositing a conductive metal material into the multiple grooves; etching away the metal on the sidewalls of the insulating layer, leaving only the metal between adjacent insulating layers, thus replacing the sacrificial layer material and forming 10 conductive layers, namely, a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64, a fifth lower conductive layer 65; a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74, and a fifth upper conductive layer 75, as shown. Figure 6A and 6B As shown. Figure 6A A schematic diagram of a horizontal cross-section along a conductive layer of an intermediate product obtained from an intermediate step in a method for manufacturing a semiconductor structure, as provided in an exemplary embodiment of this application. Figure 6B for Figure 6A The diagram shows a vertical cross-section of the intermediate product taken along a plane parallel to the first direction.

[0106] S600: Remove a portion of each of the conductive posts and each insulating ring.

[0107] Exemplary steps may include: removing a portion of the material from the conductive pillars and insulating rings by etching, so that the conductive pillars and insulating rings in each through-hole have the same height, but the conductive pillars and insulating rings in different through-holes have different heights, with the heights of the conductive pillars and insulating rings in through-holes K1 to K5 gradually increasing, and the upper part of the conductive pillars and insulating rings in each through-hole being empty, such as... Figure 7 As shown. Figure 7 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0108] S700: An exemplary step may include: depositing the same material as the conductive pillars into each via using an ALD process, and then flushing the upper surface of the stacked structure using a CMP process, such as... Figure 8 As shown. Figure 8 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0109] S800: Forms each lower insulating ring and each lower conductive segment.

[0110] Exemplary steps may include: etching the conductive pillars within each through-hole to different heights using a staircase process, such that the first lower insulating ring 11 in through-hole K1 has a height T1 and the first lower conductive segment 21 has a height H1; and so on, the second lower insulating ring 12 in through-hole K2 has a height T2 and the second lower conductive segment 22 has a height H2; the third lower insulating ring 13 in through-hole K3 has a height T3 and the third lower conductive segment 23 has a height H3; the fourth lower insulating ring 14 in through-hole K4 has a height T4 and the fourth lower conductive segment 24 has a height H4; and the fifth lower insulating ring 15 in through-hole K5 has a height T5 and the fifth lower conductive segment 25 has a height H5, as shown. Figure 9 As shown. Figure 9 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0111] Figure 9 The diagram shows that heights H1 to H5 gradually increase, and heights T1 to T5 gradually increase. However, in other exemplary embodiments, heights H1 to H5 may also gradually decrease, and heights T1 to T5 may also gradually decrease; or, height H3 may be the largest, gradually decreasing towards both sides, i.e., H3 to H1 and H3 to H5 gradually decrease; similarly, T3 to T1 and T3 to T5 gradually decrease.

[0112] Figure 9 It is also shown that the first lower conductive segment 21 is electrically connected only to the first lower conductive layer 61, the second lower conductive segment 22 is electrically connected only to the second lower conductive layer 62, the third lower conductive segment 23 is electrically connected only to the third lower conductive layer 63, the fourth lower conductive segment 24 is electrically connected only to the fourth lower conductive layer 64, and the fifth lower conductive segment 25 is electrically connected only to the fifth lower conductive layer 65. That is, the lower conductive segment in each via is electrically connected only to one lower conductive layer and electrically insulated from other lower conductive layers through their respective lower insulating rings. This enables each layer to share a bit line and be electrically connected to the corresponding sensing amplifier below.

[0113] S900: An exemplary step may include: depositing an insulating material film to fill each via, and then using a CMP process to flush the upper surface of the laminated structure, such as... Figure 10 As shown. Figure 10 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0114] In an exemplary embodiment, the insulating materials may be materials such as HfO2 or Al2O3.

[0115] S1000: Forms each insulation section.

[0116] Exemplary steps may include: using a step process to etch the insulating layer within each through-hole to different depths, forming a first insulating segment 31, a second insulating segment 32, a third insulating segment 33, a fourth insulating segment 34, and a fifth insulating segment 35, such as... Figure 11 As shown. Figure 11 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0117] S1100: Form each upper insulating ring.

[0118] Exemplary steps may include: depositing an insulating film around the inner wall and bottom of each of the vias using an ALD method; anisotropically etching the insulating layer at the bottom while retaining only the insulating layer on the inner wall of the via; etching the insulating layer to expose the metal cross-section to be connected, forming a first upper insulating ring 51, a second upper insulating ring 52, a third upper insulating ring 53, a fourth upper insulating ring 54, and a fifth upper insulating ring 55, as shown. Figure 12 As shown. Figure 12 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0119] S1200: Forms each upper conductive segment.

[0120] An exemplary step may include: continuing to deposit conductive metal material on the exposed metal cross-sections within each through-hole in the aforementioned steps, and using a CMP process to flush the upper surface of the stacked structure, forming a first upper conductive segment 41, a second upper conductive segment 42, a third upper conductive segment 43, a fourth upper conductive segment 44, and a fifth upper conductive segment 45, as shown. Figure 13 As shown. Figure 13 This is a schematic diagram of a vertical cross-section of an intermediate product obtained from an intermediate step in a semiconductor structure manufacturing method provided by an exemplary embodiment of this application, taken along a plane parallel to a first direction.

[0121] Figure 13 It is shown that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71, the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72, the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73, the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74, and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75. That is, the upper conductive segment in each via is electrically connected only to one upper conductive layer and electrically insulated from other upper conductive layers through their respective upper insulating rings. This enables the shared bit line of each layer to be electrically connected to the corresponding sensing amplifier above the bit line.

[0122] The method of this application enables the common bit line in the memory cell array to be connected to both devices located below the memory cell array, such as the SA on the memory array chip, and devices located above the memory cell array, such as the SA in the bonding chip.

[0123] An exemplary embodiment of this application also provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0124] S1000: A stacked structure is formed on a substrate, the stacked structure including a lower sacrificial layer and an upper sacrificial layer above the lower sacrificial layer, the lower sacrificial layer including a plurality of sacrificial layers stacked vertically at intervals, the upper sacrificial layer including a plurality of sacrificial layers stacked vertically at intervals, the upper sacrificial layer and the lower sacrificial layer having the same number of layers, each sacrificial layer having a preset common connection area and a preset memory cell area located on at least one side of the preset common connection area;

[0125] S1100: A plurality of through holes are formed in the preset common connection area and along the extension direction of the preset common connection area, the through holes penetrating the stacked structure, and the number of through holes is equal to the number of layers of the lower group of sacrificial layers;

[0126] S1200: A conductive post and an insulating ring surrounding the conductive post are formed in each through hole;

[0127] S1300: Pattern the stacked structure so that the preset common connection area forms a common connection area and the preset storage unit area forms a storage unit area;

[0128] S1400: Replace the material of each of the sacrificial layers with a conductive material to form a corresponding lower conductive layer and an upper conductive layer;

[0129] S1500: Conductive pillars and insulating rings of different heights are formed in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers.

[0130] S1600: The insulating segment is formed above each of the lower conductive segments;

[0131] S1700: Conductive pillars and insulating rings of different heights are formed on the insulating segment to form each upper conductive segment and each upper insulating ring, and each upper conductive segment is electrically connected to each of the conductive layers in the upper group of conductive layers.

[0132] In an exemplary implementation, step S1500 may include:

[0133] S1510: Deposit an insulating thin film on the inner sidewall and bottom surface of each of the through holes;

[0134] S1520: Remove the insulating film from the bottom surface of the through hole to form an insulating ring located on the inner wall of the through hole;

[0135] S1530: Deposit conductive material within each of the aforementioned through holes to form conductive pillars;

[0136] S1540: Remove part of the material of the insulating ring and the conductive post in the through hole to the same height, so that the height of the insulating ring and the conductive post in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and higher than the height of the next layer of conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form a groove of different height in each through hole;

[0137] S1550: Deposit conductive material into each empty slot until each empty slot is filled;

[0138] S1560: Remove a portion of the conductive material in each of the empty slots, such that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers.

[0139] In an exemplary implementation, step S1700 may include:

[0140] S1710: An insulating film is deposited over the insulating segment within each of the vias, and the insulating film at the top of each of the insulating segments is removed to form each of the upper insulating rings; wherein one end of each insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

[0141] S1720: Remove a portion of the insulating segment within each of the vias, such that the end of each insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0142] S1730: Deposit conductive material in each of the empty slots to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers.

[0143] Exemplary embodiments of this application also provide a memory, including:

[0144] A substrate on which multiple first devices are disposed;

[0145] The lower conductive layer is located above the substrate and includes a plurality of conductive layers stacked at vertical intervals.

[0146] An upper conductive layer is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals. The upper conductive layer and the lower conductive layer have the same number of conductive layers. Each conductive layer has a common connection area and a memory cell area located on at least one side of the common connection area.

[0147] A bonding chip is located above the upper conductive layer and has multiple second devices disposed thereon;

[0148] Multiple through holes are disposed in the common connection area and spaced apart along the extension direction of the common connection area. The through holes penetrate the multiple conductive layers, and the number of through holes is equal to the number of layers in the lower group of conductive layers.

[0149] Multiple conductive pillars are disposed one-to-one within each of the vias. Each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment. The end of each lower conductive segment away from the substrate is electrically connected to each conductive layer in the lower conductive layer group, and the end closer to the substrate is electrically connected to each of the first devices. The end of each upper conductive segment away from the bonding chip is electrically connected to each conductive layer in the upper conductive layer group, and the end closer to the bonding chip is electrically connected to each of the second devices.

[0150] In an exemplary embodiment, the common connection area is a shared bit line area and both the first device and the second device are sense amplifiers, or the common connection area is a shared word line area and both the first device and the second device are sub-word line drivers.

[0151] In an exemplary embodiment, the memory further includes a plurality of lower insulating rings and a plurality of upper insulating rings. Each lower insulating ring is disposed in each of the vias and surrounds the corresponding lower conductive segment. The height of each lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment. Each upper insulating ring is disposed in each of the vias and surrounds the corresponding upper conductive segment. The end of each upper insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer. The height of the lower conductive segment is greater than the height of the conductive layer it is electrically connected to and less than the height of the next conductive layer adjacent to the electrically connected conductive layer. The end of the upper conductive segment near the substrate is located between the conductive layer it is electrically connected to and the adjacent next conductive layer.

[0152] Although the embodiments disclosed in this application are as described above, the content is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The lower conductive layer is located above the substrate and includes a plurality of conductive layers stacked at vertical intervals. An upper conductive layer is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals. The upper conductive layer and the lower conductive layer have the same number of layers. Each conductive layer has a common connection area and a memory cell area located on at least one side of the common connection area. Multiple through holes are disposed in the common connection area and spaced apart along the extension direction of the common connection area. The through holes penetrate the upper conductive layer and the lower conductive layer, and the number of through holes is equal to the number of layers in the lower conductive layer. Multiple conductive pillars are disposed in each of the through holes. Each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment. Each lower conductive segment is electrically connected to each conductive layer in the lower group of conductive layers, and each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers.

2. The semiconductor structure according to claim 1, characterized in that, It also includes multiple lower insulating rings and multiple upper insulating rings. Each lower insulating ring is disposed in each of the vias and surrounds the corresponding lower conductive segment. The height of each lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment. Each upper insulating ring is disposed in each of the vias and surrounds the corresponding upper conductive segment. The end of each upper insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

3. The semiconductor structure according to claim 1, characterized in that, Along the extension direction of the common connection area, the height of the lower conductive segment in each of the through holes gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in each of the through holes gradually decreases, while the height of the upper conductive segment gradually increases.

4. The semiconductor structure according to claim 1, characterized in that, Along the extension direction of the common connection area, the distance between adjacent through holes is the same.

5. A memory, characterized in that, include: A substrate on which multiple first devices are disposed; The lower conductive layer is located above the substrate and includes a plurality of conductive layers stacked at vertical intervals. An upper conductive layer is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals. The upper conductive layer and the lower conductive layer have the same number of conductive layers. Each conductive layer has a common connection area and a memory cell area located on at least one side of the common connection area. A bonding chip is located above the upper conductive layer and has multiple second devices disposed thereon; Multiple through holes are disposed in the common connection area and spaced apart along the extension direction of the common connection area. The through holes penetrate the multiple conductive layers, and the number of through holes is equal to the number of layers in the lower group of conductive layers. Multiple conductive pillars are disposed one-to-one within each of the vias. Each conductive pillar includes a lower conductive segment and an upper conductive segment separated by an insulating segment. The end of each lower conductive segment away from the substrate is electrically connected to each conductive layer in the lower conductive layer group, and the end closer to the substrate is electrically connected to each of the first devices. The end of each upper conductive segment away from the bonding chip is electrically connected to each conductive layer in the upper conductive layer group, and the end closer to the bonding chip is electrically connected to each of the second devices.

6. The memory according to claim 5, characterized in that, The common connection area is a shared bit line area and both the first device and the second device are sense amplifiers, or the common connection area is a shared word line area and both the first device and the second device are sub-word line drivers.

7. The memory according to claim 5, characterized in that, It also includes multiple lower insulating rings and multiple upper insulating rings. Each lower insulating ring is correspondingly disposed in each of the through holes and surrounds the corresponding lower conductive segment. The height of each lower insulating ring is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment. Each upper insulating ring is correspondingly disposed in each of the through holes and surrounds the corresponding upper conductive segment. The end of each upper insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer. The height of each lower conductive segment is greater than the height of the conductive layer it is electrically connected to and less than the height of the next conductive layer adjacent to the electrically connected conductive layer. The end of each upper conductive segment near the substrate is located between the conductive layer it is electrically connected to and the adjacent next conductive layer.

8. A method for manufacturing a semiconductor structure, characterized in that, include: A stacked structure is formed on a substrate, the stacked structure including a lower sacrificial layer and an upper sacrificial layer above the lower sacrificial layer. The lower sacrificial layer includes a plurality of sacrificial layers stacked vertically at intervals, and the upper sacrificial layer includes a plurality of sacrificial layers stacked vertically at intervals. The upper sacrificial layer and the lower sacrificial layer have the same number of layers. Each sacrificial layer has a preset common connection area and a preset memory cell area located on at least one side of the preset common connection area. Multiple through holes are formed at intervals in the preset common connection area and along the extension direction of the preset common connection area. The through holes penetrate the stacked structure, and the number of through holes is equal to the number of layers of the lower sacrificial layer. Conductive pillars and insulating rings surrounding the conductive pillars are formed within each through hole; The stacked structure is patterned such that the preset common connection area forms a common connection area and the preset storage unit area forms a storage unit area. The material of each of the sacrificial layers is replaced with a conductive material to form the corresponding lower conductive layer and upper conductive layer; Conductive pillars and insulating rings of different heights are formed in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers. An insulating section is formed above each of the lower conductive sections; Conductive pillars and insulating rings of different heights are formed on the insulating segment to form each upper conductive segment and each upper insulating ring, and each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers in a one-to-one correspondence.

9. The manufacturing method according to claim 8, characterized in that, The method of forming conductive pillars and insulating rings of different heights within each through-hole to form lower conductive segments and lower insulating rings, wherein each lower conductive segment is electrically connected to each conductive layer in the lower group of conductive layers in a one-to-one correspondence, includes: An insulating thin film is deposited on the inner sidewall and bottom surface of each of the through holes; Remove the insulating film from the bottom surface of the through hole to form an insulating ring located on the inner sidewall of the through hole; Conductive material is deposited within each of the aforementioned through-holes to form conductive pillars; Remove part of the material of the insulating ring and the conductive post in the through hole to the same height, so that the height of the insulating ring and the conductive post in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and higher than the height of the next layer of conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form a groove of different height in each through hole; Deposit conductive material into each empty slot until each slot is filled; Remove a portion of the conductive material from each of the empty slots, such that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers.

10. The manufacturing method according to claim 9, characterized in that, The process of forming conductive pillars and insulating rings of different heights on the insulating segment to form upper conductive segments and upper insulating rings, wherein each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers in a one-to-one correspondence, includes: An insulating film is deposited above the insulating segment within each of the vias, and the insulating film at the top of each of the insulating segments is removed to form each of the upper insulating rings; wherein the end of each insulating ring near the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer. Remove a portion of the insulating segment within each of the vias, such that the end of each insulating segment away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer; Conductive material is deposited in each of the empty slots to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers.

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