Semiconductor memory device

Abstract

The invention provides a semiconductor memory device. The present invention is provided with: a substrate; a first via wiring extending in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring; a memory unit arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged in the first direction and facing the plurality of first semiconductor layers; a plurality of first wirings arranged in the first direction and extending in a second direction intersecting the first direction, the plurality of first wirings being electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of second gate electrodes arranged in the first direction and facing the plurality of second semiconductor layers; a second via wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and a plurality of second wirings arranged in the first direction and extending in a third direction intersecting the first direction and the second direction, the second wirings being electrically connected to the second semiconductor layers.

Description

Technical Field

[0001] This embodiment relates to a semiconductor storage device. Background Art

[0002] As semiconductor memory devices become more highly integrated, research into making semiconductor memory devices three-dimensional is underway.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0399340

[0006] Patent Document 2: U.S. Patent Application Publication No. 2022 / 0352169

[0007] Patent Document 3: Japanese Patent Application Publication No. 2022-147872 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Provided is a semiconductor memory device that operates well.

[0010] Technical solutions to solve problems

[0011] A semiconductor storage device involved in one embodiment comprises: a substrate; a first via wiring extending in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring; a storage portion arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged in the first direction and opposite to the plurality of first semiconductor layers; a plurality of first wirings arranged in the first direction and extending in a second direction intersecting the first direction, and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of second gate electrodes arranged in the first direction and opposite to the plurality of second semiconductor layers; a second via wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and a plurality of second wirings arranged in the first direction and extending in a third direction intersecting the first and second directions, and electrically connected to the plurality of second semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic circuit diagram showing a partial structure of the semiconductor memory device according to the first embodiment.

[0013] Figure 2 This is a schematic circuit diagram for explaining the read operation of the semiconductor memory device.

[0014] Figure 3 This is a schematic perspective view showing a part of the structure of the semiconductor memory device.

[0015] Figure 4 This is a schematic perspective view showing a part of the structure of the semiconductor memory device.

[0016] Figure 5 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device.

[0017] Figure 6 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device.

[0018] Figure 7 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device.

[0019] Figure 8 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device.

[0020] Fig. 9 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device.

[0021] Fig.10 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device.

[0022] Fig.11 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device.

[0023] Fig.12 It is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor memory device.

[0024] Fig.13 It is a schematic cross-sectional view for explaining the manufacturing method.

[0025] Fig.14 It is a schematic cross-sectional view for explaining the manufacturing method.

[0026] Fig.15 It is a schematic cross-sectional view for explaining the manufacturing method.

[0027] Fig.16 It is a schematic cross-sectional view for explaining the manufacturing method.

[0028] Fig.17 It is a schematic cross-sectional view for explaining the manufacturing method.

[0029] Fig.18 It is a schematic cross-sectional view for explaining the manufacturing method.

[0030] Fig.19 It is a schematic cross-sectional view for explaining the manufacturing method.

[0031] Fig. 20 It is a schematic cross-sectional view for explaining the manufacturing method.

[0032] Fig.21 It is a schematic cross-sectional view for explaining the manufacturing method.

[0033] Fig. 22 It is a schematic cross-sectional view for explaining the manufacturing method.

[0034] Fig.23 It is a schematic cross-sectional view for explaining the manufacturing method.

[0035] Fig.24 It is a schematic cross-sectional view for explaining the manufacturing method.

[0036] Fig.25 It is a schematic cross-sectional view for explaining the manufacturing method.

[0037] Fig.26 It is a schematic cross-sectional view for explaining the manufacturing method.

[0038] Fig. 27 It is a schematic cross-sectional view for explaining the manufacturing method.

[0039] Fig.28 It is a schematic cross-sectional view for explaining the manufacturing method.

[0040] Fig.29 It is a schematic cross-sectional view for explaining the manufacturing method.

[0041] Fig.30 It is a schematic cross-sectional view for explaining the manufacturing method.

[0042] Fig.31 It is a schematic cross-sectional view for explaining the manufacturing method.

[0043] Fig.32 It is a schematic cross-sectional view for explaining the manufacturing method.

[0044] Fig.33 It is a schematic cross-sectional view for explaining the manufacturing method.

[0045] Fig.34 It is a schematic cross-sectional view for explaining the manufacturing method.

[0046] Fig.35 It is a schematic cross-sectional view for explaining the manufacturing method.

[0047] Fig.36It is a schematic cross-sectional view for explaining the manufacturing method.

[0048] Fig.37 It is a schematic cross-sectional view for explaining the manufacturing method.

[0049] Fig.38 It is a schematic cross-sectional view for explaining the manufacturing method.

[0050] Fig.39 It is a schematic cross-sectional view for explaining the manufacturing method.

[0051] Fig.40 It is a schematic cross-sectional view for explaining the manufacturing method.

[0052] Fig.41 It is a schematic cross-sectional view for explaining the manufacturing method.

[0053] Fig.42 It is a schematic cross-sectional view for explaining the manufacturing method.

[0054] Fig.43 It is a schematic cross-sectional view for explaining the manufacturing method.

[0055] Fig.44 It is a schematic cross-sectional view for explaining the manufacturing method.

[0056] Fig.45 It is a schematic cross-sectional view for explaining the manufacturing method.

[0057] Fig.46 It is a schematic cross-sectional view for explaining the manufacturing method.

[0058] Fig.47 It is a schematic cross-sectional view for explaining the manufacturing method.

[0059] Fig.48 It is a schematic cross-sectional view for explaining the manufacturing method.

[0060] Fig.49 It is a schematic cross-sectional view for explaining the manufacturing method.

[0061] Fig.50 It is a schematic cross-sectional view for explaining the manufacturing method.

[0062] Fig.51 It is a schematic cross-sectional view for explaining the manufacturing method.

[0063] Fig.52 It is a schematic cross-sectional view for explaining the manufacturing method.

[0064] Fig.53 It is a schematic cross-sectional view for explaining the manufacturing method.

[0065] Fig.54 It is a schematic cross-sectional view for explaining the manufacturing method.

[0066] Fig.55 It is a schematic cross-sectional view for explaining the manufacturing method.

[0067] Fig.56 It is a schematic cross-sectional view for explaining the manufacturing method.

[0068] Fig.57 It is a schematic cross-sectional view for explaining the manufacturing method.

[0069] Fig.58 It is a schematic cross-sectional view for explaining the manufacturing method.

[0070] Fig.59 It is a schematic cross-sectional view for explaining the manufacturing method.

[0071] Fig.60 It is a schematic cross-sectional view for explaining the manufacturing method.

[0072] Fig.61 It is a schematic cross-sectional view for explaining the manufacturing method.

[0073] Fig.62 It is a schematic cross-sectional view for explaining the manufacturing method.

[0074] Fig.63 It is a schematic cross-sectional view for explaining the manufacturing method.

[0075] Fig.64 It is a schematic cross-sectional view for explaining the manufacturing method.

[0076] Fig.65 It is a schematic cross-sectional view for explaining the manufacturing method.

[0077] Fig.66 It is a schematic cross-sectional view for explaining the manufacturing method.

[0078] Fig.67 It is a schematic cross-sectional view for explaining the manufacturing method.

[0079] Fig.68 It is a schematic cross-sectional view for explaining the manufacturing method.

[0080] Fig.69 It is a schematic cross-sectional view for explaining the manufacturing method.

[0081] Fig.70 It is a schematic cross-sectional view for explaining the manufacturing method.

[0082] Fig.71It is a schematic cross-sectional view for explaining the manufacturing method.

[0083] Fig.72 It is a schematic cross-sectional view for explaining the manufacturing method.

[0084] Fig.73 It is a schematic cross-sectional view for explaining the manufacturing method.

[0085] Fig.74 It is a schematic cross-sectional view for explaining the manufacturing method.

[0086] Fig.75 It is a schematic cross-sectional view for explaining the manufacturing method.

[0087] Fig.76 It is a schematic cross-sectional view for explaining the manufacturing method.

[0088] Fig.77 It is a schematic cross-sectional view for explaining the manufacturing method.

[0089] Fig.78 It is a schematic cross-sectional view for explaining the manufacturing method.

[0090] Fig.79 It is a schematic cross-sectional view for explaining the manufacturing method.

[0091] Fig.80 It is a schematic cross-sectional view for explaining the manufacturing method.

[0092] Fig.81 It is a schematic cross-sectional view for explaining the manufacturing method.

[0093] Fig.82 It is a schematic cross-sectional view for explaining the manufacturing method.

[0094] Fig.83 It is a schematic cross-sectional view for explaining the manufacturing method.

[0095] Fig.84 It is a schematic cross-sectional view for explaining the manufacturing method.

[0096] Fig.85 It is a schematic cross-sectional view for explaining the manufacturing method.

[0097] Fig.86 It is a schematic cross-sectional view for explaining the manufacturing method.

[0098] Fig.87 It is a schematic cross-sectional view for explaining the manufacturing method.

[0099] Fig.88 It is a schematic cross-sectional view for explaining the manufacturing method.

[0100] Fig.89 It is a schematic cross-sectional view for explaining the manufacturing method.

[0101] Fig.90 It is a schematic cross-sectional view for explaining the manufacturing method.

[0102] Fig.91 It is a schematic cross-sectional view for explaining the manufacturing method.

[0103] Fig.92 It is a schematic cross-sectional view for explaining the manufacturing method.

[0104] Fig.93 It is a schematic cross-sectional view for explaining the manufacturing method.

[0105] Fig.94 It is a schematic cross-sectional view for explaining the manufacturing method.

[0106] Fig.95 It is a schematic cross-sectional view for explaining the manufacturing method.

[0107] Fig.96 It is a schematic cross-sectional view for explaining the manufacturing method.

[0108] Fig.97 It is a schematic cross-sectional view for explaining the manufacturing method.

[0109] Fig.98 It is a schematic cross-sectional view for explaining the manufacturing method.

[0110] Fig.99 It is a schematic cross-sectional view for explaining the manufacturing method.

[0111] Fig.100 It is a schematic cross-sectional view for explaining the manufacturing method.

[0112] Fig.101 It is a schematic cross-sectional view for explaining the manufacturing method.

[0113] Fig.102 It is a schematic cross-sectional view for explaining the manufacturing method.

[0114] Fig.103 It is a schematic cross-sectional view for explaining the manufacturing method.

[0115] Fig.104 It is a schematic cross-sectional view for explaining the manufacturing method.

[0116] Fig.105 It is a schematic cross-sectional view for explaining the manufacturing method.

[0117] Fig.106It is a schematic cross-sectional view for explaining the manufacturing method.

[0118] Fig.107 It is a schematic cross-sectional view for explaining the manufacturing method.

[0119] Fig.108 It is a schematic cross-sectional view for explaining the manufacturing method.

[0120] Fig.109 It is a schematic cross-sectional view for explaining the manufacturing method.

[0121] Fig.110 It is a schematic cross-sectional view for explaining the manufacturing method.

[0122] Fig.111 It is a schematic cross-sectional view for explaining the manufacturing method.

[0123] Fig.112 It is a schematic cross-sectional view for explaining the manufacturing method.

[0124] Fig.113 It is a schematic cross-sectional view for explaining the manufacturing method.

[0125] Fig.114 It is a schematic cross-sectional view for explaining the manufacturing method.

[0126] Fig.115 It is a schematic cross-sectional view for explaining the manufacturing method.

[0127] Fig.116 It is a schematic cross-sectional view for explaining the manufacturing method.

[0128] Fig.117 It is a schematic cross-sectional view for explaining the manufacturing method.

[0129] Fig.118 It is a schematic cross-sectional view for explaining the manufacturing method.

[0130] Fig.119 It is a schematic cross-sectional view for explaining the manufacturing method.

[0131] Fig.120 It is a schematic cross-sectional view for explaining the manufacturing method.

[0132] Fig.121 It is a schematic cross-sectional view for explaining the manufacturing method.

[0133] Fig.122 It is a schematic cross-sectional view for explaining the manufacturing method.

[0134] Fig.123 is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to a comparative example.

[0135] Fig.124 It is a schematic circuit diagram for explaining a read operation of a semiconductor memory device according to a comparative example.

[0136] Fig.125 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the second embodiment.

[0137] Fig.126 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the second embodiment.

[0138] Fig.127 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to the second embodiment.

[0139] Fig.128 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0140] Fig.129 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0141] Fig.130 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0142] Fig.131 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0143] Fig.132 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0144] Fig.133 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0145] Fig.134 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0146] Fig.135 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0147] Fig.136 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0148] Fig.137It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0149] Fig.138 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0150] Fig.139 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0151] Fig.140 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0152] Fig.141 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0153] Fig.142 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0154] Fig.143 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment.

[0155] Fig.144 This is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to the third embodiment.

[0156] Fig.145 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the third embodiment.

[0157] Fig.146 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a third embodiment.

[0158] Fig.147 This is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0159] Fig.148 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the fourth embodiment.

[0160] Fig.149 This is a schematic cross-sectional view showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0161] Description of Reference Numerals

[0162] Sub…semiconductor substrate, ML…storage layer, BL…bit line, WL…word line, PL…plate line, TrC, TrR…transistor, CpC…capacitor, 101…insulating layer, 102…conductive layer, 104, 204…via wiring, 110, 210…transistor structure, 111, 213…semiconductor layer, 112, 214…insulating layer, 113, 215…conductive layer, 120, 501…conductive layer, 130…capacitor structure. DETAILED DESCRIPTION

[0163] Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example and is not intended to limit the present invention. In addition, the following drawings are schematic, and for the sake of convenience of description, a part of the structure is sometimes omitted. In addition, the same figure mark is sometimes marked on the parts common to multiple embodiments, and the description is omitted.

[0164] In addition, when the term "semiconductor storage device" is used in this specification, it may mean a storage die (bare chip), or a storage system including a control die such as a storage chip, a memory card, or an SSD (Solid State Drive). In addition, it may mean a configuration including a host computer such as a smartphone, a tablet terminal, or a personal computer.

[0165] In addition, in this specification, when it is expressed that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the cut-off (OFF) state.

[0166] In addition, in this specification, when it is expressed that the first structure is "electrically connected to" the second structure and the third structure "between", it may mean that the first structure, the second structure and the third structure are connected in series and the second structure is electrically connected to the third structure via the first structure.

[0167] In addition, in this specification, when it is stated that a circuit or the like makes two wirings or the like "conduct", it may mean that, for example, the circuit or the like includes a transistor or the like, the transistor or the like is provided in a current path between the two wirings, and the transistor or the like becomes in a conducting (ON) state.

[0168] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0169] In addition, in this specification, a direction along a predetermined surface is sometimes referred to as a first direction, a direction along the predetermined surface and intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the predetermined surface is sometimes referred to as a third direction. The first direction, the second direction, and the third direction may correspond to any of the X direction, the Y direction, and the Z direction, or may not correspond to any of them.

[0170] In addition, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the above-mentioned Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when a certain structure is expressed as a lower surface or lower end, it means the surface or end of the substrate side of the structure, and when it is expressed as an upper surface or upper end, it means the surface or end of the structure on the opposite side of the substrate. In addition, the surface intersecting the X direction or the Y direction is called a side surface, etc.

[0171] In the present specification, when the term "center position" of a certain structure is expressed, it may mean, for example, the position of the center of the circumscribed circle of the structure or the center of gravity of the image of the structure on a predetermined surface.

[0172] [First embodiment]

[0173] [Circuit Configuration]

[0174] Figure 1 1 is a schematic circuit diagram showing a part of the structure of the semiconductor memory device according to the first embodiment. Figure 1 As shown, the semiconductor memory device involved in this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML3 (hereinafter, sometimes referred to as "memory layers ML"), a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL, and plate lines PL connected to the plurality of memory layers ML0 to ML3.

[0175] Each of the memory layers ML0 to ML3 includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to the bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. In addition, one electrode and the other electrode of the transistor TrC function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to any one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to the plate line PL.

[0176] Each bit line BL is connected to a plurality of memory cells MC corresponding to the plurality of memory layers ML0 to ML3 . Each bit line BL is connected to a global bit line GBL.

[0177] In addition, the storage layers ML0 to ML3 respectively include a plurality of transistors TrR0a, TrR0b, TrR1a, TrR1b, TrR2a, TrR2b, TrR3a, TrR3b (hereinafter sometimes referred to as "transistor TrR") provided corresponding to the plurality of word lines WL0 to WL2. One electrode of the transistor TrR is connected to any one of the word lines WL0 to WL2. The other electrode of the transistor TrR is respectively connected to the layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, LL3b (hereinafter sometimes referred to as "layer selection line LL"). In addition, one electrode and the other electrode of the transistor TrR function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrR. Gate electrodes of the transistor TrR are connected to word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter, sometimes referred to as “word line selection lines LW”), respectively.

[0178] In addition, the word line selection line LW is connected to a plurality of transistors TrR corresponding to a plurality of storage layers ML0 to ML3. In addition, the layer selection lines LL0a, LL1a, LL2a, and LL3a are respectively connected to all transistors TrR0a, TrR1a, TrR2a, and TrR3a corresponding to the storage layers ML0 to ML3. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are respectively connected to all transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to the storage layers ML0 to ML3.

[0179] [Reading action]

[0180] Figure 2This is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the first embodiment.

[0181] In the read operation, one of the plurality of memory layers ML0 to ML3 is selected. In the example shown in the figure, the memory layer ML0 is selected. When the memory layers ML0 to ML3 are selected, for example, a voltage V is supplied to the layer selection line LL0a corresponding to the memory layer ML0 to be the target of the read operation, among the plurality of layer selection lines LL0a, LL1a, LL2a, and LL3a. ON , supply voltage V to other layer selection lines LL1a, LL2a, LL3a OFF In addition, for example, a voltage V is supplied to a plurality of layer selection lines LL0b, LL1b, LL2b, and LL3b. OFF .

[0182] Voltage V ON For example, the voltage V is large enough to turn on the transistor TrC. OFF For example, the voltage V is large enough to set the transistor TrC to the OFF state. For example, when the transistor TrC is an NMOS transistor, the voltage V ON Specific voltage V OFF In addition, for example, when the transistor TrC is a PMOS transistor, the voltage V ON Specific voltage V OFF Small.

[0183] In addition, during the read operation, one of the plurality of word lines WL0 to WL2 is selected. In the example shown in the figure, word line WL0 is selected. When word lines WL0 to WL2 are selected, for example, a voltage V is supplied to a word line selection line LW0a corresponding to the word line WL0 to be read out of the plurality of word line selection lines LW0a, LW1a, and LW2a. ON ', supply voltage V to other layer selection lines LW1a and LW2a OFF '. In addition, a voltage V is supplied to a word line selection line LW0a corresponding to the word line WL0 to be read out among the plurality of word line selection lines LW0b, LW1b, and LW2b. OFF ', supply voltage V to other layer selection lines LW1a and LW2a ON ′.

[0184] Voltage V ON ' has a magnitude, for example, large enough to turn on the transistor TrR. OFF ' has a magnitude, for example, large enough to turn off the transistor TrR. For example, when the transistor TrR is an NMOS transistor, the voltage V ON 'Ratio voltage V OFF' is large. In addition, for example, in the case where the transistor TrR is a PMOS transistor, the voltage V ON 'Ratio voltage V OFF 'Small.

[0185] Here, a voltage V is supplied to a word line WL0 (hereinafter referred to as “selected word line WL0”) connected to a memory cell MC to be read (hereinafter referred to as “selected memory cell MC”) via a transistor TrR0a. ON As a result, the transistor TrC in the selected memory cell MC becomes conductive. As a result, the voltage of the global bit line GBL changes, or a current flows through the global bit line GBL. By detecting the voltage change or current, the data stored in the selected memory cell MC can be read.

[0186] Furthermore, the voltage V is supplied to the unselected word line WL0 corresponding to the memory layer ML1, ML2, ML3 different from the selected memory cell MC via the transistors TrR1a, TrR2a, TrR3a. OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0187] In addition, the voltage V is supplied to the non-selected word lines WL1 and WL2 corresponding to the memory layers ML0, ML1, ML2, and ML3 via the transistors TrR connected to the word line selection lines LW1b and LW2b. OFF As a result, the transistor TrC in the memory cell MC is turned off.

[0188] In addition, in the following description, an example is shown in which both the transistors TrC and TrR are NMOS transistors.

[0189] [structure]

[0190] Figure 3 This is a schematic perspective view showing a partial structure of the semiconductor memory device according to the first embodiment. Figure 4 is a schematic perspective view showing a part of the structure of the semiconductor storage device, showing an enlarged Figure 3 part of. Figure 5 1 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device. Figure 6 , Figure 8 as well as Fig.10 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device, and shows Figure 5 part of. Figure 7 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Figure 6 The structure shown is a structure cut along line AA′ and observed in the direction of the arrow. Fig. 9 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Figure 8 The structure shown is a structure cut along line BB′ and observed in the direction of the arrow. Fig.11 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.10 The structure shown is a structure cut along the CC' line and observed in the direction of the arrow.

[0191] Figure 3 A portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub are shown.

[0192] The semiconductor substrate Sub is, for example, a semiconductor substrate of silicon (Si) or the like containing P-type impurities such as boron (B). An insulating layer and an electrode layer, not shown, are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer, not shown, and the electrode layer constitute a peripheral circuit for controlling the semiconductor storage device involved in the first embodiment. For example, a sense amplifier circuit is provided in an area directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the global bit line GBL. In a read operation, the sense amplifier circuit can read the data stored in the selected memory cell MC by detecting the change in the voltage or current of the bit line BL. In addition, the peripheral circuit has a sequencer that supplies a predetermined voltage to each wiring in the memory cell array MCA and each structure in the sense amplifier circuit at a predetermined timing, thereby performing a read operation, etc.

[0193] The memory cell array MCA includes a plurality of memory layers ML arranged in the Z direction. In addition, an insulating layer 103 made of silicon oxide (SiO 2 ) or the like is provided between the plurality of memory layers ML.

[0194] like Figure 5 As shown, the memory cell array MCA is provided with: a memory cell region R MC , relative to the memory cell region R MC The transistor region R is provided on one side in the Y direction. TrR , and relative to the transistor region R TrR The wiring area R provided on one side in the Y direction LL In addition, the memory cell array MCA is provided with: MC With transistor area R TrR The connection wiring area R CL1 , and are arranged in the transistor region R TrR With wiring area R LL The connection wiring area R CL2Although not shown in the figure, the transistor region R TrR , Wiring area R LL , connection wiring area R CL1 and the connection wiring area R CL2 The Y direction is arranged in the memory cell region R MC on both sides.

[0195] [Memory cell area R MC Structure of

[0196] like Figure 5 As shown, in the storage unit area R MC A plurality of insulating layers 101 are arranged in the X direction, and a conductive layer 102 is provided between two insulating layers 101 adjacent to each other in the X direction. The insulating layer 101 and the conductive layer 102 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction.

[0197] The insulating layer 101 contains, for example, silicon oxide (SiO 2 ) or the like.

[0198] The conductive layer 102 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 102 is, for example, a plate line PL ( Figure 1 ) to perform its function.

[0199] In addition, in the memory cell region R MC In the region between the insulating layer 101 and the conductive layer 102, a plurality of via wirings 104 arranged in the Y direction are provided. Figure 3 As shown, each of the plurality of storage layers ML extends in the Z direction.

[0200] like Figure 4 As shown, the via wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b of titanium nitride (TiN) or the like, and a conductive member 104c of tungsten (W) or the like. In addition, the via wiring 104 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide film 104a. In addition, the via wiring 104 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0201] In this specification, the "conductive oxide" is assumed to include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), or other conductive materials containing oxygen.

[0202] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 104b. The via wiring 104 is, for example, a bit line BL ( Figure 1 ) to perform its function.

[0203] For example, Figure 5 As shown, the storage layer ML includes: a conductive layer 120 arranged between the insulating layer 101 and a plurality of via wirings 104 and extending in the Y direction, a plurality of transistor structures 110 arranged in the Y direction corresponding to the plurality of via wirings 104, and a plurality of capacitor structures 130 arranged between the conductive layer 102 and the plurality of transistor structures 110 and arranged in the Y direction corresponding to the plurality of via wirings 104.

[0204] For example, Figure 4 As shown, the transistor structure 110 includes: a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction; an insulating layer 112 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the semiconductor layer 111; and a conductive layer 113 arranged on the upper surface, the lower surface, the two side surfaces in the Y direction, and the side surface on one side in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0205] exist Figure 6 In the XY cross section as illustrated, the two side surfaces in the X direction of the semiconductor layer 111 can be formed along a circle centered on the center position of the via wiring 104. In addition, the side surfaces of the insulating layer 112 and the conductive layer 113 on one side in the X direction (the conductive layer 120 side) can also be formed along a circle centered on the center position of the via wiring 104. In addition, the two side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 can be formed in a straight line along the side surface of the insulating layer 115.

[0206] In addition, the two side surfaces in the X direction of the semiconductor layer 111 may not be formed along a circle. Even in such a case, for example, the two side surfaces in the X direction of the semiconductor layer 111 may be curved lines when viewed from the Z direction. For example, the length in the X direction of the semiconductor layer 111 may be different depending on the position in the Y direction. For example, the length in the X direction of the semiconductor layer 111 at a position close to the insulating layer 115 may be shorter than the length in the X direction of the semiconductor layer 111 at a position far from the insulating layer 115.

[0207] The semiconductor layer 111 serves as a transistor TrC ( Figure 1) function in the channel region. The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn) and oxygen (O), or other oxide semiconductors. The plurality of semiconductor layers 111 arranged in the Z direction are commonly connected to the via wiring 104 extending in the Z direction.

[0208] The insulating layer 112 serves as, for example, a transistor TrC ( Figure 1 ) functions as a gate insulating film. The insulating layer 112 contains, for example, silicon oxide (SiO 2 ) or the like.

[0209] The conductive layer 113 serves as a transistor TrC ( Figure 1 ) functions as a gate electrode. The conductive layer 113 contains, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Figure 5 As shown, a plurality of conductive layers 113 arranged in the Y direction are connected to a conductive layer 120 extending in the Y direction. Figure 6 and Figure 7 As shown, the conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112 .

[0210] In addition, if Figure 5 As shown, an insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating layer 115 extends in the Z direction so as to penetrate through the plurality of memory layers ML.

[0211] The conductive layer 120 is, for example, a word line WL ( Figure 1 ) functions. As described above, the conductive layer 120 extends in the Y direction. The side surfaces of one side of the conductive layer 120 in the X direction are respectively connected to the plurality of conductive layers 113 arranged in the Y direction. Figure 6 and Figure 7 As shown, the conductive layer 120 includes a barrier conductive film 121 made of, for example, titanium nitride (TiN) or the like and a conductive film 122 made of tungsten (W).

[0212] For example, Figure 6 and Figure 7 As shown, the capacitor structure 130 includes: a conductive layer 131; an insulating layer 132 arranged on the upper surface, lower surface, two side surfaces in the Y direction, and one side in the X direction (the transistor structure 110 side) of the conductive layer 131; a conductive layer 133 arranged on the upper surface, lower surface, two side surfaces in the Y direction, and one side in the X direction (the transistor structure 110 side) of the insulating layer 132; and an insulating layer 134 arranged on the upper surface, lower surface, and two side surfaces in the Y direction of the conductive layer 133.

[0213] The conductive layer 131 acts as a capacitor CpC ( Figure 1 ) functions as an electrode on one side. The conductive layer 131 includes, for example, a stacked structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 131 is connected to the conductive layer 102.

[0214] The insulating layer 132 serves as a capacitor CpC ( Figure 1 ) functions as an insulating layer. The insulating layer 132 may be, for example, zirconium oxide (ZrO2), aluminum oxide (Al2O3) or other insulating metal oxides. In addition, the insulating layer 132 may also be, for example, a stacked film of multiple insulating metal oxides (for example, a stacked film of zirconium oxide and aluminum oxide).

[0215] The conductive layer 133 serves as a capacitor CpC ( Figure 1 ) functions as an electrode on the other side. Conductive layer 133 contains, for example, a conductive oxide such as indium tin oxide (ITO). Conductive layer 133 is insulated from conductive layer 131 via insulating layer 132. Conductive layer 133 is connected to a side surface of one side (conductive layer 102 side) of semiconductor layer 111 in the X direction.

[0216] The insulating layer 134 includes, for example, silicon oxide (SiO 2 ) etc. In the example shown in the figure, the insulating layer 134 is continuous with the insulating layer 112 .

[0217] [Transistor region R TrR Structure of

[0218] like Figure 5 As shown, in the transistor region R TrR There are provided: a plurality of insulating layers 201 arranged in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 202 provided between two insulating layers 201 adjacent to each other in the X direction. The insulating layers 201 and 202 extend in the Y direction and the Z direction, and divide the plurality of memory layers ML in the X direction. The insulating layers 201 and 202 contain, for example, silicon oxide (SiO2).

[0219] In addition, in the transistor region R TrR A plurality of via wirings 204 are provided in the region between the insulating layer 201 and the insulating layer 202. The plurality of via wirings 204 are arranged in the Y direction and are, for example, Fig.11 As shown, it extends in the Z direction through the plurality of storage layers ML.

[0220] The via wiring 204 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The via wiring 204 has a substantially cylindrical shape extending in the Z direction.

[0221] The plurality of via wirings 204 arranged in the Y direction serve as, for example, a word line selection line LW ( Figure 1 ) to function. For example, Figure 1 As shown, a plurality of word line selection lines LW are provided corresponding to a plurality of word lines WL included in the memory layer ML.

[0222] The memory layer ML includes a portion of a plurality of transistor structures 210 provided corresponding to the plurality of conductive layers 120 , a conductive layer 221 provided between the transistor structure 210 and the insulating layer 201 , and a conductive layer 222 provided between the transistor structure 210 and the insulating layer 202 .

[0223] like Fig.11 As shown, the transistor structure 210 includes: a portion provided in the memory layer ML, and a portion provided at a height position corresponding to the insulating layer 103. The portion provided in the memory layer ML is as shown in FIG. Fig.10 As shown in FIG. 1 , the plurality of insulating layers 211 are provided on the outer peripheral surfaces of the plurality of via wirings 204, the conductive layer 212 is provided on the outer peripheral surfaces of the plurality of insulating layers 211 and extends in the Y direction, and the semiconductor layer 213 extends in the Y direction along the side surface of one side (the insulating layer 202 side) of the conductive layer 212 in the X direction. In addition, the portion provided at the height position corresponding to the insulating layer 103 is as shown in FIG. Fig.11 As shown in the figure, the insulating layer 214 is provided on the upper surface and the lower surface of the conductive layer 212 and the semiconductor layer 213 , and the conductive layer 215 is provided on the upper surface and the lower surface of the insulating layer 214 .

[0224] exist Fig.10 In the XY cross section as illustrated, the side surfaces of the conductive layer 212 on both sides in the X direction may be formed along a plurality of overlapping circles centered at a plurality of center positions of the plurality of via wirings 204. In addition, the side surfaces of the semiconductor layer 213 on both sides in the X direction may also be formed along a plurality of overlapping circles centered at a plurality of center positions of the plurality of via wirings 204.

[0225] The insulating layer 211 contains, for example, silicon oxide (SiO 2 ) or the like. The insulating layer 211 has a substantially cylindrical shape extending in the Z direction along a portion of the outer peripheral surface of the via wiring 204 . Fig.11 )continuous.

[0226] The conductive layer 212 contains, for example, a conductive oxide. In addition, the conductive layer 212 may contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the conductive layer 212 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0227] The semiconductor layer 213 serves as a transistor TrR ( Figure 1 ) functions in the channel region. The semiconductor layer 213 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor.

[0228] The insulating layer 214 serves as, for example, a transistor TrR ( Figure 1 ) functions as a gate insulating film. The insulating layer 214 contains, for example, silicon oxide (SiO 2 ) or the like.

[0229] The conductive layer 215 serves as a transistor TrR ( Figure 1 ) functions as a gate electrode. The conductive layer 215 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The side surface of one side (insulating layer 201 side) of the conductive layer 215 in the X direction is connected to a plurality of via wirings 204 arranged in the Y direction. In the case of focusing on two semiconductor layers 213 adjacent to each other in the Z direction, a conductive layer 215 disposed therebetween is opposite to the lower surface of the semiconductor layer 213 disposed above and the upper surface of the semiconductor layer 213 disposed below, separated by the insulating layer 214. The plurality of conductive layers 215 arranged in the Z direction are commonly connected to the via wiring 204 extending in the Z direction.

[0230] Furthermore, when focusing on two conductive layers 215 adjacent to each other in the Z direction, these conductive layers 215 are connected only via the via wiring 204. That is, both ends of the two conductive layers 215 in the Y direction are separated in the Z direction. Similarly, the ends of the two conductive layers 215 on the opposite side to the via wiring 204 are also separated in the Z direction.

[0231] The conductive layer 221 is connected to the side surface of the conductive layer 212 on one side in the X direction (on the insulating layer 201 side). Figure 5 As shown, the conductive layer 221 extends from the transistor region R TrR Extending along the Y direction to the connection wiring area R CL2 , with the transistor TrR( Figure 1 ) of the other electrode and the layer selection line LL ( Figure 1 ) function of electrical connection. The conductive layer 221 contains, for example, a conductive oxide. In addition, the conductive layer 221 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the conductive layer 221 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0232] For example, Fig.11As shown, the conductive layer 221 may include: a portion formed on the lower surface of the insulating layer 103, a portion formed on the upper surface of the insulating layer 103, and a portion formed on the side surface of the conductive layer 212 on one side in the X direction (the insulating layer 201 side). In addition, insulating layers 223 and 224 such as silicon oxide (SiO2) may be provided in the region surrounded by the conductive layer 221.

[0233] The conductive layer 222 is connected to the semiconductor layer 213. Figure 5 As shown, the conductive layer 222 extends from the transistor region R TrR Extending along the Y direction to the connection wiring area R CL1 , with the transistor TrR( Figure 1 ) of the above-mentioned one electrode and the word line WL ( Figure 1 ) function of electrical connection. The conductive layer 222 contains, for example, a conductive oxide. In addition, the conductive layer 222 may also contain ruthenium (Ru), iridium (Ir) or other metals instead of the conductive oxide. In addition, the conductive layer 222 may contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir) or other metals.

[0234] For example, Fig.11 As shown, the conductive layer 222 may include: a portion formed on the lower surface of the insulating layer 103, 214; a portion formed on the upper surface of the insulating layer 103, 214; and a portion formed on the side surface of the other side (insulating layer 202 side) in the X direction of the semiconductor layer 213. Insulating layers 223, 224 such as silicon oxide (SiO2) may be provided in the region surrounded by the conductive layer 222.

[0235] [Connection wiring area R CL1 Structure of

[0236] like Figure 5 As shown, in the connection wiring area R CL1 Insulating layers 301 and 302 are arranged in the Y direction. The insulating layer 301 is connected to the end of the insulating layer 101 in the Y direction. The insulating layer 302 is provided in the memory cell region R with respect to the insulating layer 301. MC The insulating layer 302 is connected to the end of the insulating layer 202 in the Y direction. The insulating layers 301 and 302 extend in the X direction and the Z direction, and divide the plurality of memory layers ML in the Y direction. The insulating layer 301 and the insulating layer 302 contain, for example, silicon oxide (SiO2).

[0237] In addition, in the connection wiring area R CL1 In the region between the insulating layer 301 and the insulating layer 302, an insulating layer 304 made of silicon oxide (SiO2) or the like is provided. The insulating layer 304 may be, for example, Fig. 9As shown, it extends in the Z direction through the plurality of storage layers ML.

[0238] The memory layer ML includes a plurality of connection wiring portions 310 provided corresponding to the plurality of conductive layers 120 .

[0239] For example, Figure 8 As shown, the connection wiring portion 310 includes a semiconductor layer 311 made of silicon (Si) or the like provided on the outer peripheral surface of the insulating layer 304 , and a conductive layer 312 provided on the upper surface, the lower surface, and the outer peripheral surface of the semiconductor layer 311 .

[0240] exist Figure 8 In the XY cross section as illustrated, the side surfaces of the semiconductor layer 311 and the conductive layer 312 on both sides in the X direction may be formed along a circle centered at the center position of the insulating layer 304. In addition, the side surfaces of the semiconductor layer 311 and the conductive layer 312 on both sides in the Y direction may be formed in a straight line along the side surfaces of the insulating layers 301 and 302 in the Y direction.

[0241] The side surface of the conductive layer 312 on one side in the X direction is connected to the conductive layer 120. The side surface of the conductive layer 312 on the other side in the X direction is connected to the conductive layer 222. The conductive layer 312 has a transistor TrR ( Figure 1 ) of the above-mentioned one electrode and the word line WL ( Figure 1 )The function of electrical connection.

[0242] [Connection wiring area R CL2 Structure of

[0243] like Figure 5 As shown, in the connection wiring area R CL2 Insulating layers 401 and 402 are arranged in the Y direction. The insulating layer 402 is provided in the memory cell region R with respect to the insulating layer 401. MC The insulating layer 402 is connected to the end of the insulating layer 202 in the Y direction. The insulating layers 401 and 402 extend in the X direction and the Z direction, and divide the plurality of memory layers ML in the Y direction. The insulating layer 401 and the insulating layer 402 contain, for example, silicon oxide (SiO2).

[0244] In addition, in the connection wiring area R CL2 An insulating layer 404 made of silicon oxide (SiO 2 ) or the like is provided in a region between the insulating layer 401 and the insulating layer 402. The insulating layer 404 extends in the Z direction through the plurality of memory layers ML.

[0245] The memory layer ML includes a plurality of connection wiring portions 410 provided corresponding to the plurality of conductive layers 120 .

[0246] The connection wiring portion 410 includes a semiconductor layer 411 made of silicon (Si) or the like provided on the outer peripheral surface of the insulating layer 404 , and a conductive layer 412 provided on the upper surface, the lower surface, and the outer peripheral surface of the semiconductor layer 411 .

[0247] exist Figure 5 In the XY cross section as illustrated, the side surfaces of the semiconductor layer 411 and the conductive layer 412 on both sides in the X direction may be formed along a circle centered at the center position of the insulating layer 404. In addition, the side surfaces of the semiconductor layer 411 and the conductive layer 412 on both sides in the Y direction may be formed in a straight line along the side surfaces of the insulating layers 401 and 402 in the Y direction.

[0248] One side surface of the conductive layer 412 in the X direction is connected to the conductive layer 221. The other side surface of the conductive layer 412 in the X direction is connected to the wiring region R LL The conductive layer 412 has a structure that connects the transistor TrR ( Figure 1 ) of the other electrode and the layer selection line LL ( Figure 1 )The function of electrical connection.

[0249] [Wiring area R LL Structure of

[0250] The memory layer ML includes a conductive layer 501 extending in the X direction. The conductive layer 501 serves as, for example, a layer selection line LL ( Figure 1 ) functions. The conductive layer 501 extends in the X direction. The conductive layer 501 is connected to each of the plurality of conductive layers 412 arranged in the X direction. The conductive layer 501 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0251] [Manufacturing method]

[0252] Figure 12 to Figure 122 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the first embodiment. Fig.12 , Fig.21 , Fig.23 , Fig.26 , Fig.28 , Fig.30 , Fig.33 , Fig.35 , Fig.38 , Fig.40 , Fig.42 , Fig.45 , Fig.47 , Fig.49 , Fig.51 , Fig.53 , Fig.55 , Fig.57 , Fig.107 , Fig.109 , Fig.111, Fig.113 , Fig.115 , Fig.117 , Fig.119 as well as Fig.121 Shown with Figure 6 The corresponding cross section. Fig.13 , Fig. 22 , Fig.24 , Fig.25 , Fig. 27 , Fig.29 , Fig.31 , Fig.32 , Fig.34 , Fig.36 , Fig.39 , Fig.41 , Fig.43 , Fig.46 , Fig.48 , Fig.50 , Fig.52 , Fig.54 , Fig.56 , Fig.58 , Fig.108 , Fig.110 , Fig.112 , Fig.114 , Fig.116 , Fig.118 , Fig.120 as well as Fig.122 Shown with Figure 7 The corresponding cross section. Fig.14 , Fig.37 , Fig.44 as well as Fig.75 Shown with Figure 5 The corresponding cross section. Fig.15 , Fig.17 , Fig.19 , Fig.76 , Fig.80 , Fig.88 , Fig.92 , Fig.96 , Fig.100 , Fig.102 as well as Fig.104 Shown with Figure 8 The corresponding cross section. Fig.16 , Fig.18 , Fig. 20 , Fig.77 , Fig.81 , Fig.89 , Fig.93 , Fig.97 , Fig.101 , Fig.103 , Fig.105 as well as Fig.106 Shown with Fig. 9 The corresponding cross section. Fig.59 , Fig.70 , Fig.78 , Fig.82 , Fig.84 , Fig.86 , Fig.90 , Fig.94 as well as Fig.98 Shown with Fig.10 The corresponding cross section. Fig.60 , Fig.66 , Fig.67 , Fig.68 , Fig.69 , Fig.71 , Fig.72 , Fig.73 , Fig.74 , Fig.79 , Fig.83 , Fig.85 , Fig.87 , Fig.91 , Fig.95 as well as Fig.99 Shown with Fig.11 The corresponding cross section. Fig.61 , Fig.62 , Fig.63 , Fig.64 as well as Fig.65 A cross section including a via wiring 204 and an insulating layer 201 is shown.

[0253] In the manufacturing method, for example, Fig.13 As shown, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layer MLA contains, for example, silicon nitride (Si3N4). This process is performed by, for example, CVD (Chemical Vapor Deposition).

[0254] Then, for example, Fig.12 and Fig.14 As shown, insulating layers 115, 301, 302, 401, and 402 are formed. In this process, for example, openings are formed at positions corresponding to the insulating layers 115, 301, 302, 401, and 402. The openings extend in the X direction and the Z direction, and the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction are divided in the Y direction. This process is performed, for example, by RIE or the like. After the openings are formed, the insulating layers 115, 301, 302, 401, and 402 are formed. This process is performed, for example, by CVD or the like.

[0255] Then, for example, Fig.15 and Fig.16 As shown in FIG. 1 , an opening 304A is formed at a position corresponding to the insulating layer 304. The opening 304A is as shown in FIG. Fig.16 As shown, the substrate extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed by, for example, RIE or the like.

[0256] Although not shown in the figure, the connection wiring section 410 ( Figure 5 ) is formed in the same manner as the connection wiring portion 310. For example, in this process, between the insulating layer 404 ( Figure 5 ) is also formed at a position corresponding to the opening 304A. In the following steps, the steps corresponding to the connection wiring portion 310 are also performed at a position corresponding to the connection wiring portion 410.

[0257] Then, for example, Fig.17 and Fig.18 As shown, an opening 310A is formed at a position corresponding to the connection wiring portion 310. Inside the opening 310A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a portion of the side surface of the sacrificial layer MLA in the X direction, and a portion of the side surface of the insulating layers 301 and 302 in the Y direction are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 304A. This process is performed, for example, by wet etching or the like.

[0258] Then, for example, Fig.19 and Fig. 20 As shown in FIG. 1 , a sacrificial layer 304B made of silicon (Si) or the like is formed inside the opening 310A and the opening 304A. This process is performed by, for example, CVD or the like.

[0259] Then, for example, Fig.21 and Fig. 22 As shown in FIG. 1 , an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A is as shown in FIG. Fig. 22 As shown, the substrate extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed by, for example, RIE or the like.

[0260] Then, for example, Fig.23 and Fig.24 As shown, an opening 111A is formed at a position corresponding to the semiconductor layer 111. Inside the opening 111A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a portion of the side surface of the sacrificial layer MLA in the X direction, and a portion of the side surface of the insulating layer 115 in the Y direction are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 104A. This process is performed, for example, by wet etching or the like.

[0261] Then, for example, Fig.25 As shown, a part of the insulating layer 103 is removed. In this process, the width of the opening 111A in the Z direction is enlarged. This process is performed by wet etching or the like, for example.

[0262] Then, for example, Fig.26 and Fig. 27 As shown, insulating layer 114A is formed on the inner peripheral surface of opening 104A, the inner peripheral surface of opening 111A, and the upper and lower surfaces of insulating layer 103. Insulating layer 114A includes silicon oxide (SiO2) containing boron (B). This process is performed by CVD, for example.

[0263] Then, for example, Fig.28 and Fig.29 As shown, a conductive layer 113A and a sacrificial layer 111B such as silicon (Si) are formed inside the opening 111A and the opening 104A. The conductive layer 113A is formed on the upper surface, the lower surface, the exposed surface exposed to the opening 104A, the exposed surface exposed to the opening 111A, and both side surfaces in the Y direction of the insulating layer 114A. In addition, the opening 111A is filled with the sacrificial layer 111B, and the opening 104A is not filled with the sacrificial layer 111B. This process is performed by, for example, CVD.

[0264] Then, for example, Fig.30 and Fig.31 As shown in FIG. 1 , a portion of the sacrificial layer 111B is removed to expose a portion of the conductive layer 113A provided at a height position corresponding to the insulating layer 103. This step is performed by, for example, wet etching or the like.

[0265] Then, for example, Fig.32 As shown in FIG. 1 , a portion of the conductive layer 113A provided at a height position corresponding to the insulating layer 103 is removed. This step is performed by, for example, wet etching or the like.

[0266] Then, for example, Fig.33 and Fig.34 As shown, the sacrificial layer 111B is removed. This process is performed by, for example, wet etching or the like.

[0267] Then, for example, Fig.35 and Fig.36 As shown in FIG. 1 , a sacrificial layer 104B made of silicon (Si) or the like is formed inside the opening 111A and the opening 104A. This step is performed by, for example, CVD or the like.

[0268] Then, for example, Fig.37 As shown, openings 101A are formed at positions corresponding to the insulating layers 101. The openings 101A extend in the Y and Z directions and penetrate the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This process is performed, for example, by RIE.

[0269] Although not shown in the figure, the conductive layer 501 ( Figure 5) is also formed in the same manner as the conductive layer 120. For example, in this process, in the conductive layer 501 ( Figure 5 ). The opening extends in the X direction and the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, dividing these structures in the Y direction. Similarly, in the following steps, the steps corresponding to the conductive layer 120 are also performed at the positions corresponding to the conductive layer 501.

[0270] Then, for example, Fig.38 and Fig.39 As shown in FIG. 1 , an opening 120A is formed at a position corresponding to the conductive layer 120. In the opening 120A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a side surface of the insulating layer 114A in the X direction, and a side surface of the insulating layer 115 in the X direction are exposed. In this process, for example, the sacrificial layer MLA is removed through the opening 101A. This process is performed, for example, by wet etching or the like.

[0271] Then, for example, Fig.40 and Fig.41 As shown, a portion of the insulating layer 114A provided on the exposed surface of the conductive layer 113A exposed to the openings 120A and 101A in the X direction is removed through the openings 120A and 101A. This step is performed by, for example, wet etching or the like.

[0272] Then, for example, Fig.42 and Fig.43 As shown, the conductive layer 120 is formed. In this process, a barrier conductive film 121 and a conductive film 122 are formed inside the openings 120A and 101A by a method such as CVD. In this process, the opening 120A is filled with the barrier conductive film 121 and the conductive film 122, and the opening 101A is not filled. Next, a part of the barrier conductive film 121 and the conductive film 122 formed inside the opening 101A is removed by a method such as wet etching. In addition, although not shown in the figure, after performing this process, the insulating layer 101 is formed inside the opening 101A.

[0273] Then, for example, Figures 44 to 46 As shown, an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y direction and the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, and the insulating layer 115, dividing these structures in the X direction. This process is performed by, for example, RIE.

[0274] Then, for example, Fig.47 and Fig.48As shown, an opening 130A is formed at a position corresponding to the capacitor structure 130. In this process, the sacrificial layer MLA is removed through the opening 102A. This process is performed by, for example, wet etching or the like.

[0275] Then, for example, Fig.49 and Fig.50 As shown, insulating layer 114 is formed. In this step, for example, a portion of insulating layer 114A provided on the side surface of conductive layer 113A on the opening 102A side in the X direction is removed through openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0276] Then, for example, Fig.51 and Fig.52 As shown, the conductive layer 113 is formed. In this step, for example, a portion of the conductive layer 113A provided on the side surface of the sacrifice layer 104B on the opening 102A side in the X direction is removed through the openings 102A and 130A. This step is performed by, for example, wet etching or the like.

[0277] Then, for example, Fig.53 and Fig.54 As shown, the sacrificial layer 104B is removed. This process is performed by, for example, wet etching or the like.

[0278] Then, for example, Fig.55 and Fig.56 As shown, insulating layers 112, 134 and semiconductor layer 111C are formed inside openings 111A, 104A, 130A, and 102A. Insulating layers 112 and 134 are formed on: the exposed surface of conductive layer 113 exposed to opening 111A; a portion of the upper surface, a portion of the lower surface, and the exposed surface of insulating layer 103 exposed to opening 102A; the exposed surface of insulating layer 114 exposed to opening 104A; and a portion of the side surface in the Y direction of insulating layer 115. In addition, opening 111A is filled with semiconductor layer 111C, and openings 104A, 130A, and 102A are not filled with semiconductor layer 111C. This process is performed, for example, by CVD or the like.

[0279] Then, for example, Fig.57 and Fig.58 As shown, a sacrificial layer 104C made of silicon (Si) or the like is formed inside the opening 104A. Also, a sacrificial layer 102B made of silicon (Si) or the like is formed inside the opening 102A. This process is performed by, for example, CVD or the like.

[0280] Then, for example, Fig.59 and Fig.60 As shown in FIG. 1 , an opening 204A is formed at a position corresponding to the via wiring 204. The opening 204A is as shown in FIG. Fig.60As shown, the substrate extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction. This step is performed by, for example, RIE or the like.

[0281] In addition, for example, Fig.61 As shown, openings 201A are formed at positions corresponding to the insulating layers 201. The openings 201A extend in the Y and Z directions and penetrate the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This process is performed, for example, by RIE.

[0282] Then, for example, Fig.62 As shown, insulating films 201B and 204B made of silicon oxide (SiO2) or the like are formed inside the openings 201A and 204A. The openings 201A and 204A are not filled with the insulating films 201B and 204B. This process is performed by, for example, CVD or the like.

[0283] Then, for example, Fig.63 As shown, the insulating film 201B is removed. This process is performed by, for example, wet etching or the like.

[0284] Then, for example, Fig.64 As shown, a sacrificial layer 103B is formed. The sacrificial layer 103B includes, for example, silicon (Si) containing impurities such as boron (B). In this process, a portion of the insulating layer 103 is removed through the opening 201A by, for example, wet etching or the like. In addition, the sacrificial layer 103B is formed on a portion of the upper surface, a portion of the lower surface, and an exposed surface of the sacrificial layer MLA exposed to the opening 201A by, for example, CVD or the like. The opening 201A is not filled with the sacrificial layer 103B.

[0285] Then, for example, Fig.65 As shown, the insulating film 204B is removed. This process is performed by, for example, wet etching or the like.

[0286] Then, for example, Fig.66 As shown, an opening 215A is formed at a position corresponding to the conductive layer 215. A portion of the upper surface and a portion of the lower surface of the sacrificial layer MLA are exposed inside the opening 215A. In this process, for example, a portion of the insulating layer 103 is selectively removed through the opening 204A. This process is performed, for example, by wet etching or the like.

[0287] Then, for example, Fig.67 As shown, a part of the insulating layer 103 is removed. In this step, the width of the opening 215A in the Z direction is enlarged. This step is performed by, for example, wet etching or the like.

[0288] Then, for example, Fig.68As shown, a sacrificial layer 215B made of silicon (Si) or the like is formed inside the opening 215A and the opening 204A. The opening 215A is filled with the sacrificial layer 215B. The opening 204A is not filled with the sacrificial layer 215B. This process is performed by, for example, CVD or the like.

[0289] Then, for example, Fig.69 As shown, a part of the sacrificial layer 215B is removed. In this step, the sacrificial layers MLA and 103B are exposed inside the opening 204A. This step is performed by, for example, wet etching or the like.

[0290] Then, for example, Fig.70 and Fig.71 As shown, a conductive layer 212 is formed. In this process, a portion of the sacrificial layer MLA is removed by, for example, wet etching or the like. In addition, a conductive layer is formed on a portion of the upper surface, a portion of the lower surface, and an exposed surface exposed to the opening 204A of the sacrificial layer 103B, 215B by ALD (Atomic Layer Deposition) or the like. Next, a portion of the conductive layer is removed by wet etching or the like and divided in the Z direction to form a plurality of conductive layers 212 arranged in the Z direction.

[0291] Then, for example, Fig.72 As shown, the sacrificial layer 215B is removed. This process is performed by, for example, wet etching.

[0292] Then, for example, Fig.73 As shown in FIG. 1 , insulating layers 211 and 214 , conductive layer 215 , and via wiring 204 are formed inside openings 215A and 204A. This process is performed by, for example, CVD or the like.

[0293] Then, for example, Fig.74 As shown in FIG. 1 , the insulating layer 103 is formed. In this step, the sacrificial layer 103B is removed by, for example, wet etching or the like. In addition, the insulating layer 103 is formed by, for example, CVD or the like.

[0294] Then, for example, Figure 75 to Figure 79 As shown, openings 202A are formed at positions corresponding to the insulating layers 202. The openings 202A extend in the Y and Z directions and penetrate the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged in the Z direction, dividing these structures in the X direction. This step is performed, for example, by RIE.

[0295] Then, for example, Figure 80 to Figure 83As shown, openings 221A, 222A, and 213A are formed at positions corresponding to the conductive layers 221 and 222 and the semiconductor layer 213. In the opening 221A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a side surface on one side in the X direction of the conductive layer 212, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. In the opening 222A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, a side surface on one side in the X direction of the sacrificial layer 304B, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. In the opening 213A, a portion of the upper surface and a portion of the lower surface of the insulating layer 214, a side surface on the other side in the X direction of the conductive layer 212, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the openings 201A and 202A. This process is performed, for example, by wet etching or the like.

[0296] Then, for example, Fig.84 and Fig.85 As shown, semiconductor layer 213B is formed inside openings 213A, 222A, 202A, 221A, and 201A. Opening 213A is filled with semiconductor layer 213B, while openings 222A, 221A, 202A, and 201A are not filled with semiconductor layer 213B. This process is performed by, for example, CVD or the like.

[0297] Then, for example, Fig.86 and Fig.87 As shown in FIG. 2 , the semiconductor layer 213 is formed. In this step, a portion of the semiconductor layer 213B is removed by, for example, wet etching or the like. Specifically, a portion of the semiconductor layer 213B formed inside the opening 213A is left, and the other portion is removed.

[0298] Then, for example, Figures 88 to 91 As shown, a conductive layer 222B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 222A and 202A. The conductive layer 222B is formed on: a portion of the upper surface, a portion of the lower surface, and the exposed surface of the insulating layer 103 exposed to the opening 202A; the exposed surface of the sacrificial layer 304B exposed to the opening 222A; a portion of the upper surface and a portion of the lower surface of the insulating layer 214; a side surface on one side in the X direction of the semiconductor layer 213; and a side surface on one side in the Y direction of the insulating layers 301 and 402. The opening 222A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 202A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed, for example, by ALD, CVD, etc.

[0299] In addition, a conductive layer 221B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 221A and 201A. The conductive layer 221B is formed on: a portion of the upper surface, a portion of the lower surface, and the exposed surface of the insulating layer 103 exposed to the opening 201A; a side surface on one side in the X direction of the conductive layer 212; and a side surface on one side in the Y direction of the insulating layers 301 and 402. The opening 221A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 201A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed by, for example, ALD, CVD, etc.

[0300] Then, if Figures 92 to 95 As shown, conductive layers 221, 222 and insulating layer 223 are formed. In this process, the exposed surface of insulating layer 103 exposed to openings 201A, 202A is removed from conductive layers 221B, 222B, insulating layer 223A, and sacrificial layer 224A, so that insulating layer 103 is exposed to openings 201A, 202A. Thus, conductive layers 221B, 222B and insulating layer 223A are divided in the Z direction to form conductive layers 221, 222 and insulating layer 223. This process is performed, for example, by wet etching or the like.

[0301] Then, if Figure 96 to Figure 99 As shown, the sacrificial layer 224A is removed. This process is performed by, for example, wet etching. Furthermore, the insulating layer 224 is formed in the openings 221A and 222A.

[0302] Then, if Fig.100 and Fig.101 As shown, the sacrificial layer 304B is removed. This process is performed by, for example, wet etching.

[0303] Then, for example, Fig.102 and Fig.103 As shown, a conductive layer 312B and a semiconductor layer 311B are formed inside the openings 311A ​​and 304A. The conductive layer 312B is formed on: a portion of the upper surface, a portion of the lower surface, and the exposed surface exposed to the opening 304A of the insulating layer 103; a side surface on one side in the X direction of the conductive layer 222; and a side surface on one side in the X direction of the conductive layer 120. The opening 311A ​​is filled with the semiconductor layer 311B, and the opening 304A is not filled with the semiconductor layer 311B. This process is performed, for example, by CVD or the like.

[0304] Then, if Fig.104 and Fig.105As shown in FIG. 1 , a semiconductor layer 311 is formed. In this process, a portion of the inner peripheral surface of the semiconductor layer 311 formed on the insulating layer 103 and facing the opening 304A is removed, so that a portion of the conductive layer 312B is exposed to the opening 304A. As a result, the semiconductor layer 311 is divided in the Z direction to form a plurality of semiconductor layers 311 arranged in the Z direction. This process is performed, for example, by wet etching or the like.

[0305] Then, if Fig.106 As shown in FIG. 1 , a conductive layer 312 is formed. In this process, a portion of the conductive layer 312B formed on the inner peripheral surface of the insulating layer 103 facing the opening 304A is removed, so that the insulating layer 103 is exposed to the opening 304A. As a result, the conductive layer 312B is divided in the Z direction to form a plurality of conductive layers 312 arranged in the Z direction. This process is performed, for example, by wet etching. Then, the insulating layer 304 is formed in the opening 304A.

[0306] Then, for example, Fig.107 and Fig.108 As shown, the sacrificial layer 102B is removed. This process is performed by, for example, wet etching or the like.

[0307] Then, for example, Fig.109 and Fig.110 As shown, the semiconductor layer 111 is formed. In this step, a portion of the semiconductor layer 111C formed on the surface of the insulating layer 134 exposed to the openings 130A and 102A is removed, and the semiconductor layer 111C is divided in the Y direction. This step is performed by, for example, wet etching.

[0308] Then, for example, Fig.111 and Fig.112 As shown, conductive layer 133A, insulating layer 130B, and sacrificial layer 130C are formed on one side surface of semiconductor layer 111 in the X direction (side surface on the opening 102A side) and the exposed surface of insulating layer 134 exposed to openings 130A and 102A. This process is performed by ALD, CVD, etc., for example.

[0309] Then, for example, Fig.113 and Fig.114 As shown, a portion of the sacrificial layer 130C is removed through the opening 102A. In this step, for example, portions of the insulating layer 130B corresponding to the side surfaces of the insulating layer 115 and the insulating layer 103 in the X direction are exposed. This step is performed by, for example, wet etching or the like.

[0310] Then, for example, Fig.115 and Fig.116As shown in FIG. 1 , a portion of insulating layer 130B is removed through opening 102A. In this step, for example, portions of conductive layer 133A corresponding to insulating layer 115 and the side surfaces of insulating layer 103 in the X direction are exposed. This step is performed by, for example, wet etching or the like.

[0311] Then, for example, Fig.117 and Fig.118 As shown, conductive layer 133 is formed. In this step, for example, portions of conductive layer 133A provided on the side surfaces of insulating layer 115 and insulating layer 103 in the X direction are removed, and conductive layer 133A is divided in the Y direction and the Z direction. This step is performed by wet etching, for example.

[0312] Then, for example, Fig.119 and Fig.120 As shown, the sacrificial layer 130C and the insulating layer 130B are removed through the opening 102A. This process is performed by, for example, wet etching or the like.

[0313] Then, for example, Fig.121 and Fig.122 As shown, the capacitor structure 130 and the conductive layer 102 are formed. In this process, for example, the insulating layer 132 and the conductive layers 131 and 102 are formed on the upper surface, the lower surface, the side surface on one side in the X direction (the side surface on the opening 102A side) and the side surfaces on both sides in the Y direction of the conductive layer 133, and the side surface in the X direction of the insulating layer 134. This process is performed by, for example, CVD or the like.

[0314] Then, the sacrificial layer 104C is removed and the via wiring 104 and the like are formed, thereby manufacturing the semiconductor memory device according to the first embodiment.

[0315] [Comparative Example]

[0316] Fig.123 is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to a comparative example.

[0317] The memory cell array MCA' of the semiconductor memory device according to the comparative example includes a plurality of memory layers ML0' to ML3' (hereinafter sometimes referred to as "memory layer ML'"), each of which does not include a transistor TrR, but instead includes transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, TrL3b (hereinafter sometimes referred to as "transistor TrL"). One electrode of the transistor TrL is connected to any one of the word lines WL0 to WL2. The other electrode of the transistor TrL is respectively connected to the word line selection line LW. In addition, one electrode and the other electrode of the transistor TrL function as a source electrode or a drain electrode according to the voltage supplied to the transistor TrL. The gate electrode of the transistor TrL is respectively connected to the layer selection line LL.

[0318] Fig.124 It is a schematic circuit diagram for explaining a read operation of a semiconductor memory device according to a comparative example.

[0319] In a read operation of the semiconductor memory device according to the comparative example, a voltage V is supplied to the layer selection line LL0a corresponding to the memory layer ML0 to be read out among the plurality of layer selection lines LL0a, LL1a, LL2a, and LL3a. ON ' instead of voltage V ON In addition, the voltage V is supplied to other layer selection lines LL1a, LL2a, and LL3a. OFF ' instead of voltage V OFF In addition, for example, a voltage V is supplied to the layer selection line LL0b corresponding to the memory layer ML0 to be the target of the read operation among the plurality of layer selection lines LL0b, LL1b, LL2b, and LL3b. OFF ' instead of voltage V OFF In addition, the voltage V is supplied to other layer selection lines LL1b, LL2b, and LL3b. ON ' instead of voltage V OFF .

[0320] Furthermore, a voltage V is supplied to a word line selection line LW0a corresponding to the word line WL0 to be the target of the read operation among the plurality of word line selection lines LW0a, LW1a, and LW2a. ON Instead of voltage V ON '. In addition, the voltage V is supplied to the other layer selection lines LW1a and LW2a. OFF Instead of voltage V OFF '. In addition, a voltage V is supplied to the plurality of word line selection lines LW0b, LW1b, and LW2b. OFF Instead of voltage V OFF ', voltage V ON ′.

[0321] Here, in the read operation of the semiconductor memory device according to the comparative example, a voltage V is supplied to the selected word line WL0 via the transistor TrL0a. ON In addition, the voltage V is supplied to the other unselected word lines WL via the transistor TrL0a. OFF .

[0322] In the read operation, in order to quickly transfer the voltage V to the selected word line WL ON It is desirable to keep the gate-source voltage of the transistor TrL corresponding to the selected memory cell MC sufficiently higher than the threshold voltage of the transistor TrL, thereby increasing the current flowing through the transistor TrL. ON ′) is set to a large value.

[0323] However, if the gate voltage of transistor TrL is set to a large value, the gate-source voltage of a part of transistor TrL will increase, and transistor TrL needs to be configured to withstand a higher voltage. For this reason, thickening the gate insulating film of transistor TrL is considered. However, the gate voltage of transistor TrL is different for each storage layer ML', so it is necessary to set a gate electrode separately for each storage layer ML'. Therefore, if the gate insulating film of transistor TrL is thickened, the length of the entire storage layer ML' in the Z direction will increase, which will hinder the high integration of semiconductor storage devices.

[0324] [Effect]

[0325] As reference Figure 1 As described above, in the semiconductor memory device according to the first embodiment, the gate voltages of the transistors TrR are the same (common) among the plurality of memory layers ML. Fig.11 As described above, the conductive layer 215 functioning as the gate electrode of the transistor TrR can be provided at a height position corresponding to the insulating layer 103, and can be provided as a common gate electrode of two transistors TrR adjacent to each other in the Z direction. Thus, the gate insulating film of the transistor TrR can be thickened without hindering the high integration of the semiconductor memory device.

[0326] In the transistor structure 110 according to this embodiment, the conductive layer 113 faces the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111 .

[0327] In such a structure, it is possible to suppress the interference of electric fields between the plurality of semiconductor layers 111 arranged in the Z direction. Therefore, even when the memory cell array MCA is highly integrated in the Z direction, the semiconductor layer 111 can be well controlled to be in an on state or an off state, and a well-functioning semiconductor memory device can be provided.

[0328] When the transistor TrC is turned on, a channel is formed on the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111. Therefore, the on-current of the transistor TrC can be increased, thereby achieving faster and more stable operation.

[0329] In addition, in the present embodiment, the conductive layer 120 functioning as the word line WL is provided on the opposite side of the plate line PL relative to the transistor structure 110, and is provided at a position that does not overlap with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently, and can be manufactured relatively easily. In addition, the wiring resistance of the conductive layer 120 can be set to a small value while suppressing the width of the memory layer ML in the Z direction.

[0330] [Second embodiment]

[0331] [structure]

[0332] Next, refer to Figures 125 to 127 , a semiconductor storage device according to a second embodiment is described. Fig.125 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the second embodiment. Fig.126 is a schematic XY cross-sectional view showing a part of the structure of the semiconductor storage device, showing an enlarged Fig.125 part of. Fig.127 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.126 The structure shown is a structure cut along the CC' line and observed in the direction of the arrow.

[0333] The semiconductor memory device according to the second embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment. Fig.125 As shown in FIG. 1 , the semiconductor memory device according to the second embodiment includes a transistor region R TrR2 To replace the transistor area R TrR .

[0334] Transistor area R TrR2 Basically, it is configured as follows with the transistor region R TrR However, in the transistor region R TrR2In FIG. 1 , the memory layer ML includes a part of the transistor structure 610 instead of a part of the transistor structure 210 .

[0335] like Fig.127 As shown, the transistor structure 610 includes: a portion provided in the memory layer ML and a portion provided at a height position corresponding to the insulating layer 103. Fig.126 As shown, the portion provided in the memory layer ML includes a plurality of insulating layers 611 provided on the outer peripheral surfaces of the plurality of via wirings 204, and a semiconductor layer 613 provided on the outer peripheral surfaces of the plurality of insulating layers 611 and extending in the Y direction. Fig.127 As shown, the portion provided at a height position corresponding to the insulating layer 103 includes an insulating layer 614 provided on the upper surface and the lower surface of the semiconductor layer 613 and a conductive layer 615 provided on the upper surface and the lower surface of the insulating layer 614 .

[0336] exist Fig.126 In the XY cross section as illustrated, the side surfaces of the semiconductor layer 613 on both sides in the X direction can be formed along a plurality of circles overlapping each other centered around a plurality of center positions of the plurality of via wirings 204 .

[0337] The insulating layer 611 contains, for example, silicon oxide (SiO 2 ) or the like. The insulating layer 611 has a substantially cylindrical shape extending in the Z direction along a portion of the outer peripheral surface of the via wiring 204 . Fig.127 )continuous.

[0338] The semiconductor layer 613 serves as a transistor TrR ( Figure 1 ) functions in the channel region. The semiconductor layer 613 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor.

[0339] The insulating layer 614 serves as, for example, a transistor TrR ( Figure 1 ) functions as a gate insulating film. The insulating layer 614 contains, for example, silicon oxide (SiO 2 ) or the like.

[0340] The conductive layer 615 serves as a transistor TrR ( Figure 1) functions as a gate electrode. The conductive layer 615 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 615 is connected to a plurality of via wirings 204 arranged in the Y direction. In the case of focusing on two semiconductor layers 613 adjacent to each other in the Z direction, a conductive layer 615 disposed therebetween is opposite to the lower surface of the semiconductor layer 613 disposed above and the upper surface of the semiconductor layer 613 disposed below, separated by an insulating layer 614. The plurality of conductive layers 615 arranged in the Z direction are commonly connected to the via wiring 204 extending in the Z direction.

[0341] Furthermore, when focusing on two conductive layers 615 adjacent to each other in the Z direction, these conductive layers 615 are connected only via the via wiring 204. That is, the two ends of the two conductive layers 615 in the Y direction are separated in the Z direction. Similarly, the two ends of the two conductive layers 615 in the X direction are also separated in the Z direction.

[0342] [Manufacturing method]

[0343] Figures 128 to 143 It is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor memory device according to the second embodiment. Fig.128 , Fig.129 , Fig.131 , Fig.133 , Fig.135 , Fig.137 , Fig.139 , Fig.141 as well as Fig.143 Shown with Fig.127 The corresponding cross section. Fig.130 , Fig.132 , Fig.134 , Fig.136 , Fig.138 , Fig.140 as well as Fig.142 Shown with Fig.126 The corresponding cross section.

[0344] In this manufacturing method, for example, the manufacturing method of the semiconductor memory device according to the first embodiment is performed with reference to Fig.59 and Fig.60 The process described above is completed.

[0345] Then, for example, Fig.128 As shown, an opening 615A is formed at a position corresponding to the conductive layer 615. A portion of the upper surface and a portion of the lower surface of the sacrificial layer MLA are exposed inside the opening 615A. In this process, for example, a portion of the insulating layer 103 is selectively removed through the opening 204A. This process is performed, for example, by wet etching or the like.

[0346] Then, for example, Fig.129 As shown, a part of the insulating layer 103 is removed. In this process, the width of the opening 615A in the Z direction is enlarged. This process is performed by, for example, wet etching or the like.

[0347] Then, for example, Fig.130 and Fig.131 As shown in FIG. 2 , insulating layers 611 and 614, a conductive layer 615, and via wiring 204 are formed inside openings 615A and 204A. This process is performed by, for example, CVD or the like.

[0348] Then, for example, Fig.132 and Fig.133 As shown, openings 221A, 222A, and 613A are formed at positions corresponding to the conductive layers 221 and 222 and the semiconductor layer 613. Inside the opening 221A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. Inside the opening 222A, a portion of the upper surface and a portion of the lower surface of the insulating layer 103, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. Inside the opening 613A, the upper surface and the lower surface of the insulating layer 614, the outer peripheral surface of the insulating layer 611, and a portion of the side surface on one side in the Y direction of the insulating layers 301 and 402 are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the openings 221A and 222A. This process is performed, for example, by wet etching or the like.

[0349] Then, for example, Fig.134 and Fig.135 As shown, a semiconductor layer 613B is formed inside the openings 613A, 222A, 202A, 221A, and 201A. The opening 613A is filled with the semiconductor layer 613B, while the openings 222A, 202A, 221A, and 201A are not filled with the semiconductor layer 613B. This process is performed by, for example, CVD or the like.

[0350] Then, for example, Fig.136 and Fig.137 As shown in FIG. 6A , the semiconductor layer 613 is formed. In this step, a portion of the semiconductor layer 613B is removed by, for example, wet etching or the like. Specifically, a portion of the semiconductor layer 613B formed inside the opening 613A is left, and the other portion is removed.

[0351] Then, for example, Fig.88 , Fig.89 , Fig.138 as well as Fig.139As shown, a conductive layer 222B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 222A and 202A. The conductive layer 222B is formed on: a portion of the upper surface, a portion of the lower surface, and the exposed surface exposed to the opening 202A of the insulating layer 103; a portion of the upper surface and a portion of the lower surface of the insulating layer 614; the outer peripheral surface of the semiconductor layer 613; and the side surface of one side of the insulating layer 301 and 402 in the Y direction. The opening 222A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 202A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed, for example, by ALD, CVD, etc.

[0352] In addition, a conductive layer 221B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 221A and 201A. The conductive layer 221B is formed on: a portion of the upper surface, a portion of the lower surface, and the exposed surface exposed to the opening 201A of the insulating layer 103; a portion of the upper surface and a portion of the lower surface of the insulating layer 614; the outer peripheral surface of the semiconductor layer 613; and the side surface of one side of the insulating layer 301 and 402 in the Y direction. The opening 221A is filled with the insulating layer 223A and the sacrificial layer 224A, and the opening 201A is not filled with the insulating layer 223A and the sacrificial layer 224A. This process is performed, for example, by ALD, CVD, etc.

[0353] Then, if Fig.92 , Fig.93 , Fig.140 as well as Fig.141 As shown, conductive layers 221, 222 and insulating layer 223 are formed. This process is similar to that of reference Figures 92 to 95 The steps described above are performed in the same manner.

[0354] Then, if Fig.96 , Fig.97 , Fig.142 as well as Fig.143 As shown, the sacrificial layer 224A is removed. This process is performed by, for example, wet etching or the like.

[0355] Then, for example, the method for manufacturing the semiconductor memory device according to the first embodiment is performed with reference to Fig.100 and Fig.101 The process after the process described.

[0356] [Third Embodiment]

[0357] In order to connect a plurality of layer selection lines LL to peripheral circuits, for example, it is considered that a plurality of conductive layers 501 ( Figure 5) is provided with a terrace portion, and the via contact electrode is connected to the terrace portion. The terrace portion is, for example, a portion of the upper surface of the conductive layer 501 that does not overlap with other conductive layers when viewed from above. In the memory cell array MCA, the more the number of memory layers ML arranged in the Z direction is, the more terrace portions are required.

[0358] Here, as reference Figure 2 As described above, in the read operation of the semiconductor memory device according to the first embodiment, a common voltage V is supplied to the plurality of layer selection lines LL0b, LL1b, LL2b, and LL3b. OFF Therefore, for example, by short-circuiting the layer selection lines LL0b, LL1b, LL2b, and LL3b, the terraces of the layer selection lines LL0b, LL1b, LL2b, and LL3b can be omitted, and the circuit area can be reduced. Hereinafter, such a configuration will be described as a semiconductor memory device according to a third embodiment.

[0359] Fig.144 This is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to the third embodiment.

[0360] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, as shown in the figure, the semiconductor memory device according to the third embodiment includes wiring LLc instead of the layer selection lines LL0b, LL1b, LL2b, and LL3b. The wiring LLc is commonly connected to the transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to the word lines WL0, WL1, and WL2.

[0361] Fig.145 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the third embodiment. Fig.146 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.145 The structure shown is a structure cut along line DD′ and observed in the direction of the arrow.

[0362] The structure of the semiconductor memory device according to the third embodiment is basically the same as the structure of the semiconductor memory device according to the first embodiment. Fig.145 As shown, the semiconductor memory device according to the third embodiment includes a wiring region R LLc Instead of wiring area R LL . Wiring area R LLc It is formed so as to straddle two memory cell arrays MCA adjacent to each other in the Y direction.

[0363] Although not shown in the figure, similarly to the first embodiment, the memory cell region R MC A wiring area R is provided in an area on one side in the Y direction. LL .

[0364] In the wiring area R LLc A conductive layer 503 is provided. The conductive layer 503 extends in the X direction and the Z direction. Fig.146 As shown in FIG. 5 , the plurality of memory layers ML are divided in the Y direction. The conductive layer 503 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 503 is, for example, a wiring LLc ( Fig.144 ) to perform its function.

[0365] In addition, in the wiring area R LLc The memory layer ML includes a conductive layer 502 extending in the X direction. The conductive layer 502 is respectively connected to a plurality of conductive layers 412 arranged in the X direction ( Fig.145 ). In addition, the conductive layer 502 is connected to the conductive layer 503. The conductive layer 502 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0366] Furthermore, the semiconductor memory device according to the third embodiment may include the transistor region R according to the second embodiment. TrR2 ( Fig.125 ) instead of the transistor region R involved in the first embodiment TrR .

[0367] [Fourth embodiment]

[0368] As reference Figure 2 As described above, in the read operation of the semiconductor memory device according to the first embodiment, a common voltage V is supplied to the plurality of layer selection lines LL0b, LL1b, LL2b, and LL3b. OFF In such a configuration, for example, not only the layer selection lines LL0b, LL1b, LL2b, and LL3b but also the transistors TrR0b, TrR1b, TrR2b, and TrR3b can be omitted, and the circuit area can be further reduced. Hereinafter, such a configuration will be described as a semiconductor memory device according to a fourth embodiment.

[0369] Fig.147 This is a schematic circuit diagram showing a partial structure of a semiconductor memory device according to a fourth embodiment.

[0370] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment. However, as shown in the figure, the semiconductor memory device according to the fourth embodiment includes a resistor R instead of the transistors TrR0b, TrR1b, TrR2b, and TrR3b. The resistor R is provided in the current path between the plurality of word lines WL and the wiring LLc.

[0371] Fig.148 It is a schematic XY cross-sectional view showing a part of the structure of the semiconductor memory device according to the fourth embodiment. Fig.149 is a schematic cross-sectional view showing a part of the structure of the semiconductor storage device. Fig.148 The structure shown is a structure cut along line DD′ and observed in the direction of the arrow.

[0372] The structure of the semiconductor memory device according to the fourth embodiment is basically the same as the structure of the semiconductor memory device according to the third embodiment. Fig.148 As shown, the semiconductor memory device according to the fourth embodiment includes a wiring region R LLc2 To replace the transistor area R TrR , Wiring area R LLc and the connection wiring area R CL1 , R CL2 . Wiring area R LLc2 It is formed so as to straddle two memory cell arrays MCA adjacent to each other in the Y direction.

[0373] Although not shown in the figure, similarly to the first embodiment, the memory cell region R MC A transistor region R is provided in a region on one side in the Y direction. TrR , Wiring area R LL and the connection wiring area R CL1 , R CL2 .

[0374] In the wiring area R LLc2 A conductive layer 513 is provided. The conductive layer 513 extends in the X direction and the Z direction. Fig.149 As shown in FIG. 5 , the plurality of memory layers ML are divided in the Y direction. The conductive layer 513 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 513 is, for example, a wiring LLc ( Fig.147 ) to perform its function.

[0375] In addition, in the wiring area R LLc2 A semiconductor layer 514 is provided. The semiconductor layer 514 is connected to the conductive layer 513 and the plurality of conductive layers 120. The semiconductor layer 514 is used as a resistor R ( Fig.147) to function. The semiconductor layer 514 may also be Fig.149 As shown in FIG. 5 , the semiconductor layer 514 may include a portion provided in the memory layer ML. Fig.149 As shown in the figure, the semiconductor layer 514 includes a portion extending in the Z direction. However, the configuration of the semiconductor layer 514 can be adjusted as appropriate. For example, one of the portion provided in the memory layer ML and the portion extending in the Z direction in the semiconductor layer 514 may be omitted.

[0376] Furthermore, the semiconductor memory device according to the fourth embodiment may also include the transistor region R according to the second embodiment. TrR2 ( Fig.125 ) instead of the transistor region R involved in the first embodiment TrR .

[0377] [Other embodiments]

[0378] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and specific configurations and the like can be appropriately adjusted.

[0379] For example, in the semiconductor memory devices according to the first to fourth embodiments, the via wiring 104 functioning as a bit line includes a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structure 110 instead of the via wiring 104 extending in the Z direction. In addition, the via wiring 104 and the transistor structure 110 may include other materials.

[0380] In addition, in the semiconductor storage devices involved in the first to fourth embodiments, the conductive layer 113, 215, 615 that functions as the gate electrode of the transistor TrC, TrR may be opposite to only one of the upper surface and the lower surface of the semiconductor layer 111, 213, 613 that functions as the channel region of the transistor TrC, TrR.

[0381] In the semiconductor memory devices according to the first to fourth embodiments, the semiconductor layer 111, 213, 613 functioning as the channel region of the transistors TrC and TrR may face the upper and lower surfaces of the conductive layer 113, 215, 615 functioning as the gate electrode of the transistors TrC and TrR.

[0382] In addition, in the above description, an example of using a capacitor CpC as a storage unit connected to the transistor structure 110 is described. However, the storage unit may not be a capacitor CpC. For example, the storage unit may be a storage unit that includes a ferroelectric (strong dielectric) body, a ferromagnetic (strong magnetic) body, a chalcogen material such as GeSbTe, or other materials and uses the characteristics of these materials to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor CpC may include any of these materials.

[0383] Furthermore, the methods for manufacturing the semiconductor memory device according to the first to fourth embodiments can be adjusted as appropriate. For example, the order of any two of the above steps can be reversed, or any two of the above steps can be performed simultaneously.

[0384] [other]

[0385] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor storage device comprising: substrate; A first via wiring extending in a first direction intersecting the surface of the substrate; A plurality of first semiconductor layers arranged in the first direction and electrically connected to the first via wiring; A storage unit arranged in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged in the first direction and facing the plurality of first semiconductor layers; a plurality of first wirings arranged in the first direction and extending in a second direction intersecting the first direction and electrically connected to the plurality of first gate electrodes; a plurality of second semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of second gate electrodes arranged in the first direction and facing the plurality of second semiconductor layers; a second via wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; as well as The plurality of second wirings are arranged in the first direction and extend in a third direction intersecting the first direction and the second direction, and are electrically connected to the plurality of second semiconductor layers.

2. The semiconductor memory device according to claim 1, Of the plurality of second gate electrodes, two second gate electrodes adjacent to each other in the first direction have both ends in the second direction separated from each other in the first direction.

3. The semiconductor memory device according to claim 1, A plurality of insulating layers are provided, wherein the plurality of insulating layers and the plurality of second semiconductor layers are arranged alternately in the first direction, The plurality of second gate electrodes are respectively provided at positions in the first direction corresponding to the plurality of insulating layers.

4. The semiconductor memory device according to claim 1, One of the plurality of second gate electrodes is provided between two second semiconductor layers adjacent to each other in the first direction among the plurality of second semiconductor layers, and faces the two second semiconductor layers.

5. The semiconductor memory device according to claim 1, The second semiconductor layer contains at least one element of gallium and aluminum, indium, zinc, and oxygen.

6. The semiconductor memory device according to claim 1, The first gate electrode faces one surface and the other surface of the first semiconductor layer in the first direction and one surface and the other surface of the first semiconductor layer in the second direction.

7. The semiconductor memory device according to claim 1, The storage unit comprises: a first electrode electrically connected to the first semiconductor layer; a second electrode, opposite to the first electrode; and The insulating layer is provided between the first electrode and the second electrode.

8. The semiconductor memory device according to claim 1, The first semiconductor layer contains at least one element of gallium and aluminum, indium, zinc, and oxygen.

9. The semiconductor memory device according to claim 1, have: a plurality of third semiconductor layers arranged in the first direction and electrically connected to the plurality of first wirings; a plurality of third gate electrodes arranged in the first direction and facing the plurality of third semiconductor layers; and a third via wiring extending in the first direction and electrically connected to the plurality of third gate electrodes; The position of the first via wiring in the second direction is between the position of the second via wiring in the second direction and the position of the third via wiring in the second direction.

10. The semiconductor memory device according to claim 9, A plurality of third wirings are provided, the plurality of third wirings are arranged in the first direction, extend in the third direction, and are electrically connected to the plurality of third semiconductor layers.

11. The semiconductor memory device according to claim 9, A fourth wiring is provided, the fourth wiring extending in the first direction and the third direction and electrically connected to the plurality of third semiconductor layers.

12. The semiconductor memory device according to claim 9, Of the plurality of third gate electrodes, two third gate electrodes adjacent to each other in the first direction have both ends in the second direction separated from each other in the first direction.

13. The semiconductor memory device according to claim 9, A plurality of insulating layers are provided, wherein the plurality of insulating layers and the plurality of third semiconductor layers are arranged alternately in the first direction, The plurality of third gate electrodes are respectively provided at positions in the first direction corresponding to the plurality of insulating layers.

14. The semiconductor memory device according to claim 9, One of the plurality of third gate electrodes is provided between two third semiconductor layers adjacent to each other in the first direction among the plurality of third semiconductor layers, and is opposed to the two third semiconductor layers.

15. The semiconductor memory device according to claim 9, The third semiconductor layer contains at least one element of gallium and aluminum, indium, zinc, and oxygen.

16. The semiconductor memory device according to claim 1, have: a fifth wiring extending in the first direction and the third direction and electrically connected to the plurality of first wirings; and a resistor provided in a current path between the plurality of first wirings and the fifth wiring, The position of the first via wiring in the second direction is between the position of the second via wiring in the second direction and the position of the fifth wiring in the second direction.

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