Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first conductor, first and second insulators, a memory pillar, a second conductor, and first and second films. The first insulators are arranged alternately with the first conductors in the first direction in the first region. The second insulators are arranged alternately with the first insulators in the first direction in the second region. The memory pillar passes through the first conductor and the first insulator in the first region, and includes a semiconductor and a film. The second conductor has first, second, and third portions, the second portion electrically connecting the first portion and the third portion, and the third portion electrically connecting the semiconductor. The first film extends in the first direction in the second region and has an angle with respect to the first direction. The second film is in contact with the first film, extends in the first direction, and has an angle with respect to the first direction. The at least one second insulator includes a portion extending along the first and second films in the second region.

Description

[0001] [Reference to related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2023-155519 (filing date: September 21, 2023). The present application incorporates all the contents of the basic application by reference. Technical Field

[0003] Embodiments generally relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0004] A semiconductor memory device is known in which memory cells are arranged three-dimensionally. In order to increase the storage capacity of a semiconductor memory device, the components of the semiconductor memory device are becoming increasingly miniaturized. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor memory device having less variation in electrical characteristics and a method for manufacturing the semiconductor memory device.

[0006] A semiconductor memory device according to an embodiment includes a plurality of first conductors, a plurality of first insulators, a plurality of second insulators, a memory column, a second conductor, a first film, and a second film. The plurality of first insulators are arranged alternately with the plurality of first conductors one by one in a first region in a first direction. The plurality of second insulators are arranged alternately with the plurality of first insulators one by one in a second region in the first direction. The memory column is a memory column that penetrates the plurality of first conductors and the plurality of first insulators in the first region, and the memory column includes a semiconductor and a film surrounding the side surface of the semiconductor. The second conductor includes a first portion, a second portion, and a third portion, the second portion electrically connects the first portion to the third portion, and the side surface of the third portion is electrically connected to the semiconductor. The first film extends along the first direction in the second region and has an angle with respect to the first direction. The second film is in contact with the first film, extends along the first direction and has an angle with respect to the first direction, and includes carbon or metal. At least one of the plurality of second insulators includes a portion extending along the first film and the second film in the second region, and the portion is located at a position separated from the second film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is an example showing components of the semiconductor memory device according to the first embodiment and connections between the components.

[0008] Figure 2The diagram shows components of one block of the semiconductor memory device according to the first embodiment and connections between the components.

[0009] Figure 3 The basic structure of the semiconductor memory device according to the first embodiment is schematically shown.

[0010] Figure 4 This is an example of a structure along a plane of a portion of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 This is an example of a cross-sectional structure schematically showing a portion of the semiconductor memory device according to the first embodiment.

[0012] Figure 6 FIG. 1 is an example of a cross-sectional structure of a memory column in the semiconductor memory device according to the first embodiment.

[0013] Figure 7 This is an example of a cross-sectional structure of a portion of the semiconductor memory device according to the first embodiment.

[0014] Figure 8 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0015] Fig. 9 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0016] Fig.10 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0017] Fig.11 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0018] Fig.12 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0019] Fig.13 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0020] Fig.14 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0021] Fig.15 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0022] Fig.16 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0023] Fig.17 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0024] Fig.18 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0025] Fig.19 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0026] Fig. 20 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0027] Fig.21 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0028] Fig. 22 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0029] Fig.23 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0030] Fig.24 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0031] Fig.25 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0032] Fig.26 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0033] Fig. 27 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0034] Fig.28 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0035] Fig.29This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0036] Fig.30 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the first embodiment.

[0037] Fig.31 This is an example of a cross-sectional structure schematically showing a portion of the semiconductor memory device according to the second embodiment.

[0038] Fig.32 This is an example of a cross-sectional structure of a portion of the semiconductor memory device according to the second embodiment.

[0039] Fig.33 This is an example of a cross-sectional structure of a portion during the manufacturing process of the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0040] The following describes the embodiments with reference to the accompanying drawings. In order to distinguish between multiple components having substantially the same function and structure in a certain embodiment or different embodiments, there is a case where numbers or letters are further added to the end of the reference symbol. In the subsequent embodiments of a certain embodiment, the main aspects different from the embodiments described are described. All descriptions of a certain embodiment are also applicable as descriptions of other embodiments as long as they are not explicitly or naturally excluded.

[0041] The drawings are schematic diagrams, and the relationship between thickness and plane size, the ratio of thickness of each layer, etc. may be different from the actual object. In addition, the drawings may also include parts with different dimensional relationships, arrangements, and (or) ratios.

[0042] 1. First Implementation Method

[0043] 1.1. Composition (structure)

[0044] Figure 1 The semiconductor memory device 1 is an example of components and connections of the components of the first embodiment. The semiconductor memory device 1 is a device that uses a storage unit to store data. The semiconductor memory device 1 is controlled by an external memory controller. The semiconductor memory device 1 operates, for example, according to a command CMD and address information ADD received from the memory controller. The semiconductor memory device 1 receives written data DAT and outputs the data stored in the semiconductor memory device 1.

[0045] The semiconductor memory device 1 includes components such as a memory cell array 10 , a row decoder 11 , a register 12 , a sequencer 13 , a voltage generating circuit 14 , a driver 15 , and a sense amplifier 17 .

[0046] The memory cell array 10 is a collection of arranged memory cells. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK. Each block BLK includes a plurality of memory cell transistors MT (not shown). The memory cell array 10 is also provided with wiring such as word lines WL (not shown) and bit lines BL (not shown).

[0047] The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transmits a voltage supplied from the driver 15 to one block BLK selected based on a block address received from the register 12 by the row decoder 11 .

[0048] The register 12 is a circuit for storing the command CMD and address information ADD received by the semiconductor memory device 1. The command CMD instructs the sequencer 13 to perform various operations including data reading, data writing, and data erasing. The address information ADD specifies the target of access in the memory cell array 10.

[0049] The sequencer 13 is a circuit for controlling the overall operation of the semiconductor memory device 1. The sequencer 13 controls the row decoder 11, the driver 15, and the sense amplifier 17 according to the command CMD received by the sequencer 13 to perform various operations including data reading, data writing, and data erasing.

[0050] The voltage generating circuit 14 is a circuit that generates a plurality of voltages of different magnitudes. The voltage generating circuit 14 receives a power supply voltage from outside the semiconductor memory device 1 and generates a plurality of voltages from the power supply voltage. The voltage generating circuit 14 supplies the generated voltage to components such as the memory cell array 10, the driver 15, and the sense amplifier 17.

[0051] The driver 15 is a circuit that applies various voltages required for the operation of the semiconductor memory device 1 to some components. The driver 15 receives a plurality of voltages from the voltage generating circuit 14 and supplies a voltage selected from the plurality of voltages to one or more row decoders 11 .

[0052] The sense amplifier 17 is a circuit that outputs a signal based on data stored in the memory cell array 10. The sense amplifier 17 senses the state of the memory cell transistor MT, generates read data according to the sensed state, and applies a voltage based on write data to the bit line BL.

[0053] 1.1.1. Memory cell array

[0054] Figure 2 1 is a diagram showing components of one block of the semiconductor memory device according to the first embodiment and connections of the components. A plurality of blocks BLK, for example, all blocks BLK include Figure 2 The components and connections shown.

[0055] One block BLK includes multiple string components SU. Figure 2 An example of five string units SU_0 to SU_4 is shown.

[0056] like Figure 2 As shown, each of the m bit lines BL_0 to BL_m-1 is connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK. m is a positive integer.

[0057] Each NAND string NS includes a selection gate transistor ST, n memory cell transistors MT (MT_0 to MT_n-1), and a selection gate transistor DT (DT0, DT1, DT2, DT3, or DT4). n is a positive integer. The memory cell transistor MT is an element that stores data non-volatilely. The memory cell transistor MT includes a control gate electrode or a gate electrode (word line WL), and a charge storage film insulated from the surroundings, and stores data non-volatilely according to the charge in the charge storage film. The memory cell transistor MT writes data by injecting electrons into the charge storage film.

[0058] The selection gate transistor ST, the memory cell transistors MT_0 to MT_n-1, and the selection gate transistor DT are connected in series in this order between the source line SL and one bit line BL.

[0059] Multiple NAND strings NS connected to different bit lines BL constitute a string unit SU. In each string unit SU, control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A group of memory cell transistors MT sharing a word line WL in a string unit SU is called a unit unit CU.

[0060] The select gate transistors DT0 to DT4 belong to the string components SU_0 to SU_4 respectively. Figure 2 , the select gate transistors DT2, DT3, and DT4 are omitted from the illustration. The gate of the select gate transistor DT0 of each of the multiple NAND strings NS of the string component SU_0 is connected to the select gate line SGDL0. Similarly, the gate of the select gate transistors DT1, DT2, DT3, and DT4 of each of the multiple NAND strings NS of the string components SU_1, SU_2, SU_3, and SU_4 is connected to the select gate lines SGDL1, SGDL2, SGDL3, and SGDL4.

[0061] The gate of the select gate transistor ST is connected to the select gate line SGSL.

[0062] 1.1.2. Basic structure of semiconductor memory device

[0063] Figure 3 FIG. 2 schematically shows the basic structure of the semiconductor memory device according to the first embodiment. Figure 3 As shown, the semiconductor memory device 1 includes a first structure 100 and a second structure 200 arranged along the Z axis. The first structure and the second structure extend along a certain surface. The extended surface of the first structure and the second structure is called an XY plane. The XY plane includes an X axis and a Y axis that are orthogonal to each other. The direction along the X axis is called an X direction or a +X direction. The direction along the Y axis is called a Y direction or a +Y direction. The direction orthogonal to the XY plane and from the first structure 100 toward the second structure 200 is called a Z direction or a +Z direction.

[0064] The first structure 100 and the second structure 200 are manufactured separately and then bonded to each other. Specifically, the second structure 200 is formed to be inverted with respect to the XY plane, and the formed structure is inverted with respect to the XY plane, and the first structure 100 and the second structure 200 are bonded. Figure 3 For ease of understanding, the state before bonding is shown.

[0065] The first structure 100 includes a plurality of conductive bonding pads BP1. The second structure 200 includes a plurality of conductive bonding pads BP2. Each bonding pad BP1 of the first structure 100 faces one bonding pad BP2 of the second structure 200. After the first structure 100 and the second structure 200 are bonded, each bonding pad BP1 of the first structure is in contact with one bonding pad BP2 of the second structure 200.

[0066] In one example, the first structure 100 includes a structure that functions as a constituent element of the memory cell array 10. In one example, the second structure 200 includes a structure that functions as a constituent element of the row decoder 11, the register 12, the sequencer 13, the voltage generating circuit 14, the driver 15, and the sense amplifier 17.

[0067] 1.1.3. Structure of semiconductor memory device

[0068] Figure 4 This is an example of a structure along a plane of a portion of the semiconductor memory device according to the first embodiment. Figure 4 1 shows the structure of the semiconductor memory device 1 when viewed from the +Z direction. The semiconductor device 1 extends along the XY plane. The semiconductor device 1 has a quadrilateral shape. The semiconductor device 1 includes a cell region CA, a wall region WA, and a peripheral region PA.

[0069] The cell region CA is located in a region including the center of the region along the XY plane of the semiconductor device 1. The cell region CA is a region including the memory cell transistor MT.

[0070] The wall region WA is a region surrounding the cell region CA along the XY plane. The wall region WA has a square ring shape. The wall region WA includes one or more sealing members. Figure 4 An example of three sealing components ES1, ES2, and ES3 is shown. Sealing components ES1, ES2, and ES3 have a square ring shape. Sealing component ES2 surrounds sealing component ES1 along the XY plane. Sealing component ES3 surrounds sealing component ES3 along the XY plane. Sealing components ES1, ES2, and ES3 each extend in the +Z direction and include a plurality of conductor groups connected to each other. One or more of sealing components ES1, ES2, and ES3 have the function of fixing the periphery of semiconductor device 1 to the same potential (for example, ground potential VSS), stabilizing the potential of power lines, wells, etc., and (or) escaping static electricity to the substrate 21 described below.

[0071] The peripheral area PA is an area surrounding the wall area WA along the XY plane. The peripheral area PA has a square ring shape. The peripheral area PA is the outermost area along the XY plane of the semiconductor device 1. The peripheral area PA does not include the circuits required for the operation of the semiconductor storage device 1, such as the memory cell array 10, the row decoder 11, the register 12, the sequencer 13, the voltage generating circuit 14, the driver 15, and the sense amplifier 17, and does not include the elements and conductors included in such circuits. In addition, the peripheral area PA does not include sealing components such as the sealing components ES1, ES2, and ES3.

[0072] Figure 5 This is an example of a cross-sectional structure schematically showing a portion of the semiconductor memory device according to the first embodiment. Figure 5 It represents the structure along the XZ plane. Figure 5 A portion of the structure shown will be described in detail later. Figure 5 In the description, the Z direction refers to the upper direction, the -Z direction refers to the lower direction, the Y direction refers to the right direction, and the -Y direction refers to the left direction.

[0073] like Figure 5 As shown, the first structure 100 further includes a substrate 21 of a semiconductor such as silicon, a MOS (Metal Oxide Semiconductor) transistor Tr, a conductor group 22, and an insulator 23.

[0074] The transistor Tr is located in a region including the upper surface and the upper surface of the substrate 21. The conductor group 22 includes a plurality of conductors. The conductors adjacent to each other in the Z direction in the conductor group 22 are in contact with each other. The conductor group 22 is connected to the bonding pad PD1 at its upper end.

[0075] In the first structure 100, an insulator 23 is provided in a region from the upper surface of the substrate 21 to the upper surface of the bonding pad PD1. In one example, the insulator 23 includes silicon oxide.

[0076] The second structure 200 includes the cell area CA and the peripheral area PA. The second structure 200 further includes the conductor group 26, the conductor 27, the conductor 28, the conductor 31, the insulator 30, the insulator 32, the conductor 33, the insulator 34, the insulator 36, the conductor 38, the insulator 39, the insulator 41, the conductor 42, the insulator 43, the insulator 45, the conductor 46, and the conductor 47 in the cell area CA.

[0077] The lower surface of the bonding pad PD2 is in contact with the upper surface of the bonding pad PD1.

[0078] The conductor group 26 includes a plurality of conductors. The conductors adjacent to each other in the Z direction in the conductor group 26 are in contact with each other. The lower surface of the conductor group 26 is connected to the upper surface of one bonding pad PD2.

[0079] Each conductor 27 is disposed on the upper surface of one conductor group 26 . The conductor 27 functions as one bit line BL. In one example, the conductor 27 includes tungsten. Each conductor 28 is disposed on the upper surface of the conductor 27 .

[0080] The conductor 31 is disposed above the layer of the conductor 28 in the cell area CA. The conductor 31 extends along the XY plane and has a plate-like shape. The conductor 31 functions as at least a portion of the selection gate line SGDL. In one example, the conductor 31 includes tungsten. The conductor 31 may further include a conductor such as aluminum oxide on the surface.

[0081] The insulator 30 is disposed in a region extending from the lower surface of the second structure 200 to the conductor 31. The insulator 30 extends over the cell area CA and the peripheral area PA. In one example, the insulator 30 includes silicon oxide.

[0082] The insulator 32 is disposed on the upper surface of the conductor 31. The insulator 32 extends along the XY plane and has a plate-like shape. The insulator 32 extends across the cell area CA and the peripheral area PA. In one example, the insulator 32 includes silicon oxide.

[0083] A plurality of conductors 33 and a plurality of insulators 34 are alternately arranged one by one along the Z direction on the upper surface of the insulator 32 in the cell area CA. Therefore, the conductors 33 are separated from each other or arranged along the Z direction with intervals. The conductors 33 and the insulators 34 extend along the XY plane and have a plate-like shape. Each conductor 33 functions as at least a part of the word line WL. In one example, the conductor 33 includes tungsten. The conductor 33 may further include a conductor such as aluminum oxide on the surface. In one example, the insulator 34 includes silicon oxide.

[0084] The insulator 36 is arranged on the upper surface of the uppermost conductor 33. The insulator 36 extends along the XY plane and has a plate-like shape. The insulator 36 extends across the cell area CA and the peripheral area PA. In one example, the insulator 36 includes silicon oxide. The insulator 36 includes a concave portion 361 and a convex portion 362 in the peripheral area PA. The concave portion 361 is concave toward the Z direction. The convex portion 362 is located above the concave portion 361.

[0085] A plurality of conductors 38 and a plurality of insulators 39 are alternately arranged one by one along the Z direction on the upper surface of the insulator 36 in the cell area CA. Therefore, the conductors 38 are separated from each other or arranged along the Z direction with intervals. The conductors 38 and the insulators 39 extend along the XY plane and have a plate-like shape. Each conductor 38 functions as at least a part of the word line WL. In one example, the conductor 38 includes tungsten. The conductor 38 may further include a conductor such as aluminum oxide on the surface. In one example, the insulator 39 includes silicon oxide.

[0086] The insulator 41 is disposed on the upper surface of the uppermost conductor 38. The insulator 41 extends along the XY plane and has a plate-like shape. The insulator 41 extends across the cell area CA and the peripheral area PA. In one example, the insulator 41 includes silicon oxide.

[0087] The conductor 42 is disposed on the upper surface of the insulator 41. The conductor 42 extends along the XY plane and has a plate-like shape. The conductor 42 functions as at least a portion of the selection gate line SGSL. In one example, the conductor 42 includes tungsten. The conductor 42 may further include a conductor such as aluminum oxide on the surface.

[0088] The insulator 43 is disposed on the upper surface of the conductor 42. The insulator 43 extends along the XY plane and has a plate-like shape. The insulator 43 extends across the cell area CA and the peripheral area PA. In one example, the insulator 43 includes silicon oxide.

[0089] The memory column MP is arranged in the cell area CA. The memory column MP extends along the Z direction and has a column shape. The memory column MP is arranged in a laminated structure including the conductors 31, 33, 38, and 42 and the insulators 30, 32, 34, 36, 39, 41, and 43. The memory column MP penetrates the group of the conductors 31, 33, 38, and 42 and the insulators 30, 32, 34, 36, 39, 41, and 43. The memory column MP has a lower surface located in the insulator 30.

[0090] Each memory column MP includes a memory column LMP and a memory column UMP. The lower surface of the memory column LMP is connected to the upper surface of the memory column UMP. The memory column LMP passes through the group of conductors 38 and 42 and insulators 36, 39, 41, and 43. The memory column LMP has an upper surface located in the insulator 45 and a lower surface located in the insulator 36. The memory column UMP passes through the group of conductors 31 and 33 and insulators 30, 32, 34, and 36. The memory column UMP has a lower surface located in the insulator 30.

[0091] The memory columns LMP and UMP each have an XY area that decreases from the lower surface toward the upper surface. The XY area is the area of ​​the surface along the XY plane. The XY area of ​​the lower surface of the memory column LMP is larger than the XY area of ​​the upper surface of the memory column UMP. Therefore, the side of the memory column LMP deviates from the extension line of the side of the memory column UMP and is inconsistent. Therefore, the XY area of ​​the memory column MP changes continuously along the Z axis with the change of position toward the Z direction, and on the other hand, changes discontinuously before and after the boundary between the memory column LMP and UMP. The deviation of the side of the memory column LMP from the extension line of the side of the memory column UMP is not limited to Figure 4 It occurs in the XZ section shown, and also in other sections containing the Z axis.

[0092] Each memory column MP includes a core 50, a semiconductor 51, and a laminate 52. The core 50 extends along the Z direction and has a column shape. The side of the core 50 extends along the side of the memory column MP. That is, the core 50 includes a portion included in the memory column LMP and a portion included in the memory column UMP. The lower surface of the portion of the core 50 included in the memory column LMP is connected to the upper surface of the portion included in the memory column UMP. The portion of the core 50 included in the memory column LMP and the portion included in the memory column UMP each have an XY area that decreases from the lower surface toward the upper surface. In one example, the core 50 includes silicon oxide.

[0093] The semiconductor 51 covers the surface of the core 50. The side surface of the semiconductor 51 extends along the side surface of the memory pillar MP. In one example, the semiconductor 51 includes silicon. The uppermost portion of the semiconductor 51 has a groove 511. The groove 511 extends along the Z direction. The upper end of the groove 511 reaches above the upper surface of the insulator 43. The uppermost portion of the semiconductor 51 extends along the XY plane above the insulator 43. For the structure of the uppermost portion of the semiconductor 51, refer to Figure 7 , which will be described in detail later.

[0094] The laminate 52 covers the side surfaces of the semiconductor 51 . The side surfaces of the laminate 52 extend along the side surfaces of the memory pillars MP. The uppermost portion of the laminate 52 is located above the upper surface of the insulator 43 .

[0095] The portion of the memory column MP facing the conductor 31 functions as a selection gate transistor DT. The portion of the memory column MP facing a conductor 33 or 38 functions as a memory cell transistor MT. The portion of the memory column MP facing the conductor 42 functions as a selection gate transistor DT. A plurality of conductors 31 are provided, and the portion of the plurality of conductors 31 facing the memory column MP can also function as a plurality of selection gate transistors DT connected in series. A plurality of conductors 42 are provided, and the portion of the plurality of conductors 42 facing the memory column MP can also function as a plurality of selection gate transistors ST connected in series.

[0096] The insulator 45 is arranged on the upper surface of the insulator 43. The insulator 45 extends along the XY plane and has a plate-like shape. The insulator 45 extends across the cell area CA and the peripheral area PA. The insulator 45 has an opening 451 extending from the upper surface to the lower surface above the memory column MP. The uppermost portion of the memory column MP is located in the opening 451. In one example, the insulator 45 includes silicon oxide.

[0097] The conductor 46 is disposed on the upper surface of the insulator 43. The conductor 46 has a portion located on the side surface of the insulator 45 in the opening 451 of the insulator 45. The conductor 46 covers the surface of the groove 511 of the semiconductor 51, and covers the semiconductor 51 in the groove 511. In one example, the conductor 46 includes titanium and (or) titanium nitride. The structure of the portion of the conductor 46 above the memory pillar MP will be described with reference to FIG. Figure 7 , which will be described in detail later.

[0098] The conductor 47 covers the conductor 46. The conductor 47 functions as at least a part of the source line SL. In one example, the conductor 47 includes tungsten.

[0099] The peripheral area PA of the second structure 200 further includes insulators SM1 , SM2 , SM3 , SM4 , and spacer films 61 , 62 , 63 , and 64 .

[0100] The insulator SM1 is disposed between the insulator 30 and the insulator 32. The insulator SM1 extends along the XY plane and has a plate-like shape. In one example, the insulator SM1 includes silicon nitride.

[0101] A plurality of insulators SM2 and a plurality of insulators 34 are alternately arranged one by one along the Z direction on the upper surface of the insulator 32. Therefore, the insulators SM2 are separated from each other or arranged along the Z direction with intervals. The insulator SM2 extends along the XY plane and has a plate-like shape. In one example, the insulator SM2 includes silicon nitride. The plurality of insulators SM2 arranged along the Z direction including the top and the plurality of adjacent insulators 34 including the top have a portion protruding in the Z direction in the recess 361.

[0102] The insulator 36 is arranged on the upper surface of the uppermost insulator SM2 in the peripheral area PA.

[0103] A plurality of insulators SM3 and a plurality of insulators 39 are alternately arranged one by one along the Z direction on the upper surface of the insulator 36. Therefore, the insulators SM3 are separated from each other or arranged along the Z direction with intervals. The insulator SM3 extends along the XY plane and has a plate-like shape. In one example, the insulator SM3 includes silicon nitride. The plurality of insulators SM3 arranged along the Z direction including the bottom and the plurality of insulators 39 arranged along the Z direction including the bottom have a portion protruding in the Z direction along the convex portion 362.

[0104] The insulator 41 is disposed on the upper surface of the uppermost insulator SM3 , and has a portion protruding in the Z direction along the convex portion 362 .

[0105] The insulator SM4 is disposed on the upper surface of the insulator 41. The insulator SM4 extends along the XY plane and has a plate-like shape. In one example, the insulator SM4 includes silicon nitride. The insulator SM4 has a portion protruding in the Z direction along the convex portion 362.

[0106] The spacer membrane 61 is located in the insulator 36. The spacer membrane 61 extends along the Z direction and has an angle relative to the Z axis. The two spacer membranes 61 are two independent parts of the original one membrane. The two spacer membranes 61 have a line symmetric relationship with respect to the YZ plane. The interval between the upper ends of the two spacer membranes 61 is narrower than the interval between the lower ends of the two spacer membranes 61. The two spacer membranes 61 are located in the recess 361. The two spacer membranes 61 surround the portions of the insulators SM2 and 34 that protrude in the Z direction. The portions of the insulators SM2 and 34 that protrude in the Z direction have portions extending along each spacer membrane 61. The lower end of the spacer membrane 61 is aligned with the boundary between the memory column LMP and the memory column UMP. Examples of the spacer membrane 61 include polysilicon, silicon oxide, and carbon.

[0107] The spacer membrane 62 extends along the Z direction and has an angle relative to the Z axis. The two spacer membranes 62 are two independent parts of the original one membrane. The two spacer membranes 62 have a line symmetric relationship about the YZ plane. The interval between the upper ends of the two spacer membranes 62 is narrower than the interval between the lower ends of the two spacer membranes 62. The lower end of the spacer membrane 62 is parallel to the boundary between the memory column LMP and the memory column UMP. The group of two spacer membranes 62 is located on the inner side of the group of two spacer membranes 61. Each spacer membrane 62 is configured on the side of one spacer membrane 61. The spacer membrane 62 on the left side is configured on the side of the right side of the spacer membrane 61 on the left side. The spacer membrane 62 on the right side is configured on the side of the left side of the spacer membrane 61 on the right side. The material of the spacer membrane 62 is different from the material of the insulators SM2, 34, 32, SM1, and 30. In one example, the spacer membrane 62 contains carbon or metal.

[0108] The spacer film 63 is located in the insulator 45. The spacer film 63 extends along the Z direction and has an angle with respect to the Z axis. The two spacer films 63 are two independent parts of the original one film. The two spacer films 63 have a line symmetric relationship with respect to the YZ plane. The interval between the upper ends of the two spacer films 63 is narrower than the interval between the lower ends of the two spacer films 63. The two spacer films 63 surround the portions of the insulators SM3, SM4, and 39 protruding in the Z direction. The portions of the insulators SM3 and 39 protruding in the Z direction have portions extending along each spacer film 63. The spacer film 63 is arranged on the layer of the conductor 42 close to the Z direction. In one example, the spacer film 63 includes polysilicon.

[0109] The spacer membrane 64 extends along the Z direction and has an angle with respect to the Z axis. The two spacer membranes 64 are two independent parts of the original one membrane. The two spacer membranes 64 have a line symmetric relationship with respect to the YZ plane. The interval between the upper ends of the two spacer membranes 64 is narrower than the interval between the lower ends of the two spacer membranes 64. The group of two spacer membranes 64 is located inside the group of two spacer membranes 63. Each spacer membrane 64 is arranged on the side of one spacer membrane 63. The spacer membrane 64 on the left side is arranged on the side of the right side of the spacer membrane 63 on the left side. The spacer membrane 64 on the right side is arranged on the side of the left side of the spacer membrane 63 on the right side. The material of the spacer membrane 64 is different from the material of the insulator 43, SM4, 41, SM3, 39, and 36. In one example, the spacer membrane 64 includes carbon or metal.

[0110] Figure 6 FIG. 1 is an example of a cross-sectional structure of a memory column of a semiconductor memory device according to the first embodiment. Specifically, Figure 6 It means along Figure 5 The cross section of the VI-VI line. Figure 6 As shown, in one example, the laminate 52 includes a tunnel insulator 53 , a charge storage film 54 , and a blocking insulator 55 .

[0111] The tunnel insulator 53 surrounds the side surface of the semiconductor 51. The charge storage film 54 surrounds the side surface of the tunnel insulator 53. The blocking insulator 55 surrounds the side surface of the charge storage film 54. The conductor 33 surrounds the side surface of the blocking insulator 55.

[0112] The semiconductor 51 functions as a channel (current path) of the memory cell transistor MT and the select gate transistors DT and ST. The tunnel insulator 53 and the blocking insulator 55 each include, for example, silicon oxide. The charge storage film 54 stores charges. The charge storage film 54 includes, for example, silicon nitride.

[0113] Figure 7 This is an example of a cross-sectional structure of a portion of the semiconductor memory device according to the first embodiment. Figure 7 Will Figure 6 The uppermost portion of the structure shown is shown enlarged and represents the unit area CA. Figure 7 In the description, the Z direction refers to the upper direction, the -Z direction refers to the lower direction, the Y direction refers to the right direction, and the -Y direction refers to the left direction.

[0114] The uppermost portion of the blocking insulator 55 includes a portion located on the upper surface of the insulator 43 and a portion located on the side surface of the insulator 45 .

[0115] The uppermost portion of the charge storage film 54 has a shape along the shape of the blocking insulator 55 and covers the surface of the blocking insulator 55. That is, the uppermost portion of the charge storage film 54 includes a portion extending along the XY plane above the insulator 43 and a portion extending along the Z direction.

[0116] The uppermost portion of the tunnel insulator 53 has a shape along the shape of the charge storage film 54 and covers the surface of the charge storage film 54. That is, the uppermost portion of the tunnel insulator 53 includes a portion extending along the XY plane above the insulator 43 and a portion extending along the Z direction.

[0117] The bottom of the groove 511 of the semiconductor 51 is in contact with the upper surface of the core 50. The portion of the semiconductor 51 surrounding the side of the groove 511 covers the surface of the tunnel insulator 53. The uppermost portion of the semiconductor 51 has a shape along the shape of the tunnel insulator 53 and covers the surface of the tunnel insulator 53. That is, the uppermost portion of the semiconductor 51 includes a portion extending along the XY plane above the insulator 43 and a portion extending along the Z direction.

[0118] The conductor 46 covers the upper surface of the insulator 45, the portion of the side surface of the insulator 45 not covered by the blocking insulator 55, the upper surface of the blocking insulator 55, the upper surface of the charge storage film 54, the upper surface of the tunnel insulator 53, the upper surface of the semiconductor 51, and the surface of the groove 511 of the semiconductor 51.

[0119] The conductor 47 covers the surface of the conductor 46. The conductor 47 includes a first portion 471, a plurality of second portions 472, and a plurality of third portions 473. The first portion 471 occupies the uppermost portion of the conductor 47 and has a straight line shape extending in the X direction. Each second portion 472 occupies a portion in the opening 451 of the insulator 45. The upper end of each second portion 472 is connected to the lower surface of the first portion 471. Each third portion 473 occupies a portion in one groove 511 of the semiconductor 51. The third portion 473 extends along the Z direction. The upper end of each third portion 473 is connected to the lower end of one second portion 472.

[0120] 1.2. Manufacturing method

[0121] Figure 8 to Figure 30 The cross-sectional structures during the manufacturing process of the semiconductor memory device according to the first embodiment are sequentially shown. Figure 8 to Figure 26 express Figure 5 The region shown represents the first structure 100 . Figure 27 to Figure 30 express Figure 7 The area shown.

[0122] The first structure 100 is sequentially formed along the −Z direction toward the −Z direction, and then the structure of the first structure 100 in the process of being manufactured is inverted with respect to the XY plane and bonded to the second structure 200 . Figure 8 to Figure 26 express Figure 5 The first structure 100 shown in FIG. 1 is in the state of being reversed upside down. Figure 8 to Figure 26 In the description of , “up” refers to the -Z direction and “down” refers to the Z direction.

[0123] like Figure 8 As shown, an insulator 72 is deposited on the upper surface of a substrate 71 such as silicon. Examples of deposition methods include CVD (Chemical Vapor Deposition). The substrate 71 and the insulator 72 extend along the XY plane. In one example, the insulator 72 includes silicon oxide.

[0124] On the upper surface of the insulator 72, a film 73 is formed. The film 73 extends along the XY plane. The film 73 includes the same material as the spacer film 63.

[0125] An insulator 45A is formed on the upper surface of the film 73. The insulator 45A is an element formed into the insulator 45 in a subsequent step. The insulator 45A extends along the XY plane.

[0126] like Fig. 9 As shown, the opening 451 is formed by partially removing the insulator 45A. Specifically, on the upper surface of the insulator 45A, a mask having an opening is formed above a predetermined area where the opening 451 is to be formed, and the insulator 45 is partially removed by anisotropic etching through the opening of the mask. Examples of anisotropic etching include RIE (Reactive Ion Etching). The opening 451 extends from the upper surface of the insulator 45A to the lower surface. By forming the opening 451, the insulator 45B in the insulator 45A remains. In one example, the upper end of the opening 451 has an XY area that is smaller than the lower end. The XY area is the area along the XY plane.

[0127] like Fig.10 As shown, a film 63A is deposited. Examples of the deposition method include CVD. The film 63A is an element formed into the spacer film 63 in a subsequent process. The film 63A covers the upper surface of the insulator 45B and fills the opening 451 in the cell area CA. The film 63A covers the surface of the opening 451 in the peripheral area PA.

[0128] like Fig.11As shown in FIG. 1 , the film 63A is partially removed by etching back. The portion of the film 63A on the upper surface of the insulator 45B is removed. The film 63A remains in the opening 451 in the cell area CA and becomes the film 63B. The film 63B is only located at the lower part in the opening 451. The height of the portion of the film 63A removed from the upper surface is very small compared to the height of the memory pillar MP. Therefore, the position of the upper surface of the film 63B is less uneven.

[0129] The film 63A has a portion on the bottom surface of the opening 451 removed in the peripheral region PA. The portion on the side surface of the opening 451 in the peripheral region PA of the film 63A is thinned to form the spacer film 63 .

[0130] like Fig.12 As shown, a film 64A is deposited. Examples of the deposition method include CVD. The film 64A is an element formed into the spacer film 64 in a subsequent process. The material of the film 64A includes a material different from the material of the insulators 43, SM4, 41, SM3, 39, and 36. The film 64A covers the upper surface of the insulator 45B. The film 64A also fills the area of ​​the opening 451 in the cell area CA that is not filled by the film 63B. The film 64A covers the spacer film 63 in the peripheral area PA and covers the bottom surface of the opening 451.

[0131] like Fig.13 As shown in FIG. 1 , the film 64A is partially removed by etching back. The portion of the film 64A on the upper surface of the insulator 45B is removed. The film 64A remains in the opening 451 in the cell region CA and becomes the film 64B. Fig.10 As described above, since the positional variation of the upper surface of the film 63B is small, the positional variation of the lower surface of the film 64B is also small. The film 64A is removed from the bottom surface of the opening 451 in the peripheral area PA. The portion of the film 64A on the spacer film 63 remains and becomes the spacer film 64.

[0132] like Fig.14As shown, a laminate including insulators 43, SM4, 41, SM3, 39, and 36 is deposited. Examples of deposition methods include CVD. Insulator SM4 is deposited on the upper surface of insulator 43. Insulator 41 is deposited on the upper surface of insulator SM4. Insulators SM3 and 39 are deposited alternately one by one on the upper surface of insulator 41. Insulator 36 is deposited on the upper surface of the uppermost insulator SM3. Insulator SM4 occupies a predetermined area for forming conductor 42. Insulator SM3 occupies a predetermined area for forming conductor 38. The laminate is formed on the upper surface of insulator 45B and film 64B in unit area CA. In peripheral area PA, a portion of the lowermost portion of the laminate is located in opening 451. Opening 451 of peripheral area PA is filled with a portion of the laminate. Since a portion of the lower portion of the laminate is located in opening 451, a concave portion 361 and a convex portion 362 of insulator 36 are formed above opening 451.

[0133] like Fig.15 As shown, a memory hole LMH is formed. Specifically, first, a mask is formed. The mask has an opening above a predetermined area where the memory pillar LMP is to be formed. Using the mask, anisotropic etching such as RIE is performed. As a result, the laminate including the insulator 43, SM4, 41, SM3, 39, and 36 is partially removed to form a memory hole LMH. The memory hole LMH extends along the Z direction to reach below the insulator 43.

[0134] The material of the film 64B is different from the material of the insulators 43, SM4, 41, SM3, 39, and 36. Therefore, the film 64B functions as an etching stopper for the insulators 43, SM4, 41, SM3, 39, and 36. That is, the film 64B is only slightly etched by etching the insulators 43, SM4, 41, SM3, 39, and 36. Therefore, the position of the bottom of the memory hole LMH is suppressed from being uneven.

[0135] like Fig.16 As shown in FIG. 1 , the mask and the film 64B of the cell region CA are removed. As a result, the upper portion of the opening 451 is formed again in the cell region CA. The position of the bottom of the upper portion of the opening 451 depends on the position of the upper surface of the film 64B, as shown in FIG. Fig.10 As described above, the positional variation of the upper surface of the film 64B is small. Therefore, the positional variation of the bottom of the upper portion of the opening 451 is small.

[0136] like Fig.17As shown, a film 61A is deposited. Examples of the deposition method include CVD. The film 61A is an element formed into the spacer film 61 in a subsequent process. The film 61A covers the upper surface of the insulator 36. The film 61A fills the upper part of the opening 451 and the memory hole LMH in the cell area CA. The film 61A covers the surface of the recess 361 in the peripheral area PA.

[0137] like Fig.18 As shown in FIG. 1 , the film 61A is partially removed by etching back. The portion on the upper surface of the insulator 36 in the film 61A is removed. The uppermost portion of the portion in the memory hole LMH in the film 61A is removed. As a result, a space is formed at the uppermost portion of the memory hole LMH. The portion other than the uppermost portion in the memory hole LMH in the film 61A remains, forming the film 61B. The portion on the bottom surface of the recess 361 in the peripheral area PA of the film 61A is removed. The portion on the side surface of the recess 361 in the film 61A remains, forming the spacer film 61.

[0138] like Fig.19 As shown, a film 62A is deposited. Examples of the deposition method include CVD. The film 62A is an element formed into the spacer film 62 in a subsequent process. The material of the film 62A is different from the material of the insulators SM2, 34, 32, SM1, and 30. The film 62A covers the upper surface of the insulator 36. The film 62A fills the uppermost part of the memory hole LMH. The film 62A covers the spacer film 61 in the peripheral area PA and covers the bottom of the recess 361.

[0139] like Fig. 20 As shown in FIG. 1 , the film 62A is partially removed by etching back. The portion of the film 62A on the upper surface of the insulator 36 is removed. The film 62A remains at the uppermost portion of the memory hole LMH and becomes the film 62B. The film 62A is partially removed on the bottom surface of the opening 451 in the peripheral area PA. The portion of the film 62A on the spacer film 61 remains and becomes the spacer film 62.

[0140] like Fig.21 As shown, the uppermost portion of the insulator 36 is deposited on the upper surface of the insulator 36 and the film 62B, and then the laminate including the insulators SM2, SM4, SM3, SM1, and SM0 is deposited. Examples of the deposition method include CVD. The uppermost portion of the insulator 36 covers the surface of the recess 361. The insulators SM2 and SM3 are deposited alternately one by one on the upper surface of the insulator 36. The insulator SM2 occupies the predetermined region for forming the conductor 33. The insulator SM1 occupies the predetermined region for forming the conductor 31.

[0141] The insulator 32 is deposited on the upper surface of the uppermost insulator SM2. The insulator SM1 is deposited on the upper surface of the insulator 32. The insulator SM1 occupies a predetermined area for forming the conductor 31. The insulator 30 is deposited on the upper surface of the insulator SM1.

[0142] In the peripheral area PA, a part of the lowermost portion of the laminate is located in the recess 361. The recess 361 is filled with a part of the laminate.

[0143] like Fig. 22 As shown, a memory hole UMH is formed. Specifically, first, a mask 77 is formed. The mask 77 has an opening above a predetermined area where the memory pillar UMP is to be formed. Anisotropic etching such as RIE is performed using the mask 77. Thus, the laminate including the insulators SM2, 34, 32, SM1, and 30 is partially removed to form a memory hole UMH. The memory hole UMH extends along the Z direction to reach below the lowest insulator SM2.

[0144] The material of the film 62B is different from the material of the insulators SM2, 34, 32, SM1, and 30. Therefore, the film 62B functions as an etching stopper for the insulators SM2, 34, 32, SM1, and 30. The uppermost portion of the film 62B is removed by etching.

[0145] like Fig.23 As shown, the mask 77 and the film 62B are removed. Examples of the removal method include wet etching. As a result of the removal of the film 62B, the uppermost portion of the memory hole LMH is formed again, and the upper surface of the film 61B is exposed.

[0146] like Fig.24 As shown, the film 61B is removed. Examples of the removal method include wet etching and ashing. As a result of the removal of the film 61B, the entire memory hole LMH and the upper portion of the opening 451 are formed again.

[0147] like Fig.25 and Fig. 27 As shown, a laminate 52A, a semiconductor 51A, and a core 50A are deposited. The laminate 52A is an element formed into the laminate 52 in a later process. The semiconductor 51A is an element formed into the semiconductor 51 in a later process. The core 50A is an element formed into the core 50 in a later process.

[0148] Specifically, first, a blocking insulator 55A, a charge storage film 54A, a tunnel insulator 53A, a semiconductor 51A, and a core 50A are deposited on the surface of the memory hole UMH and LMH. Examples of the deposition method include CVD. The blocking insulator 55A is an element formed into the blocking insulator 55 in a subsequent process. The charge storage film 54A is an element formed into the charge storage film 54 in a subsequent process. The tunnel insulator 53A is an element formed into the tunnel insulator 53 in a subsequent process. By depositing the core 50A on the surface of the semiconductor 51A, the center of the memory hole UMH and LMH and the center of the upper part of the opening 451 are buried by the core 50A.

[0149] The upper portion of the core 50A is removed, and a semiconductor 51A is formed in the removed portion. The upper surface of the semiconductor 51 is planarized together with the upper surface of the insulator 30. Examples of the planarization method include CMP (Chemical Mechanical Polishing).

[0150] like Fig.26 As shown, in the unit area CA, the insulator SM1 is replaced by the conductor 31, the insulator SM2 is replaced by the conductor 33, the insulator SM4 is replaced by the conductor 42, and the insulator SM3 is replaced by the conductor 38. Specifically, first, the insulators SM1, SM2, SM3, and SM4 are removed. Examples of removal methods include wet etching. The wet etching solution reaches the insulators SM1, SM2, SM3, and SM4 in the slits (not shown) extending along the Z direction in the same manner as the group of memory holes UMH and LMH, and removes the insulators SM1, SM2, SM3, and SM4. As a result, a space is formed in the area where the insulators SM1, SM2, SM3, and SM4 are located. Next, the conductors 31, 33, 38, and 42 are formed in the space. Examples of formation methods include CVD.

[0151] In the subsequent Figure 28 to Figure 30 During the process, the peripheral area is covered by a mask.

[0152] like Fig.28 As shown, the substrate 71 is peeled off, and then the insulator 72 is removed. Examples of the removal method include wet etching.

[0153] The film 63B is removed. Examples of the removal method include wet etching. As a result of the removal, the upper portion of the opening 451 is formed again, and the upper surface of the blocking insulator 55A is exposed.

[0154] like Fig.29As shown, the uppermost portion of the blocking insulator 55A, the charge storage film 54A, the tunnel insulator 53A, the semiconductor 51A, and the core 50A is removed. Examples of the removal method include RIE. The removal is performed until the core 50A is exposed. As a result of the removal, the blocking insulator 55, the charge storage film 54, the tunnel insulator 53, the semiconductor 51A, and the core 50B are formed. In the process of removal, the upper portion of the insulator 45B is also removed to form the insulator 45.

[0155] like Fig.30 As shown, the uppermost portion of the core 50B is removed. Examples of the removal method include wet etching. By the removal, the groove 511 is formed in the removed area and the core 50 is formed.

[0156] like Figure 5 and Figure 7 As shown, a conductor 46 is deposited. Examples of deposition methods include PVD (Physical Vapor Deposition). A conductor 47 is deposited. Examples of deposition methods include CVD.

[0157] 1.3. Advantages (effects)

[0158] According to the first embodiment, as described below, a semiconductor memory device having less variation in electrical characteristics is provided.

[0159] The structure of the reference example for comparison, which is considered to be the same as the first structure 100, is manufactured by the following method. Figure 8 In a process corresponding to the above process, an insulator 45A is formed on the upper surface of the substrate 71. On the upper surface of the insulator 45A, a laminate including insulators 43, SM1, 41, SM2, 39, and 36 is deposited. Fig.15 The memory hole LMH is formed by the same process as the above process. The insulator 45A, the insulator 43, SM4, 41, SM3, 39, and 36 all contain the same material (silicon), so the etching selection between the insulator 45A and the insulators 43, SM4, 41, SM3, 39, and 36 is relatively small. Therefore, the upper surface of the substrate 71 is removed by etching, and a groove is formed in the substrate 71 below the memory hole LMH. In general, etching is inevitably performed at different speeds depending on the location, so the depth of the groove is uneven. In particular, like the memory hole LMH, the deeper the groove, the greater the unevenness of the position of the bottom of the groove. Next, the groove is filled by epitaxially growing a semiconductor such as silicon. Because the depth of the groove is uneven, the height of the upper surface of the semiconductor is uneven.

[0160] Next, on the upper surface of the semiconductor, Fig.16The memory pillars are formed by the same process as the process after the process. Since the memory pillars are located on the upper surface of the semiconductor, the positions of the bottoms of the memory pillars are uneven.

[0161] Then, by referring to Figure 28 to Figure 30 The same process as the above process is performed to form a groove 511 at the uppermost portion of the core 50. At this time, as described above, the depth of the groove 511 is uneven because the positions of the bottoms of the memory pillars are uneven. The depth of the groove 511 affects the area of ​​the surface where the conductor 46 and the conductor 47 are in contact with the semiconductor 51. The uneven depth of the groove makes the contact area uneven. This will lead to uneven electrical characteristics of the memory pillars.

[0162] According to the first embodiment, the spacer films 63 and 64 are provided. The spacer film 63 is provided at the Fig.11 During the described process, the film 63B remains as the film 63B, and the film 63B is formed by etching back the film 63A. The height of the portion of the film 63A removed from the upper surface is very small, so the height variation of the film 63B is small. During the etching process for forming the memory hole LMH, the spacer film 64 is located as the film 64B at the bottom of the predetermined area for forming the memory hole LMH. Moreover, since the film 64B is located on the upper surface of the film 63B with small height variation, the height variation of the lower surface of the film 64B is small. Moreover, since the material of the film 64B is different from the material of the insulators 43, SM4, 41, SM3, 39, and 36, the film 64B functions as a stop layer for etching the insulators 43, SM4, 41, SM3, 39, and 36, and the upper surface of the film 63B is not removed, so that the height variation of the film 63B is maintained small. Therefore, by referring to Fig.28 and Fig.29 The height variation of the upper surface of the core 50B exposed by the etching process described above is small. Fig.30 The depth variation of the groove 511 formed in the above process is small. Therefore, the contact area variation between the group of conductors 46 and 47 and the semiconductor 51 is small. This can suppress the variation of the electrical characteristics of the memory pillar MP. Therefore, it is possible to provide a semiconductor memory device 1 with small variation of electrical characteristics.

[0163] 2. Second Implementation Method

[0164] Based on the first embodiment, the second embodiment is different from the first embodiment in the structure of the memory pillars.

[0165] Fig.31 This is an example of a cross-sectional structure schematically showing a portion of the semiconductor memory device according to the second embodiment. Fig.32 FIG. 2 is a cross-sectional structure of a portion of a semiconductor memory device according to a second embodiment. Fig.31 A part of is shown enlarged. Fig.31 and Fig.32 In the description, the Z direction refers to the upper direction, the -Z direction refers to the lower direction, the Y direction refers to the right direction, and the -Y direction refers to the left direction.

[0166] The memory column UMPb of the semiconductor storage device 1b of the second embodiment includes a first part UMPb1 and a second part UMPb2. The lower surface of the first part UMPb1 is connected to the upper surface of the second part UMPb2. The first part UMPb1 and the second part UMPb2 each have an XY area that decreases from the lower surface toward the upper surface. The XY area of ​​the lower surface of the first part UMPb1 is larger than the XY area of ​​the upper surface of the second part UMPb2. Therefore, the side surface of the first part UMPb1 is deviated from the extension line of the side surface of the second part UMPb2 and is inconsistent. The XY area of ​​the lower surface of the memory column LMP is larger than the XY area of ​​the upper surface of the first part UMPb1. Therefore, the side surface of the memory column LMP is deviated from the extension line of the side surface of the first part UMPb1 and is inconsistent. Therefore, the XY area of ​​the memory column MP changes continuously in the Z direction as the position on the Z axis changes, and on the other hand, changes discontinuously at the boundary between the first part UMPb1 and the second part UMPb2, and at the boundary between the side surface of the LMP and the first part UMPb1. The deviation of the side surface of the first part UMPb1 from the extension line of the side surface of the second part UMPb2, and the deviation of the side surface of the memory column LMP from the extension line of the side surface of the first part UMPb1 are not limited to the deviation of the side surface of the memory column LMP from the extension line of the side surface of the first part UMPb1. Fig.31 It occurs in the XZ section shown, and also in other sections containing the Z axis.

[0167] In the first embodiment, refer to Fig. 22 In the above process, the center of the memory hole UMH and the center of the memory hole LMH are inevitably offset due to the inevitable positional deviation of the mask in the photolithography process for forming the opening of the mask 77. Therefore, in practice, Fig.32 As shown, the center line CLL of the memory pin LMP is offset from the center line CLU of the memory pins UMPb (UMPb1 and UMPb2). The occurrence of the offset between the center line CLL of the memory pin LMP and the center line CLU of the memory pin UMP is also applicable to the first embodiment.

[0168] The side surfaces of the core 50b, the semiconductor 51b, and the laminate 52b extend along the side surfaces of the memory pillar MPb.

[0169] Fig.33 2 is a diagram showing a cross-sectional structure of a semiconductor memory device during manufacturing according to the second embodiment. Fig.31 The region shown represents the first structure 100 . Fig.33 It is indicated that the first embodiment is referred to Fig. 22The construction during the process after the process described. Fig.33 In the description of , “up” refers to the -Z direction and “down” refers to the Z direction.

[0170] To manufacture the semiconductor memory device 1b, first, the process described in the first embodiment is performed. Figures 8 to 22 Next, Fig.33 As shown, a spacer film 79 is deposited. Examples of the deposition method include CVD. In one example, the spacer film 79 includes silicon oxide and (or) carbon. The spacer film 79 covers the upper surface of the insulator 30 and the side surface of the upper portion of the memory hole UMH. At the lower portion of the memory hole UMH, the insulators SM2 and 34 are exposed.

[0171] In the lower part of the memory hole UMH, the insulators SM2 and SM34 are partially removed. Examples of the removal method include wet etching. By removing, the XY area of ​​the region not covered by the spacer film 79 in the lower part of the memory hole UMH is expanded. Thus, the region forming the first portion UMPb1 of the memory pillar UMPb is formed.

[0172] In reference Fig.33 After the steps described above, the first embodiment is performed Figure 23 to Figure 29 Thus, we obtain Fig.31 The structure shown.

[0173] According to the second embodiment, in addition to the same advantages as those of the first embodiment, the following advantages are obtained.

[0174] As the capacity of the semiconductor memory device increases, the memory column MP becomes very long along the Z direction. Therefore, the difference between the XY area of ​​the lower part and the XY area of ​​the upper part of the memory holes UMH and LMH formed by anisotropic etching is large. This will cause the characteristics of the memory cell transistor to vary greatly depending on the layer where the memory cell transistor is located. Therefore, it is preferred that the XY area of ​​the memory hole in each layer has a small variation. Therefore, it is considered that in reference Fig. 22 After the above process, the XY area of ​​the lowest part of the memory hole UMH is enlarged. If the film 61B in the memory hole LMH is exposed at the bottom of the upper memory hole UMH during the XY area enlargement, the film 61B is removed and then the lower memory hole UMH is also enlarged. This will unintentionally increase the difference in the XY area of ​​the entire memory pillar MP.

[0175] According to the second embodiment, a spacer film 62 is provided. The spacer film 62 is provided in the reference Fig.32During the above process, the film 62B remains, and the film 62B covers the upper surface of the film 61B. Therefore, while the width of the memory hole UMH is expanded, the film 61B is removed, and thereby the XY area of ​​the memory hole LMH is prevented from being unintentionally increased. Therefore, a semiconductor memory device 1b with less uneven electrical characteristics can be provided.

[0176] 3. Variations, etc.

[0177] The memory pillar MP may include three or more connected parts. In this case, spacer films 61 and 62 are provided at the boundaries between each two connected parts, and films 61A and 62A that are formed into the spacer films 61 and 62 are provided during the manufacturing process.

[0178] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are also included in the invention described in the claims and the scope equivalent thereto.

[0179] [Explanation of Symbols]

[0180] 1: Semiconductor storage device

[0181] CA:Unit Area

[0182] PA: Surrounding area

[0183] PD1, PD2: Lamination pad

[0184] 21: Substrate

[0185] Tr: Transistor

[0186] 22, 26: Conductor group

[0187] 23, 32, 34, 36, 39, 41, 43, 45: Insulator

[0188] 27, 28, 31, 33, 38, 42, 46, 47: Conductors

[0189] MP, LMP, UMP: Memory column

[0190] 50:Core

[0191] 51: Semiconductors

[0192] 52:Laminated body

[0193] 45: Insulator

[0194] 53: Tunnel insulator

[0195] 54: Charge storage membrane

[0196] 55: Blocking insulator

[0197] 451: Opening

[0198] 511: Slot

[0199] 61, 62, 63, 64: spacer film

[0200] SM1, SM2, SM3, SM4: insulators.

Claims

1. A semiconductor storage device comprising: a plurality of first conductors; A plurality of first insulators are arranged alternately one by one with the plurality of first conductors in a first direction in a first region; a plurality of second insulators arranged alternately one by one with the plurality of first insulators in the second region in the first direction; a memory pillar penetrating the plurality of first conductors and the plurality of first insulators in the first region, wherein the memory pillar includes a semiconductor and a film surrounding a side surface of the semiconductor; a second conductor having a first portion, a second portion, and a third portion, wherein the second portion electrically connects the first portion to the third portion, and a side surface of the third portion is electrically connected to the semiconductor; a first film extending in the second region along the first direction and having an angle with respect to the first direction; as well as a second film, which is in contact with the first film, extends along the first direction, has an angle with respect to the first direction, and comprises carbon or metal; At least one of the plurality of second insulators includes a portion extending along the first film and the second film in the second region, and the portion is located at a position separated from the second film.

2. The semiconductor memory device according to claim 1, further comprising: a third film extending in the second region along the first direction and having an angle with respect to the first direction; and a fourth film, which is in contact with the third film, extends along the first direction, has an angle with respect to the first direction, and contains carbon or metal; The first film is in contact with the side surface of the second film on the second direction side. The set of the first film and the second film is located closer to the second direction than the set of the third film and the fourth film.

3. The semiconductor memory device according to claim 2, wherein The set of the first film and the second film and the set of the third film and the fourth film are arranged along the second direction.

4. The semiconductor memory device according to claim 3, wherein The distance between the upper end of the second film and the upper end of the fourth film is smaller than the distance between the lower end of the second film and the lower end of the fourth film.

5. The semiconductor memory device according to claim 2, further comprising: a fifth film extending in the second region along the first direction; and a sixth film extending along the first direction and in contact with the fifth film; The first film and the second film are located closer to the first direction than the fifth film and the sixth film, and at least one of the plurality of second insulators includes a portion extending along the fifth film and the sixth film in the second region.

6. The semiconductor memory device according to claim 5, further comprising: a seventh film extending in the second region along the first direction; and an eighth film extending along the first direction and contacting the side surface of the seventh film on the second direction side; The fifth film is in contact with the side surface of the sixth film on the second direction side, The set of the fifth film and the sixth film is located closer to the second direction than the set of the seventh film and the eighth film.

7. The semiconductor memory device according to claim 6, wherein The set of the fifth film and the sixth film and the set of the seventh film and the eighth film are arranged along the second direction.

8. The semiconductor memory device according to claim 6, wherein The material of the first film, the material of the second film, the material of the third film, the material of the fourth film, the material of the fifth film, the material of the sixth film, the material of the seventh film, and the material of the eighth film are different from the materials of the multiple first insulators and the materials of the multiple second insulators.

9. The semiconductor memory device according to claim 6, wherein The first film, the third film, the fifth film, and the seventh film include silicon, The second film, the fourth film, the sixth film, and the eighth film include carbon or metal, The plurality of first insulators include silicon oxide, The plurality of second insulators include silicon nitride.

10. The semiconductor memory device according to claim 5, wherein The memory column includes: a fourth portion and a fifth portion connected to the fourth portion in the first direction from the fourth portion. The area of ​​the surface of the memory column intersecting the first direction changes toward the first direction and changes discontinuously at the boundary between the fourth portion and the fifth portion. The fifth film and the sixth film are arranged along the second direction and at the boundary.

11. The semiconductor memory device according to claim 5, wherein The memory column includes: a fourth portion, a fifth portion connected to the fourth portion in the first direction from the fourth portion, and a sixth portion connected to the fifth portion in the first direction from the fifth portion. The area of ​​the surface of the memory pillar intersecting the first direction changes toward the first direction and changes discontinuously at a boundary between the fourth portion and the fifth portion and at a boundary between the fifth portion and the sixth portion.

12. The semiconductor memory device according to claim 1, wherein A material of the first film and a material of the second film are different from a material of the plurality of first insulators and a material of the plurality of second insulators.

13. The semiconductor memory device according to claim 1, wherein The first film includes silicon, The second film includes carbon or metal, The plurality of first insulators include silicon oxide, The plurality of second insulators include silicon nitride.

14. A method for manufacturing a semiconductor memory device, comprising: forming a first insulator including a first opening; forming a first film in a portion of the first opening; forming a second film on a portion of the first opening on the first direction side; forming a first hole, the first hole penetrating through a plurality of third insulators and a plurality of fourth insulators, the plurality of third insulators and the plurality of fourth insulators being formed on the first insulator and the second film and arranged alternately one by one in the first direction, and the first hole reaching the second film; removing the second film to form a first space; forming a second hole, the second hole penetrating through a plurality of fifth insulators and a plurality of sixth insulators, the plurality of fifth insulators and the plurality of sixth insulators being formed on the first direction side of the plurality of third insulators and the plurality of fourth insulators and being alternately arranged one by one in the first direction, and the second hole reaching the first hole; forming a laminate including a semiconductor in the first hole, the first space, and the second hole; Exposing the first surface of the laminate on the second direction side opposite to the first direction; exposing a side surface of the semiconductor; as well as A first conductor is formed in contact with the exposed side surface of the semiconductor.

15. The method for manufacturing a semiconductor memory device according to claim 14, wherein Exposing the first surface of the laminate in the second direction includes removing the first film from the second direction side.

16. The method for manufacturing a semiconductor memory device according to claim 15, wherein The laminate further comprises: a seventh insulator covered by the semiconductor, Exposing the side surface of the semiconductor includes: removing part of the laminate from the second direction side; and A portion of the seventh insulator on the second direction side is removed toward the first direction.

17. The method for manufacturing a semiconductor memory device according to claim 16, wherein After forming the first space and before forming the layered body, the method further comprises: forming an eighth insulator in the first portion within the first hole and the first space; and forming a third film on the eighth insulator; Forming the second hole comprises: removing the third film; and The eighth insulator is removed.

18. The method for manufacturing a semiconductor memory device according to claim 17, wherein After forming the third film and before removing the third film, the method further includes: enlarging a portion of the second hole.

19. The method for manufacturing a semiconductor memory device according to claim 18, wherein Enlarging the portion of the second hole comprises: covering a portion of the side surface of the second hole on the second direction side with a fourth film; and At least a portion of the side surface of the second hole that is not covered with the fourth film is removed in a direction to enlarge the second hole.

20. The method for manufacturing a semiconductor memory device according to claim 15, further comprising: Each of the plurality of fourth insulators and the sixth insulator is replaced with the second conductor.

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