A silicon carbide-based electrostatic induction thyristor and its preparation method

Abstract

This invention relates to a silicon carbide-based electrostatic induction thyristor, comprising an N+ rectangular channel region near the N-type drift region and an N+ curved channel region located on the N+ rectangular channel region; the P+ type gate region has a three-segment gate structure, specifically including a P+ type rectangular gate region near the N-type drift region, a P-type curved gate region located on the P+ type rectangular gate region, and a portion of the gate region on the P-type curved gate region adjacent to the aluminum contact electrode; the bottom of the trench structure cathode also has a cathode bottom P+ region opposite to the P-type curved gate region. This novel structural design achieves stronger gate control capability, higher breakdown voltage, and better current uniformity distribution.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor devices, specifically to a silicon carbide-based electrostatic induction thyristor and its fabrication method. Background Technology

[0002] In the power electronics industry, thyristors are widely used semiconductor devices, primarily for medium- and high-voltage and high-current control applications. Traditional thyristors are made from silicon, but this material has limitations in performance under high temperature, high voltage, and high-frequency conditions. For example, silicon has a thermal conductivity of 1.56 W / (cm*K), lower than silicon carbide's 4.9 W / (cm*K); and the breakdown voltage of silicon devices (2.5 eV) is relatively low. 5 The voltage (V / cm) also limits its application in high-voltage applications. Compared to silicon, silicon carbide has unique electrical properties, such as a wide bandgap, high thermal conductivity, high critical electric field strength, and higher critical electric field strength, thermal conductivity, and electron mobility. These properties allow silicon carbide-based semiconductor devices to withstand higher voltages within the same size, while also exhibiting faster switching speeds and better thermal stability. Compared to the pioneering exploration of materials such as silicon carbide and gallium nitride in power devices like VDMOS, thyristors have lagged behind in using third-generation semiconductor materials such as silicon carbide as device substrates.

[0003] However, traditional thyristors have relatively large input, output, and feedback capacitances, resulting in a relatively slow switching speed, which limits their performance in high-frequency applications. In circuits requiring fast switching, this speed limitation can lead to insufficient device performance. Furthermore, the design of traditional thyristor devices often involves a series of trade-offs and compromises. For example, increasing the current carrying capacity usually involves increasing the on-resistance, while reducing the on-resistance may affect the device's switching performance and control sensitivity. These factors limit the device's performance in high-efficiency and high-power-density applications. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention aims to overcome the shortcomings of traditional silicon-based thyristors in terms of control precision, voltage withstand capability, gate conductivity, high-frequency characteristics, and high-temperature stability. By introducing a novel structural design, it achieves stronger gate control capability, higher breakdown voltage, and better current uniformity distribution, thereby providing an innovative solution for the field of high-performance power electronic devices.

[0005] The silicon carbide-based electrostatic induction thyristor of the present invention includes an anode P+ region, an N-type drift region located on the anode P+ region, an N+ channel region located on the N-type drift region, a P+ type gate region, and a trench structure cathode;

[0006] The N+ channel region includes an N+ rectangular channel region near the N-type drift region and an N+ curved channel region located on the N+ rectangular channel region;

[0007] The P+ type gate region is a three-segment gate structure, specifically including a P+ type rectangular gate region near the N-type drift region, a P-type curved gate region located on the P+ type rectangular gate region, and a portion of the gate region located on the P-type curved gate region adjacent to the aluminum contact electrode.

[0008] The bottom of the grooved cathode is also provided with a cathode bottom P+ region opposite to the P-shaped curved grid region.

[0009] Furthermore, the P-type curved gate region of the silicon carbide-based electrostatic induction thyristor described in this invention has an inwardly concave structure.

[0010] Furthermore, the bottom P+ region of the cathode of the silicon carbide-based electrostatic induction thyristor of the present invention is an outwardly convex structure corresponding to the P-type curved gate region.

[0011] Furthermore, the N+ curved channel region of the silicon carbide-based electrostatic induction thyristor of the present invention is realized by a concave P-type curved gate region and an outwardly convex cathode bottom P+ region.

[0012] Furthermore, the thickness of the anode P+ region of the silicon carbide-based electrostatic induction thyristor described in this invention is 150~200μm, and the doping concentration is 5e. 19 ~3e 20 / cm 3 The doping concentration of both the P+ type rectangular gate region and the P type curved gate region is 3e. 18 ~7e 18 / cm 3 The doping concentration of the portion of the gate region adjacent to the aluminum contact electrode is 3.5e. 19 ~8e 19 / cm 3 The doping concentration of the P+ region at the bottom of the cathode is 2e. 19 ~5e 19 / cm 3 If the doping concentration in the P+ region at the bottom of the cathode is too high, the saddle-shaped barrier will be difficult to establish, and the modulation effect of the gate on the saddle-shaped peak will be reduced; if the concentration is too low, the device bulk resistance will be too high, and the on-state voltage drop will be too high, which will easily cause the device to burn out.

[0013] Furthermore, the lateral spacing between the bottom P+ region trench structure cathode and the aluminum contact electrode portion adjacent to the gate region is 3~5μm, and the epitaxial doping concentration of the N+ bend-shaped channel region is 1.1~4 times that of the N+ bend-shaped channel region.

[0014] On the other hand, the present invention also provides a method for preparing a silicon carbide-based electrostatic induction thyristor based on any of the above-described methods, specifically including the following steps:

[0015] 1) Use a doping concentration of 5e 19 ~3e 20 / cm 3 The P-type silicon carbide wafer serves as the anode P+ region and also as the device substrate, with an N-type doped region epitaxially grown on its surface as the device region.

[0016] 2) N+ rectangular channel regions and P+ rectangular gate regions are formed using step-by-step epitaxy and step-by-step implantation, and nitride layers are deposited to block ion implantation. Each implantation step uses the same dose and temperature but different energies, with the injection energy decreasing sequentially. The step-by-step implantation uses an incident angle of 45° towards the cathode region. The step-by-step epitaxy uses a doping concentration of 5e. 12 ~1e 13 / cm 3 N-type epitaxy;

[0017] 3) Ion implantation of the P-type curved gate region is performed at an angle perpendicular to the wafer, and the width of the P-type curved gate region is smaller than the width of the P+ type rectangular gate region;

[0018] 4) Similarly, step-by-step epitaxy and step-by-step injection are used to form the bottom P+ region of the cathode, thereby forming the N+ curved channel region realized by the concave P-type curved gate region and the convex P+ region of the bottom of the cathode.

[0019] 5) Use a doping concentration of 2e 13 ~1e 14 / cm 3 The N-type epitaxial layer is ion implanted at an incident angle of 45° towards the cathode region to form an aluminum contact electrode portion adjacent to the gate region with the same width as the P+ type rectangular gate region.

[0020] In step 1), to balance the breakdown voltage characteristics in the off state with the low on-state voltage drop, a doping concentration of 1e is used. 13 ~5e 13 / cm 3 N-type silicon carbide wafers are used as device substrates.

[0021] In step 5), the anode and cathode electric fields are longitudinal and have no component in the lateral direction. In order to reduce the channel body resistance, ion implantation is used to form an aluminum contact electrode portion adjacent to the gate region with the same width as the P+ type rectangular gate region, which can also improve the breakdown voltage when the gate cathode is reverse biased.

[0022] In the preparation method, the P+ type rectangular gate region, the P-type curved gate region, and the P+ region at the bottom of the cathode are all epitaxially formed stepwise using high-temperature and high-energy ion implantation to form a high-quality gate with a high doping concentration. During ion implantation, nitride is used as a protective layer to prevent damage to the surface lattice of the non-implanted region during high-energy particle implantation. After implantation, the damaged valence bonds are restored by high-temperature annealing.

[0023] The P+ type rectangular gate region is formed by rotating the wafer at a 45° angle with the ion implantation direction, and then performing high-temperature, high-energy ion implantation four times, rotating the wafer 90° each time, to form a rectangular P+ type gate region slightly larger than the mask aperture. This region utilizes a superjunction structure to achieve preliminary control of the channel barrier, increasing the breakdown voltage range, and also increasing the area of ​​the conductive region perpendicular to the structural plane, thereby increasing conductivity.

[0024] Furthermore, the preparation method of the present invention also includes a thermal diffusion process, which specifically involves holding at a temperature of 1400~1600K for 30~50 minutes.

[0025] Furthermore, the preparation method of the present invention also includes depositing a protective layer to prevent the gate from contacting the cathode, while etching a cathode trench, depositing aluminum, and leading out a metal electrode.

[0026] Compared with the prior art, the present invention has the following beneficial technical effects:

[0027] The silicon carbide-based electrostatic induction thyristor of this invention employs a three-segment gate structure. The concave P-type curved gate region in the middle segment, together with the convex P+ region at the bottom of the cathode, forms an N+ curved channel region. This design incorporates a "turning structure" into the channel region, increasing the contact area between the metallurgical junction and this region while maintaining the same controlled area, thereby significantly enhancing the gate's control over the channel. Furthermore, the convex P+ region at the bottom of the cathode prevents current from flowing directly from the anode to the cathode, instead directing it through the N+ curved channel regions on either side of the P+ region at the bottom of the cathode, thus avoiding current concentration effects.

[0028] The trench structure cathode design of the silicon carbide-based electrostatic induction thyristor described in this invention increases the contact area between the cathode and the device, improves conductivity, and increases the spacing between the cathode and the aluminum contact electrode portion adjacent to the gate region in the lateral direction, thereby improving the gate-cathode breakdown voltage and enhancing the stability of the device in high-voltage applications.

[0029] The design of the bottom P+ region of the cathode in the silicon carbide-based electrostatic induction thyristor described in this invention can further improve the gate-anode breakdown voltage, increase the robustness of gate control, reduce the risk of breakdown, and make the device more reliable under high-voltage environments. By increasing the spacing between the lateral portion of the aluminum contact electrode and the gate region, a larger contact area is achieved, increasing conductivity. Simultaneously, by increasing the doping concentration in the intermediate region, the width of the space charge region is reduced, ultimately increasing the gate-cathode breakdown voltage.

[0030] The superjunction structure design of the silicon carbide-based electrostatic induction thyristor described in this invention features a P+ type rectangular gate region. In electrostatic induction thyristors, the gate current is relatively large, which can easily lead to false gate turn-on or partial gate failure during large-scale integration. This design enhances gate conductivity, ensuring that the gate potential remains at a consistent level across a large integration area. Simultaneously, it controls the shape change of the depletion region during blocking, which determines the breakdown voltage region of the device in the off-state. This design ensures that the channel depletion region expands synchronously during turn-off.

[0031] The anode P+ region and the aluminum metal layer deposited on the anode achieve ohmic contact; the cathode is a Schottky contact. Since the current inside the device can only flow from the anode to the cathode, the Schottky contact provides more electrons to the device, increases the electron current, and reduces the current pooling effect.

[0032] Furthermore, the fabrication method described in this invention utilizes a submicron process mask to form a high-quality gate through stepwise epitaxial implantation using a high-temperature, high-energy ion implantation method. Simultaneously, to reduce surface lattice damage caused by high-energy particle implantation, a nitride layer is generated during each ion implantation to protect the non-implanted region. This combines the advantages of surface gate and buried gate structures, optimizing the potential distribution by precisely controlling the depth and width of the gate adjacent to the barrier control region. This design enhances the potential's control over charge carriers, while simultaneously improving device switching speed and reducing power loss.

[0033] The silicon carbide-based electrostatic induction thyristor described in this invention has an operating range of 50MHz to 400MHz and a blocking gain of G=900. It features low static loss in the blocking state, high operating frequency compared to other high-power devices, low gate current in both the off and on states, and the ability to be integrated on a large scale.

[0034] The device can withstand a blocking voltage of 2000~3000V and is not easily broken down. Its on-state voltage drop is 0.8V, threshold voltage is 3V, and on-resistance is less than 0.5mΩ / cm. 2 The input capacitance is 9.2*10. -11 F / cm 2 The output capacitor is 2.1*10. -11 F / cm 2 The feedback capacitor is 1.3*10-11 F / cm 2 The novel electrostatic induction thyristor uses 4H-SiC as the substrate, leveraging its wide bandgap characteristics to significantly improve the device's withstand voltage. Due to the widespread use of lithium batteries (3.7V) and lead-acid batteries (12V) in industry and daily life, this invention utilizes a lower gate voltage control (3~5V), offering a wider range of applications compared to the traditional silicon carbide VDMOS control voltage (15~20V). While VDMOS requires weak and strong inversion to form the conductive channel, which is affected by the inversion carrier generation rate and cannot achieve high frequencies, this device controls conduction and turn-off through barrier control, enabling its application in ultra-high frequency circuits. Its main applications include radar, aviation, and base stations. Attached Figure Description

[0035] Figure 1 This is an equivalent schematic diagram of a traditional surface-gate electrostatic induction thyristor structure;

[0036] Figure 2 This is an equivalent schematic diagram of a traditional buried-gate electrostatic induction thyristor structure;

[0037] Figure 3 This is a schematic diagram of the equivalent structure of the silicon carbide-based electrostatic induction thyristor described in this invention;

[0038] Figure 4 This is an equivalent schematic diagram of the P-type anode region deposited on the anode;

[0039] Figure 5 This is an equivalent schematic diagram of the superjunction structure formed by step-by-step epitaxy and injection;

[0040] Figure 6 This is an equivalent schematic diagram of epitaxy and ion implantation of the strong gate region;

[0041] Figure 7 This is an equivalent schematic diagram of the P-type region at the bottom of the cathode formed by injection;

[0042] Figure 8 This is an equivalent schematic diagram of epitaxy and ion implantation to increase the gate bar height;

[0043] Figure 9 This is an equivalent schematic diagram of forming an oxide layer between electrodes, etching cathode trenches, and depositing etched aluminum.

[0044] Figure 10 yes Figure 3 3D diagram:

[0045] Among them: 1. Anode P+ region, 2. P+ type rectangular grid region, 3. P type curved grid region, 4. Cathode bottom P+ region, 5. N+ curved channel region, 6. Grid region adjacent to aluminum contact electrode, 7. Trench structure cathode, 8. Protective layer, 9. N type drift region, 10. N+ rectangular channel region. Detailed Implementation

[0046] To provide a deeper and clearer understanding of the technical content and effects of this invention, detailed embodiments of the invention will be described with reference to the accompanying drawings. It should be noted that the embodiments described are merely one possible implementation of the invention and are not limited to all possible implementations. Under the guidance of this invention, those skilled in the art can derive all alternative implementations without inventive effort, and these alternative implementations also fall within the scope of protection covered by this invention. For parts of the derivational embodiments where conditions are not specifically specified, operation should be performed according to industry-standard conditions or conditions recommended by the manufacturer.

[0047] In the following description, unless otherwise specified, the same reference numerals generally refer to the same or similar elements. The embodiments provided herein do not reflect all implementations of the invention, but are merely exemplary embodiments illustrating apparatuses and methods consistent with certain aspects of the claims of the invention. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Specific implementation method one:

[0049] A silicon carbide-based electrostatic induction thyristor includes an anode P+ region, an N-type drift region located on the anode P+ region, an N+ channel region located on the N-type drift region, a P+ type gate region, and a trench structure cathode;

[0050] The N+ channel region includes an N+ rectangular channel region near the N-type drift region and an N+ curved channel region located on the N+ rectangular channel region;

[0051] The P+ type gate region is a three-segment gate structure, specifically including a P+ type rectangular gate region near the N-type drift region, a P-type curved gate region located on the P+ type rectangular gate region, and a portion of the gate region located on the P-type curved gate region adjacent to the aluminum contact electrode.

[0052] The bottom of the grooved cathode is also provided with a cathode bottom P+ region opposite to the P-shaped curved grid region.

[0053] In some other embodiments, the P-type curved gate region of the silicon carbide-based electrostatic induction thyristor has a concave structure.

[0054] In some other embodiments, the bottom P+ region of the cathode of the silicon carbide-based electrostatic induction thyristor is an outwardly convex structure corresponding to the P-type curved gate region.

[0055] In some other embodiments, the N+ curved channel region of the silicon carbide-based electrostatic induction thyristor is realized by a concave P-type curved gate region and an outwardly convex cathode bottom P+ region.

[0056] In some other embodiments, the thickness of the anode P+ region of the silicon carbide-based electrostatic induction thyristor is 150~200 μm, and the doping concentration is 5e. 19 ~3e 20 / cm 3 The doping concentration of both the P+ type rectangular gate region and the P type curved gate region is 3e. 18 ~7e 18 / cm 3 The doping concentration of the portion of the gate region adjacent to the aluminum contact electrode is 3.5e. 19 ~8e 19 / cm 3 The doping concentration of the P+ region at the bottom of the cathode is 2e. 19 ~5e 19 / cm 3 .

[0057] In some other embodiments, the lateral spacing between the bottom P+ region trench structure cathode and the aluminum contact electrode portion adjacent to the gate region is 3~5μm, and the epitaxial doping concentration of the N+ bend-shaped channel region is 1.1~4 times that of the N+ bend-shaped channel region. Specific Implementation Method Two:

[0059] A method for fabricating a silicon carbide-based electrostatic induction thyristor based on any of the above specific embodiments specifically includes the following steps:

[0060] 1) Use a doping concentration of 5e 19 ~3e 20 / cm 3 A P-type heavily doped silicon carbide wafer is used as the anode P+ region, and then an epitaxial N-type doped layer is used as the substrate.

[0061] 2) N+ rectangular channel regions and P+ rectangular gate regions are formed using step-by-step epitaxy and step-by-step implantation, and nitride layers are deposited to block ion implantation. Each implantation step uses the same dose and temperature but different energies, with the injection energy decreasing sequentially. The step-by-step implantation uses an incident angle of 45° towards the cathode region. The step-by-step epitaxy uses a doping concentration of 5e. 12 ~1e 13 / cm 3 N-type epitaxy;

[0062] 3) Ion implantation of the P-type curved gate region is performed at an angle perpendicular to the wafer, and the width of the P-type curved gate region is smaller than the width of the P+ type rectangular gate region;

[0063] 4) Similarly, step-by-step epitaxy and step-by-step injection are used to form the bottom P+ region of the cathode, thereby forming the N+ curved channel region realized by the concave P-type curved gate region and the convex P+ region of the bottom of the cathode.

[0064] 5) Use a doping concentration of 2e 13 ~1e 14 / cm 3 The N-type epitaxial layer is ion implanted at an incident angle of 45° towards the cathode region to form an aluminum contact electrode portion adjacent to the gate region with the same width as the P+ type rectangular gate region.

[0065] In some other embodiments, the preparation method further includes a thermal diffusion process, specifically a heat treatment process of holding at 1400~1600K for 30~50 minutes.

[0066] In some other embodiments, the preparation method further includes depositing a protective layer to prevent the gate from contacting the cathode, while etching a cathode trench, depositing aluminum, and leading out a metal electrode. Example 1:

[0067] The present invention discloses a silicon carbide-based electrostatic induction thyristor. In crystal materials, because atoms are arranged in a regular lattice, the atomic arrangement gaps are larger in certain specific crystal orientations. When ions are injected along these crystal orientations, they encounter the fewest collisions and penetrate deeper. Therefore, the {0 0 0 1} crystal orientation is selected and the tilt angle is set to 4 degrees.

[0068] See appendix Figure 3 and Figure 10 This figure is a global structural image of the present invention. Due to regional limitations, the regions are labeled in detail in the following figures.

[0069] See appendix Figure 4 The present invention uses a P-type heavily doped silicon carbide wafer with a doping concentration of 5e19~3e20 / cm3 as the anode P+ region 1, and then an epitaxial N-type doped layer as the substrate.

[0070] See appendix Figure 5 In the figure, the P+ type rectangular gate region 2 adopts a six-stage distributed epitaxy and implantation process to ensure uniform doping concentration while conforming to the actual process conditions. This step-by-step epitaxy and distributed implantation ensures the uniformity of doping across the entire region, as well as precise shaping of the region's morphology and uniform conductivity. For each deposited layer, a doping concentration of 5e is used. 12 ~1e13 / cm 3 N-type epitaxy with high doping concentration. To achieve high-temperature, high-energy ion implantation, a nitride layer is deposited to block ion implantation instead of photoresist. To ensure uniform implantation, the same doping concentration (3e) is used after each deposition. 16 / cm 2 At the same temperature of 500K, the concentration was controlled by multiple injections at different energies of 700keV, 500keV, 360keV, 240keV, 120keV, and 30keV to ensure the continuity of doping in the multilayer injection region. The injection energies were injected sequentially from high to low.

[0071] See appendix Figure 6 In the figure, the P-type curved gate region 3 uses a different ion implantation angle compared to the P+ type rectangular gate region 2. The P+ type rectangular gate region 2 uses an incident angle of 45° towards the cathode region for ion implantation. The wafer rotates 90° four times, completing one rotation for implantation, making the area slightly larger than the nitride aperture after mask etching. The P-type curved gate region 3 uses an implantation angle perpendicular to the wafer for ion implantation, resulting in a P-type curved gate region 3 with a width slightly smaller than the P+ type rectangular gate region 2, to achieve better control of the channel region by the overall gate region.

[0072] See appendix Figure 7 To reduce the current pooling effect at the bottom of the cathode and change the current flow path, thereby forcing the current to flow through the N+ bend-shaped channel region 5 to the cathode and enhance the control of the current, the P+ region 4 at the bottom of the cathode is added by ion implantation. This region adopts the same implantation method and related parameters as the gate region to form the structure shown in the figure.

[0073] See appendix Figure 8 Using a doping concentration of 2e 13 ~1e 14 / cm 3 N-type epitaxy with high doping concentration. Ion implantation is performed at an incident angle of 45° biased towards the cathode region. A gate region of the same width as the P+ type rectangular gate region 2 is formed adjacent to the aluminum contact electrode portion 6.

[0074] See appendix Figure 9 The gate electrode is prevented from contacting the cathode by depositing a protective layer 8, while the cathode trench is etched, aluminum is deposited, and a metal electrode is brought out.

[0075] In this embodiment 1, the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is L μm, and L is 3.7 μm. The epitaxial doping concentration of the N+ curved channel region 5 is N times the doping concentration of the N+ curved channel region 5, and N is 2. Example 2:

[0076] The only difference between this embodiment 2 and embodiment 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 3μm. Example 3:

[0077] The only difference between this embodiment 3 and embodiment 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 5 μm. Example 4:

[0078] The only difference between Example 4 and Example 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 1.1 times that of the N+ curved channel region 5. Example 5:

[0079] The only difference between Example 5 and Example 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 4 times that of the N+ curved channel region 5.

[0080] Comparative Example 1

[0081] like Figure 1 As shown, Comparative Example 1 is a conventional surface-gate thyristor. Because the device structure uses single diffusion, the junction depth is relatively shallow. At the same time, a higher gate voltage is required to control the saddle-shaped barrier at the bottom of the cathode. This makes the device more prone to breakdown, and the device has a lower blocking voltage drop.

[0082] Comparative Example 2

[0083] like Figure 2 As shown in the figure, Comparative Example 2 is a traditional buried-gate thyristor. Due to the buried-gate structure, the high-frequency characteristics of the device are relatively weak. At the same time, the gate current of the thyristor is relatively large, making it impossible to keep the device in a uniform conduction state globally in high-power applications, thus failing to achieve partial turn-on, partial turn-off, or weak turn-on.

[0084] Comparative Example 3:

[0085] The only difference between Comparative Example 3 and Example 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 2 μm.

[0086] Comparative Example 4:

[0087] The only difference between Comparative Example 4 and Example 1 is that the lateral distance between the trench structure cathode 7 and the aluminum contact electrode portion 6 adjacent to the gate region is 7 μm.

[0088] Comparative Example 5:

[0089] The only difference between Comparative Example 5 and Example 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 0.5 times that of the N+ curved channel region 5.

[0090] Comparative Example 6:

[0091] The only difference between Comparative Example 6 and Example 1 is that the epitaxial doping concentration of the N+ curved channel region 5 is 6 times that of the N+ curved channel region 5.

[0092] Table 1. Performance parameters of devices in Examples 1-5 and Comparative Examples 3-6

[0093]

[0094] Having seen the above description of the embodiments and examples, those skilled in the art should understand that the present invention can be modified and equivalently substituted without departing from its scope of protection. Parts not specifically described in this specification belong to technical knowledge known to those skilled in the art. Furthermore, the present invention may be modified according to specific implementation scenarios, which will not depart from the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims, encompassing all various implementations covered by the claims of the present invention.

Claims

1. A silicon carbide-based electrostatic induction thyristor, characterized in that, It includes an anode P+ region (1), an N-type drift region (9) located on the anode P+ region (1), an N+ channel region and a P+ type gate region located on the N-type drift region (9), and a trench structure cathode (7). The N+ channel region includes an N+ rectangular channel region (10) near the N-type drift region (9) and an N+ curved channel region (5) located on the N+ rectangular channel region (10). The P+ type gate region is a three-segment gate structure, specifically including a P+ type rectangular gate region (2) close to the N type drift region (9), a P-type curved gate region (3) located on the P+ type rectangular gate region (2), and a gate region adjacent to the aluminum contact electrode portion (6) located on the P-type curved gate region (3). The bottom of the grooved cathode (7) is also provided with a cathode bottom P+ region (4) opposite to the P-type curved grid region (3).

2. The silicon carbide-based electrostatic induction thyristor according to claim 1, characterized in that, The P-shaped curved grid area (3) has a concave structure.

3. The silicon carbide-based electrostatic induction thyristor according to claim 2, characterized in that, The bottom P+ region (4) of the cathode is an outwardly convex structure corresponding to the P-type curved grid region (3).

4. The silicon carbide-based electrostatic induction thyristor according to claim 3, characterized in that, The N+ curved channel region (5) is realized by the concave P-type curved gate region (3) and the convex cathode bottom P+ region (4).

5. The silicon carbide-based electrostatic induction thyristor according to claim 1, characterized in that, The thickness of the anode P+ region (1) is 150~200μm, and the doping concentration is 5e. 19 ~3e 20 / cm 3 The doping concentration of both the P+ type rectangular gate region (2) and the P type curved gate region (3) is 3e. 18 ~7e 18 / cm 3 The doping concentration of the portion of the gate region adjacent to the aluminum contact electrode (6) is 3.5e. 19 ~8e 19 / cm 3 The doping concentration of the bottom P+ region (4) of the cathode is 2e. 19 ~5e 19 / cm 3 .

6. The silicon carbide-based electrostatic induction thyristor according to claim 1, characterized in that, The lateral spacing between the trench structure cathode (7) and the aluminum contact electrode portion (6) adjacent to the gate region is 3~5μm, and the epitaxial doping concentration of the N+ curved channel region (5) is 1.1~4 times that of the N+ curved channel region (5).

7. A method for preparing a silicon carbide-based electrostatic induction thyristor according to any one of claims 1 to 6, characterized in that, Specifically, the steps include the following: 1) Use a doping concentration of 5e 19 ~3e 20 / cm 3 A P-type heavily doped silicon carbide wafer is used as the anode P+ region (1), and then an epitaxial N-type doped layer is used as the substrate; 2) N+ rectangular channel region (10) and P+ rectangular gate region (2) are formed by step epitaxy and step implantation, and nitride layer is deposited to block ion implantation. Each implantation step uses the same dose and temperature but different energy, and the injection energy is implanted sequentially from large to small. The step implantation adopts an incident angle of 45° towards the cathode region. The step epitaxy adopts a doping concentration of 5e 12 ~1e 13 / cm 3 N-type epitaxy; 3) Ion implantation of the P-type curved gate region (3) is performed at an angle perpendicular to the wafer, and the width of the P-type curved gate region (3) is smaller than the width of the P+ type rectangular gate region (2). 4) Similarly, step-by-step epitaxy and step-by-step injection are used to form the bottom P+ region of the cathode (4), thereby forming the N+ curved channel region (5) realized by the concave P-type curved gate region (3) and the convex P+ region of the bottom of the cathode (4). 5) Use a doping concentration of 2e 13 ~1e 14 / cm 3 The N-type epitaxial layer is formed by ion implantation at an incident angle of 45° towards the cathode region to form a gate region adjacent to the aluminum contact electrode portion (6) with the same width as the P+ type rectangular gate region (2).

8. The preparation method according to claim 7, characterized in that, The preparation method includes a stepwise epitaxy and a thermal diffusion process after ion implantation to form the gate, wherein the thermal diffusion process is specifically a holding temperature of 1400~1600K for 30~50min.

9. The preparation method according to claim 8, characterized in that, The method also includes depositing a protective layer (8) to prevent the gate from contacting the cathode, while etching the cathode trench, depositing aluminum, and leading out the metal electrode.

Images