Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device with high performance, low power consumption and optimized structure, including a buffer layer, a channel layer, a barrier layer, a contact layer, and a source, a drain and a gate electrode. The buffer layer provides lattice matching and thermal stability, the channel layer has high electron mobility and saturation velocity, and the barrier layer optimizes the device performance by adjusting the band structure. A first groove and a second groove that completely penetrate the upper surface of the channel layer are introduced into the barrier layer, which enhances the control ability of the gate over the channel region. At the same time, this groove design overlaps with the projection of the edge of the contact layer, which enhances the electric field effect of the gate edge. In addition, a multi-layer buffer strategy is used to optimize the interlayer stress, and the device performance is further improved by optimizing the thickness of each functional layer. The manufacturing process includes steps such as substrate preparation, layer growth, etching treatment, electrode formation and passivation layer deposition. The semiconductor device of the present application achieves high performance, low power consumption and high reliability by optimizing the structural design and manufacturing process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Gallium nitride (GaN) materials have become a hot material in the field of power electronic devices due to their unique physical properties, such as large bandgap, high breakdown field strength and high electron mobility. In particular, in AlGaN / GaN heterostructures, high-concentration, high-electron-mobility two-dimensional electron gas (2DEG) can be formed. This feature makes GaN materials very suitable for use in high-frequency, high-power, and high-voltage power electronic devices, and plays an important role in modern electronic systems, including but not limited to electric vehicles, high-speed communications, energy conversion and storage. In specific applications, for safety reasons, devices are often required to operate in a normally-off state, which means that when the device is in a high-voltage state, even if the gate is out of control, the device will not accidentally turn on, thereby avoiding potential failure risks. For normally-off power devices, it is crucial to have a sufficiently high positive threshold voltage and a sufficiently small device off-state leakage current. However, due to the high concentration of 2DEG in the AlGaN / GaN heterojunction, traditional GaN devices often exhibit normally-on characteristics, which is contrary to the requirements of normally-off devices.

[0003] To solve this problem, researchers have explored a possible effective method, which is to reduce the polarization effect by thinning the thickness of the AlGaN barrier layer, thereby reducing the 2DEG concentration in the area below the gate. Although this method has made progress to a certain extent, how to effectively reduce the 2DEG concentration while maintaining the high performance of the device is still a problem that needs to be solved in the application of GaN power electronic devices. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device that can not only effectively reduce the carrier concentration formed by polarization to meet the needs of high-threshold normally-off devices, but also reduce the on-resistance while keeping the lateral electron mobility basically unaffected. The purpose of the present application is achieved through the following technical solutions, and the semiconductor device of the present application specifically includes:

[0005] Buffer layer;

[0006] a channel layer formed on the buffer layer;

[0007] a barrier layer formed on the channel layer;

[0008] a contact layer formed on the barrier layer;

[0009] A source electrode, a drain electrode and a gate electrode, wherein the gate electrode is formed on the contact layer, and the source electrode and the drain electrode extend into the buffer layer;

[0010] The barrier layer has a first groove and a second groove, the first groove and the second groove penetrate the barrier layer, a vertical projection of one side of the first groove overlaps with a vertical projection of one side of the contact layer, and a vertical projection of one side of the second groove overlaps with a vertical projection of another side of the contact layer;

[0011] The width of the first groove and the second groove is in the range of 2 to 4 μm.

[0012] In one of the embodiments, a passivation layer is further included, wherein the passivation layer is formed on inner surfaces of the first trench and the second trench and on a surface of the barrier layer that is not covered by the contact layer.

[0013] In one embodiment, it also includes:

[0014] substrate;

[0015] a nucleation layer formed on the substrate;

[0016] a superlattice layer formed on the nucleation layer;

[0017] The buffer layer is formed on the superlattice layer.

[0018] In one embodiment, the material of the buffer layer is AlGaN, the material of the channel layer is GaN, the material of the barrier layer is AlGaN, and the material of the contact layer is p-GaN.

[0019] In one of the embodiments, the content of the Al component in the buffer layer increases continuously from 10% to 20%.

[0020] In one embodiment, the thickness of the buffer layer is in the range of 0.8-4.5 μm, the thickness of the channel layer is in the range of 200-800 nm, the thickness of the barrier layer is in the range of 15-45 nm, and the thickness of the contact layer is in the range of 10-40 nm.

[0021] In one embodiment, the first trench is located on one side of the source electrode, the second trench is located on one side of the drain electrode, and the width of the first trench is smaller than the width of the second trench.

[0022] The present application further provides a method for manufacturing a semiconductor device, comprising:

[0023] Providing a substrate, and growing a nucleation layer, a superlattice layer, a buffer layer, a channel layer, a barrier layer, and a contact layer on the substrate;

[0024] Etching the contact layer and forming a first trench and a second trench in the barrier layer, wherein the first trench and the second trench penetrate the barrier layer, a vertical projection of one side of the first trench overlaps with a vertical projection of one side of the contact layer, and a vertical projection of one side of the second trench overlaps with a vertical projection of another side of the contact layer;

[0025] forming a gate electrode on the contact layer;

[0026] forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode extend into the buffer layer;

[0027] Wherein, the width of the first groove and the second groove is in the range of 2 to 4 μm.

[0028] In one embodiment, after forming the first trench and the second trench, a step of forming a passivation layer on the surface of the intermediate structure is further included, and before forming the gate electrode, a step of removing the passivation layer on the upper surface of the contact layer is further included.

[0029] In one embodiment, the step of forming the source electrode and the drain electrode includes the steps of forming a buried portion, an intermediate connecting portion, and a top electrode portion, respectively.

[0030] Compared with the prior art, this application has the following beneficial effects:

[0031] The present application sets a first groove and a second groove in the barrier layer. These grooves penetrate the barrier layer, and the vertical projection of one side of the groove overlaps with the vertical projection of one side of the contact layer. This structure interrupts the continuity of the AlGaN barrier layer, thereby effectively weakening the polarization effect, thereby reducing the 2DEG concentration in the area below the gate, so that the device can achieve the requirements of high-threshold normally-off devices while maintaining high performance, and improve the safety and reliability of the device. In addition, by precisely controlling the width and position of the grooves, and optimizing the materials and thickness of each layer, the present application reduces the 2DEG concentration while also ensuring that the on-resistance of the device is effectively reduced. When the device is in the on state, electrons can smoothly pass through the channel layer, thereby reducing the on-resistance, improving the efficiency and performance of the device, and keeping the lateral electron mobility basically unaffected: Although the groove structure is introduced, the present application ensures that the lateral electron mobility of the device is basically unaffected through fine process control and material selection, so that the device can achieve the requirements of normally-off devices while maintaining high mobility.

[0032] By forming a passivation layer on the inner surface of the first groove and the second groove and on the surface of the barrier layer not covered by the contact layer, the present application further improves the stability and reliability of the device. The passivation layer can effectively protect the device from erosion by the external environment and extend the service life of the device. The present application also provides a method for manufacturing a semiconductor device, and the stability of the device is improved by process control in the method. The semiconductor device provided by the present application achieves technical effects such as reducing the carrier concentration formed by polarization, reducing the on-resistance, and keeping the lateral electron mobility basically unaffected. It can be widely used in high-frequency, high-power, and high-voltage power electronic systems, such as electric vehicles, high-speed communications, energy conversion and storage, and has huge market potential and economic value. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0034] Figure 2 is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present application;

[0035] Figure 3-10 It is a structural schematic diagram of the manufacturing process of the semiconductor device in the embodiment of the present application.

[0036] Explanation of the accompanying drawings: 100, substrate; 101, nucleation layer; 102, superlattice layer; 103, buffer layer; 104, channel layer; 105, barrier layer; 106, contact layer; 201, passivation layer; 202, gate electrode; 203, source electrode; 204, drain electrode; 205, dielectric layer; 301, first trench; 302, second trench. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some structures related to the present application are shown in the accompanying drawings, rather than all structures. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0038] The terms "including" and "having" and any variations thereof in this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0039] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0040] Traditional gallium nitride-based heterojunction HEMT devices often exhibit normally-on characteristics, limiting their use in certain application scenarios that require normally-off devices. In order to meet this demand, researchers are constantly exploring new device structures and manufacturing processes to reduce the 2DEG concentration and realize high-threshold normally-off GaN HEMT devices. The gallium nitride HEMT-related devices of this application will be introduced in detail below. The semiconductor device provided in this application can effectively reduce the carrier concentration formed by polarization, meet the needs of high-threshold normally-off devices, while maintaining excellent conduction performance and lateral electron mobility, and provide new ideas and methods for the development of GaNHEMT devices. Next, the structural characteristics, principles, manufacturing processes, etc. of the device will be specifically introduced. Please refer to Figure 1 , the semiconductor device of the present application comprises:

[0041] Buffer layer 103;

[0042] A channel layer 104 formed on the buffer layer 103;

[0043] A barrier layer 105 formed on the channel layer 104;

[0044] A contact layer 106 formed on the barrier layer 105;

[0045] A source electrode 203, a drain electrode 204 and a gate electrode 202, wherein the gate electrode 202 is formed on the contact layer 106, and the source electrode 203 and the drain electrode 204 extend into the buffer layer 103 and have a preset distance from the bottom of the buffer layer 103;

[0046] The barrier layer 105 has a first trench 301 and a second trench 302, the first trench 301 and the second trench 302 penetrate the barrier layer 105, that is, the bottom of the first trench 301 and the second trench 302 is the upper surface of the channel layer 104, the vertical projection of one side of the first trench 301 overlaps with the vertical projection of one side of the contact layer 106, and the vertical projection of one side of the second trench 302 overlaps with the vertical projection of the other side of the contact layer 106, that is, a trench structure is formed on both sides of the gate electrode. It should be noted that other layers can be formed in subsequent steps, and when it is determined that the vertical projections overlap here, other layers formed in subsequent steps are not considered.

[0047] The buffer layer 103 is the basis of the functional structure of the device. It can first provide good lattice matching and thermal stability, and provide a basis for the growth of subsequent layer structures. The channel layer 104 is formed on the buffer layer 103 and is the main channel for carrier transmission. The barrier layer 105 is located on the channel layer 104. By adjusting its band structure, the carrier concentration in the channel is effectively controlled, thereby adjusting the switching speed and other performance of the device. The contact layer 106 is formed on the barrier layer 105 and is used to establish electrical contact with the gate electrode 202. The material selection is intended to minimize the contact resistance and ensure efficient signal transmission.

[0048] In particular, the present application introduces a first groove 301 and a second groove 302 in the barrier layer 105. The two grooves completely penetrate the barrier layer 105 and reach the upper surface of the channel layer 104 without damaging the channel layer 104 itself. This design enhances the gate's ability to control the channel region, helps reduce gate leakage current, and improves the reliability of the device. The projection of one side edge of the first groove 301 in the vertical direction overlaps with the projection of one side edge of the contact layer 106, while the corresponding edge projection of the second groove 302 overlaps with the projection of the other side edge of the contact layer 106, and is aligned with the sides of the first groove 301 and the second groove 302 on both sides of the gate electrode 202, respectively. This structure can enhance the electric field effect of the gate edge, enhance the gate's electric field control of the channel region, and make the channel control more precise. The presence of the groove structure helps to block unnecessary current paths, helps to improve the device's threshold voltage control capability and subthreshold slope, and thus improves the device's performance parameters. In addition, the source and drain electrodes 204 extend deep into the buffer layer 103, but maintain a certain preset distance from the bottom of the buffer layer 103. This design helps to reduce parasitic capacitance and improve the frequency response of the device. Without sacrificing performance, this innovative structure also helps to reduce the size of the device.

[0049] The buffer layer 103, the channel layer 104, the barrier layer 105 and the contact layer 106 and other structural layers can all be deposited with high precision and high quality by using advanced metal organic chemical vapor deposition (MOCVD). The MOCVD technology can ensure the precise thickness, composition distribution and interface quality of these layers during the growth process. In the semiconductor device structure of the present application, in order to achieve specific functional requirements, the width of the groove is precisely controlled and set within the range of 2~4µm. This width is smaller than the diffusion length of electrons in the GaN material, and can achieve effective longitudinal electron blocking: since the groove width is smaller than the electron diffusion length, the longitudinal electrons in the gate region are effectively blocked. When the gate is negatively biased, the electrons in the channel can be quickly and effectively depleted, thereby achieving a normally closed function, which can improve the switching speed of the device, so that the device can reach a closed state under a very small negative bias, thereby greatly reducing the power consumption of the device. On the other hand, lateral electron transport is basically unaffected. Since the lateral diffusion length of electrons in the GaN material is greater than the width of the groove, the lateral transport of electrons in the channel layer 104 is basically unaffected. This design ensures that the device can maintain good current conduction capability while maintaining high-speed switching characteristics, thereby ensuring the overall performance of the device.

[0050] While pursuing high performance and low power consumption of semiconductor devices, the stability of the device is also crucial. For this reason, a passivation layer 201 is further introduced in the above structure. Specifically, the passivation layer 201 is formed on the inner surface of the first trench 301 and the second trench 302, as well as those areas on the barrier layer 105 that are not covered by the contact layer 106. In addition, the passivation layer 201 also extends to cover all or part of the side of the contact layer 106, which not only enhances the protection of the internal structure of the device, but also further reduces the adverse effects of the external environment on the performance of the device. In terms of material selection, a material with high insulation, good chemical stability and thermal stability is used. (Aluminum oxide) is used as the material of the passivation layer 201 . These properties enable it to protect semiconductor devices from corrosion by moisture, oxygen and other contaminants.

[0051] In terms of the formation method, the atomic layer deposition (ALD) technology is used. With its layer-by-layer deposition, high uniformity and precise thickness control capabilities, the passivation layer 201 is ensured to be fully covered and adhered to the device surface. The passivation layer 201 not only has an extremely low defect density, but also can effectively reduce charge traps at the interface, thereby ensuring the stability and reliability of the device.

[0052] In the construction of semiconductor devices, in order to build an efficient, stable and compatible manufacturing method with multiple manufacturing processes, the relevant structures are further optimized. As the support of the entire semiconductor device, a silicon substrate is selected as the base 100. The silicon substrate has good mechanical strength, thermal stability and mature manufacturing process, and has become one of the most commonly used materials for the base 100 in the semiconductor industry. The selection of the silicon substrate as the base 100 can also ensure the mechanical strength and thermal stability of the device, and also make it compatible with a variety of mature semiconductor manufacturing processes, such as lithography, etching, ion implantation, etc. On the silicon substrate 100, a nucleation layer 101 is deposited. The main function of the nucleation layer 101 is to provide an interface with good lattice matching with the subsequent deposition layer, and promote the growth of high-quality epitaxial layers. By optimizing the material and thickness of the nucleation layer 101, the defects and stress in the epitaxial layer can be effectively reduced, thereby improving the performance and reliability of the device. Next to the nucleation layer 101, a superlattice layer 102 is deposited. The superlattice layer 102 is composed of two or more different materials deposited alternately to form a periodic structure. This structure can not only effectively adjust the energy band structure and improve the carrier mobility, but also further reduce the scattering and leakage current in the device through its unique interface effect. The aforementioned buffer layer 103 is deposited on the superlattice layer 102 to smooth the surface of the superlattice layer 102, reduce defects and stress at the interface, and provide a good growth platform for subsequent channel layers 104, barrier layers 105, etc. At the same time, the electrical performance and thermal stability of the device can be improved by optimizing the material and thickness of the buffer layer 103.

[0053] In the semiconductor device of the present application, in order to optimize the performance of the device and improve its reliability, the materials of each layer are further selected, and the growth conditions and doping processes of the key layers are carefully regulated. AlGaN is selected as the material of the buffer layer 103, which has good lattice matching, can effectively reduce defects and stress in the epitaxial layer, and also has high thermal conductivity, which helps to improve the thermal stability of the device. The channel layer 104 is made of GaN material, which has high electron mobility and saturation velocity. GaN also has a high breakdown electric field, which enables the device to work stably under high voltage, and is an ideal choice for realizing high-speed, high-power electronic devices. Of course, other possible materials can also be used as the channel layer 104 of the semiconductor device of the present application.

[0054] The barrier layer 105 is also made of AlGaN material. By adjusting the Al component in AlGaN, the height and width of the barrier layer 105 can be flexibly adjusted, thereby optimizing the key parameters of the device such as the threshold voltage and transconductance. The contact layer 106 is made of p-GaN material and doped with Mg to improve its conductivity. During the growth process, the growth temperature is strictly controlled to 800~1000℃ to ensure the effective activation of Mg and the high-quality growth of p-GaN. In addition, the doping concentration is controlled at> The above steps ensure that the contact layer 106 has good conductivity and good contact with the subsequent electrodes. After the growth of the above layers is completed, the device surface is cleaned to remove impurities and contaminants remaining during the growth process.

[0055] In the semiconductor epitaxial growth process, in order to optimize the quality of the epitaxial layer, reduce interlayer stress, and improve device performance, specific nucleation layer 101 and superlattice layer 102 materials are used, and a multi-layer buffer growth strategy is combined. AlN is selected as the nucleation layer 101 material. AlN has good lattice matching with the subsequent AlGaN / GaN superlattice layer 102, which can effectively reduce interlayer stress and lay the foundation for the subsequent growth of high-quality epitaxial layers. The superlattice layer 102 adopts an AlGaN / GaN alternating structure, which can effectively adjust the band structure, improve carrier mobility, and reduce scattering and leakage through periodic interface effects. More importantly, by adjusting the thickness ratio of AlGaN and GaN, the interlayer stress can be further controlled and the overall quality of the epitaxial layer can be optimized.

[0056] In order to more effectively control stress and improve the quality of the epitaxial layer, a multi-layer buffer growth method can be further adopted. For example, a three-stage AlN nucleation layer 101 growth method is adopted. First, the first stage of growth is carried out to grow an initial nucleus layer with a thickness of 50-100nm at a low temperature (500-600°C) to provide a stable starting point for subsequent epitaxial growth. Next is the second stage of growth, increasing the growth temperature to 600-800°C and growing a growth healing layer with a thickness of 300-500nm. This stage aims to promote the healing and growth of crystals, reduce defects, and improve the overall quality of the epitaxial layer. In the third stage of growth, the growth temperature is lowered again to 500-600°C to grow a stress release layer with a thickness of 50-100nm. In this stage, a specific microstructure is formed to effectively release the stress accumulated in the previous growth process, further reduce the interlayer stress, and improve the stability of the epitaxial layer.

[0057] In the epitaxial growth process of semiconductor devices, in order to optimize device performance, especially to reduce stress in subsequent epitaxial layers (such as AlGaN and GaN), a specially designed buffer layer 103 material can be further used. When using AlGaN material, the content of its Al component increases continuously from 10% to 20%. In a more precise expression, the Al component changes continuously from 0.1 (or 10%) to 0.2 (or 20%). By gradually increasing the Al component, a smooth transition of stress between the buffer layer 103 and the subsequent epitaxial layer is achieved, thereby reducing interlayer stress and improving the quality of the epitaxial layer. During the growth process, the continuous increase of the Al component in the buffer layer 103 is achieved by precisely controlling the growth conditions (such as temperature, pressure and gas flow rate, etc.). For example, by gradually increasing the flow rate of aluminum precursor, the Al component in the formed AlGaN material continues to increase. In addition, the Al component can be regulated by gradually adjusting other growth conditions. By continuously changing the Al component, a smooth transition of stress between the buffer layer 103 and the subsequent epitaxial layer can be achieved, and the overall performance of the device can be optimized, for example, the breakdown voltage of the device can be increased, the leakage current can be reduced, and the stability and reliability of the device can be enhanced.

[0058] In the precision construction of semiconductor devices, the thickness design of each functional layer also plays a vital role in the overall performance of the device. The thickness of the buffer layer 103 is controlled within the range of 0.8 to 4.5 micrometers (μm), providing a sufficiently thick transition layer to effectively alleviate the lattice mismatch and thermal mismatch between the substrate 100 and the subsequent epitaxial layer, thereby reducing the stress accumulation and defect density in the epitaxial layer. The thicker buffer layer 103 can more fully absorb and disperse these stresses, providing a more stable and high-quality interface for the growth of subsequent epitaxial layers such as the channel layer 104 and the barrier layer 105. The thickness range of the channel layer 104 is set between 200 and 800 nanometers (nm). As the main channel for carrier transmission, the thickness of the channel layer 104 has a direct impact on the conductive performance and current handling capacity of the device. Through the present application, the first trench 301 and the second trench 302 are formed in the barrier layer 105, so that within this thickness range, the channel layer 104 can provide sufficient conductive channel width while maintaining low resistance and high carrier mobility. The thickness of the barrier layer 105 is strictly controlled within the range of 15 to 45 nanometers (nm). The main function of the barrier layer 105 is to form an electron barrier and control the carrier concentration and mobility in the channel. Within this thickness range, the barrier layer 105 can effectively block the leakage of electrons from the channel layer 104 to the substrate 100 or other non-conductive areas, while maintaining good control over the carriers in the channel. The thickness range of the contact layer 106 is set between 10 and 40 nanometers (nm). The contact layer 106 serves as the connection interface between the device gate and the external circuit. Its thickness has an important influence on the contact resistance and current injection efficiency of the device. In conjunction with the structure of the first groove 301 and the second groove 302 of the present application, within this thickness range, the contact layer 106 can provide sufficient surface area and conductive channel to ensure good ohmic contact and reduce contact resistance and power consumption.

[0059] In the above semiconductor device structure, in order to further optimize the electrical performance and reliability of the device, the trench structure design is further optimized. Specifically, the first trench 301 and the second trench 302 are located on one side of the source electrode 203 and the drain electrode 204, respectively, and the width of the first trench 301 (located on the side of the source electrode 203) is set to be smaller than the width of the second trench 302 (located on the side of the drain electrode 204). During the manufacturing process, the two trenches are accurately formed by advanced etching technology, and the etching parameters (such as etching time, etching rate and etching solution concentration, etc.) are accurately controlled to ensure that the width and depth of the trench are within the set range, and at the same time ensure that the trench is accurately aligned with the source electrode 203 and the drain electrode 204. By adjusting the width of the first groove 301 and the second groove 302, the current distribution inside the device can be effectively regulated. The narrower first groove 301 (located on the side of the source electrode 203) helps to limit the diffusion of current in the source region, thereby improving the current injection efficiency and the switching speed of the device, while the wider second groove 302 (located on the side of the drain electrode 204) can increase the distance between the gate and the drain, and can prevent leakage and current collapse of the device. The groove design of different widths can also affect the electric field distribution inside the device. By optimizing the width ratio of the groove, the width of the second groove 302 is 1.1-1.4 of the width of the first groove 301. Within the above range, the distribution of the electric field inside the device can be better controlled, thereby reducing the risk of electric field concentration and breakdown, and improving the breakdown voltage and reliability of the device. In addition, the above structure further improves the overall performance of the device by reducing unfavorable factors such as parasitic capacitance and inductance, which helps to improve the switching speed of the device, reduce power consumption, enhance anti-interference ability and improve long-term stability.

[0060] In addition, in the process of constructing the semiconductor device, a dielectric layer 205 is deposited on the top of the device structure layer. The dielectric layer 205 is made of silicon nitride ( ) as its main material, the gate structure is precisely constructed inside the dielectric layer 205 to ensure effective isolation of the gate and the channel area, and also realizes the electrical connection between the gate and the lower circuit through the through hole (i.e., contact hole or gate via) made in the dielectric layer 205, ensuring that the gate control signal can be accurately transmitted to the channel area, thereby realizing precise control of the channel current. At the same time, the source electrode 203 and the drain electrode 204 are directly designed to extend to the upper surface of the dielectric layer 205, reducing the additional steps and interfaces required for connecting the electrodes to the external circuit, reducing the contact resistance, and improving the current transmission efficiency.

[0061] The present application further provides a method for manufacturing a semiconductor device, see Figure 2-Figure 10 , the manufacturing method specifically comprises:

[0062] A substrate 100 is provided, on which a nucleation layer 101, a superlattice layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a contact layer 106 are grown. A substrate 100 is prepared as a basic support for the device, on which a nucleation layer 101, a superlattice layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a contact layer 106 are sequentially grown to form the main part of the device, wherein the nucleation layer 101 helps the uniform growth of subsequent layers, the superlattice layer 102 may be used to adjust the band structure, the buffer layer 103 is used to alleviate the lattice mismatch, the channel layer 104 is the main path for current flow, the barrier layer 105 is used to regulate the transport of carriers, and the contact layer 106 facilitates the connection with the external circuit.

[0063] During the epitaxial growth process, the bonding strength between the layers can be significantly improved by selecting the materials of the nucleation layer 101 and the superlattice layer 102 and combining them with a specific growth process. In a specific embodiment, the nucleation layer 101 uses aluminum nitride (AlN), and the superlattice layer 102 uses a combination of aluminum gallium nitride / gallium nitride (AlGaN / GaN). The advantage of this material selection is that AlN has high thermal conductivity, good chemical stability and a lattice constant that matches GaN. It can effectively serve as a growth substrate 100 for GaN-based materials and reduce stress problems caused by lattice mismatch. The AlGaN / GaN superlattice layer 102 further adjusts the material's band structure and stress state through periodically changing components, thereby optimizing the electrical performance of the device.

[0064] In order to further reduce the stress between layers and improve the quality of the epitaxial layer, a multi-layer buffer strategy is adopted to achieve fine stress regulation. Specifically, the growth mode of the AlN nucleation layer 101 is designed to be three-stage, and each stage has its own specific parameter settings: the first stage forms a low-temperature core layer, and a 50-100nm thick AlN layer is grown at a lower temperature of 500-600℃. The main purpose of this stage is to initially form a uniform and dense AlN core layer on the substrate to provide a stable starting point for subsequent growth. Low-temperature growth helps to reduce the formation of defects and promote good adhesion between AlN and the substrate. The second stage grows a healing layer at a medium-high temperature. Subsequently, a 300-500nm thick AlN layer is grown at a higher temperature of 600-800℃. The high-temperature growth not only accelerates the deposition rate of the material, but more importantly, promotes the healing of defects in the previously formed core layer, reduces the dislocation density, and enhances the crystallization quality of the AlN layer, providing a smoother and less defective interface for subsequent superlattice growth. In the third stage, a low-temperature stress release layer is grown, and a 50-100nm thick AlN layer is grown again at a low temperature of 500-600℃. This layer serves as a stress release layer. By adjusting the growth conditions (such as temperature and thickness), the stress accumulated in the previous two layers can be effectively relieved, avoiding cracks or warping during the epitaxial growth process, thereby further improving the overall quality of the epitaxial layer.

[0065] The multi-layer buffer strategy combined with specific growth conditions provides greater flexibility and precision for stress regulation, which helps to achieve more complex and high-performance device structures. The buffer layer 103 uses AlGaN material. By matching its lattice constant with the substrate 100 material, it effectively reduces the lattice mismatch stress during the epitaxial growth process and improves the stability of the overall structure and the epitaxial quality. The channel layer 104 uses GaN material because it has excellent electron mobility and breakdown voltage, which is very suitable for high-speed and high-power electronic devices. The barrier layer 105 also uses AlGaN. By adjusting the Al component, the band structure can be accurately controlled, thereby affecting the electron concentration and mobility in the channel and optimizing device performance. As for the contact layer 106, the temperature of the p-GaN contact layer 106 is controlled between 800°C and 1000°C during the growth process. The high temperature helps the effective incorporation of Mg (magnesium). Mg is a commonly used acceptor impurity in p-GaN, which can introduce holes in GaN to form p-type conductivity. The doping concentration is set to be greater than This high doping level not only enhances the conductivity of the p-GaN layer, but also helps reduce contact resistance and improve the current driving capability and efficiency of the device.

[0066] After the growth of all layers is completed, the surface of the p-GaN contact layer 106 is cleaned to remove surface contaminants, particles, and impurities such as unreacted source gas that may remain during the growth process. The use of appropriate cleaning processes (such as wet chemical cleaning combined with ultrasonic treatment) can effectively improve the surface cleanliness and ensure the formation of good ohmic contact, which is crucial to improving the performance and reliability of the device.

[0067] The contact layer 106 is etched, and a first groove 301 and a second groove 302 are formed in the barrier layer 105. The first groove 301 and the second groove 302 penetrate the barrier layer 105. The vertical projection of one side of the first groove 301 overlaps with the vertical projection of one side of the contact layer 106, and the vertical projection of one side of the second groove 302 overlaps with the vertical projection of the other side of the contact layer 106. Through the etching process, the first groove 301 and the second groove 302 are formed in the barrier layer 105 below the contact layer 106. Both grooves completely penetrate the barrier layer 105. The projection of one side edge of the first groove 301 in the vertical direction overlaps with the projection of one side edge of the contact layer 106, and the second groove 302 overlaps with the projection of the other side edge of the contact layer 106 accordingly, which provides an accurate reference for the subsequent positioning of the gate electrode 202, and also ensures the effective electrical isolation between the gate electrode 202 and the channel layer 104, while optimizing the gate's control ability over the channel current.

[0068] The trench formation method uses etching technology to selectively use HBr and The mixed gas is used as the etching medium. In this process, HBr gas can not only effectively etch the material and gradually form the required groove structure, but also, due to its specific chemical properties, HBr can provide a certain protection to the side of the groove during etching, which helps to maintain the verticality of the groove side wall and reduce unnecessary side etching. On the other hand, The gas participates in the chemical reaction during the etching process, which helps to form an extremely smooth etched section. The smooth surface characteristics are crucial to the performance of subsequent devices. It can reduce the surface roughness and thus reduce the leakage current problem caused by surface defects. Reducing leakage current by optimizing the etching section is of great significance to improving the overall performance of the device. As a method of corrosive gas, precise control of the etching depth of the double-channel gate layer and the source and drain electrodes is achieved, ensuring the accuracy of the device structure. By improving the smoothness of the etched section and reducing the surface defect density, the leakage current is effectively reduced, and the reliability and energy efficiency of semiconductor devices are improved.

[0069] A gate electrode 202 is formed on the contact layer 106, specifically, the gate electrode 202 is deposited and patterned on the contact layer 106 after etching. The position and size of the gate electrode 202 are precisely controlled to ensure that it can cover part of the barrier layer 105 and the groove area overlapping with the edge projection of the contact layer 106, so as to achieve precise control of the channel current. Finally, a source electrode 203 and a drain electrode 204 are formed. These two electrodes are not only located on the contact layer 106, but also extend into the buffer layer 103 through specific process steps to form a good ohmic contact with the channel layer 104. This design of deep into the buffer layer 103 helps to reduce contact resistance and improve current injection efficiency, thereby enhancing the overall performance of the device.

[0070] Specifically, after forming the first trench 301 and the second trench 302, a step of forming a passivation layer 201 on the surface of the intermediate structure is further included, and before forming the gate electrode 202, a step of removing the passivation layer 201 on the upper surface of the contact layer 106 is further included. The specific material of the passivation layer 201 is selected from , using the ALD method with very precise component ratios to deposit on the surface The deposition temperature is 220~250℃, and the temperature before deposition is 300~350℃. The cavity is pretreated and filled and pumped for 5 times. The cavity is in an oxygen-rich state to deposit a thin film with excellent density and dielectric properties. The deposition thickness is 50~200nm as the passivation layer 201 of the gate electrode and the drain electrode, which reduces the leakage current between the gate electrode and the drain electrode and the side semiconductor. For the structure with two grooves in this application, the ALD method can ensure the integrity and density of the passivation layer 201, and can prevent the groove structure in this application from failing.

[0071] The process also includes the step of forming a dielectric layer 205. The dielectric layer 205 can form a flat surface, which is conducive to the accurate formation of the corresponding structure in the photolithography step. This flattening process has a far-reaching impact on the subsequent photolithography steps. The dielectric layer 205 can effectively eliminate the problems of surface unevenness, defects or steps that may occur in the previous process steps through filling and flattening capabilities. A highly flat surface is a prerequisite for the accurate transfer of patterns to silicon wafers by photolithography technology. During the photolithography process, the light source needs to be projected onto the surface through a series of precise optical elements. Any tiny surface unevenness may cause light scattering and inaccurate focusing, thereby affecting the resolution and edge quality of the pattern. Therefore, the introduction of the dielectric layer 205 and its flattening effect improve the accuracy and reliability of the photolithography step, ensure that the pattern can be transferred from the photolithography mask to the substrate with extremely high fidelity, and the flat dielectric layer 205 also helps to reduce the error accumulation in the photolithography process and improve the yield and repeatability of the overall manufacturing process.

[0072] The steps of forming the source electrode 203 and the drain electrode 204 are optimized to ensure the performance and reliability of the device. Specifically, they include three steps of forming the buried part, the intermediate connection part and the top electrode part respectively. The buried part is the basic part of the electrode. The buried part is usually formed first and embedded in the semiconductor substrate or the corresponding insulating layer to provide direct electrical contact with the channel. The formation of the buried part needs to control its depth, shape and position to ensure good electrical contact and mechanical stability. The intermediate connection part is located above the buried part. The intermediate connection part serves to connect the buried part with the top electrode part. It may include multiple layers of metal or alloy to enhance the current transmission capacity and provide necessary mechanical support. The design of the intermediate connection part needs to consider the selection of materials, the thickness of the layer and the interface quality between the layers to ensure good electrical conductivity and thermal stability. As the outermost layer of the electrode, the top electrode part is directly exposed to the external environment and connected to the external circuit. It usually has excellent electrical conductivity and corrosion resistance and can withstand long-term electrical stress and environmental erosion. The formation of the top electrode part also needs to consider its compatibility with the packaging material to ensure good packaging sealing and reliability. When forming each of the above parts, a corresponding dielectric layer 205 can also be formed accordingly. These dielectric layers 205 not only play the role of isolating and protecting the various parts of the electrode to prevent electrical short circuits or unnecessary electrical contacts between them, but also provide a flat surface, which is conducive to the precise implementation of subsequent processes. The material selection, thickness and uniformity of the dielectric layer 205 have an important impact on the performance and reliability of the device.

[0073] After completing the main structure of the device, the chip will undergo an annealing process. This step is usually carried out in the temperature range of 400-420℃ and lasts for about 10-15 minutes. Annealing improves the internal microstructure of the material through a thermal activation process, such as eliminating stress, promoting grain growth, optimizing interface quality, etc., which helps to improve the electrical performance, thermal stability and long-term reliability of the device. In addition, annealing can effectively remove impurities and defects that may be introduced during the manufacturing process, further improving the quality of the device. In order to meet the requirements of package size and weight, and to improve the heat dissipation performance of the device, the chip will be thinned by high-precision machinery. This step usually reduces the thickness of the chip to within the range of 300~500 microns (μm). The thinning is carried out with precise thickness control to ensure that the surface of the thinned chip is flat and undamaged, which helps the smooth progress of the subsequent packaging process and improves the overall performance and reliability of the device. After the thinning process is completed, the chip will be cut by a high-precision machine wheel to separate the single device and ensure the consistency of the size, shape and performance of each device. Specific embodiments

[0075] Some specific implementation methods will be further introduced below to further explain the technical solution of this application in detail.

[0076] The growth of semiconductor materials is carried out by Metal Organic Vapor Chemical Deposition (MOCVD), which is a delicate and efficient process. Specifically, the process begins with the sequential growth of multiple layers of key structures on a Si substrate. First, an AlN nucleation layer is deposited in a suitable growth temperature range of 800~1000°C. This layer serves as the cornerstone of subsequent growth and helps to improve the stability and quality of the overall structure. Next, an AlGaN / GaN superlattice layer is grown. By alternately stacking AlGaN and GaN layers of different components, stress can be effectively managed and interface properties can be optimized. An AlGaN buffer layer is deposited, which further enhances the mechanical strength and thermal stability of the structure. On this basis, an undoped GaN channel layer is grown as the main path for electron transmission, followed by the deposition of an AlGaN barrier layer, which forms a heterojunction with the GaN channel layer. Finally, a p-GaN contact layer is grown, in which Mg is deliberately doped to achieve p-type conductivity, and the doping concentration needs to be maintained at> After all layers are grown, the surface needs to be thoroughly cleaned to remove any impurities or contaminants that may remain in order to ensure the smooth progress of subsequent processes and optimize device performance.

[0077] Plasma Enhanced Chemical Vapor Deposition (PECVD) is used to precisely deposit a layer of silicon nitride on the surface of the material. ) film, the process is particularly critical to the control of temperature and thickness. During the deposition process, the working environment is maintained in a suitable temperature range of 280 to 300 ° C. This temperature range helps to ensure the efficient chemical reaction and the optimization of film quality. At the same time, by precisely controlling the deposition parameters, the deposited Layer thicknesses of 200 to 300 nanometers (nm) were achieved.

[0078] Through the photolithography process, the first and second grooves are formed in the AlGaN barrier layer. The length of the grooves is precisely controlled between 20 and 50 microns (μm), and the width is between 2 and 4 microns (μm). Specifically, the buffered oxide etchant (BOE) is used to immerse the surface of the AlGaN barrier layer at a constant temperature of 25°C for 50 to 70 seconds to effectively remove the silicon nitride ( ) layer, the selective etching capability of BOE ensures The layer is completely removed while protecting the underlying p-GaN layer from damage to the maximum extent. Next, the inductively coupled plasma (ICP) etching technology is used to accurately etch the p-GaN layer to the AlGaN barrier layer below to ensure the verticality and smoothness of the channel sidewalls. After that, the sample is immersed in a potassium hydroxide (KOH) solution at 85 to 90°C for 5 to 30 seconds to selectively remove the AlGaN barrier layer. The KOH solution exhibits good etching rate and selectivity within this temperature range, ensuring the precise removal of the AlGaN layer while protecting other material layers from being affected. The photoresist used in the photolithography process is removed through a standard stripping process.

[0079] Subsequently, an aluminum oxide layer was deposited on the surface using atomic layer deposition (ALD). ) film, the deposition temperature is controlled in the range of 220 to 250 ° C, and the deposited The layer thickness is precisely controlled between 50 and 200 nanometers (nm). Before deposition, multiple cycles of chamber and surface pretreatment are performed to thoroughly remove impurities, residues or pollutants that may exist in the chamber and material surface to ensure the purity of the deposition environment and the effective adsorption of reactants. The pretreatment process may include high-temperature baking, inert gas purging, chemical cleaning and other steps to ensure the cleanliness and reactivity of the surface before deposition.

[0080] Using photolithography technology, a photolithography matrix pattern with a diameter of 500 to 5000 microns (μm) and a spacing of 50 to 100 μm is formed on the surface of the material. The sample is immersed in BOE at a constant temperature of 25°C for 50 to 70 seconds to effectively remove the silicon nitride deposited on the surface. ) layer, and then use ICP to etch the material to the AlGaN buffer layer below, and remove the photoresist used in the lithography process through a stripping process.

[0081] Then, photolithography was used to form a gate array pattern on the p-GaN layer. The sample was immersed in BOE at a constant temperature of 25°C for 50 to 70 seconds to remove the aluminum oxide ( ) layer, the selective etching capability of BOE ensures The layer is completely removed, while the p-GaN layer below is protected from damage to the maximum extent. Then, a titanium nitride (TiN) metal layer is evaporated on the processed Gate array pattern by electron beam evaporation as the Gate electrode. During the evaporation process, the evaporation thickness is controlled to ensure that it is within the range of 200 to 300 nanometers (nm). The TiN metal layer has excellent conductivity, chemical stability and thermal stability. Finally, the photoresist used in the photolithography process is removed through the degumming process.

[0082] Continuing to use photolithography technology, a source electrode and drain electrode array pattern with a length of 100 microns (μm) and a width of 10 to 100 μm was formed. Subsequently, the electron beam evaporation method was used to sequentially evaporate TiN, Ni, Ti, AlCu and Ti metal layers as the source electrode and drain electrode, and the evaporation thickness was precisely controlled between 100 and 600 nanometers (nm). After the evaporation was completed, the photoresist was completely removed by the degumming process. Then, a layer of silicon nitride ( ) film, the deposition temperature is maintained between 260 and 280°C, and the thickness is controlled between 400 and 600nm. Using photolithography technology, an intermediate connection electrode array pattern with a length of 50 to 500μm and a width of 10 to 100μm is formed. Then, a buffered oxide etchant (BOE) is used to immerse at 25°C for 50 to 70 seconds to accurately remove the covering on the intermediate connection electrode pattern. Then, Ti, Ni, Ti, AlCu and Ti metal layers were sequentially deposited as intermediate connecting electrodes by electron beam evaporation, and the evaporation thickness was controlled between 50 and 200 nm. After the evaporation was completed, the photoresist was removed by a stripping process.

[0083] Subsequently, a layer of The film, deposition conditions and thickness are the same as the previous layer to further protect the structure below. Repeat the steps of photolithography, BOE etching and electron beam evaporation, but this time the evaporation thickness of the intermediate connecting electrode is in the range of 50 to 1000nm. Similarly, the degumming process is also performed after the evaporation is completed.

[0084] The above chips are placed in a high-temperature environment for annealing, with the annealing temperature controlled between 400 and 420 degrees Celsius for 10 to 15 minutes to ensure the stability and performance of the chip material. Subsequently, the chips are thinned using high-precision mechanical processes, with their thickness precisely controlled between 300 and 500 microns. Then, the annealed and thinned wafers are precisely separated into individual devices using high-precision machine wheel cutting technology. Through the above series of process flows, the device is manufactured.

[0085] As can be seen from the foregoing, the present application provides a high-performance, low-power and structurally optimized semiconductor device, the main structure of which includes a buffer layer, a channel layer, a barrier layer, a contact layer, and a source, a drain and a gate electrode. The buffer layer of the device serves as the basis of the functional structure, and the channel layer is located above the buffer layer. It is the main channel for carrier transmission and has high electron mobility and saturation velocity. The present application introduces a first groove and a second groove in the barrier layer. These two grooves completely penetrate the barrier layer and reach the upper surface of the channel layer, but do not damage the channel layer itself, thereby enhancing the gate's control over the channel region, helping to reduce gate leakage current and improve the reliability of the device. At the same time, the sides of the first groove and the second groove overlap with the projections of the two side edges of the contact layer, respectively. This structure can enhance the electric field effect at the gate edge, making channel control more precise.

[0086] In order to further optimize the device performance, this application also adopts a multi-layer buffer strategy, which effectively reduces the interlayer stress and improves the quality of the epitaxial layer by precisely controlling the materials and growth conditions of the nucleation layer, superlattice layer, and buffer layer. In addition, the overall performance of the device is further improved by optimizing the thickness design of each functional layer, such as the buffer layer, channel layer, barrier layer, and contact layer.

[0087] In terms of manufacturing methods, the process flow provided in this application includes the steps of substrate preparation, growth of each layer, etching treatment, electrode formation, and passivation layer deposition. The first groove and the second groove are formed by etching technology, and the gate electrode is formed by deposition and patterning processes. The source and drain electrodes extend into the buffer layer and maintain a certain preset distance from the bottom of the buffer layer to reduce parasitic capacitance and improve the frequency response of the device. In addition, the present application also introduces a passivation layer to enhance the protection of the internal structure of the device and reduce the adverse effects of the external environment on the performance of the device. The passivation layer is made of a material with high insulation, good chemical stability and thermal stability. Materials are deposited and the thickness is precisely controlled and fully covered by atomic layer deposition (ALD) technology. In summary, the semiconductor device of the present application achieves high performance, low power consumption and high reliability by optimizing the structural design and manufacturing process, providing strong support for the application of high-speed and high-power electronic devices.

[0088] The above is only a specific implementation of the present application, and any other improvements made based on the concept of the present application are deemed to be within the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: Buffer layer; a channel layer formed on the buffer layer; a barrier layer formed on the channel layer; a contact layer formed on the barrier layer; A source electrode, a drain electrode and a gate electrode, wherein the gate electrode is formed on the contact layer, and the source electrode and the drain electrode extend into the buffer layer; The barrier layer has a first groove and a second groove, the first groove and the second groove penetrate the barrier layer, a vertical projection of one side of the first groove overlaps with a vertical projection of one side of the contact layer, and a vertical projection of one side of the second groove overlaps with a vertical projection of another side of the contact layer; The width of the first groove and the second groove is in the range of 2 to 4 μm.

2. The semiconductor device according to claim 1, wherein: A passivation layer is also included, and the passivation layer is formed on inner surfaces of the first trench and the second trench and on a surface of the barrier layer that is not covered by the contact layer.

3. The semiconductor device according to claim 1, wherein: Also includes: substrate; a nucleation layer formed on the substrate; a superlattice layer formed on the nucleation layer; The buffer layer is formed on the superlattice layer.

4. The semiconductor device according to claim 3, characterized in that The material of the buffer layer is AlGaN, the material of the channel layer is GaN, the material of the barrier layer is AlGaN, and the material of the contact layer is p-GaN.

5. The semiconductor device according to claim 4, characterized in that The content of the Al component in the buffer layer increases continuously from 10% to 20%.

6. The semiconductor device according to claim 4, characterized in that The thickness of the buffer layer is in the range of 0.8-4.5 μm, the thickness of the channel layer is in the range of 200-800 nm, the thickness of the barrier layer is in the range of 15-45 nm, and the thickness of the contact layer is in the range of 10-40 nm.

7. The semiconductor device according to claim 1, wherein: The first trench is located at one side of the source electrode, the second trench is located at one side of the drain electrode, and the width of the first trench is smaller than the width of the second trench.

8. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and growing a nucleation layer, a superlattice layer, a buffer layer, a channel layer, a barrier layer, and a contact layer on the substrate; Etching the contact layer and forming a first trench and a second trench in the barrier layer, wherein the first trench and the second trench penetrate the barrier layer, a vertical projection of one side of the first trench overlaps with a vertical projection of one side of the contact layer, and a vertical projection of one side of the second trench overlaps with a vertical projection of another side of the contact layer; forming a gate electrode on the contact layer; forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode extend into the buffer layer; Wherein, the width of the first groove and the second groove is in the range of 2 to 4 μm.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After forming the first trench and the second trench, the method further includes forming a passivation layer on the surface of the intermediate structure, and before forming the gate electrode, the method further includes removing the passivation layer on the upper surface of the contact layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: The step of forming the source electrode and the drain electrode includes the steps of forming a buried portion, an intermediate connecting portion, and a top electrode portion, respectively.

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