Semiconductor device

Abstract

The invention relates to a semiconductor device. According to one embodiment, the semiconductor device 1 includes: a semiconductor substrate having an upper surface and a lower surface; and an emitter wiring, in which the semiconductor substrate has an active region including a plurality of IGBTs, a termination region, and a main bonding region, in which the semiconductor substrate of the main bonding region has an N-type drift layer and a P-type bonding impurity layer, wherein the semiconductor substrate of the termination region has an N-type drift layer and a P-type floating layer, and wherein at least the main bonding region has a trench electrode provided within the trench and a trench insulating film provided between the trench electrode and the semiconductor substrate, and wherein the trench electrode and the P-type bonding impurity layer are connected to the emitter wiring.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-149992 filed on September 15, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, for example, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Freewheeling Diode) and a semiconductor device including an RC-IGBT (Reverse Conducting IGBT). Background Art

[0004] Patent Document 1 describes a semiconductor device having an IGBT.

[0005] [Prior art literature]

[0006] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2017-079308 Summary of the invention

[0008] Electric field concentration in a semiconductor device causes the occurrence of single event burnout (hereinafter referred to as SEB). There is a need for a semiconductor device that can alleviate electric field concentration and reduce the occurrence rate of SEB.

[0009] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; and an emitter wiring provided on the first main surface via an insulating film, wherein when viewed from the first main surface side, the semiconductor substrate includes: an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination region arranged to surround the active region; and a main bonding region arranged between the active region and the termination region, wherein the semiconductor substrate of the main bonding region includes: a drift layer of a first conductivity type; and a bonding impurity layer of a second conductivity type provided to be larger than The drift layer is closer to the first main surface side, wherein the semiconductor substrate in the termination area includes: the drift layer; and a floating layer of the second conductivity type, which is provided closer to the first main surface side than the drift layer, wherein at least the main bonding area of ​​the semiconductor substrate includes: a trench electrode, which is provided in a trench formed in the first main surface; and a trench insulating film, which is provided between the trench electrode and the semiconductor substrate, wherein when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main bonding area toward the termination area, and wherein the trench electrode and the bonding impurity layer are connected to the emitter wiring in the main bonding area.

[0011] According to one embodiment, a semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; and an emitter wiring provided on the first main surface via an insulating film, wherein when viewed from the first main surface side, the semiconductor substrate includes: an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination region arranged to surround the active region; and a main bonding region arranged between the active region and the termination region, wherein the semiconductor substrate in the main bonding region includes: a drift layer of a first conductivity type; and a bonding impurity layer of a second conductivity type provided closer to the first main surface side than the drift layer, wherein the semiconductor substrate in the termination region includes: a drift layer; and a floating layer of a second conductivity type provided closer to the first main surface side than the drift layer, wherein at least the main bonding region of the semiconductor substrate includes: a trench electrode provided in the first a first main surface; a trench insulating film provided between a trench electrode and a semiconductor substrate, wherein the trench electrode includes a portion extending from an active region toward a termination region in one direction when viewed from the first main surface side, and wherein the trench electrode and the combined impurity layer are connected to an emitter wiring in the main combined region, wherein the IGBT includes: a drift layer; a barrier layer of a first conductivity type provided closer to the first main surface side than the drift layer; a channel layer of a second conductivity type provided closer to the first main surface side than the barrier layer; an emitter layer of a first conductivity type provided closer to the first main surface side than the channel layer; a gate trench electrode provided to clamp the barrier layer, the channel layer and the emitter layer in another direction intersecting with the one direction in a plane parallel to the first main surface; and a gate trench insulating film provided between each of the gate trench electrodes and the semiconductor substrate.

[0012] According to this embodiment, a semiconductor device that can reduce the occurrence rate of SEB can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a plan view illustrating a semiconductor device according to a reference example.

[0014] Figure 2 is a cross-sectional view illustrating a semiconductor device according to a reference example, showing a semiconductor device along Figure 1 Cross section along line II.

[0015] Figure 3 is a schematic diagram illustrating a simulation result of an electric field intensity distribution when a reverse bias is applied to a collector in a semiconductor device according to a comparative example.

[0016] Figure 4 is a schematic diagram illustrating a simulation result of an electric field intensity distribution when a reverse bias is applied to a collector in a semiconductor device according to a comparative example, and is Figure 3Magnified view of section IV.

[0017] Figure 5 is a graph illustrating electric field intensity distribution when a reverse bias is applied to a collector in a semiconductor device according to a comparative example, wherein the horizontal axis represents the position in a direction from an active region to a termination region of the semiconductor device, and the vertical axis represents the electric field intensity.

[0018] Figure 6 is a plan view illustrating the semiconductor device according to the first embodiment.

[0019] Figure 7 is a plan view illustrating a semiconductor device according to a comparative example, showing Figure 6 Magnified view of section VII.

[0020] Figure 8 is a cross-sectional view illustrating a main bonding region and a termination region of a semiconductor device related to a comparative example, showing a cross-sectional view along Figure 7 Cross section along line VIII-VIII.

[0021] Fig. 9 is a cross-sectional view illustrating an IGBT formed on a semiconductor substrate in a semiconductor device related to a comparative example, showing a cross-sectional view along Figure 7 Cross section along line IX-IX.

[0022] Fig.10 is a plan view illustrating a semiconductor device according to a first embodiment, having Figure 6 Magnified view of section X.

[0023] Fig.11 is a cross-sectional view illustrating a semiconductor device according to a first embodiment, showing a semiconductor device along Fig.10 A cross section along the line XI-XI.

[0024] Fig.12 is a cross-sectional view illustrating a semiconductor device according to a first embodiment, showing a semiconductor device along Fig.10 Cross section along line XII-XII.

[0025] Fig.13 is a plan view illustrating a semiconductor device according to a first modified example of the first embodiment.

[0026] Fig.14 is a cross-sectional view illustrating a semiconductor device according to a first modified example of the first embodiment, showing a semiconductor device along Fig.13 Cross section along line XIV-XIV.

[0027] Fig.15is a plan view illustrating a semiconductor device according to a second modified example of the first embodiment.

[0028] Fig.16 is a plan view illustrating another example of the semiconductor device according to another version of the second modified example.

[0029] Fig.17 is a plan view illustrating a semiconductor device according to a third modified example of the first embodiment.

[0030] Fig.18 is a plan view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in a semiconductor device related to a comparative example.

[0031] Fig.19 is a plan view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in the semiconductor device according to the first embodiment.

[0032] Fig. 20 is a perspective view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in a semiconductor device related to a comparative example, showing a direction along Fig.18 A cross-sectional perspective view of line XX-XX.

[0033] Fig.21 is a perspective view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in a semiconductor device according to a first embodiment, showing a direction along Fig.19 A perspective view of a section along line XXI-XXI.

[0034] Fig. 22 is a cross-sectional view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in a semiconductor device related to a comparative example.

[0035] Fig.23 is a cross-sectional view illustrating a simulation result of an electric field intensity distribution at a boundary between a main bonding region and a termination region in the semiconductor device according to the first embodiment.

[0036] Fig.24 is a graph illustrating electric field intensity distributions of the semiconductor device related to the comparative example and the semiconductor device according to the first embodiment, wherein the horizontal axis represents the position at the boundary between the main bonding region and the termination region and the vertical axis represents the electric field intensity.

[0037] Fig.25: is a graph illustrating collector breakdown voltages of a semiconductor device related to a comparative example and a semiconductor device according to the first embodiment, in which the horizontal axis represents the collector voltage and the vertical axis represents the leakage current.

[0038] Fig.26 is a plan view illustrating a semiconductor device according to a second embodiment.

[0039] Fig. 27 is a cross-sectional view illustrating a semiconductor device according to a second embodiment, showing a semiconductor device along Fig.26 Cross section along line XXVII-XXVII.

[0040] Fig.28 is a plan view illustrating a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0041] For the sake of clarity of explanation, the following description and drawings are appropriately omitted and simplified. In addition, in the drawings, when the hatching, etc. would make the drawings too complicated or when the area with the gap is clearly distinguished, the hatching, etc. may be omitted in the cross section. Note that in each of the drawings, the same elements are designated by the same reference numerals, and redundant explanations will be omitted when necessary. In addition, symbols are appropriately omitted to avoid confusing the drawings.

[0042] First, in <Cosmic ray resistance>, cosmic ray resistance related to the occurrence of SEB in a semiconductor device will be explained. In <Reference example>, a semiconductor device according to the reference example will be described. In <Problem newly discovered by the inventor>, a semiconductor device of the comparative example will be explained, and then a problem newly discovered by the inventor regarding the semiconductor device of the comparative example will be explained. In <First embodiment>, a semiconductor device according to the first embodiment will be described. At this time, the comparative example of <Semiconductor device of comparative example> and the embodiment of <Semiconductor device of first embodiment> will be compared and explained. Thereafter, in <Second embodiment> and <Third embodiment>, a semiconductor device of each embodiment will be described. Note that cosmic ray resistance, semiconductor devices according to the reference example and the comparative example, and problems newly discovered by the inventor are all within the scope of the technical ideas of the embodiments.

[0043] <Cosmic ray resistance>

[0044] Power devices including IGBTs, diodes, etc. need to have cosmic ray (also called cosmic radiation) resistance (referred to as cosmic ray resistance). For example, industrial products and automotive products need to have strict cosmic ray resistance of several FITs / chips or less. Cosmic ray resistance is the probabilistic resistance to neutron radiation.

[0045] When cosmic rays reach the Earth, they react with oxygen, nitrogen, etc. in the atmosphere and generate secondary particles. The generated secondary particles still have high energy and further react with oxygen, nitrogen, etc. in the atmosphere. Due to this cascade reaction, neutrons fall to the ground as neutron beams. Neutron beams can cause errors, resulting in malfunctions in semiconductor devices.

[0046] For example, as described below, errors occur in semiconductor devices due to the interaction between semiconductor devices and high-energy neutron beams. That is, first, a high-energy neutron beam enters the semiconductor device. This results in a nuclear reaction between the neutron beam and the atoms that constitute the semiconductor. Then, secondary particles are generated. The generated secondary particles enter the sensitive area. This will cause a single event phenomenon. A single event phenomenon is a general term for phenomena such as failures and damages that occur when a single particle including protons and heavy ions (such as He ions and Fe ions) is incident on a semiconductor device.

[0047] This single event phenomenon can cause both soft errors and hard errors. The problem with power devices including IGBTs, diodes, etc. is mainly hard errors including single event burnout (hereinafter referred to as SEB). In short, cosmic rays are converted into high-energy neutron beams (neutron beams cannot be shielded) before entering the semiconductor chip. Then, the neutron beams entering the high electric field region within the semiconductor chip generate secondary particles, which cause hard errors due to the single event phenomenon.

[0048] As the manufacturing process of semiconductor devices becomes more miniaturized, the cosmic ray resistance of semiconductor devices decreases. Therefore, one challenge is to improve the cosmic ray resistance against such neutron beam-induced failures.

[0049] For example, to improve cosmic ray resistance, one approach is to increase the thickness of the n-type drift layer in the semiconductor chip to reduce the electric field strength. However, increasing the thickness of the semiconductor chip deteriorates performance, such as collector-emitter saturation voltage VCE(sat) and switching (SW) loss. Therefore, there is a trade-off between cosmic ray resistance and the performance of power devices.

[0050] <Reference example>

[0051] A semiconductor device according to a reference example is described. Figure 1 is a plan view illustrating a semiconductor device 100 according to a reference example. Figure 2 is a cross-sectional view illustrating a semiconductor device 100 according to a reference example, showing a semiconductor device 100 along Figure 1 The cross section of line II. Figure 1 and 2As shown, the semiconductor device 100 of the reference example is formed in a semiconductor chip CP. The semiconductor chip CP includes, for example, a rectangular plate-shaped semiconductor substrate 150. The semiconductor substrate 150 has two plate surfaces and a chip edge 150E. For convenience, the two plate surfaces are referred to as an upper surface 151 and a lower surface 152.

[0052] Here, in order to facilitate the description of the semiconductor device 100, etc., an XYZ orthogonal coordinate system is introduced. The direction perpendicular to the upper surface 151 is defined as the Z-axis direction, and the two directions orthogonal to the Z-axis direction are defined as the X-axis and Y-axis directions. The +Z-axis direction is defined as the direction from the lower surface 152 toward the upper surface 151. For convenience, the +Z-axis direction is referred to as upward, and the -Z-axis direction is referred to as downward. Note that upward and downward are directions for convenience of explanation and do not represent the actual orientation when the semiconductor device 100 is used.

[0053] The four sides of the rectangular plate form the chip edge 150E of the semiconductor chip CP. When viewed from the upper surface 151 side, the semiconductor device 100 includes an active area ACT and a termination area TER. In the semiconductor device 100 of the reference example, the active area ACT is also referred to as an active cell area. In addition, the semiconductor device 100 has a gate pad GPD and an emitter pad EPD on the upper surface 151.

[0054] The active area ACT is located at the central part of the upper surface 151 of the semiconductor chip CP. The active area ACT includes, for example, a plurality of semiconductor devices, such as IGBTs. In the active area ACT, a plurality of IGBTs are arranged in a matrix. The gates of the plurality of IGBTs are connected to a gate path line GPL extending from a gate pad GPD. The emitters of the plurality of IGBTs are connected to an emitter pad EPD.

[0055] The termination region TER is arranged to surround the active region ACT. The termination region TER is located between the active region ACT and the chip edge 150E.

[0056] like Figure 2As shown, the semiconductor substrate 150 in the termination region TER has a field limiting ring (FLR). Specifically, for example, the semiconductor substrate 150 in the termination region TER includes an N-type drift layer 153 including an N-epitaxial layer, an N+ type field stop layer 157 including an N+ substrate, and a P++ type collector layer 158. In addition, the semiconductor substrate 150 in the termination region TER has a plurality of FLRs on the N-type drift layer 153. The FLR includes a P-type floating layer. The P-type floating layer includes a P-type impurity layer. For example, the semiconductor device 100 includes seven FLRs consisting of seven P-type floating layers p1 to p7 in the termination region TER. By adding the FLR, the semiconductor device 100 can promote the extension of the depletion layer and maintain a high voltage resistance. Therefore, in semiconductor devices 100 such as power MOS, an FLR structure that can relatively easily achieve high voltage resistance even with a shallow junction is often used.

[0057] <Newly discovered problem>

[0058] Figure 3 is a schematic diagram illustrating a simulation result of an electric field intensity distribution when a reverse bias is applied to the collector in the semiconductor device 101 according to the comparative example. Figure 4 is a schematic diagram illustrating a simulation result of an electric field intensity distribution when a reverse bias is applied to a collector in a semiconductor device 101 according to a comparative example, and is Figure 3 An enlarged view of section IV of Figure 3 and 4 and will be described later Figure 7 and 8 As shown, when viewed from the top surface 151 side, the semiconductor device 101 according to the comparative example has a semiconductor substrate 150 having an active region ACT, a main bonding region CON, and a termination region TER. As will be described later, the main bonding region CON is located between the active region ACT and the termination region TER. The main bonding region CON has a bonding impurity layer connected to an emitter wiring.

[0059] Figure 5 is a graph illustrating the distribution of electric field intensity when a reverse bias is applied to the collector in the semiconductor device 101 according to the comparative example, wherein the horizontal axis represents the position in the X-axis direction from the active region ACT toward the termination region TER of the semiconductor device 101, and the vertical axis represents the electric field intensity. Figures 3 to 5 As shown, the electric field intensity in the semiconductor device 101 according to the comparative example tends to be stronger in the main bonding region CON and the termination region TER than in the active region ACT. Figure 4 and 5The portion surrounded by the dotted line V in φ particularly indicates a region where the electric field intensity becomes high. In the case where there is a path connected to the emitter wiring, such as in the main bonding region CON, the incidence of SEB may increase after the neutron ray is incident on such a site.

[0060] So far, it is believed that SEB occurs only in the active region ACT. However, SEB may also occur in the outermost portion of the main bonding region CON. This is believed to be because there is a path to the emitter wiring, resulting in a high electric field region. The following embodiments solve at least one of the problems expected in the semiconductor device 101 of the comparative example.

[0061] First embodiment

[0062] Next, a semiconductor device according to Embodiment 1 will be described. Figure 6 1 is a plan view illustrating a semiconductor device 1 according to a first embodiment. Figure 6 As shown, the semiconductor device 1 of this embodiment includes a semiconductor substrate 150 having an upper surface 151 (first main surface) and a lower surface 152 (second main surface). The upper surface 151 is a surface opposite to the lower surface 152. Note that the use of Figure 6 Instead, the description of the semiconductor device 101 of the comparative example will be described.

[0063] When viewed from the upper surface 151 side, the semiconductor device 1 has a semiconductor substrate 150 having an active area ACT, a main bonding area CON, and a termination area TER. The active area ACT includes a plurality of semiconductor elements such as IGBTs formed on the semiconductor substrate 150. The main bonding area CON is located between the active area ACT and the termination area TER. The main bonding area CON is arranged to surround the active area ACT. The termination area TER is arranged to surround both the active area ACT and the main bonding area CON.

[0064] Generally speaking, the main bonding region CON is in the shape of a rectangular frame. Note that the shape of the main bonding region CON is not limited to the rectangular frame and may be changed according to the outer shape of the semiconductor device 1. Hereinafter, the shape of the main bonding region CON will be described as a rectangular frame. When viewed from the top surface 151 side, the main bonding region CON includes regions 121, 122, 123, and 124.

[0065] The region 121 is a portion on the +Y axis side of the active region ACT. The region 121 extends in the X axis direction. The region 121 is located between the end portion on the +Y axis side of the active region ACT in the Y axis direction and the termination region TER. The region 121 separates the active region ACT from the termination region TER in the Y axis direction. The region 122 is a portion on the +X axis side of the active region ACT. The region 122 extends in the Y axis direction. The region 122 is located between the end portion on the +X axis side of the active region ACT in the X axis direction and the termination region TER. The region 122 separates the active region ACT from the termination region TER in the X axis direction.

[0066] Region 123 is a portion on the -Y axis side of the active region ACT. Region 123 extends in the X axis direction. Region 123 is located between the -Y axis side end of the active region ACT in the Y axis direction and the termination region TER. Region 123 separates the active region ACT from the termination region TER in the Y axis direction. Region 124 is a portion on the -X axis side of the active region ACT. Region 124 extends in the Y axis direction. Region 124 is located between the -X axis side end of the active region ACT in the X axis direction and the termination region TER. Region 124 separates the active region ACT from the termination region TER in the X axis direction. Regions 121 and 123 extending in the X axis direction are referred to as first main bonding portions, and regions 122 and 124 extending in the Y axis direction are referred to as second main bonding portions.

[0067] In addition, the main bonding area CON includes a corner 125 (third main bonding portion). The corner 125 includes a connection portion connecting the area 121 and the area 122, a connection portion connecting the area 122 and the area 123, a connection portion connecting the area 123 and the area 124, and a connection portion connecting the area 124 and the area 121. The corner 125 may be appropriately provided with a round shape having a radius R.

[0068] The termination region TER is in the shape of a rectangular frame. Note that the shape of the termination region TER is not limited to a rectangular frame and may be changed according to the outer shape of the semiconductor device 1 and the main bonding region CON, etc. Hereinafter, the shape of the termination region TER will be described as a rectangular frame. When viewed from the top surface 151 side, the termination region TER includes regions 131, 132, 133, and 134.

[0069] The region 131 is a portion closer to the +Y axis side than the region 121. The region 131 extends in the X axis direction. The region 131 is sandwiched between the active regions ACT in the Y axis direction. The region 132 is a portion located on the +X axis side relative to the region 122. The region 132 extends in the Y axis direction. In the X axis direction, the region 132 is located between the active region ACT and the region 122.

[0070] Region 133 is a portion located on the -Y axis side relative to region 123. Region 133 extends in the X axis direction. In the Y axis direction, region 133 is located between active region ACT and region 123. Region 134 is a portion located on the -X axis side relative to region 124. Region 134 extends in the Y axis direction. In the X axis direction, region 134 is located between active region ACT and region 124. Regions 131 and 133 extending in the X axis direction are referred to as first termination portions, and regions 132 and 134 extending in the Y axis direction are referred to as second termination portions.

[0071] In addition, the termination region TER includes a corner 135 (third termination portion). The corner 135 includes a connection portion connecting the region 131 and the region 132, a connection portion connecting the region 132 and the region 133, a connection portion connecting the region 133 and the region 134, and a connection portion connecting the region 134 and the region 131. The corner 135 may be appropriately provided with a rounded shape having a radius R.

[0072] In this embodiment, the semiconductor device 1 has the main bonding region CON arranged in connection with the termination region TER in the region around the active region ACT.

[0073] Next, the configuration of the semiconductor device 1 according to the embodiment will be explained in comparison with the configuration of the semiconductor device 101 according to the comparative example. Therefore, first, the configuration of the semiconductor device 101 according to the comparative example will be explained.

[0074] <Semiconductor Device of Comparative Example>

[0075] Figure 7 is a plan view illustrating a semiconductor device 101 according to a comparative example, showing Figure 6 Magnified view of section VII. Figure 8 is a cross-sectional view illustrating a main bonding region CON and a termination region TER of a semiconductor device 101 according to a comparative example, showing a cross-sectional view along Figure 7 Cross section along line VIII-VIII. Fig. 9 is a cross-sectional view illustrating an IGBT 10a in an active region ACT of a semiconductor device 101 according to a comparative example, showing a cross-sectional view along Figure 7 Cross section along line IX-IX.

[0076] like Figures 7 to 9As shown, when viewed from above, the semiconductor device 101 of the comparative example has an active region ACT, a main bonding region CON, and a termination region. The semiconductor device 101 includes an emitter wiring 141, a gate wiring 147, and a termination wiring 181 provided on an upper surface 151 of a semiconductor substrate 150 via an insulating film 164. The emitter wiring 141, the gate wiring 147, and the termination wiring 181 may be aluminum wirings including aluminum (Al).

[0077] <Active Area>

[0078] In the semiconductor substrate 150 in the active region ACT, for example, a plurality of IGBTs 10a are formed. Figure 7 In the active region ACT of FIG. 1 , the gate trench electrodes 160 of the plurality of IGBTs 10a are simplified and schematically shown. Fig. 9 As shown, for example, the IGBT 10a has an N-type drift layer 153, an N+ type barrier layer 154, a P type channel layer 155, an N+ type emitter layer 156, a gate trench electrode 160, a gate trench insulating film 165, an N+ type field stop layer 157, a P++ type collector layer 158, and a P type floating layer 159. Note that the IGBT 10a may include additional components in addition to these components, or some of these components may be omitted. In order to avoid confusing the drawings, the gate trench insulating film 165 and the insulating film 164 on the semiconductor substrate 150 are shown with thick lines. The P type floating layer 159 may be referred to as an IGBT floating layer.

[0079] Note that N++ type and P++ type represent low resistance N-type and P-type conductivities, respectively. The resistance of N+ type and P+ type is higher than that of N++ type and P++ type, respectively, but represents that the resistance of N-type and P-type conductivities is lower than that of N-type and P-type. P-type and N-type represent that their resistance of N-type and P-type conductivities is higher than that of N-type and P-type, respectively. Therefore, N-type and P-type represent that they are N-type and P-type conductivities, and the resistance is between N+ type and P+ type and P-type and N-type, respectively. N+ type and P+ type represent that they are N-type and P-type conductivities, and the resistance is between N++ type and P++ type and P-type and N-type, respectively. In the following, unless specifically mentioned, the same meaning is implied. N-type conductivity may be referred to as a first conductivity type, and P-type conductivity may be referred to as a second conductivity type.

[0080] Note that N-type conductivity can be considered as a second conductivity type, and P-type conductivity can be considered as a first conductivity type. In addition, semiconductor devices in which the conductivity type of each component is opposite to the conductivity type disclosed herein are also within the scope of the technical ideas of the present disclosure. Moreover, the resistances of N++-type, N+-type, N-type, and N-type semiconductor layers are examples. The resistance may be greater than the resistance shown in the present disclosure, or may be smaller. Similarly, the resistances of P++-type, P+-type, P-type, and P-type semiconductor layers are examples. The relative resistance of each semiconductor layer may be reversed depending on the situation.

[0081] The N-type drift layer 153 is provided on the surface 151 side above the N+ type field stop layer 157. The N-type drift layer 153 is provided across the active region ACT, the main coupling region CON, and the termination region TER.

[0082] The N+ type barrier layer 154 is provided on the surface 151 side above the N- type drift layer 153. For example, when viewed from the surface 151 side, the N+ type barrier layer 154 extends in the Y-axis direction. The N+ type barrier layer 154 is sandwiched on both sides in the X-axis direction by the gate trench electrode 160. That is, the N+ type barrier layer 154 is located inside and is sandwiched by the gate trench electrode 160.

[0083] The P-type channel layer 155 is provided on the surface 151 side above the N+ type barrier layer 154. The P-type channel layer 155 is sandwiched on both sides in the X-axis direction by the gate trench electrode 160. The P-type channel layer 155 is connected to the emitter wiring 141 filled in the through hole penetrating the insulating film 164 and the N+ type emitter layer 156.

[0084] The N+ type emitter layer 156 is provided on the surface 151 side above the P type channel layer 155. The N+ type emitter layer 156 is located inside, surrounded by the gate trench electrode 160. The N+ type emitter layer 156 is connected to the emitter wiring 141 filled in the through hole penetrating the insulating film 164.

[0085] A pair of gate trench electrodes 160 is provided to sandwich the N+ type barrier layer 154, the P type channel layer 155, and the N+ type emitter layer 156 from both sides in the X-axis direction. Each gate trench electrode 160 includes, for example, a portion extending in the Y-axis direction when viewed from the surface 151 side. For example, in a pair of gate trench electrodes 160, one gate trench electrode 160 on the -X axis side is referred to as a gate trench electrode 161, and one gate trench electrode 160 on the +X axis side is referred to as a gate trench electrode 162. Therefore, a pair of gate trench electrodes 160 of the IGBT 10a includes the gate trench electrode 161 and the gate trench electrode 162.

[0086] The gate trench electrode 161 is connected to the gate wiring 147, for example. The gate trench electrode 162 is connected to the emitter wiring 141, which is filled in the through hole penetrating the insulating film 164. Therefore, the N+ type emitter layer 156, the P type channel layer 155 and the gate trench electrode 162 are connected to the emitter wiring 141. The structure between a pair of gate trench electrodes 160 is called a trench structure. For example, the trench structure of the IGBT 10a includes an N+ type barrier layer 154, a P type channel layer 155 and an N+ type emitter layer 156. The trench structure of the IGBT 10a may include other components such as a contact layer.

[0087] The P-type floating layer 159 is provided between adjacent IGBTs 10a among the plurality of IGBTs 10a. For example, the P-type floating layer 159 is provided between the gate trench electrode 162 of the IGBT 10a on the -X axis side and the gate trench electrode 161 of the IGBT 10a on the +X axis side among the adjacent IGBTs 10a. The P-type floating layer 159 is provided on opposite sides of the N+ type barrier layer 154, the P-type channel layer 155, and the N+ type emitter layer 156 across the gate trench electrode 160.

[0088] The P-type floating layer 159 is provided on the surface 151 side above the N-type drift layer 153. Therefore, on the N-type drift layer 153, from the -X axis direction side, the P-type floating layer 159, the gate trench electrode 161 (covered by the gate trench insulating film 165), the trench structure, the gate channel electrode 162 (covered by the gate channel insulating film 165), and the P-type floating layer 159 are arranged along the X axis direction. In the active region ACT, this configuration is arranged to be repeated in the X axis direction.

[0089] The P-type floating layer 159 between the P-type floating layer 159 at the +X-axis direction end portion of the active region ACT in the X-axis direction and the P-type floating layer 159 at the -X-axis direction end portion of the active region ACT in the X-axis direction is in contact with the gate trench electrodes 161 and 162. In other words, the P-type floating layer 159 is formed between the adjacent IGBTs 10a except for the end portion of the active region ACT in the X-axis direction.

[0090] The gate trench insulating film 165 is provided between the gate trench electrode 160 and the semiconductor substrate 150. Specifically, the gate trench insulating film 165 is provided between the gate trench electrode 160 and the N-type drift layer 153, the N+ type barrier layer 154, the P-type channel layer 155, the N+ type emitter layer 156 and the P type floating layer 159.

[0091] An N+ type field stop layer 157 is provided on the surface 152 side below the N- type drift layer 153. A P++ type collector layer 158 is provided on the surface 152 side below the N+ type field stop layer 157. The P++ type collector layer 158 is connected to a collector wiring. Note that the collector wiring is omitted in order not to complicate the drawing.

[0092] <Main Binding Area>

[0093] The semiconductor substrate 150 of the main bonding region CON has an N-type drift layer 153, an N+ type field stop layer 157, a P++ type collector layer 158, and a P type bonding impurity layer 170. In addition, the semiconductor substrate 150 of the main bonding region CON may include other components in addition to these components, or some of these components may be omitted. The P type bonding impurity layer 170 is provided on the surface 151 side above the N-type drift layer 153. The N+ type field stop layer 157 is provided on the surface 152 side below the N-type drift layer 153. The P++ type collector layer 158 is provided on the surface 152 side below the N+ type field stop layer 157.

[0094] The P-type bonding impurity layer 170 is connected to the emitter wiring 141 in the main bonding region CON. The emitter wiring 141 has, for example, a main body portion 142 and a contact 143. The contact 143 is a portion connected to the P-type bonding impurity layer 170 in the emitter wiring 141. The P-type bonding impurity layer 170 is connected to the emitter wiring 141 through the contact 143. Note that Figure 7 and 8 The contact 143 in FIG. 1 is composed of three parts, but is not limited thereto, and may be composed of one part or a plurality of parts other than three.

[0095] <Termination Area>

[0096] The semiconductor substrate 150 in the termination region TER has an N-type drift layer 153, an N+ type field stop layer 157, a P++ type collector layer 158, and a plurality of P-type floating layers 190. The plurality of P-type floating layers 190 are provided on the upper surface 151 side above the N-type drift layer 153. The N+ type field stop layer 157 is provided on the lower surface 152 side below the N-type drift layer 153. The P++ type collector layer 158 is provided on the lower surface 152 side below the N+ type field stop layer 157. The plurality of P-type floating layers 190 form an FLR.

[0097] The P-type floating layer 190 is connected to the termination wiring 181 in the termination region TER. The termination wiring 181 has, for example, a body 182 and a contact 183. The contact 183 is a portion connected to the P-type floating layer 190 in the termination wiring 181. The P-type floating layer 190 is connected to the termination wiring 181 via the contact 183.

[0098] The P-type floating layer 190a closest to the main bonding region CON in the termination region TER is referred to as a first ring layer p1. The second P-type floating layer 190b from the main bonding region CON side in the termination region TER is referred to as a second ring layer p2. Similarly, the k-th P-type floating layer 190 from the main bonding region CON side in the termination region TER is referred to as a k-th ring layer pk.

[0099] The termination wiring 181 is not formed on the first ring layer p1, that is, on the P-type floating layer 190a. Therefore, the P-type floating layer 190a constituting the first ring layer p1 is not connected to the termination wiring 181. On the other hand, the termination wiring 181 is formed on the second ring layer p2 (P-type floating layer 190b), the third ring layer p3, and the k-th ring layer pk. The P-type floating layers 190 other than the P-type floating layer 190a are connected to the termination wiring 181 via the contact 183.

[0100] The termination wiring 181 is not connected to the emitter wiring 141 and is in a floating state. Therefore, the P-type floating layer 190 constituting the FLR is in a floating state. Therefore, the P-type floating layer 190 is not connected to the emitter wiring 141 in the termination region TER.

[0101] <Semiconductor Device of First Embodiment>

[0102] Next, the semiconductor device of the first embodiment will be described. Fig.10 is a plan view illustrating a semiconductor device 1 according to a first embodiment, and is a plan view illustrating Figure 6 Magnified view of section X. Fig.11 is a cross-sectional view illustrating a semiconductor device 1 according to a first embodiment, showing a semiconductor device 1 along Fig.10 A cross section along the line XI-XI. Fig.12 is a cross-sectional view illustrating a semiconductor device 1 according to a first embodiment, showing a semiconductor device 1 along Fig.10 Cross section along line XII-XII. Fig.10 and 11 An enlarged view of a portion of the primary bonding area CON is also shown.

[0103] like Fig.10 As shown, similar to the comparative example semiconductor device 101, when viewed from above, the semiconductor device 1 of this embodiment has an active region ACT, a main bonding region CON, and a termination region. In the semiconductor device 1 of this embodiment, at least the main bonding region CON of the semiconductor substrate 150 has a trench electrode 260 and a trench insulating film 265. Fig.10In order to avoid complicating the drawings, the trench electrode 260 and the trench insulating film 265 are represented by lines. A single line represents both the trench electrode 260 and the trench insulating film 265. Therefore, in the drawings, the shape of the trench electrode 260 is rectangular. That is, when viewed from the top surface 151 side, the trench electrode 260 is, for example, annular in which both ends of the two portions extending in the X-axis direction are connected.

[0104] In the drawing, the trench electrode 260 is formed in the regions 122 and 132 on the +X axis side of the active region ACT, but it may be formed in the regions 124 and 134 on the −X axis side of the active region ACT.

[0105] <Trench Electrode>

[0106] like Figures 10 to 12 As shown, the trench electrode 260 is provided in the trench formed on the top surface 151 of the semiconductor substrate 150. A trench insulating film 265 is provided between the trench electrode 260 and the semiconductor substrate 150. When viewed from the top surface 151 side, the trench electrode 260 includes a portion extending from the main bonding region CON toward the termination region TER in the X-axis direction. Specifically, one end of the trench electrode 260 in the X-axis direction is located in the main bonding region CON, and the other end is located in the termination region TER. For example, the end of the trench electrode 260 on the -X axis side is located in the P-type bonding impurity layer 170 of the main bonding region CON, and the end on the +X axis side is located in the P-type floating layer 190a of the termination region TER. Fig.11 and 12 The cross-sectional shapes of the trench electrodes 260 in FIG. 2 are schematic diagrams.

[0107] The termination region TER has a plurality of P-type floating layers 190, including a portion extending in the Y-axis direction. As mentioned earlier, among the plurality of P-type floating layers 190 in the termination region TER, one P-type floating layer 190 closest to the main bonding region CON is considered to be a first P-type floating layer. The P-type floating layer 190b adjacent to the first P-type floating layer is considered to be a second P-type floating layer. In this case, the end portion of the trench electrode 260 on the termination region TER side is located in the first P-type floating layer (190a).

[0108] like Fig.11 and 12 As shown, the lower end of the trench electrode 260 (ie, the end on the −Z axis side) is located in the P-type combined impurity layer 170 and the P-type floating layer 190 a . The lower end of the trench electrode 260 may also be located in the N-type drift layer 153 .

[0109] The trench electrode 260 is connected to the emitter wiring 141 in the main bonding region CON. The emitter wiring 141 also has a contact 144. The contact 144 may include a first contact 145 and a second contact 146. The contact 144 may be referred to as an emitter contact. The first contact 145 and the second contact 146 may be referred to as a first emitter contact and a second emitter contact, respectively. The first contact 145 is connected to the P-type bonding impurity layer 170 and the trench electrode 260 within the annular trench electrode 260. The second contact 146 is connected to the P-type bonding impurity layer 170 between the annular trench electrodes 260 adjacent in the Y-axis direction.

[0110] The first contact 145 and the second contact 146 are formed within the range of the main coupling region CON. The first contact 145 and the second contact 146 are not formed in the P-type floating layer 190a in the termination region TER.

[0111] The semiconductor substrate 150 of the main bonding region CON may have a P-type contact layer 174 provided on the surface 151 side above the P-type bonding impurity layer 170. The P-type contact layer 174 includes a higher concentration of P-type impurities than the P-type bonding impurity layer 170. The P-type contact layer 174 may include a first contact layer 175 and a second contact layer 176. The P-type contact layer 174 may be referred to as an emitter contact layer. The first contact layer 175 and the second contact layer 176 may be referred to as a first emitter contact layer and a second emitter contact layer, respectively.

[0112] The first contact layer 175 is located in the annular trench electrode 260. The second contact layer 176 is located between the annular trench electrodes 260 adjacent in the Y-axis direction. The first contact 145 is connected to the P-type combined impurity layer 170 via the first contact layer 175. The second contact 146 is connected to the P-type combined impurity layer 170 via the second contact layer 176. The upper end of the trench electrode 260 on the +Z axis side has a step relative to the lower end of the first contact 145 on the -Z axis side. The trench electrode 260 is connected to the emitter wiring through the step. Therefore, the trench electrode 260 can increase the contact area with the emitter wiring 141.

[0113] The contact 144 is connected to the P-type combined impurity layer 170 and the trench electrode 260. Therefore, the trench electrode 260 is connected to the emitter wiring 141. In this way, the semiconductor device 1 of this embodiment has a trench electrode 260 connected to the emitter potential of the emitter wiring 141 at least in the main combined region CON. The semiconductor device 1 has a contact 144 for fixing the trench electrode 260 to the emitter potential. In addition, the semiconductor device 1 has a contact 144 for enhancing hole discharge during shutdown. Therefore, the semiconductor device 1 can suppress the occurrence of SEB caused by electric field relaxation by forming a contact 144 connected to the emitter wiring 141. This can improve the resistance to cosmic rays and the collector withstand voltage and hole discharge effect. Therefore, the semiconductor device 1 can suppress current concentration and improve the anti-destruction performance (reverse bias safe operating area, hereinafter referred to as RBSOA).

[0114] <First Modification Example>

[0115] Fig.13 is a plan view illustrating a semiconductor device 1 a according to a first modified example of the first embodiment. Fig.14 is a cross-sectional view illustrating a semiconductor device 1a according to a first modified example of the first embodiment, showing a semiconductor device 1a along Fig.13 Cross section along line XIV-XIV. Fig.14 An enlarged view of a portion of the primary bonding area CON is also shown.

[0116] like Fig.13 and 14 As shown, in the semiconductor device 1a according to the first modification, the contact 144 is formed across a plurality of annular trench electrodes 260 and a P-type combined impurity layer 170 arranged along the Y-axis direction. The upper end of the trench electrode 260 is formed to be flat so as to be aligned with the upper surface 151 of the semiconductor substrate 150. Therefore, the contact 144 is connected to the P-type combined impurity layer 170 via the first contact layer 175 and the second contact layer 176. The upper end of the +Z-axis side of the trench electrode 260 is connected to the lower end of the contact 144. By arranging the contact 144 formed across a plurality of annular trench electrodes 260 and a P-type combined impurity layer 170, the contact area can be increased and the manufacturing process can be simplified.

[0117] <Second Modification Example>

[0118] Fig.15 1 is a plan view illustrating a semiconductor device 1b according to a second modification of the first embodiment. Fig.15As shown, in the semiconductor device 1b of the second modification, the trench electrode 260 is formed in the regions 121 and 131 located more on the +Y axis side than the active region ACT. The trench electrode 260 includes a portion extending from the active region ACT toward the termination region TER in the Y axis direction. It should be noted that the trench electrode 260 may be formed in the regions 123 and 133 located more on the -Y axis side than the active region ACT.

[0119] Also in this modification, when viewed from the upper surface 151 side, the trench electrode 260 includes a portion extending in the direction from the main bonding region CON toward the termination region TER, but the trench electrode 260 extends in the Y-axis direction. Specifically, one end of the trench electrode 260 in the Y-axis direction is located in the main bonding region CON, and the other end is located in the termination region TER. For example, the end of the trench electrode 260 on the -Y-axis side is located in the P-type bonding impurity layer 170 of the main bonding region CON, and the end of the trench electrode 260 on the +Y-axis side is located in the P-type floating layer 190a of the termination region TER.

[0120] In the region 131, the termination region TER has a plurality of P-type floating layers 190, including a portion extending in the X-axis direction. Among the plurality of P-type floating layers 190 in the termination region TER, the P-type floating layer 190a closest to the main coupling region CON is considered to be a first P-type floating layer. When the P-type floating layer 190b adjacent to the first P-type floating layer is considered to be a second P-type floating layer, the end portion of the trench electrode 260 on the termination region TER side is located in the first P-type floating layer.

[0121] When viewed from the upper surface 151 side, the semiconductor substrate 150 has a gate wiring region GAT arranged between the main bonding region CON and the active region ACT in the Y-axis direction. The gate wiring region GAT has a gate wiring 147 arranged on the upper surface 151 of the semiconductor substrate 150 via an insulating film 164. The gate trench electrode 161 of the IGBT 10a is connected to the gate wiring 147 in the gate wiring region GAT.

[0122] If located at least in the main bonding region CON, the trench electrode 260 may extend to the gate wiring region GAT in the Y-axis direction, or may extend to the termination region TER. In addition, the trench electrode 260 may be arranged only in the main bonding region CON.

[0123] In the semiconductor device 1 b of the second modified example, the contact 144 of the emitter wiring 141 may have a first contact 145 and a second contact 146 . Furthermore, the contact 144 may be connected to the plurality of ring-shaped trench electrodes 260 and the P-type junction impurity layer 170 .

[0124] Fig.16 1 is a plan view illustrating a semiconductor device 1bb according to another example of the second modified example of the first embodiment. Fig.16 As shown, the semiconductor device 1bb may not include the contact 144. Since the semiconductor device 1bb has the gate wiring 147, the current flows through the path indicated by the arrow XV in the drawing. Due to this current, if there is an influence of potential fluctuation, the contact 144 of the emitter wiring 141 can be allowed to be reduced. Although the carrier extraction effect is reduced, the dynamic avalanche is suppressed by the electric field relaxation effect. Therefore, compared with the semiconductor device 101 of the comparative example, the RBSOA resistance can be improved.

[0125] <Third Modification Example>

[0126] Fig.17 1 is a plan view illustrating a semiconductor device 1c according to a third modified example of the first embodiment. Fig.17 As shown, in the semiconductor device 1c of the modified example 3, the trench electrode 260 is formed at the corner 125. The trench electrode 260 includes a portion extending along the X-axis direction or the Y-axis direction at the corner 125. The trench electrode 260 may include a portion extending from the corner 125 to the corner 135. In addition, the trench electrode 260 may include a portion extending from the corner 125 to the gate wiring area GAT. By placing the trench electrode 260 at the corner 125, the electric field at the corner 125 and the like of the semiconductor device 1c can be relaxed.

[0127] When there is a possibility of affecting the shape of the FLR in the termination region TER, it is desirable to optimize the structure of the trench electrode 260 and the FLR. In addition, the trench electrode 260 is not limited to a shape including a portion extending in the X-axis direction or the Y-axis direction, but may be bent to match the shape of the FLR.

[0128] Next, the effect of this embodiment will be explained. In the semiconductor devices 1, 1a, 1b, 1bb and 1c (hereinafter referred to as semiconductor device 1) of this embodiment, the trench electrode 260 and the P-type bonding impurity layer 170 in the main bonding region CON are connected to the emitter wiring 141. Therefore, the semiconductor device 1 can form a hole discharge path in the main bonding region CON and improve the hole discharge effect. Therefore, local current concentration can be suppressed and RBSOA resistance can be improved. The semiconductor device 1 of this embodiment, for example, Figures 3 to 5 The highest electric field region shown has an electric field relaxation effect. This allows the withstand voltage to be increased due to the relaxation effect of the critical electric field.

[0129] Fig.18 and 191 and 2 are plan views illustrating simulation results of electric field intensity distribution at the boundary between the main bonding region CON and the termination region TER in the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, respectively. Fig. 20 and Fig.21 are perspective views illustrating simulation results of electric field intensity distribution at the boundary between the main bonding region CON and the termination region TER in the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, respectively, showing the electric field intensity distribution at the boundary between the main bonding region CON and the termination region TER along Fig.18 The line XX-XX and Fig.19 A perspective view of a section along line XXI-XXI. Fig. 22 and 23 1 and 2 are cross-sectional views illustrating simulation results of electric field intensity distribution at a boundary between a main bonding region CON and a termination region TER in a semiconductor device 101 according to a comparative example and a semiconductor device 1 according to Embodiment 1, respectively.

[0130] like Fig.18 , 20 22, a plurality of contact grooves of the contact 143 of the emitter wiring 141 in the P-type bonding impurity layer 170 connected to the main bonding region CON of the semiconductor device 101 according to the comparative example are in the high electric field region. Fig.19 , 21 As shown in FIG. 23, in addition to the plurality of contact grooves having the contacts 144 connected to the emitter wiring 141 in the P-type bonding impurity layer 170 of the main bonding region CON, the semiconductor device 1 according to this embodiment further has a trench electrode 260 connected to the emitter wiring 41. This allows relaxation of the electric field in the P-type bonding impurity layer 170 of the main bonding region CON.

[0131] Fig.24 is a graph illustrating the electric field intensity distribution of the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to Embodiment 1, wherein the horizontal axis represents the position at the boundary between the main bonding region CON and the termination region TER, and the vertical axis represents the electric field intensity. Fig.24 As shown, in the semiconductor device 101 of the comparative example, the electric field intensity in the main bonding region CON is much higher than the electric field intensity in the termination region TER.

[0132] In contrast, in the semiconductor device 101 according to the first embodiment, the electric field intensity in the main bonding region CON is reduced compared to the comparative example, and the electric field density in the termination region TER is higher than that in the comparative example. Therefore, the electric field intensity difference between the main bonding region CON and the termination region TER in the semiconductor device 1 of the first embodiment is reduced. Therefore, the semiconductor device 1 of the first embodiment can alleviate the electric field concentration in the main bonding region CON.

[0133] Fig.25 is a graph illustrating collector breakdown voltages of the semiconductor device 101 according to the comparative example and the semiconductor device 1 according to the first embodiment, wherein the horizontal axis represents the collector voltage VC and the vertical axis represents the leakage current ICES. Fig.25 As shown, the collector breakdown voltage of the semiconductor device 1 of the first embodiment can be significantly improved compared with the semiconductor device 101 of the comparative example.

[0134] In the semiconductor device 1 of this embodiment, the electric field relaxation structure is due to the trench electrode 260 at the emitter potential. Therefore, even if hot carriers are generated, there is no influence on the characteristic change with respect to the trench electrode 260 at the emitter potential.

[0135] <Second Embodiment>

[0136] Next, a semiconductor device according to a second embodiment will be described. Fig.26 is a plan view illustrating a semiconductor device 2 according to the second embodiment. Fig. 27 is a cross-sectional view illustrating a semiconductor device 2 according to a second embodiment, showing a semiconductor device 2 along Fig.26 Cross section along line XXVII-XXVII. Fig.26 and 27 An enlarged view of a portion of the termination region TER is also shown. Fig.26 and 27 As shown, in the semiconductor device 2, the end portion of the trench electrode 260 on the termination region TER side is located in the second P-type floating layer 190b from the main bonding region CON side.

[0137] The P-type floating layer 190b is connected to the terminal wiring 181 via the contact 184. The contact 184 includes a first contact 185 and a second contact 186. The first contact 185 is connected to the P-type floating layer 190b within the annular trench electrode 260. The second contact 186 is connected to the P-type floating layer 190b between adjacent annular trench electrodes 260.

[0138] The first contact 185 is not connected to the trench electrode 260. In the main bonding region CON, the trench electrode 260 is connected to the first contact 145 or the contact 144. On the other hand, in the termination region TER, the trench electrode 260 is not connected to the first contact 185. Therefore, the trench electrode 260 can maintain the emitter potential. In addition, the termination wiring 181 including the first contact 185 can be maintained in a floating state.

[0139] In semiconductor device 2, contacts 184 including first contact 185 and second contact 186 extend in the X-axis direction in which trench electrode 260 extends. Therefore, connection of P-type floating layer 190b to trench electrode 260 can be suppressed and P-type floating layer 190b can be prevented from becoming an emitter potential.

[0140] In the termination region TER, the semiconductor substrate 150 may have a P-type contact layer 194, which is provided on the surface 151 side above the P-type floating layer 190b. The P-type contact layer 194 includes a higher concentration of P-type impurities than the P-type floating layer 190b. The P-type contact layer 194 includes a first contact layer 195 and a second contact layer 196. The first contact layer 195 is located within the annular trench electrode 260. The second contact layer 196 is placed between adjacent annular trench electrodes 260. The first contact 185 is connected to the P-type floating layer 190b through the first contact layer 195. The second contact 186 is connected to the P-type floating layer 190b through the second contact layer 196.

[0141] According to the semiconductor device 2 of this embodiment, since the trench electrode 260 extends to the P-type floating layer 190b, the electric field relaxation region can be extended to the second FLR in the termination region TER. The interval of the FLR can be widened toward the periphery of the semiconductor device 2. In this case, it is considered that the electric field strength relative to the trench electrode 260 increases. Therefore, by making the trench electrode 260 an emitter potential, the electric field can be relaxed, the collector withstand voltage can be improved, and it can be shrunk. Therefore, the relaxation of the electric field by the trench electrode 260 can be optimized at an interval corresponding to the FLR. When the interval of the FLR is fixed, the range from the ring layer p0 to the ring layer p1 or about the ring layer p2 becomes a high electric field. Therefore, by extending the trench electrode 260 to such a high electric field range, the electric field concentration can be alleviated.

[0142] <Third Embodiment>

[0143] A semiconductor device according to the third embodiment is described. Fig.28 1 is a plan view illustrating a semiconductor device 3 according to a third embodiment. Fig.28 As shown, in the semiconductor device 3 of this embodiment, the end of the trench electrode 260 on the termination region TER side is located in the P-type bonding impurity layer 170 in the main bonding region CON. Therefore, both ends of the trench electrode 260 in the X-axis direction are located in the main bonding region CON. The contact 144 may include a first contact 145 and a second contact 146. The contact 144 is connected to the trench electrode 260 and the P-type bonding impurity layer 170. Even with this configuration, electric field concentration can be alleviated.

[0144] The present disclosure made by the inventor has been specifically described based on the embodiment, but it goes without saying that the present disclosure is not limited to the described embodiments and modifications, and various changes can be made without departing from the gist thereof. For example, a combination of the configurations of the first to third embodiments and the first to third modifications is also within the scope of the technical concept of the embodiment. In addition, the following configurations are also within the scope of the technical concept of the embodiment.

[0145] (Note 1)

[0146] a semiconductor substrate having a first main surface and a second main surface opposite to the floating first main surface; and

[0147] an emitter wiring provided on the floating first main surface via an insulating film,

[0148] wherein when viewed from the floating first main surface side, the floating semiconductor substrate comprises:

[0149] an active region including a plurality of IGBTs formed on a floating semiconductor substrate;

[0150] a termination region arranged to surround the floating active region; and

[0151] The main bonding area is arranged between the floating active area and the floating termination area,

[0152] The floating semiconductor substrate of the floating main bonding region comprises:

[0153] A drift layer of a first conductivity type; and

[0154] a second conductivity type combined impurity layer provided closer to the floating first main surface side than the floating drift layer,

[0155] The floating semiconductor substrate in the floating termination region includes:

[0156] a floating drift layer; and

[0157] a floating layer of a floating second conductivity type provided closer to the floating first main surface side than the floating drift layer,

[0158] Wherein at least the floating main bonding region of the floating semiconductor substrate comprises:

[0159] a trench electrode provided in a trench formed in the floating first main surface; and

[0160] a trench insulating film provided between the floating trench electrode and the floating semiconductor substrate,

[0161] wherein the floating trench electrode includes a portion extending in one direction from the floating main bonding region toward the floating termination region when viewed from the floating first main surface side, and

[0162] The floating trench electrode and the floating junction impurity layer are connected to the floating emitter wiring in the floating main junction region.

[0163] The IGBTs include:

[0164] floating drift layer;

[0165] a floating first conductivity type barrier layer provided closer to the floating first main surface side than the floating drift layer;

[0166] a floating second conductivity type channel layer provided closer to the floating first main surface side than the floating barrier layer;

[0167] a floating first conductivity type emitter layer provided closer to the floating first main surface side than the floating channel layer;

[0168] a gate trench electrode provided to sandwich the floating barrier layer, the floating channel layer, and the floating emitter layer in one direction in a plane parallel to the floating first main surface;

[0169] A gate trench insulating film is provided between each of the floating gate trench electrodes and the floating semiconductor substrate.

[0170] (Note 2)

[0171] The semiconductor device according to note 1, further comprising:

[0172] a gate wiring provided on the first main surface via an insulating film,

[0173] wherein the semiconductor substrate includes a gate wiring region arranged between the main bonding region and the active region in one direction when viewed from the first main surface side, and

[0174] The gate trench electrode is connected to the gate wiring in the gate wiring region.

[0175] (Note 3)

[0176] According to Note 2 of the semiconductor device,

[0177] wherein the trench electrode includes a portion extending from the gate wiring region to the termination region when viewed from the first main surface side, and

[0178] One end of the trench electrode in one direction is located in the gate wiring region, and the other end is located in the termination region.

[0179] (Note 4)

[0180] According to Note 2 of the semiconductor device,

[0181] wherein the trench electrode includes a portion extending from the gate wiring region to the main bonding region when viewed from the first main surface side, and

[0182] One end of the trench electrode in one direction is located in the gate wiring region, and the other end is located in the main bonding region.

[0183] [Description of Reference Numerals]

[0184] 1, 1a, 1b, 1bb, 1c, 2, 3: semiconductor device 10a: IGBT

[0185] 100, 101: Semiconductor devices

[0186] 121, 122, 123, 124: Area

[0187] 125: Corner

[0188] 131, 132, 133, 134: Area

[0189] 135: Corner

[0190] 141: Emitter wiring

[0191] 142: Main body

[0192] 143, 144: Contact

[0193] 145: First Contact

[0194] 146: Second Contact

[0195] 147: Gate wiring

[0196] 150: Semiconductor substrate

[0197] 150E: Chip Edge

[0198] 151: Upper surface

[0199] 152: Lower surface

[0200] 153: N-type drift layer

[0201] 154: N+ type barrier layer

[0202] 155: P-type channel layer

[0203] 156: N+ type emitter layer

[0204] 157: N+ type field stop layer

[0205] 158: P++ type collector layer

[0206] 159: P-type floating layer

[0207] 160, 161, 162: Gate trench electrodes

[0208] 164: Insulation film

[0209] 165: Gate trench insulation film

[0210] 170: P-type combined impurity layer

[0211] 174: P-type contact layer

[0212] 175: First contact layer

[0213] 176: Second contact layer

[0214] 181: Termination wiring

[0215] 182: Main body

[0216] 183, 184: Contact

[0217] 185: First Contact

[0218] 186: Second Contact

[0219] 190, 190a, 190b: P-type floating layer

[0220] 194: P-type contact layer

[0221] 195: First contact layer

[0222] 196: Second contact layer

[0223] 260: Grooved Electrode

[0224] 265: Trench insulation film

[0225] ACT: Active Area

[0226] CON: Main binding region

[0227] CP: semiconductor chip

[0228] EPD: Emitter Pad

[0229] GAT: Gate wiring area

[0230] GPD: Gate Pad

[0231] GPL: Gate Path Line

[0232] TER: Termination region

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; as well as an emitter wiring provided on the first main surface via an insulating film, wherein when viewed from the first main surface side, the semiconductor substrate comprises: an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination region arranged to surround the active region; and a main bonding region, arranged between the active region and the termination region, wherein the semiconductor substrate of the main bonding region comprises: A drift layer of a first conductivity type; and A second conductivity type combined impurity layer is provided closer to the first main surface side than the drift layer, The semiconductor substrate in the termination region comprises: the drift layer; and The second conductivity type floating layer is provided closer to the first main surface side than the drift layer, Wherein at least the main bonding region of the semiconductor substrate comprises: a trench electrode provided in a trench formed in the first main surface; and a trench insulating film provided between the trench electrode and the semiconductor substrate, wherein when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main bonding region toward the termination region, and wherein the trench electrode and the bonding impurity layer are connected to the emitter wiring in the main bonding region. 2 . The semiconductor device according to claim 1 , wherein both ends of the trench electrode in the one direction are located in the main bonding region when viewed from the first main surface side.

3. The semiconductor device according to claim 1, wherein when viewed from the first main surface side, the trench electrode includes a portion extending from the main bonding region to the termination region, and One end of the trench electrode in the one direction is located in the main bonding region, and the other end is located in the termination region.

4. The semiconductor device according to claim 3, wherein the termination region has a plurality of floating layers, the plurality of floating layers including portions extending in another direction intersecting the one direction, The plurality of floating layers include: a first floating layer, closest to the main bonding area; as well as a second floating layer, adjacent to the first floating layer, and The other end is located in the first floating layer.

5. The semiconductor device according to claim 3, wherein the termination region has a plurality of floating layers, the plurality of floating layers including portions extending in another direction intersecting the one direction, The plurality of floating layers include: a first floating layer, closest to the main bonding area; as well as a second floating layer, adjacent to the first floating layer, and The other end is located in the second floating layer. 6 . The semiconductor device according to claim 1 , wherein the floating layer is not connected to the emitter wiring in the termination region.

7. The semiconductor device according to claim 1, The emitter wiring comprises: The main part; as well as an emitter contact connected to the combined impurity layer, and The combined impurity layer is connected to the emitter wiring through the emitter contact.

8. The semiconductor device according to claim 7, wherein the groove comprises a plurality of grooves, wherein the trench electrode comprises a plurality of trench electrodes, each of the plurality of trench electrodes being provided in one of the trenches, wherein each of the trench electrodes and each of the trenches is annular when viewed from the first main surface side, wherein the emitter contact comprises: a first emitter contact connected to the combined impurity layer in the annular trench electrode; as well as The second emitter contact is connected to the combined impurity layer between two adjacent annular trench electrodes.

9. The semiconductor device according to claim 8, wherein the semiconductor substrate in the main bonding region includes an emitter contact layer of the second conductivity type, the emitter contact layer being provided closer to the first main surface side than the bonding impurity layer, the emitter contact layer including a higher concentration of the second conductivity type impurity than the bonding impurity layer, The emitter contact layer comprises: A first emitter contact layer is arranged in the annular trench electrode; as well as a second emitter contact layer, arranged between the two adjacent annular trench electrodes, wherein the first emitter contact is connected to the combined impurity layer through the first emitter contact layer, and The second emitter contact is connected to the combined impurity layer through the second emitter contact layer.

10. The semiconductor device according to claim 9, wherein an upper end of the trench electrode on the first main surface side has a step relative to a lower end of the trench electrode on the second main surface side of the first emitter contact, and The trench electrode is connected to the emitter wiring through the step.

11. The semiconductor device according to claim 7, wherein the groove comprises a plurality of grooves, wherein the trench electrode comprises a plurality of trench electrodes, each of the plurality of trench electrodes being provided in one of the trenches, wherein one of the trench electrodes and each of the trenches is annular when viewed from the first main surface side, and wherein the emitter contact is formed across the plurality of annular trench electrodes and the combined impurity layer.

12. The semiconductor device according to claim 11, wherein the semiconductor substrate in the main bonding region includes an emitter contact layer of the second conductivity type, the emitter contact layer being provided closer to the first main surface side than the bonding impurity layer, the emitter contact layer including a higher concentration of the second conductivity type impurity than the bonding impurity layer, The emitter contact layer comprises: A first emitter contact layer is arranged in the annular trench electrode; as well as a second emitter contact layer, arranged between the two adjacent annular trench electrodes, wherein the emitter contact is connected to the combined impurity layer through the first emitter contact layer and the second emitter contact layer. 13 . The semiconductor device according to claim 12 , wherein an upper end of the first main surface side of the trench electrode is connected to a lower end of the emitter contact.

14. The semiconductor device according to claim 1, wherein the IGBT comprises: the drift layer; The barrier layer of the first conductivity type is provided closer to the first main surface side than the drift layer; The second conductivity type channel layer is provided closer to the first main surface side than the barrier layer; The emitter layer of the first conductivity type is provided closer to the first main surface side than the channel layer; a gate trench electrode provided to sandwich the barrier layer, the channel layer, and the emitter layer in one direction in a plane parallel to the first main surface; a gate trench insulating film provided between each of the gate trench electrodes and the semiconductor substrate; as well as The second conductivity type IGBT floating layer is provided on the opposite sides of the barrier layer, the channel layer, and the emitter layer across the gate trench electrode.

15. The semiconductor device according to claim 1, Wherein when viewed from the first main surface side, the main bonding area includes: a first main joining portion extending in said one direction; a second main joining portion extending in a second direction intersecting the one direction; as well as a third main joining portion located at the corner where the first main joining portion and the second main joining portion are connected, and The trench electrode includes a portion extending in the one direction or the second direction at the third main bonding portion.

16. The semiconductor device according to claim 15, Wherein when viewed from the first main surface side, the termination area comprises: a first terminating portion extending in the one direction; a second terminating portion extending in the second direction; as well as a third terminating portion at a corner where the first terminating portion and the second terminating portion are connected, and The trench electrode includes a portion extending from the third main bonding portion to the third termination portion.

17. The semiconductor device according to claim 5, further comprising: wherein in the termination region, a termination wiring is provided on the first main surface via an insulating film, The termination wiring comprises: the main body; and a termination contact connected to the second floating layer, and The second floating layer is connected to the termination wiring via the termination contact.

18. The semiconductor device according to claim 17, wherein the groove comprises a plurality of grooves, wherein the trench electrode comprises a plurality of trench electrodes, each of the plurality of trench electrodes being provided in one of the trenches, wherein each of the trench electrodes and each of the trenches is annular when viewed from the first main surface side, and Wherein the termination contacts include: a first terminal contact connected to the second floating layer in the annular trench electrode, and The second terminal contact is connected to the second floating layer between two adjacent annular trench electrodes.

19. The semiconductor device according to claim 18, wherein the semiconductor substrate in the termination region includes a termination contact layer of the second conductivity type, the termination contact layer being provided closer to the first main surface side than the second floating layer, the termination contact layer including a higher concentration of the second conductivity type impurity than the second floating layer, The termination contact layer comprises: A first terminal contact layer is arranged in the annular groove electrode; as well as A second termination contact layer is arranged between two adjacent annular trench electrodes, and wherein the first termination contact is connected to the second floating layer via the first termination contact layer, and The second termination contact is connected to the second floating layer via the second termination contact layer.

20. A semiconductor device comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; as well as an emitter wiring provided on the first main surface via an insulating film, wherein when viewed from the first main surface side, the semiconductor substrate comprises: an active region including a plurality of IGBTs formed on the semiconductor substrate; a termination region arranged to surround the active region; and a main bonding region, arranged between the active region and the termination region, wherein the semiconductor substrate of the main bonding region comprises: A drift layer of a first conductivity type; and A second conductivity type combined impurity layer is provided closer to the first main surface side than the drift layer, The semiconductor substrate in the termination region comprises: the drift layer; and The second conductivity type floating layer is provided closer to the first main surface side than the drift layer, Wherein at least the main bonding region of the semiconductor substrate comprises: a trench electrode provided in a trench formed in the first main surface; and a trench insulating film provided between the trench electrode and the semiconductor substrate, wherein when viewed from the first main surface side, the trench electrode includes a portion extending in one direction from the main bonding region toward the termination region, wherein the trench electrode and the bonding impurity layer are connected to the emitter wiring in the main bonding region, and The IGBT comprises: the drift layer; The barrier layer of the first conductivity type is provided closer to the first main surface side than the drift layer; The second conductivity type channel layer is provided closer to the first main surface side than the barrier layer; The emitter layer of the first conductivity type is provided closer to the first main surface side than the channel layer; a gate trench electrode provided so as to sandwich the barrier layer, the channel layer, and the emitter layer in another direction intersecting the one direction in a plane parallel to the first main surface; a gate trench insulating film provided between each of the gate trench electrodes and the semiconductor substrate; and The second conductivity type IGBT floating layer is provided on the opposite sides of the barrier layer, the channel layer, and the emitter layer across the gate trench electrode.

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