Novel process method of BCDMOS

Abstract

The invention discloses a novel process method of a BCDMOS. The novel process method comprises the following steps: preparing a silicon substrate; growing a first oxide layer on the substrate by using a thermal oxidation method; growing a second oxide layer on the first oxide layer, wherein the thickness of the second oxide layer is greater than that of the first oxide layer; a nitride layer is deposited on the second oxide layer, a photoresist definition pattern is used for etching, the etching comprises nitride etching, dry etching and wet etching in sequence, and slopes extending from the second oxide layer to the first oxide layer are formed on the edges of the first oxide layer and the second oxide layer after etching. According to the method, the oxide layer structure is designed, the optimal thickness proportion of the multiple oxide layers is optimized, the subsequent etching process is carried out based on the optimal thickness proportion, a traditional beak structure is improved into a slope-shaped structure, the on-resistance per unit area is effectively improved, and the breakdown voltage is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a new process method for BCDMOS. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) process is a monolithic integration process technology that makes bipolar junction transistor (BJT) devices, complementary metal oxide semiconductor (CMOS) devices and double-diffused metal oxide semiconductor (DMOS) devices on the same chip. Devices manufactured using the BCD process are widely used in power management, display drive, automotive electronics, industrial control and other fields.

[0003] In the traditional LOCOS (Local Oxidation of Silicon) process, the field plate of the drift region is placed on the LOCOS of the drift region, and a short LOCOS bird's beak is formed between the gate oxide (GOX) and the field oxide layer. When the concentration of the drift region is high, according to Gauss's theorem, it is very easy to generate a very strong electric field in the silicon under the thick oxide layer close to the LOCOS, thereby causing breakdown, making the breakdown voltage of the MOS low. The existing manufacturing process increases the breakdown voltage by reducing the concentration of the drift region or reducing the overlap size of the drift region and GOX, but this will increase the on-resistance of the MOS. How to balance the performance of on-resistance and breakdown voltage is a problem to be solved.

[0004] Therefore, there is still a need for designing a new process method for BCDMOS in the prior art. Summary of the invention

[0005] In view of this, the purpose of an embodiment of the present invention is to propose a new process method for BCDMOS, design an oxide layer structure and optimize the optimal thickness ratio of the multi-layer oxide layer, perform subsequent etching process based on the optimal thickness ratio, improve the traditional bird's beak structure into a slope structure, effectively increase the on-resistance per unit area, and improve the breakdown voltage.

[0006] Based on the above purpose, an embodiment of the present invention provides a new process method for BCDMOS, including the following steps:

[0007] preparing a silicon substrate;

[0008] growing a first oxide layer on the substrate by using a thermal oxidation method;

[0009] growing a second oxide layer on the first oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer;

[0010] Depositing a nitride layer on the second oxide layer, and performing etching using a photoresist-defined pattern, wherein the etching includes sequentially performing nitride etching, dry etching, and wet etching, and after etching, the edges of the first oxide layer and the second oxide layer form a slope extending from the second oxide layer to the first oxide layer;

[0011] In some embodiments, the method further comprises:

[0012] The nitride layer is removed and a polysilicon layer is deposited. The polysilicon layer is etched to form a gate, and source and drain electrodes are implanted to form a BCDMOS.

[0013] In some embodiments, the wet etching includes performing longitudinal etching and lateral etching simultaneously, and the lateral etching forms a slope extending from the second oxide layer to the first oxide layer.

[0014] In some embodiments, the slope is a multi-gradient slope, forming a first angle at an edge of the first oxide layer and forming a second angle at an edge of the second oxide layer.

[0015] In some embodiments, the first angle ranges from 20 to 70 degrees, and the second angle ranges from 20 to 90 degrees.

[0016] In some embodiments, the first oxide layer and the second oxide layer are both silicon dioxide layers, and the thickness of the first oxide layer is The thickness of the second oxide layer is

[0017] In some embodiments, after dry etching, the thickness of the first oxide layer and the second oxide layer is

[0018] In some embodiments, the second oxide layer is grown by vapor deposition.

[0019] In some embodiments, the thickness ratio of the first oxide layer to the second oxide layer is 10% to 100%.

[0020] In some embodiments, the thickness ratio of the first oxide layer to the second oxide layer is 42% to 65%.

[0021] The present invention has at least the following beneficial technical effects:

[0022] The present invention provides a new process method for BCDMOS, which grows a GOX oxide layer by a thermal oxidation method, and then grows a thicker HTO high-temperature oxide layer by vapor deposition, and optimizes the thickness ratio of the oxide layer to be 42% to 65%. The subsequent etching process includes dry etching and wet etching. Due to the different densities of the GOX layer and the HTO layer, the etching rates of the wet etching process are different, thereby forming a slope field plate, shortening the effective field plate, shortening the distance between the source and the drain, and effectively improving the on-resistance per unit area to improve the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flow chart of an embodiment of a new process method for BCDMOS provided by the present invention;

[0025] Figure 2 A flow chart of an embodiment of an etching process provided by the present invention;

[0026] Figure 3 A schematic diagram of an embodiment of a device structure prepared based on the method of the present invention;

[0027] Figure 4 It is a schematic diagram of an embodiment of the present invention based on a slope field plate structure;

[0028] Figure 5 A scanning electron microscope image of a sloped field plate structure is provided for the present invention;

[0029] Figure 6 The electrical property test diagram of the BCDMOS device prepared based on different oxide layer thickness ratios provided by the present invention. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field of the present invention; the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. For example, the directions or positions indicated by the terms "length", "width", "up", "down", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the drawings, which are only for the convenience of description and should not be understood as limitations on the present technical solution.

[0032] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions; the terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0033] In the specification and claims of the present invention and the above-mentioned drawings, when an element is referred to as being "fixed to" or "mounted on" or "disposed on" or "connected to" another element, it may be directly or indirectly located on the other element. For example, when an element is referred to as being "connected to" another element, it may be directly or indirectly connected to the other element.

[0034] In addition, reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The field plate of the BCDMOS device in the prior art is usually formed by growing an oxide layer on a silicon substrate, and then forming a bird's beak field plate by thermal oxidation reaction after photoresist etching. According to Gauss's theorem, it is very easy to generate a very strong electric field in the silicon under the thick oxide layer close to LOCOS, thereby causing breakdown, making the breakdown voltage of MOS low. Therefore, the present invention provides a new process method for BCDMOS, such as Figure 1 Shown is the process flow of the present invention, comprising the following steps:

[0036] S1, prepare silicon substrate;

[0037] S2, growing a first oxide layer on the substrate by using a thermal oxidation method;

[0038] S3, growing a second oxide layer on the first oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer;

[0039] S4. Deposit a nitride layer on the second oxide layer, and perform etching using a photoresist-defined pattern. The etching includes sequentially performing silicon nitride etching, dry etching, and wet etching. After etching, the edges of the first oxide layer and the second oxide layer form a slope extending from the second oxide layer to the first oxide layer.

[0040] Furthermore, the method further comprises:

[0041] S5, removing the nitride layer and depositing a polysilicon layer, etching the polysilicon layer to form a gate, and performing source and drain implantation to form a BCDMOS.

[0042] Furthermore, if Figure 1 The method flow of the present invention is shown in sequence, as shown in FIG. Figure 1 -a, the structure from bottom to top includes a substrate layer (Sub), a first oxide layer GOX, a second oxide layer HTO layer and a nitride layer, wherein the GOX layer is grown by thermal oxidation, and the HTO is a high temperature grown oxide layer. In some embodiments, the second oxide layer is grown by vapor deposition. In some embodiments, the nitride layer is a silicon nitride layer. The nitride layer is etched using a photoresist to define a pattern, such as Figure 1 As shown in Fig. 2-b, the silicon nitride layer is first etched, and then the oxide layer is etched to form a slope extending from the second oxide layer to the first oxide layer, such as Figure 1 -c, remove the nitride layer, such as Figure 1 -d and 1-e, after depositing the polysilicon layer, photoresist is used to define the pattern and then etching is performed to form the gate.

[0043] Furthermore, if Figure 2 FIG. 1 is a flow chart of an embodiment of an etching process, wherein the etching includes nitride layer etching and oxide layer etching, wherein the etching of the oxide layer includes dry etching and wet etching. Figure 3 It is a schematic diagram of an embodiment of a device structure prepared based on the method of the present invention, which improves the traditional bird's beak structure into a slope-shaped structure, effectively improving the on-resistance per unit area and enhancing the breakdown voltage.

[0044] Furthermore, the purpose of dry etching is to remove part of the first oxide layer. In some embodiments, the first oxide layer and the second oxide layer are both silicon dioxide layers, and the thickness of the first oxide layer is The thickness of the second oxide layer is After dry etching, the thickness of the first oxide layer and the second oxide layer is

[0045] Further, the remaining first oxide layer and the second oxide layer are etched by wet etching, and the wet etching includes longitudinal etching and lateral etching at the same time, wherein the lateral etching forms a slope extending from the second oxide layer to the first oxide layer. Under ideal conditions, the angle of each position of the slope is uniform. However, since the GOX oxide layer formed by thermal growth is denser than the HTO layer formed by a high-temperature thermal process, the etching rate in the lateral etching process is significantly different. The etching rate of the GOX oxide layer is slower than that of the HTO layer. Therefore, the angles of the edges formed are different, and the slope is a multi-gradient slope, such as Figure 4 As shown, a first angle is formed at the edge of the first oxide layer, and a second angle is formed at the edge of the second oxide layer. In some embodiments, the first angle ranges from 20 to 70 degrees, and the second angle ranges from 20 to 90 degrees.

[0046] Furthermore, the thickness of the second oxide layer is greater than that of the first oxide layer. In some embodiments, the thickness ratio of the first oxide layer to the second oxide layer is 10% to 100%. Preferably, the thickness ratio of the first oxide layer to the second oxide layer is 42% to 65%. Different oxide layer thickness ratios further lead to different slope angle results of wet etching.

[0047] The multiple embodiments shown in Table 1 are multi-gradient slope angle data formed after wet etching at different oxide layer thickness ratios. Figure 5 This is a scanning electron microscope image of the slope field plate structure based on Example 3, the first angle is 24°, the second angle is 85°, and the etching thickness is 74.2 nm.

[0048] Table 1 Multi-gradient slope angle data

[0049]

[0050] like Figure 6 The electrical test diagrams of the above-mentioned multiple embodiments are shown, and linear current tests and breakdown voltage tests are performed on them respectively. The horizontal axis shows the above-mentioned seven embodiments, wherein GOX is the first oxide layer, HTO is the second oxide layer, and the GOX / HTO ratio is the thickness ratio of the first oxide layer to the second oxide layer. The left axis shows the linear current test data, and the right axis shows the breakdown voltage test data. It can be seen that as the GOX / HTO ratio gradually increases, the breakdown voltage steadily increases, and the linear current is relatively stable. Among them, when the GOX / HTO ratio increases to 53%, the breakdown voltage reaches the maximum value. When the ratio is increased again, the breakdown voltage begins to decrease, and the linear current begins to decrease significantly. Therefore, it can be concluded that the thickness ratio of the first oxide layer to the second oxide layer is preferably 42% to 65%. In this ratio range, the breakdown voltage can be increased while meeting the on-resistance requirement.

[0051] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0052] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0053] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0054] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A new process method for BCDMOS, characterized in that: include: preparing a silicon substrate; growing a first oxide layer on the substrate by using a thermal oxidation method; growing a second oxide layer on the first oxide layer, wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer; A nitride layer is deposited on the second oxide layer, and etching is performed using a photoresist-defined pattern. The etching includes sequentially performing nitride etching, dry etching, and wet etching. After etching, the edges of the first oxide layer and the second oxide layer form a slope extending from the second oxide layer to the first oxide layer.

2. The new process method for BCDMOS according to any one of claim 1, characterized in that: Also includes: The nitride layer is removed and a polysilicon layer is deposited. The polysilicon layer is etched to form a gate, and source and drain electrodes are implanted to form a BCDMOS.

3. The new process method for BCDMOS according to any one of claim 1, characterized in that: The wet etching includes performing longitudinal etching and lateral etching simultaneously, and the lateral etching forms a slope extending from the second oxide layer to the first oxide layer.

4. The new process method of BCDMOS according to claim 3, characterized in that: The slope is a multi-gradient slope, forming a first angle at the edge of the first oxide layer and a second angle at the edge of the second oxide layer.

5. The new process method of BCDMOS according to claim 4, characterized in that: The first angle ranges from 20 to 70 degrees, and the second angle ranges from 20 to 90 degrees.

6. The new process method of BCDMOS according to claim 1, characterized in that: The first oxide layer and the second oxide layer are both silicon dioxide layers, and the thickness of the first oxide layer is The thickness of the second oxide layer is 7. The new process method of BCDMOS according to claim 6, characterized in that: After the dry etching, the thickness of the first oxide layer and the second oxide layer is 8. The new process method of BCDMOS according to claim 1, characterized in that: The second oxide layer is grown by a vapor deposition method.

9. The new process method of BCDMOS according to claim 1, characterized in that: The thickness ratio of the first oxide layer to the second oxide layer is 10% to 100%.

10. The new process method of BCDMOS according to claim 9, characterized in that: The thickness ratio of the first oxide layer to the second oxide layer is 42% to 65%.

Images