Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes: an insulating layer including a first surface, a second surface, and an element isolation trench; an insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a lower wiring structure on the second surface of the insulating layer; and a via extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, in which the insulating layer may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the via, and a third portion on a bottom surface of the element isolation trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0122775 filed in the Korean Intellectual Property Office on September 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device. Background Art

[0004] Semiconductor materials are materials that belong to the intermediate category between conductors and non-conductors and can refer to materials that conduct electricity under predetermined conditions. Such semiconductor materials can be used to manufacture various semiconductor devices, such as memory devices. These semiconductor devices can be used in various electronic devices.

[0005] The requirements for the characteristics of semiconductor devices have gradually increased. For example, the demand for semiconductor devices with higher reliability, higher speed and / or more functions has gradually increased. In order to obtain these required characteristics, the structure in the semiconductor device has gradually become complex and has been integrated at a higher density.

[0006] Before or during the process of implementing the embodiments of the present application, the information disclosed in this background technology section has been known or obtained by the inventor, or the information disclosed in this background technology section is technical information acquired during the process of implementing the embodiments. Therefore, it may include information that does not form prior art known to the public. Summary of the invention

[0007] One or more example embodiments provide a semiconductor device having improved reliability.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0009] According to an aspect of an example embodiment, a semiconductor device may include: an insulating layer including a first surface, a second surface, and an element isolation trench; an insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a lower wiring structure on the second surface of the insulating layer; and a through-hole member extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, wherein the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-hole member, and a third portion on the bottom surface of the element isolation trench.

[0010] According to an aspect of an example embodiment, a semiconductor device may include: an insulating layer including a first surface and a second surface; an insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a dummy source / drain pattern extending in at least a portion of the insulating pattern and located below the source / drain pattern; a lower wiring structure below the second surface of the insulating layer; and a through-hole member extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, wherein the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-hole member, and a fourth portion at least partially surrounding the dummy source / drain pattern.

[0011] According to an aspect of an example embodiment, a semiconductor device may include: an insulating layer including a first surface, a second surface, and an element isolation trench; an insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a dummy source / drain pattern extending in at least a portion of the insulating pattern and below the source / drain pattern; a gate electrode on the insulating pattern and at least partially surrounding the channel pattern; a lower wiring structure below the second surface of the insulating layer; and a via extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, wherein the insulating pattern may include a first portion between the insulating layer and the gate electrode, a second portion surrounding at least a portion of the via, a third portion on an inner wall and a bottom surface of the element isolation trench, and a fourth portion at least partially surrounding the dummy source / drain pattern, and wherein the via may include a first via portion at least partially surrounded by a second portion of the second insulating pattern and a second via portion between the first via portion and the lower wiring structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a plan view illustrating a semiconductor device according to one or more example embodiments;

[0014] Figure 2 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line AA' in FIG.

[0015] Figure 3 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line BB' in FIG.

[0016] Figure 4 According to one or more example embodiments Figure 2 An enlarged cross-sectional view of the S1 region in FIG.

[0017] Figures 5 to 8 is a method according to one or more example embodiments corresponding to Figure 2 A cross-sectional view of a portion of a semiconductor device in an S1 region;

[0018] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0019] as well as

[0020] Figures 10 to 27 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more example embodiments. DETAILED DESCRIPTION

[0021] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions thereof will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms.

[0022] In addition, for the sake of understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for the sake of clarity, the thickness of layers, films, plates, regions, etc. may be exaggerated. In the drawings, for the sake of understanding and ease of description, the thickness of some layers and regions is exaggerated.

[0023] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than the individual elements of the list. For example, the expression "at least one of A, B, and C" should be understood to include only A, only B, only C, both A and B, both A and C, both B and C, or all of A, B, and C.

[0024] It should be understood that when an element or layer is referred to as being “on,” “over,” “on,” “under,” “under,” “under,” “connected to,” or “coupled to,” it can be directly on, directly over, directly on, directly under, directly under, directly under, directly connected to, or directly coupled to, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to,” there are no intervening elements or layers.

[0025] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0026] For example, in a semiconductor device according to one or more example embodiments, a transistor may have a gate all around (GAA) field effect transistor (FET) (GAAFET) structure, a multi-bridge channel FET (MBCFET) structure, or a gate all around (GAA) field effect transistor (FET) structure. TM ) structure, etc., in which the four sides of each channel are surrounded by gate electrodes. However, the present disclosure is not limited thereto, and according to various technologies, the transistor can be formed in a fin FET (FinFET) structure, or can be formed in a three-dimensional stacked FET (3DSFET) structure, a complementary FET (CFET) structure, etc.

[0027] Below, we will refer to Figures 1 to 4 A semiconductor device according to an embodiment is described.

[0028] Throughout the specification, singular components and components provided in plural may be referred to interchangeably in the singular and / or the plural.

[0029] Figure 1 is a plan view illustrating a semiconductor device according to one or more example embodiments. Figure 2 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line AA' in FIG. Figure 3 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line BB' in FIG. Figure 4 According to one or more example embodiments Figure 2Magnified cross-sectional view of the S1 region in .

[0030] First, refer to Figures 1 to 3 , a semiconductor device according to some embodiments may include an insulating layer 100 , an insulating pattern 200 , an active pattern AP, a field insulating layer 105 , a gate structure GS, a source / drain pattern 150 , a dummy source / drain pattern 160 , a lower wiring structure 410 , and a through-hole member 300 .

[0031] The insulating layer 100 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or a combination thereof. In the drawings, the insulating layer 100 is shown as a single layer; however, this is only for ease of explanation, and a plurality of insulating layers may be provided. The insulating layer 100 may have an element isolation trench STI.

[0032] The insulating layer 100 may have a first surface 100 a and a second surface 100 b .

[0033] The first surface 100a and the second surface 100b of the insulating layer 100 may be flat surfaces parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. The first surface 100a of the insulating layer 100 may be opposite to the second surface 100b in the third direction D3. The first surface 100a of the insulating layer 100 may be referred to as the front or upper surface of the insulating layer 100. The second surface 100b of the insulating layer 100 may be referred to as the back or lower surface of the insulating layer 100. In some embodiments, a logic circuit in a cell region may be implemented on the first surface 100a of the insulating layer 100.

[0034] The insulating pattern 200 may be located on the first surface 100a of the insulating layer 100. The insulating pattern 200 may be located vertically below the lower pattern BP (to be described below) in the third direction D3 (e.g., the thickness direction of the insulating layer 100). The insulating pattern 200 may be located vertically below the plurality of channel patterns NS (to be described below) in the third direction D3. The insulating pattern 200 may be located vertically below the gate structure GS (to be described below) in the third direction D3 (e.g., the thickness direction of the insulating layer 100).

[0035] In an embodiment, the insulating pattern 200 may be located between the first surface 100a of the insulating layer 100 and the lower pattern BP. In addition, the insulating pattern 200 may surround at least a portion of the via member 300. The insulating pattern 200 may be located between the insulating layer 100 and the via member 300. In addition, the insulating pattern 200 may be located in the element isolation trench STI in the insulating layer 100. In other words, the insulating pattern 200 may be located between the insulating layer 100 and the interlayer insulating layer 190. In addition, the insulating pattern 200 may surround the dummy source / drain pattern 160. The insulating pattern 200 may be located between the insulating layer 100 and the dummy source / drain pattern 160.

[0036] Therefore, the insulating pattern 200 may include a first portion 210 located between the lower pattern BP and the insulating layer 100, a second portion 220 surrounding at least a portion of the through-hole member 300, a third portion 230 located on the inner wall and bottom surface of the element isolation trench STI, and a fourth portion 240 surrounding the dummy source / drain pattern 160. In this case, the first portion 210 to the fourth portion 240 of each insulating pattern 200 may be integrally formed without any interface; however, the present disclosure is not limited thereto. Figure 4 The first to fourth portions 210 to 240 of the insulation pattern 200 are described in detail.

[0037] The insulating pattern 200 may include various insulating materials. The insulating pattern 200 may include a material having an etching selectivity to the insulating layer 100. For example, the insulating pattern 200 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN). Alternatively, the insulating pattern 200 may include a metal oxide or a metal nitride, such as aluminum oxide (Al2O3). 2 O 3 ) or aluminum nitride (AlN).

[0038] The active pattern AP may be located on the insulating pattern 200. The active pattern AP may extend in the first direction D1. As an example, the active pattern AP may be located in a region where a p-type metal oxide semiconductor (MOS) (PMOS) is formed. As another example, the active pattern AP may be located in a region where an n-type MOS (NMOS) is formed.

[0039] The active pattern AP may be a multi-channel active pattern. The active pattern AP may include a lower pattern BP and a plurality of channel patterns NS. In an embodiment, the lower pattern BP and the plurality of channel patterns NS may have a nanosheet shape and may be a semiconductor pattern including a semiconductor material. The lower pattern BP may be located on the insulating layer 100. The lower pattern BP may extend in the first direction D1.

[0040] A plurality of channel patterns NS may be located on an upper surface of the lower pattern BP. A plurality of channel patterns NS may be spaced apart from the lower pattern BP in the third direction D3. A plurality of channel patterns NS may be spaced apart in the third direction D3. The third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 may be a thickness direction of the insulating layer 100. The second direction D2 may be a direction intersecting the first direction D1.

[0041] exist Figure 2 and Figure 3 , four channel patterns NS are stacked so as to be spaced apart from each other along the third direction D3; however, this is only for convenience of explanation, and the present disclosure is not limited thereto. For example, less than four or more than four channel patterns NS may be stacked so as to be spaced apart from each other along the third direction D3.

[0042] The lower pattern BP may be formed by etching the substrate 111 ( Fig.10 ) and may include an epitaxial layer grown from the substrate 111. The lower pattern BP may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In addition, the lower pattern BP may include a compound semiconductor and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0043] The Group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0044] The III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, and a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V group elements.

[0045] The plurality of channel patterns NS may include one of silicon (Si) and silicon germanium (SiGe) as elemental semiconductor materials, IV-IV compound semiconductors, and III-V compound semiconductors. Each of the plurality of channel patterns NS may include the same material as that in the lower pattern BP, and may include a material different from that in the lower pattern BP.

[0046] In an embodiment, the lower pattern BP and the plurality of channel patterns NS may include silicon (Si). As another example, the lower pattern BP and the plurality of channel patterns NS may include silicon germanium (SiGe). As yet another example, the lower pattern BP may include silicon (Si), and the plurality of channel patterns NS may include silicon germanium (SiGe).

[0047] The field insulation layer 105 may be located on the insulation pattern 200. The field insulation layer 105 may cover the side surface 200_S of at least one protrusion 200_P of the insulation pattern 200. The at least one protrusion 200_P of the insulation pattern 200 may refer to a portion of the insulation pattern 200 protruding from the upper surface of the insulation layer 100 in the third direction D3. In other words, in an embodiment, the side surface 200_S of the at least one protrusion 200_P of the insulation pattern 200 may refer to a side surface of a portion of the insulation pattern 200 protruding from the upper surface of the insulation layer 100 in the third direction D3. Therefore, the field insulation layer 105 may extend over the at least one protrusion 200_P of the insulation pattern 200 in the second direction D2. In addition, the field insulation layer 105 may not be located on a portion of the insulation pattern 200 vertically located below the lower pattern BP in the third direction D3. In other words, the field insulation layer 105 may not be located between the insulation pattern 200 and the lower pattern BP.

[0048] In addition, the field insulating layer 105 may be located on the sidewall BP_S of the lower pattern BP. As an example, the field insulating layer 105 may completely cover the sidewall BP_S of the lower pattern BP. Therefore, the field insulating layer 105 may be located vertically below the lower pattern BP in the third direction D3.

[0049] exist Figure 3 , it is shown that the field insulating layer 105 completely covers the sidewall BP_S of the lower pattern BP; however, the present disclosure is not limited thereto. For example, the field insulating layer 105 may cover at least a portion of the sidewall BP_S of the lower pattern BP. In other words, at least a portion of the sidewall BP_S of the lower pattern BP may be covered by the field insulating layer 105, and the other portion of the sidewall BP_S of the lower pattern BP may be covered by the gate structure GS to be described below. In this case, the lower pattern BP may extend above the gate structure GS in the second direction D2.

[0050] Alternatively, as another example, the field insulating layer 105 may not be located on the sidewall BP_S of the lower pattern BP. In other words, the field insulating layer 105 may be located on the side surface 200_S of at least one protrusion 200_P of the insulating pattern 200, and the gate structure GS may be located on the sidewall BP_S of the lower pattern BP. In this case, the field insulating layer 105 may not extend over the lower pattern BP in the second direction D2. As yet another example, the gate structure GS may cover at least a portion of the upper portion of the entire side surface of the lower pattern BP extending in the second direction D2 and the side surface 200_S of at least one protrusion 200_P of the insulating pattern 200, and the field insulating layer 105 may cover at least a portion of the side surface 200_S of at least one protrusion 200_P of the insulating pattern 200. In this case, at least a portion of the at least one protrusion 200_P of the insulating pattern 200 may extend over the field insulating layer 105 in the second direction D2, and the other portion of the at least one protrusion 200_P of the insulating pattern 200 may extend over the gate structure GS in the second direction D2.

[0051] The field insulating layer 105 may include, for example, a film formed of oxide, nitride, oxynitride, or a combination thereof. In the drawings, the field insulating layer 105 is illustrated as a single layer; however, this is only for convenience of explanation, and the field insulating layer is not limited thereto.

[0052] The gate structure GS may be located on the insulating layer 100. The gate structure GS may extend in the second direction D2. A plurality of gate structures GS may be disposed spaced apart from each other in the first direction D1.

[0053] The gate structure GS may be located on the active pattern AP. The gate structure GS may intersect with the active pattern AP. A plurality of gate structures GS may surround a plurality of channel patterns NS, respectively.

[0054] The gate structure GS may include a plurality of sub-gate structures S_GS and a main gate structure M_GS. The plurality of sub-gate structures S_GS may be located between each two channel patterns adjacent to each other in the third direction D3 among the plurality of channel patterns NS, and between the lower pattern BP and the lowermost channel pattern NS. The main gate structure M_GS may be located on the uppermost channel pattern NS.

[0055] Specifically, the plurality of sub-gate structures S_GS may be located between the upper surface of the lower pattern BP and the lower surface of the lowermost channel pattern NS, and between the upper surface of the channel pattern NS and the lower surface of the channel pattern NS facing each other in the third direction D3. The plurality of sub-gate structures S_GS may be adjacent to the source / drain pattern 150 to be described below. The main gate structure M_GS may be located on the plurality of sub-gate structures S_GS and the channel pattern NS.

[0056] According to an embodiment, each of the active patterns AP may include a plurality of channel patterns NS, and each of the gate structures GS may include a plurality of sub-gate structures S_GS. In this case, the number of the plurality of sub-gate structures S_GS may be proportional to the number of the plurality of channel patterns NS included in the active pattern AP.

[0057] For example, the number of the plurality of sub-gate structures S_GS may be the same as the number of the plurality of channel patterns NS. Figure 2 and Figure 3 As shown, the number of the plurality of sub-gate structures S_GS may be four. However, the number of the plurality of sub-gate structures S_GS is not limited thereto, and each gate structure GS may include three or less, or five or more sub-gate structures S_GS.

[0058] Each of the plurality of sub-gate structures S_GS may include a sub-gate electrode 120S and a sub-gate insulating layer 130S.

[0059] The sub-gate electrode 120S may be formed on the lower pattern BP. The sub-gate electrode 120S may intersect the lower pattern BP. The sub-gate electrode 120S may surround the plurality of channel patterns NS.

[0060] At least a portion of the sub-gate electrode 120S may be located on a structure in which another sub-gate electrode 120S and a plurality of channel patterns NS are stacked. Other portions of the sub-gate electrode 120S may be formed to cover both side surfaces of the structure in which another sub-gate electrode 120S and a plurality of channel patterns NS are stacked. In this case, four sides of the plurality of channel patterns NS may be surrounded by the sub-gate electrode 120S.

[0061] The sub-gate electrode 120S may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The sub-gate electrode 120S may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN ), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof, but not limited thereto. The conductive metal oxide and the conductive metal oxynitride may include oxides of the above materials, but not limited thereto.

[0062] The sub-gate insulating layer 130S may extend along the upper surface of the lower pattern BP. The sub-gate insulating layer 130S may be disposed along the periphery of the plurality of channel patterns NS. The sub-gate insulating layer 130S may directly contact the lower pattern BP, the inner gate spacer 135, and the plurality of channel patterns NS. The sub-gate insulating layer 130S may be inserted between the plurality of channel patterns NS and the sub-gate electrode 120S. In addition, the sub-gate insulating layer 130S may extend along the upper surface of the field insulating layer 105. The sub-gate insulating layer 130S may include various insulating materials.

[0063] In the embodiment, each sub-gate insulating layer 130S is shown as a single layer in the drawings, but is not limited thereto. For example, each sub-gate insulating layer 130S may include a silicon oxide (SiO 2 ) and multiple layers of high dielectric constant materials. In this case, the high dielectric constant material may include a dielectric constant having a dielectric constant greater than silicon oxide (SiO 2 )'s dielectric constant is a material with a high dielectric constant, such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO).

[0064] Each main gate structure M_GS may be located on the sub-gate structure S_GS and the plurality of channel patterns NS. The main gate structure M_GS may be located on an upper surface of the plurality of channel patterns NS.

[0065] The main gate structure M_GS may include a main gate electrode 120M and a main gate insulating layer 130M.

[0066] The main gate electrode 120M may be located on the sub-gate structure S_GS and the plurality of channel patterns NS. The main gate electrode 120M may be located on the upper surface of the plurality of channel patterns NS. The main gate electrode 120M may include the same material as that in the sub-gate electrode 120S. For example, the main gate electrode 120M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0067] The main gate insulating layer 130M may extend along a side surface of the main gate electrode 120M. The main gate insulating layer 130M may extend along a side surface of the gate spacer 140. The main gate insulating layer 130M may include various insulating materials.

[0068] In the embodiment, each main gate insulating layer 130M is shown as a single layer in the drawings, but is not limited thereto. For example, each main gate insulating layer 130M may include a silicon oxide (SiO 2 ) and multiple layers of high dielectric constant materials. In this case, the high dielectric constant material may include a dielectric constant having a dielectric constant greater than silicon oxide (SiO 2 )'s dielectric constant is a material with a high dielectric constant, such as hafnium oxide (HfO), aluminum oxide (AlO) or tantalum oxide (TaO).

[0069] The semiconductor device according to some embodiments may further include an inner gate spacer 135 , a gate spacer 140 , and a capping layer 145 .

[0070] The inner gate spacer 135 may be located on the side surface of the sub-gate structure S_GS. For example, the inner gate spacer 135 may be located between the source / drain pattern 150 and the sub-gate structure S_GS. The inner gate spacer 135 may not be located on the side surface of the main gate structure M_GS.

[0071] The gate spacer 140 may be located on the side surface of the main gate electrode 120M. The gate spacer 140 may not be disposed between the lower pattern BP and the plurality of channel patterns NS. The gate spacer 140 may not be disposed between the plurality of channel patterns NS adjacent to each other in the third direction D3.

[0072] The gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. In the drawings, each gate spacer 140 is shown as a single layer; however, this is only for ease of explanation, and the gate spacer 140 is not limited thereto.

[0073] The capping layer 145 may be located on the main gate structure M_GS and the gate spacer 140. The upper surface of the capping layer 145 may be located in the same plane together with the upper surface of the interlayer insulating layer 190. Unlike shown in the drawings, the capping layer 145 may be located between the gate spacers 140.

[0074] The capping layer 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The capping layer 145 may include a material having an etching selectivity to the interlayer insulating layer 190 .

[0075] The source / drain pattern 150 may be located at both sides of each of the sub-gate structures S_GS. The source / drain pattern 150 may contact the side surface of the channel pattern NS and the side surface of the inner gate spacer 135. The source / drain pattern 150 may be coupled to the channel pattern NS. In an embodiment, the source / drain pattern 150 may be coupled to a dummy source / drain pattern 160 or a through-hole member 300. For example, some of the source / drain patterns 150 may be coupled to the dummy source / drain pattern 160 to be described below, and the others of the source / drain patterns 150 may be coupled to the through-hole member 300 to be described below.

[0076] The source / drain pattern 150 may be located in a source / drain recess 150R extending in the third direction D3. The source / drain recess 150R may be filled with the source / drain pattern 150. The bottom surface of the source / drain recess 150R may be defined by a dummy source / drain pattern 160 or a through-hole member 300. The side surface of the source / drain recess 150R may be defined by an inner gate spacer 135 and an active pattern AP.

[0077] In an embodiment, the lower surface 150U of the source / drain pattern 150 may be located at a lower level than the lower surfaces of the plurality of sub-gate structures S_GS. Figure 4 As shown, the lower surface 150U of the source / drain pattern 150 may be placed closer to the second surface 100b of the insulating layer 100 than the lower surface of the lowermost sub-gate structure S_GS. In other words, the length from the second surface 100b of the insulating layer 100 to the lower surface 150U of the source / drain pattern 150 in the third direction D3 may be less than the length from the second surface 100b of the insulating layer 100 to the lower surface of the lowermost sub-gate structure S_GS in the third direction D3.

[0078] In addition, the lower surface 150U of the source / drain pattern 150 may be located at a lower level than the lower surface 210U of the first portion 210 of the insulating pattern 200. Figure 4As shown, the lower surface 150U of the source / drain pattern 150 may be positioned closer to the second surface 100b of the insulating layer 100 than the lower surface 210U of the first portion 210. In other words, the length from the second surface 100b of the insulating layer 100 to the lower surface 150U of the source / drain pattern 150 in the third direction D3 may be shorter than the length from the second surface 100b of the insulating layer 100 to the lower surface 210U of the first portion 210 in the third direction D3.

[0079] The source / drain pattern 150 may be an epitaxial pattern formed by a selective epitaxial growth process using the active pattern AP as a seed. The channel pattern NS may be a portion of the active pattern AP extending between the source / drain patterns 150. The source / drain pattern 150 may serve as a source and a drain of a transistor using the channel pattern NS as a channel region.

[0080] The source / drain pattern 150 of the semiconductor device according to some embodiments may include a first source / drain pattern 151 and a second source / drain pattern 152 .

[0081] The second source / drain pattern 152 may be formed along the inner wall and bottom surface of the source / drain recess 150R. The second source / drain pattern 152 formed along the inner wall of the source / drain recess 150R may directly contact the inner gate spacer 135 and the active pattern AP. The second source / drain pattern 152 formed along the bottom surface of the source / drain recess 150R may be coupled to the dummy source / drain pattern 160 or the through-hole member 300. The second source / drain pattern 152 may include a first material as a semiconductor material. For example, the second source / drain pattern 152 may include silicon (Si) or germanium (Ge) as a semiconductor material.

[0082] The first source / drain pattern 151 may be located on the second source / drain pattern 152. The second source / drain pattern 152 may be formed in at least a portion of the source / drain recess 150R, and the remaining portion of the source / drain recess may be filled with the first source / drain pattern 151. The first source / drain pattern 151 may include a semiconductor material.

[0083] The first source / drain pattern 151 may include a first material and a second material different from the first material. The second material may include, for example, carbon (C), silicon (Si), germanium (Ge), or tin (Sn). As an example, the second source / drain pattern 152 may include silicon (Si), and the first source / drain pattern 151 may include silicon germanium (SiGe).

[0084] However, the present disclosure is not limited thereto, and as another example, the first source / drain pattern 151 may include the same material as that in the second source / drain pattern 152. In this case, the concentrations of the constituent materials in the first source / drain pattern 151 and the second source / drain pattern 152 may be different. For example, when the first source / drain pattern 151 and the second source / drain pattern 152 include silicon germanium (SiGe), the concentration of germanium (Ge) in the first source / drain pattern 151 may be greater than the concentration of germanium (Ge) in the second source / drain pattern 152; however, the present disclosure is not limited thereto. As yet another example, the first source / drain pattern 151 and the second source / drain pattern 152 may include the same material, and the first source / drain pattern 151 and the second source / drain pattern 152 may have the same concentration of constituent materials.

[0085] According to some embodiments, it has been described that each source / drain pattern 150 includes a plurality of layers; however, each source / drain pattern 150 is not limited thereto and may include a single layer including a semiconductor material.

[0086] The dummy source / drain pattern 160 may be located on the insulating layer 100. The dummy source / drain pattern 160 may be located between the insulating layer 100 and the source / drain pattern 150. The dummy source / drain pattern 160 may be coupled to the source / drain pattern 150.

[0087] The dummy source / drain pattern 160 may be located in a dummy source / drain recess 160R extending in the third direction D3. The dummy source / drain recess 160R may be filled with the dummy source / drain pattern 160. A lower surface and a side surface of the dummy source / drain pattern 160 may be defined by the fourth portion 240 of the insulating pattern 200.

[0088] According to some embodiments, a plurality of dummy source / drain patterns 160 may be provided. In this case, the lengths of the dummy source / drain patterns 160 in the third direction D3 may be different. Specifically, as the width of each of the dummy source / drain patterns 160 in the first direction D1 increases, the length of the corresponding dummy source / drain pattern 160 in the third direction D3 may increase. Therefore, a length distribution of the dummy source / drain patterns 160 in the third direction D3 may occur.

[0089] According to some embodiments, the dummy source / drain pattern 160 may be surrounded by the fourth portion 240 of the insulating pattern 200. The lower surface and the side surface of the dummy source / drain pattern 160 may be completely covered by the fourth portion 240 of the insulating pattern 200. The dummy source / drain pattern 160 may contact the fourth portion 240 of the insulating pattern 200. Therefore, the dummy source / drain pattern 160 may be spaced apart from the insulating layer 100.

[0090] According to some embodiments, the upper surface of the dummy source / drain pattern 160 may be located at a lower level than the lower surface 210U of the first portion 210 of the insulating pattern 200. Figure 4 As shown, the upper surface of the dummy source / drain pattern 160 may be placed closer to the second surface 100b of the insulating layer 100 than the lower surface 210U of the first portion 210. In other words, the length from the second surface 100b of the insulating layer 100 to the upper surface of the dummy source / drain pattern 160 in the third direction D3 may be less than the length from the second surface 100b of the insulating layer 100 to the lower surface 210U of the first portion 210 in the third direction D3.

[0091] Therefore, the upper surface of the dummy source / drain pattern 160 may be positioned closer to the second surface 100b of the insulating layer 100 than the lower surface of the lowermost sub-gate structure S_GS. In other words, the length from the second surface 100b of the insulating layer 100 to the upper surface of the dummy source / drain pattern 160 in the third direction D3 may be shorter than the length from the second surface 100b of the insulating layer 100 to the lower surface of the lowermost sub-gate structure S_GS in the third direction D3.

[0092] The dummy source / drain pattern 160 may include the same material as the source / drain pattern 150. For example, the dummy source / drain pattern 160 may include a first material and a second material. The second material may be a material different from the first material. The second material may include, for example, carbon (C), silicon (Si), germanium (Ge), or tin (Sn).

[0093] In this case, the concentration of the second material in the dummy source / drain pattern 160 may be lower than the concentration of the second material included in the first source / drain pattern 151. As an example, when the first material includes silicon (Si) and the second material includes germanium (Ge), the concentration of germanium (Ge) included in the dummy source / drain pattern 160 may be lower than the concentration of germanium (Ge) included in the first source / drain pattern 151. However, the present disclosure is not limited thereto, and the concentration of the second material in the dummy source / drain pattern 160 may be greater than the concentration of the second material included in the first source / drain pattern 151. In addition, for example, when the second source / drain pattern 152 and the dummy source / drain pattern 160 include silicon germanium (SiGe), the concentration of germanium (Ge) in the dummy source / drain pattern 160 may be greater than the concentration of germanium (Ge) in the second source / drain pattern 152. Figure 2 , the dummy source / drain pattern 160 is shown to be located between the via members 300; however, this is only for convenience of explanation, and the dummy source / drain pattern is not limited thereto.

[0094] The semiconductor device according to some embodiments may further include an interlayer insulating layer 190 .

[0095] The interlayer insulating layer 190 may be located on the side surface of the gate spacer 140, the side surface of the capping layer 145, and the upper surface of the source / drain pattern 150. The interlayer insulating layer 190 may not cover the upper surface of the capping layer 145. In addition, the element isolation trench STI may be filled with the interlayer insulating layer 190. For example, the interlayer insulating layer 190 may be located on the third portion 230 of the insulating pattern 200 located on the inner wall and bottom surface of the element isolation trench STI. Therefore, the interlayer insulating layer 190 may be placed apart from the insulating layer 100.

[0096] The interlayer insulating layer 190 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material. The low dielectric constant material may include, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxytetrabutylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen Silazen (TOSZ), fluorinated silicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but is not limited thereto.

[0097] According to some embodiments, an etch stop film may be further disposed between the gate spacer 140 and the interlayer insulating layer 190 and between the source / drain pattern 150 and the interlayer insulating layer 190. The etch stop film may include a material having an etching selectivity to the interlayer insulating layer 190. The etch stop film may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0098] The semiconductor device according to some embodiments may further include an upper insulating layer 195 .

[0099] The upper insulating layer 195 may be located on the upper surface of the capping layer 145 and the upper surface of the interlayer insulating layer 190. The upper insulating layer 195 may include the same material as that in the interlayer insulating layer 190. For example, the upper insulating layer 195 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material.

[0100] The semiconductor device according to some embodiments may further include a contact electrode CT.

[0101] The contact electrode CT may be located on the source / drain pattern 150. The contact electrode CT may pass through the interlayer insulating layer 190 and the upper insulating layer 195 and be electrically connected to the source / drain pattern 150.

[0102] The lower surface of the contact electrode CT may be located, for example, at a level similar to that of the upper surface of the uppermost channel pattern among the plurality of channel patterns NS. However, the present disclosure is not limited thereto, and the lower surface of the contact electrode CT may be higher or lower than the lower surface of the uppermost channel pattern among the plurality of channel patterns NS. Alternatively, the lower surface of the contact electrode CT may be located between the lower surface of the lowermost channel pattern and the lower surface of the uppermost channel pattern among the plurality of channel patterns NS.

[0103] The contact electrode CT may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0104] According to some embodiments, a silicide film may be further provided between the source / drain pattern 150 and the contact electrode CT. The silicide film may surround a portion of the contact electrode CT that is recessed into the source / drain pattern 150. The silicide film may include a metal silicide. For example, the silicide film may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0105] The semiconductor device according to some embodiments may further include an upper wiring structure 420 .

[0106] The upper wiring structure 420 may be located on the upper insulating layer 195. The upper wiring structure 420 may include an upper wiring 421 and an upper wiring insulating layer 422.

[0107] The upper wiring 421 may be located on the upper insulating layer 195. The upper wiring 421 may include a metal (eg, copper). The upper wiring 421 may be electrically coupled to the contact electrode CT.

[0108] The upper wiring insulating layer 422 may be located on the upper insulating layer 195. The upper wiring insulating layer 422 may cover the upper wiring structure 420. In other words, the upper wiring insulating layer 422 may cover the upper wiring 421, and the upper wiring 421 may be located in the upper wiring insulating layer 422. The upper wiring insulating layer 422 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric constant material.

[0109] The lower wiring structure 410 may be located on the second surface 100b of the insulating layer 100. The lower wiring structure 410 may be, for example, a power delivery network that supplies a voltage (eg, a power voltage, etc.) to the source / drain patterns 150.

[0110] The lower wiring structure 410 may include a lower wiring 411 and a lower wiring insulating layer 412 .

[0111] The lower wiring 411 may be located on the second surface 100 b of the insulating layer 100 . The lower wiring 411 may include a metal (eg, copper). The lower wiring 411 may be electrically coupled to the via 300 .

[0112] The lower wiring insulating layer 412 may be located on the second surface 100b of the insulating layer 100. The lower wiring insulating layer 412 may cover the lower wiring structure 410. In other words, the lower wiring insulating layer 412 may cover the lower wiring 411, and the lower wiring 411 may be located in the lower wiring insulating layer 412. The lower wiring insulating layer 412 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric constant material.

[0113] The via member 300 may be located between the source / drain pattern 150 and the lower wiring structure 410. Each via member 300 may be coupled to one source / drain pattern 150. For example, the via member 300 may be electrically coupled to the source / drain pattern 150 that is not coupled to the contact electrode CT. However, the via member 300 is not limited thereto and may be electrically coupled to the source / drain pattern 150 coupled to the contact electrode CT.

[0114] Reference will be made herein to a single through-hole feature.

[0115] The via member 300 may extend from the source / drain pattern 150 to the lower wiring structure 410 in the third direction D3. An upper surface of the via member 300 may be coupled to the source / drain pattern 150. According to some embodiments, the source / drain pattern 150 and the lower wiring structure 410 may be electrically coupled to each other through the via member 300. In other words, a voltage (e.g., a power voltage, etc.) may be applied from the lower wiring structure 410 to the source / drain pattern 150 through the via member 300.

[0116] Reference together Figure 4 The via 300 of the semiconductor device according to some embodiments may include a first via portion 310 surrounded by the second portion 220 of the insulating pattern 200 and a second via portion 320 between the first via portion 310 and the lower wiring structure 410. The first via portion 310 may refer to a portion of the via 300 surrounded by the second portion 220 of the insulating pattern 200.

[0117] The first via portion 310 may extend from the lower surface 150U of the source / drain pattern 150 in the third direction D3 . The first via portion 310 may be vertically below the source / drain pattern 150 in the third direction D3 . The first via portion 310 may be electrically coupled to the second via portion 320 .

[0118] The first via portion 310 may be surrounded by at least a portion of the insulating pattern 200. For example, the first via portion 310 may be surrounded by the second portion 220 of the insulating pattern 200. In other words, the first via portion 310 may extend on the second portion 220 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2). The first via portion 310 may abut the second portion 220. The first via portion 310 may be spaced apart from the insulating layer 100 by the second portion 220.

[0119] According to some embodiments, the first width W1 of the first via portion 310 in the first direction D1 may decrease from the first surface 100a of the insulating layer 100. This may be due to the characteristics of the process of forming the first via portion 310 in the space formed by removing the dummy source / drain pattern 160. However, the present disclosure is not limited thereto, and for example, the first via portion 310 may also include a portion in which the first width W1 of each first via portion in the first direction D1 increases from the first surface 100a of the insulating layer 100. In other words, the width of the first via portion 310 in the first direction D1 may increase from the first surface 100a of the insulating layer 100 and then decrease. As another example, the first width W1 of the first via portion 310 in the first direction D1 may be constant.

[0120] According to some embodiments, Figure 2 As shown, a plurality of first via portions 310 may be provided, and the plurality of first via portions 310 may be located on the lower surface of the source / drain pattern 150. In this case, the plurality of first via portions 310 may have different shapes. For example, Figure 2As shown, in the cross-sections taken along the first direction D1 and the third direction D3, the side surfaces of the plurality of first via parts 310 may include different curved surfaces. As an example, the side surface of one of the plurality of first via parts 310 may have a curvature different from the curvature of the side surface of another of the plurality of first via parts 310. Alternatively, the minimum width of one of the plurality of first via parts 310 in the first direction D1 may be different from the minimum width of another of the plurality of first via parts 310 in the first direction D1. For example, the width of an end portion on one side of one of the plurality of first via parts 310 in the first direction D1 may be different from the width of an end portion on one side of another of the plurality of first via parts 310 in the first direction D1.

[0121] This is because, in the process of forming the dummy source / drain pattern 160 of the semiconductor device according to some embodiments, the dummy source / drain recess 160R ( Fig.11 ) may be different in length in the third direction D3. For example, as the width of each dummy source / drain recess 160R in the first direction D1 increases, the length of the corresponding dummy source / drain recess 160R in the third direction D3 may increase. In other words, according to some embodiments, a length distribution of the dummy source / drain recess 160R in the third direction D3 may occur, and therefore, in cross sections taken along the first direction D1 and the third direction D3, the side surface shapes of the dummy source / drain recess 160R may be different.

[0122] In this case, even when there is a length distribution of the dummy source / drain pattern 160, the method of manufacturing a semiconductor device according to some embodiments may form the first via hole TH1 ( Fig.23 ), thereby easily exposing the dummy source / drain pattern 160 filled in the dummy source / drain recess 160R. Then, the method can form the first via portion 310 in the space formed by removing the dummy source / drain pattern 160. Therefore, the side surface shapes of the plurality of first via portions 310 may be different. This will be described in detail below.

[0123] The first via portion 310 may include the same material as that in the contact electrode CT. The first via portion 310 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. However, the first via portion 310 is not limited thereto and may include a material different from that in the contact electrode CT.

[0124] The second via portion 320 may be located between the first via portion 310 and the lower wiring structure 410. The second via portion 320 may extend from the lower surface of the first via portion 310 toward the second surface 100b of the insulating layer 100 in the third direction D3. In other words, the second via portion 320 may extend in the third direction D3 and directly contact the lower surface of the first via portion 310. The second via portion 320 may be located vertically below the first via portion 310 in the third direction D3. The second via portion 320 may pass through the insulating layer 100 and contact the lower wiring structure 410. The second via portion 320 may be electrically coupled to the lower wiring 411 of the lower wiring structure 410.

[0125] According to some embodiments, a bent portion may be provided at a portion where the second via portion 320 and the first via portion 310 are adjacent to each other. Therefore, the second width W2 of the second via portion 320 in the first direction D1 may be greater than the first width W1 of the first via portion 310 in the first direction D1. For example, the width of the upper surface of the second via portion 320 in the first direction D1 may be greater than the maximum width of the first via portion 310 in the first direction D1. This may be due to the characteristics of the following processes: first forming the first via hole TH1 so that some portions of the insulating pattern 200 are exposed, etching the exposed portion of the insulating pattern 200 to remove the dummy source / drain pattern 160, forming the first via portion 310 in the space formed by removing the dummy source / drain pattern 160, and forming the second via portion 320 in the first via hole TH1 during the process of forming the second via portion 320. This will be described in detail below.

[0126] Therefore, the upper surface of the second via portion 320 may contact the first via portion 310, the second portion 220 of the insulating pattern 200, and the insulating layer 100. The side surface of the second via portion 320 may contact the insulating layer 100. The second via portion 320 may not extend on the second portion 220 of the insulating pattern 200 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2). In other words, the side surface of the second via portion 320 may not contact the insulating pattern 200. However, the present disclosure is not limited thereto, and at least a portion of the side surface of the second via portion 320 may contact the second portion 220 of the insulating pattern 200. This will be referred to below. Figure 5 Give a description.

[0127] The second via portion 320 may include the same material as that in the first via portion 310. The second via portion 320 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride. In this case, the second via portion 320 may be formed integrally with the first via portion 310 without any interface. However, the second via portion 320 is not limited thereto, and may include a material different from that in the first via portion 310.

[0128] The semiconductor device according to some embodiments may further include a silicide layer 260 .

[0129] The silicide layer 260 may be located between the source / drain pattern 150 and the first via member portion 310. The silicide layer 260 may be disposed along the boundary of the first via member portion 310 to abut against the source / drain pattern 150. The silicide layer 260 may contact the second portion 220 of the insulating pattern 200, but is not limited thereto. The silicide layer 260 may include a metal silicide. For example, the silicide layer 260 may include, for example, at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. In some embodiments, a barrier metal layer may also be disposed between the silicide layer 260 and the via member 300, but the present disclosure is not limited thereto.

[0130] In the following, reference will be made to Figure 2 and Figure 4 The insulation pattern 200 according to some embodiments is described in detail.

[0131] Reference Figure 2 and Figure 4 According to some embodiments, the insulating pattern 200 of the semiconductor device may include a first portion 210 located between the lower pattern BP and the insulating layer 100, a second portion 220 surrounding at least a portion of the through-hole member 300, a third portion 230 located on the inner wall and bottom surface of the element isolation trench STI, and a fourth portion 240 surrounding the dummy source / drain pattern 160.

[0132] The first portion 210 of the insulating pattern 200 may be located on the first surface 100a of the insulating layer 100. The first portion 210 may be located between the first surface 100a of the insulating layer 100 and the lower surface of the lower pattern BP. Therefore, the first portion 210 may be located between the sub-gate structure S_GS and the insulating layer 100. For example, the first portion 210 may be located between the lowermost sub-gate structure S_GS and the insulating layer 100. The first portion 210 may be located vertically below the sub-gate structure S_GS in the third direction D3. The first portion 210 may be located on the first surface 100a of the insulating layer 100 to conform thereto.

[0133] According to some embodiments, the lower surface 210U of the first portion 210 may be located at a higher level than the lower surface 150U of the source / drain pattern 150. In other words, the lower surface 210U of the first portion 210 may be located farther from the second surface 100b of the insulating layer 100 than the lower surface 150U of the source / drain pattern 150. In other words, the lower surface 210U of the first portion 210 may be located farther from the second surface 100b of the insulating layer 100 than the upper surface of the via member 300. Therefore, the lower pattern BP located on the first portion 210 and the via member 300 are spaced apart from each other, and the lower pattern BP and the via member 300 may be electrically insulated from each other.

[0134] The second portion 220 of the insulating pattern 200 may extend in the third direction D3. The second portion 220 may surround at least a portion of the via 300. For example, the second portion 220 may surround the first via portion 310 of the via 300. The second portion 220 may be located between the insulating layer 100 and the first via portion 310 of the via 300. In other words, the second portion 220 may conformally cover the first via portion 310 of the via 300 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2).

[0135] According to some embodiments, the second portion 220 may be located on the second via portion 320 of the via 300. The second portion 220 may be located on the upper surface of the second via portion 320 of the via 300. The lower surface of the second portion 220 may contact the upper surface of the second via portion 320 of the via 300. Therefore, the second portion 220 may extend below at least a portion of the via 300 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2). For example, the second portion 220 may extend below the first via portion 310 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2). In addition, the second portion 220 may not extend above or below the second via portion 320 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2).

[0136] In an embodiment, the second portion 220 may extend along the third direction D3 and cover at least a portion of a side surface of the source / drain pattern 150. The second portion 220 may surround at least a portion of a side surface of the source / drain pattern 150. Therefore, the source / drain pattern 150 may be spaced apart from the insulating layer 100 by the second portion 220.

[0137] The second portion 220 may cover at least a portion of the side surface of the first via portion 310 and the side surface of the source / drain pattern 150. In addition, the lower surface of the first portion 210 may be located at a higher level than the upper surface of the via 300. Therefore, the first portion 210 and the second portion 220 may be located between the lower pattern BP and the via 300 and / or between the sub-gate structure S_GS located on the first portion 210 and the via 300. In other words, the lower pattern BP and the via 300 may be spaced apart from each other, and / or the sub-gate structure S_GS and the via 300 may be spaced apart from each other. Therefore, the lower pattern BP and the via 300 and / or the sub-gate structure S_GS and the via 300 may be electrically insulated from each other by the first portion 210 and the second portion 220.

[0138] According to some embodiments, the width between the outer surfaces of each second portion 220 in the first direction D1 may decrease from the first surface 100a of the insulating layer 100. This may be due to the characteristics of the following process: the dummy source / drain pattern 160 is formed, and then the second portion 220 is formed along the outer surface of the dummy source / drain pattern 160. However, the present disclosure is not limited thereto, and the second portion 220 may also include a portion in which the width between the outer surfaces of each second portion 220 in the first direction D1 increases from the first surface 100a of the insulating layer 100. In other words, the width between the outer surfaces of each second portion 220 in the first direction D1 may increase from the first surface 100a of the insulating layer 100 and then decrease.

[0139] According to some embodiments, a plurality of second portions 220 may be provided and disposed on the side surfaces of the first via portion 310, respectively. In this case, the plurality of second portions 220 may have different shapes. For example, in cross sections taken along the first direction D1 and the third direction D3, the side surfaces of the plurality of second portions 220 may include different curved surfaces. As an example, the side surface of one of the plurality of second portions 220 may have a curvature different from the curvature of the side surface of another of the plurality of second portions 220. Alternatively, the minimum distance between the second portions 220 covering the two side surfaces of one first via portion 310 may be different from the minimum distance between the second portions 220 covering the two side surfaces of another first via portion 310.

[0140] This is because, in the process of forming the dummy source / drain pattern 160 of the semiconductor device according to some embodiments, the length of the dummy source / drain recess 160R in the third direction D3 may be different. For example, as the width of each dummy source / drain recess 160R in the first direction D1 increases, the length of the corresponding dummy source / drain recess 160R in the third direction D3 may increase. In other words, according to some embodiments, the length distribution of the dummy source / drain recess 160R in the third direction D3 may occur, and therefore, in the cross-sections taken along the first direction D1 and the third direction D3, the side surface shapes of the dummy source / drain recess 160R may be different. Therefore, since the second portion 220 is formed along the outer surface of the dummy source / drain pattern 160, the shape of the side surface of the second portion 220 may be different.

[0141] Even when there is a length distribution of the dummy source / drain pattern 160 , the method of manufacturing a semiconductor device according to some embodiments may form the first via hole TH1 through a dry etching process, thereby easily exposing the second portion 220 . This will be described in detail below.

[0142] like Figure 2 As shown, the third portion 230 of the insulating pattern 200 may be located in the element isolation trench STI. Specifically, the third portion 230 may be located on the inner wall and bottom surface of the element isolation trench STI. The third portion 230 may be arranged along the inner wall and bottom surface of the element isolation trench STI to conform to them. The third portion 230 may be located between the insulating layer 100 and the interlayer insulating layer 190. The third portion 230 may contact the insulating layer 100 and the interlayer insulating layer 190.

[0143] According to some embodiments, the first height H1 of the third portion 230 in the third direction D3 may be greater than the second height H2 of the second portion 220 in the third direction D3. In this case, the upper surface of the third portion 230 may be located at a level substantially the same as that of the upper surface of the second portion 220. Therefore, the lower surface of the third portion 230 may be located at a lower level than the lower surface of the second portion 220. In other words, the lower surface of the third portion 230 may be located closer to the second surface 100b of the insulating layer 100 than the lower surface of the second portion 220.

[0144] In this case, the first height H1 of the third portion 230 in the third direction D3 may be substantially the same as the inner wall length of the element isolation trench STI in the third direction D3. In other words, according to some embodiments, the second height H2 of the second portion 220 in the third direction D3 may be less than the inner wall height of the element isolation trench STI in the third direction D3. This may be due to the characteristics of the following process: according to some embodiments, when the through-hole member 300 is formed by etching at least a portion of the insulating pattern 200, the first via hole TH1 is formed to expose the second portion 220 of the insulating pattern 200, and the exposed second portion 220 is etched.

[0145] The fourth portion 240 of the insulating pattern 200 may extend in the third direction D3. The fourth portion 240 may surround the dummy source / drain pattern 160. For example, the fourth portion 240 may surround the lower surface and the side surface of the dummy source / drain pattern 160. The fourth portion 240 may be located between the insulating layer 100 and the dummy source / drain pattern 160. In other words, the fourth portion 240 may extend below the dummy source / drain pattern 160 in the first direction D1 and / or the second direction D2.

[0146] According to some embodiments, the fourth portion 240 may extend in the third direction D3 and cover at least a portion of a side surface of the source / drain pattern 150. The fourth portion 240 may surround at least a portion of a side surface of the source / drain pattern 150. Therefore, the source / drain pattern 150 may be spaced apart from the insulating layer 100 by the fourth portion 240.

[0147] According to some embodiments, the height of the fourth portion 240 in the third direction D3 may be greater than the second height H2 of the second portion 220 in the third direction D3, but is not limited thereto. For example, the height of the fourth portion 240 in the third direction D3 may be less than or equal to the second height H2 of the second portion 220 in the third direction D3. This is because the height distribution of the dummy source / drain pattern 160 in the third direction D3 is caused by the process of forming the dummy source / drain recess 160R.

[0148] In the semiconductor device according to some embodiments, the insulating pattern 200 may be located on the first surface 100a of the insulating layer 100. Specifically, the second portion 220 of the insulating pattern 200 may surround at least a portion of the via member 300. Therefore, during the process of forming the via member 300, the surrounding material layers (e.g., the insulating layer 100, the lower pattern BP and / or the sub-gate structure S_GS) adjacent to the via member 300 may be prevented from being etched, and the problem of short circuit between the via member 300 and the surrounding material layers may be prevented. Therefore, the reliability of the semiconductor device may be improved.

[0149] Furthermore, in the semiconductor device according to some embodiments, the first portion 210 of the insulating pattern 200 may be located between the insulating layer 100 and the lower pattern BP, and the second portion 220 of the insulating pattern 200 may cover at least a portion of the side surface of the first via portion 310 and the side surface of the source / drain pattern 150. Therefore, even when the via 300 is formed, the lower pattern BP and the via 300 and / or the sub-gate structure S_GS and the via 300 may be electrically insulated from each other by the first portion 210 and the second portion 220. Therefore, the reliability of the semiconductor device may be improved.

[0150] Furthermore, even when there is a length distribution of the dummy source / drain pattern 160 , the method of manufacturing a semiconductor device according to some embodiments may form the first via hole TH1 through a dry etching process, thereby easily exposing the dummy source / drain pattern 160 filled in the dummy source / drain recess 160R.

[0151] In the following, reference will be made to Figures 5 to 9 A semiconductor device according to some embodiments is described.

[0152] Figures 5 to 8 is a method according to one or more example embodiments corresponding to Figure 2 A cross-sectional view of a portion of a semiconductor device in the S1 region.

[0153] Figure 5 is a cross-sectional view of a portion of a semiconductor device according to some embodiments, corresponding to Figure 2 The S1 region in the

[0154] Figure 5 Features similar to those described above are included, and repeated descriptions may be omitted. In some embodiments, the shape of the second portion 220 of the insulation pattern 200 may be different from the shape described above.

[0155] The semiconductor device according to some embodiments may include an insulating layer 100, an insulating pattern 200, an active pattern AP, a field insulating layer 105, a gate structure GS, a source / drain pattern 150, a dummy source / drain pattern 160, a lower wiring structure 410, and a via 300. The insulating pattern 200 may include first to fourth portions 210 to 240.

[0156] As described above, the second portion 220 of the insulating pattern 200 may extend below the first through-hole member portion 310 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2), and the second portion 220 of the insulating pattern 200 may not extend below or above the second through-hole member portion 320 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2).

[0157] Reference Figure 5 , the central axis of the first via portion 310 according to some embodiments may be spaced apart from the central axis of the second via portion 320. For example, Figure 5 As shown, the central axis of the first via portion 310 along the third direction D3 may be substantially the same as the central axis of the source / drain pattern 150 along the third direction D3. In addition, the central axis of the first via portion 310 along the third direction D3 may be spaced apart from the central axis of the second via portion 320 along the third direction D3 in the first direction D1. In other words, the second via portion 320 may not be aligned with the first via portion 310. This may be due to process characteristics: in the process of forming the second via portion 320, when the exposed dummy pattern 161 ( Fig.13 ) when the first through hole TH1 is formed.

[0158] exist Figure 5 , it is shown that in the first direction D1, the central axis of the first through-hole member portion 310 along the third direction D3 is spaced apart from the central axis of the second through-hole member portion 320 along the third direction D3; however, the present disclosure is not limited thereto. For example, the central axis of the first through-hole member portion 310 along the third direction D3 may be spaced apart from the central axis of the second through-hole member portion 320 along the third direction D3 in the first direction D1 and / or the second direction D2.

[0159] According to some embodiments, the first portion 220_G1 of the second portion 220 of the insulating pattern 200 may be located on the upper surface of the second via portion 320. The second portion 220_G2 of the second portion 220 of the insulating pattern 200 may be located on the side surface of the second via portion 320. In other words, the second portion 220_G2 of the second portion 220 may extend to the second via portion 320 in a horizontal direction (e.g., the first direction D1 and / or the second direction D2). As an example, the length of the second portion 220 extending to the second via portion 320 in the horizontal direction may be less than the length of the second via portion 320 along the third direction D3. Therefore, the side surface of the second via portion 320 may contact the insulating layer 100, the first via portion 310, and the second portion 220.

[0160] Figure 6 is a cross-sectional view of a portion of a semiconductor device according to some embodiments, corresponding to Figure 2 The S1 region in the

[0161] Figure 6 Features similar to those described above are included, and repeated descriptions may be omitted. Figure 6 In the embodiment, each insulating pattern 200 may include a plurality of layers, and will be described below.

[0162] The semiconductor device according to some embodiments may include an insulating layer 100, an insulating pattern 200, an active pattern AP, a field insulating layer 105, a gate structure GS, a source / drain pattern 150, a dummy source / drain pattern 160, a lower wiring structure 410, and a via 300. The insulating pattern 200 may include first to fourth portions 210 to 240.

[0163] As described above, the insulating pattern 200 includes the first to fourth portions 210 to 240. Each of the insulating patterns 200 may include a single layer.

[0164] Reference Figure 6 According to some embodiments, each insulating pattern 200 may include a plurality of layers. For example, the insulating pattern 200 may include an outer insulating pattern 220E and an inner insulating pattern 220I.

[0165] The outer insulating pattern 200E may be located on the first surface 100a of the insulating layer 100. The outer insulating pattern 200E may be located between the first surface 100a of the insulating layer 100 and the lower pattern BP. In addition, the outer insulating pattern 200E may surround at least a portion of the via member 300. The outer insulating pattern 200E may be located between the insulating layer 100 and the via member 300. In addition, the outer insulating pattern 200E may surround the dummy source / drain pattern 160. The insulating pattern 200 may be located between the insulating layer 100 and the dummy source / drain pattern 160. In addition, the outer insulating pattern 200E may be located in the element isolation trench STI of the insulating layer 100. In other words, the outer insulating pattern 200E may be located between the insulating layer 100 and the interlayer insulating layer 190.

[0166] Therefore, the outer insulating pattern 200E may include a first portion 211 located between the lower pattern BP and the insulating layer 100, and a second portion 212 surrounding at least a portion of the through-hole member 300. In this case, the first portion 211 and the second portion 212 of each outer insulating pattern 200E may be integrally formed without any interface, but is not limited thereto. In addition, the outer insulating pattern 200E may further include a portion located on the inner wall and bottom surface of the element isolation trench STI, and a portion surrounding the dummy source / drain pattern 160.

[0167] The outer insulating pattern 200E may include various insulating materials. The outer insulating pattern 200E may include a material having an etching selectivity to the insulating layer 100. For example, the outer insulating pattern 200E may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN). Alternatively, the outer insulating pattern 200E may include a metal oxide or a metal nitride, such as aluminum oxide (Al2O3). 2 O 3) or aluminum nitride (AlN).

[0168] The inner insulating pattern 220I may be located on the outer insulating pattern 200E. The inner insulating pattern 220I may be located on the outer insulating pattern 200E to conform to the outer insulating pattern 200E. For example, the first portion 221 of the inner insulating pattern 220I may be located on the first portion 211 of the outer insulating pattern 200E. In other words, the first portion 221 of the inner insulating pattern 220I may be located between the first portion 211 of the outer insulating pattern 200E and the lower pattern BP. In addition, the second portion 222 of the inner insulating pattern 220I may be located on the second portion 212 of the outer insulating pattern 200E. The second portion 222 of the inner insulating pattern 220I may be located between the second portion 212 of the outer insulating pattern 200E and the through-hole member 300.

[0169] The inner insulating pattern 220I may include a material different from that in the outer insulating pattern 200E. The inner insulating pattern 220I may include a material having an etching selectivity to the outer insulating pattern 200E. For example, the inner insulating pattern 220I may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), aluminum nitride (AlN), and aluminum oxide (AlO). 2 O 3 ) at least one of.

[0170] Figure 7 is a cross-sectional view of a portion of a semiconductor device according to some embodiments, corresponding to Figure 2 The S1 region in the

[0171] Figure 7 Features similar to those described above are included, and repeated descriptions may be omitted. Figure 7 In the embodiment, a barrier layer 330 is further included and will be described below.

[0172] The semiconductor device according to some embodiments may include an insulating layer 100, an insulating pattern 200, an active pattern AP, a field insulating layer 105, a gate structure GS, a source / drain pattern 150, a dummy source / drain pattern 160, a lower wiring structure 410, and a via 300. The insulating pattern 200 may include first to fourth portions 210 to 240.

[0173] As described above, the insulating pattern 200 may include the first to fourth portions 210 to 240. Each of the insulating patterns 200 may include a single layer.

[0174] Reference Figure 7 , the semiconductor device according to some embodiments may further include a barrier layer 330 between the via 300 and the second portion 220 of the insulating pattern 200 .

[0175] The barrier layer 330 may surround the via member 300. The barrier layer 330 may extend in the third direction D3 and cover the side surface of the via member 300. The barrier layer 330 may be located between the via member 300 and the silicide layer 260, but is not limited thereto. The barrier layer 330 may be located between the via member 300 and the second portion 220 of the insulating pattern 200 and between the via member 300 and the insulating layer 100. The barrier layer 330 may include a conductive material. For example, the barrier layer 330 may include at least one of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride.

[0176] Figure 8 is a cross-sectional view of a portion of a semiconductor device according to some embodiments, corresponding to Figure 2 The S1 region in the

[0177] Figure 8 Features similar to those described above are included, and repeated descriptions may be omitted. Figure 8 In the example, the lower pattern BP is not set and will be described below.

[0178] The semiconductor device according to some embodiments may include an insulating layer 100, an insulating pattern 200, an active pattern AP, a field insulating layer 105, a gate structure GS, a source / drain pattern 150, a dummy source / drain pattern 160, a lower wiring structure 410, and a via 300. The insulating pattern 200 may include first to fourth portions 210 to 240.

[0179] As described above, each active pattern AP may include a lower pattern BP and a plurality of channel patterns NS.

[0180] However, referring to Figure 8 , the semiconductor device according to some embodiments may not include the lower pattern BP. In other words, the first portion 210 of the insulating pattern 200 may contact the gate structure GS. For example, the first portion 210 may contact the lowermost sub-gate structure S_GS. In addition, the first portion 210 may contact the inner gate spacer 135. This may be because the substrate 111 between the dummy source / drain patterns 160 adjacent in the first direction D1 has been completely removed in the process of removing the substrate 111.

[0181] However, even in this case, the lower surface 210U of the first portion 210 may be located at a higher level than the lower surface 150U of the source / drain pattern 150. In other words, the lower surface 210U of the first portion 210 may be located farther from the second surface 100b of the insulating layer 100 than the lower surface 150U of the source / drain pattern 150.

[0182] Fig. 9 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments.

[0183] Fig. 9 Features similar to those described above are included, and repeated descriptions may be omitted. Fig. 9 In the embodiment, the inner gate spacer 135 is not provided and will be described below.

[0184] The semiconductor device according to some embodiments may include an insulating layer 100, an insulating pattern 200, an active pattern AP, a field insulating layer 105, a gate structure GS, a source / drain pattern 150, a dummy source / drain pattern 160, a lower wiring structure 410, and a via 300. The insulating pattern 200 may include first to fourth portions 210 to 240.

[0185] As described above, the inner gate spacer 135 may be located on the side surface of the sub-gate structure S_GS.

[0186] However, reference Fig. 9 , the semiconductor device according to some embodiments may not include the inner gate spacer 135. Therefore, the sub-gate structure S_GS may contact the source / drain pattern 150. In other words, the side surface of the source / drain pattern 150 may contact the side surface of the sub-gate structure S_GS.

[0187] In the following, reference will be made to Figures 10 to 27 A method of manufacturing a semiconductor device according to an embodiment is described.

[0188] Figures 10 to 27 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more example embodiments.

[0189] like Fig.10 As shown, an upper pattern structure U_AP is formed on the substrate 111 , and a preliminary gate insulating layer 130P, a preliminary main gate electrode 120MP and a preliminary capping layer 120_HM are formed.

[0190] First, an upper pattern structure U_AP is formed on a substrate 111. The substrate 111 may be silicon on insulator (SOI) or bulk silicon. Alternatively, the substrate 111 may be a silicon substrate, or may include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0191] The substrate 111 may have a first surface 111a and a second surface 111b. The first surface 111a and the second surface 111b of the substrate 111 may be formed as planes parallel to the first direction D1 and the second direction D2 intersecting the first direction D1. The first surface 111a of the substrate 111 may be opposite to the second surface 111b in the third direction D3. The first surface 111a of the substrate 111 may be referred to as an upper surface or a front surface of the substrate 111. The second surface 111b of the substrate 111 may be referred to as a lower surface or a back surface of the substrate 111. In some embodiments, a logic circuit in a cell region may be implemented on the first surface 111a of the substrate 111.

[0192] The upper pattern structure U_AP may be located on the first surface 111a of the substrate 111. The upper pattern structure U_AP may include sacrificial patterns SC_L and active patterns ACT_L alternately stacked on the substrate 111. For example, the sacrificial patterns SC_L may include silicon germanium (SiGe). The active patterns ACT_L may include silicon (Si).

[0193] Subsequently, the substrate 111 and at least a portion of the upper pattern structure U_AP may be etched to form an element isolation trench STI. The element isolation trench STI may pass through the upper pattern structure U_AP. The element isolation trench STI may pass through at least a portion of the substrate 111.

[0194] Next, on the upper pattern structure U_AP, a preliminary gate insulating layer 130P, a preliminary main gate electrode 120MP, and a preliminary capping layer 120_HM may be formed.

[0195] The preliminary gate insulating layer 130P may include, for example, silicon oxide (SiO 2 ), but not limited thereto. The preliminary main gate electrode 120MP may include, for example, polysilicon, but not limited thereto. The preliminary capping layer 120_HM may include, for example, silicon nitride, but not limited thereto.

[0196] On both side surfaces of each preliminary main gate electrode 120MP, a preliminary gate spacer 140P may be formed.

[0197] like Fig.11 As shown, the preliminary main gate electrode 120MP and the preliminary gate spacer 140P may be used as a mask to etch at least a portion of the upper pattern structure U_AP and the substrate 111, thereby forming a dummy source / drain recess 160R. The dummy source / drain recess 160R may pass through the upper pattern structure U_AP. The dummy source / drain recess 160R may pass through at least a portion of the substrate 111. In other words, at least a portion of the dummy source / drain recess 160R may be formed in the substrate 111.

[0198] In this case, the height of the dummy source / drain recess 160R in the third direction D3 may be different. For example, as the width of each of the dummy source / drain recesses 160R in the first direction D1 increases, the height of the corresponding dummy source / drain recess 160R in the third direction D3 may increase. According to some embodiments, a height distribution of the dummy source / drain recess 160R in the third direction D3 may occur.

[0199] As the dummy source / drain recess 160R is formed, the active pattern ACT_L may be divided, so that a plurality of channel patterns NS may be formed. On both sides of each of the dummy source / drain recesses 160R, a plurality of channel patterns NS may be provided. A structure in which a plurality of channel patterns NS and sacrificial patterns SC_L are alternately stacked may be provided. In this case, the lengths of the plurality of channel patterns NS may be different or the same.

[0200] like Fig.12 As shown, at least a portion of the exposed side surface of the sacrificial pattern SC_L may be removed, and in the space formed by the removal, an inner gate spacer 135 may be formed. The inner gate spacer 135 may be formed on the side surface of the sacrificial pattern SC_L. However, the present disclosure is not limited thereto, and according to some embodiments, the process of forming the inner gate spacer 135 may be omitted (e.g., Fig. 9 ).

[0201] like Fig.13 As shown, the dummy source / drain pattern 160 and the source / drain pattern 150 may be formed in the dummy source / drain recess 160R.

[0202] First, a dummy source / drain pattern 160 may be formed in the dummy source / drain recess 160R. The dummy source / drain pattern 160 may be formed on the substrate 111. The dummy source / drain pattern 160 may be formed using an epitaxial growth method. The dummy source / drain pattern 160 may directly contact the substrate 111. In this case, an upper surface of the dummy source / drain pattern 160 may be formed to be lower than a lower surface of the lowermost sacrificial pattern SC_L.

[0203] The dummy source / drain pattern 160 may include a first material and a second material. The second material may be a material different from the first material. The second material may include, for example, carbon (C), silicon (Si), germanium (Ge), or tin (Sn).

[0204] According to some embodiments, the dummy source / drain patterns 160 may include dummy patterns 161 that are removed in a subsequent process of forming the through-hole member 300. In other words, some of the dummy source / drain patterns 160 may be used to form the through-hole member 300 ( Figure 2) of the dummy pattern 161. In a subsequent process, the dummy pattern 161 may be removed, and the via member 300 may be formed in a space formed by the removal. Hereinafter, for convenience of explanation, the dummy source / drain pattern 160 removed in the process of forming the via member 300 is referred to as the dummy pattern 161.

[0205] According to some embodiments, the height of the dummy source / drain pattern 160 in the third direction D3 may be different. This is because the dummy source / drain pattern 160 is formed in the dummy source / drain recess 160R having different heights in the third direction D3. Therefore, a height distribution of the dummy source / drain pattern 160 in the third direction D3 may occur.

[0206] Subsequently, a source / drain pattern 150 may be formed on the dummy source / drain pattern 160. The source / drain pattern 150 may be formed using an epitaxial growth method. Specifically, a second source / drain pattern 152 may be formed along the sidewall and bottom surface of the source / drain recess 150R. Next, a first source / drain pattern 151 may be formed on the second source / drain pattern 152.

[0207] The second source / drain pattern 152 may include a first material. The first material may include a semiconductor material. For example, the first material may include silicon (Si) or germanium (Ge) as a semiconductor material.

[0208] The first source / drain pattern 151 may include the same material as that in the dummy source / drain pattern 160. The first source / drain pattern 151 may include a first material and a second material. The second material may include, for example, carbon (C), silicon (Si), germanium (Ge), or tin (Sn). As an example, the second source / drain pattern 152 may include silicon (Si), and the first source / drain pattern 151 may include silicon germanium (SiGe).

[0209] However, the present disclosure is not limited thereto, and as another example, the first source / drain pattern 151 may include the same material as that in the second source / drain pattern 152. In this case, the concentrations of the constituent materials in the first source / drain pattern 151 and the second source / drain pattern 152 may be different. For example, when the first source / drain pattern 151 and the second source / drain pattern 152 include silicon germanium (SiGe), the concentration of germanium (Ge) in the first source / drain pattern 151 may be greater than the concentration of germanium (Ge) in the second source / drain pattern 152; however, the present disclosure is not limited thereto. As yet another example, the first source / drain pattern 151 and the second source / drain pattern 152 may include the same material, and the first source / drain pattern 151 and the second source / drain pattern 152 may have the same concentration of constituent materials.

[0210] like Fig.14 As shown, an interlayer insulating layer 190 may be formed on the source / drain pattern 150. In addition, the interlayer insulating layer 190 may be formed in the element isolation trench STI.

[0211] Subsequently, at least a portion of the interlayer insulating layer 190 and the preliminary capping layer 120_HM may be removed to expose the upper surface of the preliminary main gate electrode 120MP. Some of the preliminary gate spacers 140P may be removed together, thereby forming the gate spacers 140.

[0212] like Fig.15 As shown, the preliminary gate insulating layer 130P and the preliminary main gate electrode 120MP may be removed to expose a portion of the upper pattern structure U_AP between the gate spacers 140. Subsequently, the sacrificial pattern SC_L may be removed to form a gate trench 120t between the plurality of channel patterns NS.

[0213] like Fig.16 As shown, a sub-gate insulating layer 130S and a sub-gate electrode 120S may be sequentially formed in the gate trench 120t. In addition, a main gate insulating layer 130M, a main gate electrode 120M, and a capping layer 145 may be sequentially formed.

[0214] like Fig.17 As shown, an upper insulating layer 195 may be formed on the interlayer insulating layer 190 , and a contact electrode CT may be formed to pass through the upper insulating layer 195 and the interlayer insulating layer 190 .

[0215] First, an upper insulating layer 195 may be formed to cover the upper surface of the interlayer insulating layer 190 and the upper surface of the capping layer 145. The upper insulating layer 195 may include the same material as that in the interlayer insulating layer 190. For example, the upper insulating layer 195 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) and at least one of a low dielectric constant material.

[0216] Subsequently, a contact hole may be formed to pass through the upper insulating layer 195 and the interlayer insulating layer 190 and expose the source / drain pattern 150. The contact hole may not be formed over the source / drain pattern 150 located on the dummy pattern 161, but is not limited thereto.

[0217] Next, the contact hole may be filled, and thus the contact electrode CT may be formed so as to be electrically coupled to the source / drain pattern 150. Therefore, the contact electrode CT may pass through the upper insulating layer 195 and the interlayer insulating layer 190 and be electrically coupled to the source / drain pattern 150.

[0218] like Fig.18As shown, an upper wiring structure 420 may be formed on the upper insulating layer 195. The upper wiring structure 420 may include an upper wiring 421 and an upper wiring insulating layer 422. The upper wiring 421 may be formed on the upper insulating layer 195. The upper wiring 421 may include a metal (eg, copper). The upper wiring 421 may be electrically coupled to the contact electrode CT.

[0219] like Fig.19 As shown, the semiconductor device according to some embodiments may be turned over, and the substrate 111 may be located on the carrier substrate 500. The substrate 111 may be placed so that the upper surface 420a of the upper wiring structure 420 faces the carrier substrate 500, and is attached to the carrier substrate 500. Between the upper surface 420a of the upper wiring structure 420 and the carrier substrate 500, a bonding member may be provided.

[0220] The carrier substrate 500 may have substantially the same area as that of the substrate 111, or may have a larger area. The carrier substrate 500 may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate.

[0221] like Fig. 20 As shown, the substrate 111 may be removed by performing an etching process. For example, the etching process may be performed by a dry etching method. In this case, the interlayer insulating layer 190 may include a material having an etching selectivity to the substrate 111.

[0222] The process of etching the substrate 111 may perform an etching process using an etchant having an etching selectivity to the dummy source / drain pattern 160. For example, when the substrate 111 includes silicon (Si) and the dummy source / drain pattern 160 includes silicon germanium (SiGe), the etching process may be performed using an etchant having a relatively high etching rate to silicon.

[0223] According to some embodiments, it has been described that the substrate 111 is removed by the dry etching method; however, the present disclosure is not limited thereto, and the substrate 111 may be removed using a wet etching method.

[0224] As the substrate 111 is removed, the dummy source / drain patterns 160 , the dummy patterns 161 , and the interlayer insulating layer 190 may be exposed.

[0225] At least a portion of the substrate 111 between adjacent source / drain patterns 150 in the first direction D1 may be retained to form a lower pattern BP. This is because, since the source / drain patterns 150 and the dummy source / drain patterns 160 protrude in the third direction D3, sufficient space for etching the substrate 111 may not be ensured between adjacent dummy source / drain patterns 160 in the first direction D1 and between adjacent source / drain patterns 150 in the first direction D1. Thereafter, in the process of etching the substrate 111, at least a portion of the substrate 111 may be retained between adjacent source / drain patterns 150 in the first direction D1, thereby forming the lower pattern BP. However, the present invention is not limited thereto, and according to some embodiments, the substrate 111 may be removed between adjacent source / drain patterns 150 in the first direction D1 so that the sub-gate structure S_GS is exposed (for example, Figure 8 ).

[0226] According to some embodiments, an upper surface of the source / drain pattern 150 may be positioned farther from an upper surface of the carrier substrate 500 than an upper surface of the lower pattern BP. Thus, at least a portion of a side surface of the source / drain pattern 150 may be exposed.

[0227] like Fig.21 As shown, an insulating pattern 200 may be formed on the lower pattern BP, the dummy pattern 161, the interlayer insulating layer 190, and the dummy source / drain pattern 160. The insulating pattern 200 may be formed on the lower pattern BP, the dummy pattern 161, the interlayer insulating layer 190, and the dummy source / drain pattern 160 to conform thereto.

[0228] According to some embodiments, the insulating pattern 200 may include a first portion 210 located on the lower pattern BP, a second preliminary portion 220P located on the dummy pattern 161, a third portion 230 located on the interlayer insulating layer 190, and a fourth portion 240 located on the dummy source / drain pattern 160. The first portion 210, the second preliminary portion 220P, the third portion 230, and the fourth portion 240 may be provided in plurality, but for ease of description, are described from a single perspective. The dummy pattern 161 may refer to the dummy source / drain pattern 160 that is removed in the process of the via member 300.

[0229] According to some embodiments, an upper surface of the first portion 210 may be positioned closer to an upper surface of the carrier substrate 500 than an upper surface of the source / drain pattern 150 . Thus, the first portion 210 may be located between the lower pattern BP and the dummy source / drain pattern 160 .

[0230] According to some embodiments, the second preliminary portion 220P of the insulating pattern 200 may surround the dummy pattern 161. The second preliminary portion 220P may completely cover the upper surface and the side surface of the dummy pattern 161. In addition, the second preliminary portion 220P may extend along the third direction D3 and cover at least a portion of the side surface of the source / drain pattern 150. The second preliminary portion 220P may surround at least a portion of the side surface of the source / drain pattern 150.

[0231] According to some embodiments, the fourth portion 240 of the insulating pattern 200 may surround the dummy source / drain pattern 160. The fourth portion 240 may completely cover the side surface and the upper surface of the dummy source / drain pattern 160. In addition, the fourth portion 240 may extend along the third direction D3 and cover at least a portion of the side surface of the source / drain pattern 150. The fourth portion 240 may surround at least a portion of the side surface of the source / drain pattern 150.

[0232] According to some embodiments, the heights at which the upper surfaces of the second preliminary portion 220P and the fourth portion 240 extend along the third direction D3 may be different. For example, the upper surface of the second preliminary portion 220P and the upper surface of the fourth portion 240 may have different horizontal heights from each other. This is because the insulating pattern 200 is formed on the dummy source / drain pattern 160 having different heights along the third direction D3. Therefore, a height distribution of the second preliminary portion 220P and the fourth portion 240 in the third direction D3 may occur.

[0233] The insulating pattern 200 may include various insulating materials. The insulating pattern 200 may include a material having an etching selectivity to the insulating layer 100. For example, the insulating pattern 200 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN).

[0234] like Fig. 22 As shown, the insulating layer 100 may be formed on the insulating pattern 200. For example, the insulating layer 100 may be formed to cover the first portion 210, the second preliminary portion 220P, the third portion 230, and the fourth portion 240 of the insulating pattern 200.

[0235] The insulating layer 100 may be formed by forming an insulating material layer to cover the first portion 210 , the second preliminary portion 220P, the third portion 230 , and the fourth portion 240 of the insulating pattern 200 , and then performing a chemical mechanical polishing (CMP) process to planarize an upper surface of the insulating material layer, but is not limited thereto.

[0236] like Fig.23As shown, first, the insulating layer 100 may be patterned to form a first via hole TH1 exposing at least a portion of the second preliminary portion 220P. A side surface of the first via hole TH1 may be formed of, for example, the insulating layer 100. A bottom surface of the first via hole TH1 may be formed of, for example, the insulating layer 100 and the second preliminary portion 220P.

[0237] According to some embodiments, the width of each first via hole TH1 in the first direction D1 may be greater than the width of each dummy source / drain pattern 160 in the first direction D1. Therefore, even if there is an error in aligning the first via hole TH1 and the second preliminary portion 220P along the third direction D3, the second preliminary portion 220P may be exposed.

[0238] Subsequently, the exposed second preliminary portion 220P may be removed by performing an etching process, thereby forming the second portion 220. The etching process may be performed by a wet or dry etching method, but is not limited thereto. In this case, the second portion 220 may include a material having an etching selectivity to the insulating layer 100. Thus, the dummy pattern 161 may be exposed.

[0239] In this case, the upper surface of the second portion 220 may be positioned closer to the upper surface of the carrier substrate 500 than the upper surface of the third portion 230. The height of the second portion in the third direction D3 may be smaller than the height of the third portion 230 in the third direction D3.

[0240] like Fig.24 As shown, the exposed dummy pattern 161 may be removed by performing an etching process, thereby forming the second via hole TH2.

[0241] For example, the etching process may be performed by a dry etching method, but is not limited thereto. In this case, the dummy pattern 161 may include a material having an etching selectivity to the insulating layer 100. The dummy pattern 161 may include a material having an etching selectivity to the insulating pattern 200. The dummy pattern 161 may include a material having an etching selectivity to the second source / drain pattern 152.

[0242] As the dummy pattern 161 is removed, the inner wall of the second portion 220 and the upper surface of the source / drain pattern 150 may be exposed. Since the second portion 220 covers at least a portion of the side surface of the source / drain pattern 150, even when the dummy pattern 161 is removed, the lower pattern BP and / or the sub-gate structure S_GS may not be exposed.

[0243] like Fig.25 As shown, the first and second via holes TH1 and TH2 may be filled, whereby the via member 300 may be formed so as to be electrically coupled to the source / drain pattern 150 .

[0244] In the region where the dummy pattern 161 has been removed, the first via portion 310 may be formed, and the first via hole TH1 may be filled, so that the second via portion 320 is formed to be electrically coupled with the first via portion 310. The via 300 may cover the source / drain pattern 150, and the first and second via holes TH1 and TH2 may be filled with the via 300.

[0245] The through-hole member 300 may be formed by forming a preliminary conductive layer filling the first via hole TH1 and the second via hole TH2 and covering the inner wall of the first via hole TH1, the inner surface of the second via hole TH2, the bottom surface of the second via hole TH2, and at least a portion of the second surface 100b of the insulating layer 100; and removing a portion of the preliminary conductive layer covering at least a portion of the second surface 100b of the insulating layer 100. The preliminary conductive layer may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a conductive metal carbonitride.

[0246] like Fig.26 As shown, a lower wiring structure 410 is formed on the second surface 100 b of the insulating layer 100 so as to be electrically coupled to the via member 300 .

[0247] The lower wiring structure 410 may include a lower wiring 411 and a lower wiring insulating layer 412 . The lower wiring 411 may be located on the second surface 100 b of the insulating layer 100 . The lower wiring 411 may include a metal (eg, copper). The lower wiring 411 may be electrically coupled to the via 300 .

[0248] The lower wiring insulating layer 412 may be located on the second surface 100b of the insulating layer 100. The lower wiring insulating layer 412 may cover the lower wiring structure 410. In other words, the lower wiring insulating layer 412 may cover the lower wiring 411, and the lower wiring 411 may be disposed in the lower wiring insulating layer 412. The lower wiring insulating layer 412 may include, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON) or at least one of a low dielectric constant material.

[0249] like Fig. 27 As shown, after removing the carrier substrate 500 of the semiconductor device according to some embodiments, the semiconductor device may be flipped over, thereby forming Figures 1 to 4 semiconductor devices in.

[0250] In the semiconductor device according to some embodiments, after the insulating pattern 200 is formed on the dummy pattern 161, at least a portion of the insulating pattern 200 may be etched to expose the dummy pattern 161, the exposed dummy pattern 161 may be removed, and the via member 300 may be formed in the space formed by the removal. In other words, the via member 300 may be formed in the space surrounded by the insulating pattern 200. Therefore, during the process of removing the dummy pattern 161, the surrounding material layers (e.g., the insulating layer 100, the lower pattern BP, and / or the sub-gate structure S_GS) adjacent to the via member 300 may be prevented from being etched, and a short circuit problem between the via member 300 and the sub-gate electrode 120S may be prevented. Therefore, the reliability of the semiconductor device may be improved.

[0251] Furthermore, in the semiconductor device according to some embodiments, the first via hole TH1 may be formed to expose the second portion 220 of the insulating pattern 200 surrounding the dummy source / drain pattern 160. Therefore, even if a length distribution of the dummy source / drain pattern 160 occurs in the third direction D3, the second portion 220 may be exposed through the first via hole TH1, and the through-hole member 300 may be formed so as to be coupled to the source / drain pattern 150. Therefore, the reliability of the semiconductor device may be improved.

[0252] Furthermore, in the semiconductor device according to some embodiments, the first portion 210 of the insulating pattern 200 may be located between the insulating layer 100 and the lower pattern BP, and the second portion 220 of the insulating pattern 200 may cover at least a portion of the side surface of the via member 300 and the side surface of the source / drain pattern 150. Therefore, even when the via member 300 is formed in the space formed by removing the dummy pattern 161, the lower pattern BP and the via member 300 and / or the sub-gate structure S_GS and the via member 300 may be electrically insulated from each other by the first portion 210 and the second portion 220 of the insulating pattern 200. Therefore, the reliability of the semiconductor device may be improved.

[0253] Each of the embodiments provided in the above description is not exclusive of being associated with one or more features of another example or another embodiment that is also provided herein or not provided herein but is consistent with the present invention.

[0254] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: An insulating layer comprising: a first surface; a second surface; and Component isolation trench; An insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; A lower wiring structure is disposed on the second surface of the insulating layer; and a via member extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, Wherein, the insulating pattern comprises: A first portion between the insulating layer and the active pattern; a second portion surrounding at least a portion of the through-hole member; and A third portion is on the bottom surface of the element isolation trench.

2. The semiconductor device according to claim 1, wherein The third portion of the insulating pattern is on the inner wall of the element isolation trench, and Wherein, a length of the second portion of the insulating pattern in a thickness direction of the insulating layer is smaller than a length of the third portion of the insulating pattern in the thickness direction of the insulating layer.

3. The semiconductor device according to claim 2, wherein: A lower surface of the first portion of the insulating pattern is farther away from the second surface of the insulating layer than a lower surface of the source / drain pattern.

4. The semiconductor device according to claim 1, wherein The second portion of the insulating pattern contacts at least a portion of a side surface of the source / drain pattern.

5. The semiconductor device according to claim 1, wherein The through-hole member comprises: a first via portion at least partially surrounded by the second portion of the insulation pattern; and A second via portion is between the first via portion and the lower wiring structure.

6. The semiconductor device according to claim 5, wherein: The second via portion has a width greater than a width of the first via portion.

7. The semiconductor device according to claim 5, wherein: At least a portion of the second portion of the insulation pattern extends over the second via portion in a direction parallel to the second surface of the insulation layer, and Wherein, at least another portion of the second portion of the insulation pattern does not extend over the second via portion in the direction parallel to the second surface of the insulation layer.

8. The semiconductor device according to claim 1, further comprising: a gate structure on the insulating pattern and at least partially surrounding the channel pattern, The active pattern further includes a lower pattern between the first portion of the insulating pattern and the gate structure.

9. The semiconductor device according to claim 8, further comprising: a dummy source / drain pattern below the source / drain pattern, The insulating pattern further includes a fourth portion at least partially surrounding the dummy source / drain pattern.

10. The semiconductor device according to claim 9, wherein An upper surface of the dummy source / drain pattern is closer to the second surface of the insulating layer than a lower surface of the gate structure.

11. The semiconductor device according to claim 1, further comprising: a gate structure on the insulating pattern and at least partially surrounding the channel pattern, Wherein, the first portion of the insulating pattern contacts the gate structure.

12. The semiconductor device according to claim 1, wherein The insulating pattern includes a material having an etching selectivity to the insulating layer.

13. The semiconductor device according to claim 12, wherein: The insulating pattern includes at least one of SiN, SiON, SiCN, SiOC, SiOCN, and metal oxide.

14. The semiconductor device according to claim 1, wherein The insulating pattern further comprises: an outer insulating pattern contacting the insulating layer; and an inner insulating pattern on the outer insulating pattern, and Wherein, the inner insulating pattern includes at least one of SiN, SiON, SiCN, SiOC, SiOCN, AlN and Al2O3.

15. A semiconductor device comprising: an insulating layer comprising a first surface and a second surface; An insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a dummy source / drain pattern extending in at least a portion of the insulating pattern and located below the source / drain pattern; a lower wiring structure below the second surface of the insulating layer; as well as a via member extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, Wherein, the insulating pattern comprises: A first portion between the insulating layer and the active pattern; a second portion surrounding at least a portion of the through-hole member; and A fourth portion at least partially surrounds the dummy source / drain pattern.

16. The semiconductor device according to claim 15, wherein: A length of the fourth portion of the insulation pattern in a thickness direction of the insulation layer is greater than a length of the second portion of the insulation pattern in the thickness direction of the insulation layer.

17. The semiconductor device according to claim 15, wherein: The second portion of the insulating pattern contacts at least a portion of a side surface of the source / drain pattern.

18. The semiconductor device according to claim 15, wherein A lower surface of the first portion of the insulating pattern is farther away from the second surface of the insulating layer than a lower surface of the source / drain pattern.

19. A semiconductor device comprising: An insulating layer comprising: a first surface; a second surface; and Component isolation trench; An insulating pattern on the first surface of the insulating layer; an active pattern on the insulating pattern and including a channel pattern; a source / drain pattern on at least one side of the active pattern; a dummy source / drain pattern extending in at least a portion of the insulating pattern and located below the source / drain pattern; a gate electrode on the insulating pattern and at least partially surrounding the channel pattern; a lower wiring structure below the second surface of the insulating layer; and a via member extending in the insulating layer and connecting the source / drain pattern and the lower wiring structure, Wherein, the insulating pattern comprises: A first portion, which is between the insulating layer and the gate electrode; a second portion surrounding at least a portion of the through-hole member; a third portion on the inner wall and bottom surface of the element isolation trench; and a fourth portion at least partially surrounding the dummy source / drain pattern, and Wherein, the through-hole member comprises: a first via portion at least partially surrounded by the second portion of the insulation pattern; and A second via portion is between the first via portion and the lower wiring structure.

20. The semiconductor device according to claim 19, wherein A length of the second portion of the insulation pattern in a thickness direction of the insulation layer is smaller than a length of the third portion of the insulation pattern in the thickness direction of the insulation layer.

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