Back contact cell and photovoltaic module

Abstract

The present invention discloses a back-contact cell and a photovoltaic module, which relate to the field of photovoltaic technology, in order to improve the manufacturing efficiency of back-contact cells, increase the manufacturing capacity of back-contact cells, and reduce the risk of battery leakage. The back-contact cell includes: a semiconductor substrate, a first doped silicon layer, and a second doped silicon layer. The semiconductor substrate includes a first surface and a second surface opposite to each other. The first surface has a first region and a second region spaced apart, and a spacer region between the first region and the second region. The area of ​​the first region in the first surface accounts for greater than or equal to 50% and less than or equal to 60%. The first doped silicon layer is arranged on the first region. The material of the first doped silicon layer includes polycrystalline silicon and / or monocrystalline silicon. The second doped silicon layer is arranged on the second region. The conductivity type of the second doped silicon layer is opposite to the conductivity type of the first doped silicon layer. The extinction coefficient corresponding to the first doped silicon layer is greater than the extinction coefficient corresponding to the second doped silicon layer.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back-contact cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electricity. A solar cell with both the positive and negative electrodes on the back of the cell is called a back-contact cell. Compared to a double-sided contact solar cell, the front of the back-contact cell is free of metal electrodes, allowing the light-facing side of the back-contact cell to utilize more light. Consequently, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological advancements in achieving high-efficiency crystalline silicon cells.

[0003] However, the manufacturing efficiency of existing back-contact batteries is low, which is not conducive to improving the production capacity of back-contact batteries. Summary of the Invention

[0004] The object of the present invention is to provide a back-contact cell and a photovoltaic module for improving the manufacturing efficiency of the back-contact cell, increasing the manufacturing capacity of the back-contact cell, and reducing the risk of battery leakage.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back-contact battery, comprising: a semiconductor substrate, a first doped silicon layer, and a second doped silicon layer. The semiconductor substrate comprises a first surface and a second surface opposite to each other. The first surface comprises a first region and a second region spaced apart, and a spacer region between the first region and the second region. The area of ​​the first region in the first surface accounts for greater than or equal to 50% and less than or equal to 60%. The first doped silicon layer is disposed on the first region. The material of the first doped silicon layer comprises polycrystalline silicon and / or single crystal silicon. The second doped silicon layer is disposed on the second region. The conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer. The extinction coefficient corresponding to the first doped silicon layer is greater than the extinction coefficient corresponding to the second doped silicon layer.

[0006] When the above technical solution is adopted, in the back-contact cell provided by the present invention, a first doped silicon layer is disposed on a first region of the first surface, and a second doped silicon layer is disposed on a second region of the first surface, and the first doped silicon layer and the second doped silicon layer have opposite conductivity types. Based on this, when the back-contact cell is in operation, electron and hole pairs generated by the semiconductor substrate after absorbing photons are separated by the shunting action of the first doped silicon layer located on the first region and the second doped silicon layer located on the second region, with one of the electrons and holes being collected and conducted away by the first doped silicon layer located on the first region, and the other of the electrons and holes being collected and conducted away by the second doped silicon layer located on the second region, thereby forming a photocurrent.

[0007] Compared with amorphous silicon materials, firstly, polycrystalline silicon and single crystal silicon materials have higher conductivity and a higher degree of crystallization. Therefore, when the material of the above-mentioned first doped silicon layer includes polycrystalline silicon and / or single crystal silicon, the conductivity and field passivation effect of the first doped silicon layer can be improved, which is beneficial to improving the conversion efficiency of the back contact battery. Secondly, when the material of the above-mentioned first doped silicon layer includes polycrystalline silicon and / or single crystal silicon, in the actual process of manufacturing the first doped silicon layer, the process temperature corresponding to the first doped silicon layer is relatively high. After the intrinsic silicon layer used to manufacture the first doped silicon layer is doped using a doping process such as diffusion, it is easy to form a doped silicon glass layer on the first doped silicon layer. Based on this, after the doped silicon glass layer is patterned, it can be used as a mask layer in the subsequent process of selectively etching the entire first doped silicon layer to play a protective role; and there is no need to use additional deposition to form other mask layers, which is beneficial to improving the manufacturing efficiency of the back contact battery. In the above process, because the extinction coefficient corresponding to the first doped silicon layer is greater than the extinction coefficient corresponding to the second doped silicon layer, the first doped silicon layer is relatively denser than the second doped silicon layer. Accordingly, etching the portion of the first doped silicon layer located at least on the second region is more difficult. Secondly, the doped silicon glass layer formed by oxidizing a portion of the first doped silicon layer is also relatively dense. Therefore, before performing selective etching, it is usually necessary to selectively treat the denser doped silicon glass layer using a process such as laser engraving. It is necessary to completely remove at least the portion of the doped silicon glass layer corresponding to the second region. This facilitates the subsequent complete removal of at least the second region of the first doped silicon layer and the retention of at least the portion of the first doped silicon layer corresponding to the first region under the protection of the untreated portion of the doped silicon glass layer. This prevents the portion of the denser first doped silicon layer located on the second region from being incompletely removed due to the influence of the doped silicon glass layer residue due to the presence of residues in the doped silicon glass layer, thereby reducing the risk of leakage. As can be seen from the above, the range of the first region on the first surface determines the range of formation of the first doped silicon layer, which in turn affects the range of selective processing of the entire first doped silicon layer and the entire doped silicon glass layer. Based on this, when the first region on which the first doped silicon layer is provided accounts for an area greater than or equal to 50% and less than or equal to 60% of the area on the first surface, the area of ​​the first doped silicon layer on one side of the first surface in the back contact cell also accounts for a larger area. Accordingly, when the entire doped silicon glass layer is selectively processed by processes such as laser engraving, and when the first doped silicon layer is selectively etched by processes such as wet etching, only the doped silicon glass layer and the first doped silicon layer on the remaining smaller areas of the first surface other than the first region need to be removed, thereby shortening the processing time of the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact cell, reducing production costs, increasing the manufacturing capacity of the back contact cell, and reducing the leakage risk of the second region.Furthermore, since the extinction coefficient of the second doped silicon layer is smaller than that of the first doped silicon layer, its density is also relatively small. Therefore, even if the second region on which the second doped silicon layer is arranged accounts for a relatively small area of ​​the first surface, resulting in a large amount of etching when the entire second doped silicon layer is selectively etched, the etching difficulty of the second doped silicon layer is relatively low, so a higher manufacturing efficiency of the back contact battery can be guaranteed.

[0008] In addition, the area ratio of the first region on the first surface satisfies the above range, and while improving the manufacturing capacity of the back-contact battery, it is also possible to control the area ratio of the first doped silicon layer and the second doped silicon layer on one side of the first surface, thereby regulating the area ratio of the PN junction region, achieving effective diversion of carriers, and achieving a balance between the manufacturing capacity of the back-contact battery and the effective collection of carriers, which is conducive to reducing costs and increasing efficiency.

[0009] As a possible implementation scheme, the area ratio of the second region in the first surface is greater than or equal to 20% and less than or equal to 35%, and the area ratio of the spacing region in the first surface is greater than or equal to 10% and less than or equal to 20%. In this case, the first region, the second region and the spacing region are all located on the first surface. When the area ratio of the second region and the spacing region is within the above range, it can ensure that the first region has a larger proportion on one side of the first surface, shortening the processing time of the denser doped silicon glass layer and the first doped silicon layer, while reducing the risk of leakage. In addition, the area ratio of the PN region can also be adjusted to achieve effective shunting of carriers, further reducing the risk of leakage.

[0010] As a possible implementation solution, the first doped silicon layer includes a P-type doped polysilicon layer, and the extinction coefficient of the P-type doped polysilicon layer is greater than or equal to 0.01 and less than or equal to 1.5.

[0011] In the case of adopting the above technical solution, when the first doped silicon layer includes a P-type doped silicon layer, after the first doped silicon layer is formed, a doped silicon glass layer formed on the side of the first doped silicon layer away from the semiconductor substrate is doped with P-type impurities such as boron. Because the electron affinity of P-type impurities such as boron is lower than that of N-type impurities such as phosphorus, P-type impurities such as boron are less likely to accept electrons. Furthermore, the doped silicon glass layer and the first doped silicon layer doped with P-type impurities such as boron are less likely to react with alkaline wet etching solutions, and the etching difficulty of the two is greater. Based on this, when the first doped silicon layer includes a P-type doped polysilicon layer, in the back contact battery provided by the present invention, the processing time of the P-type doped polysilicon layer and the borosilicate glass layer can be shortened by increasing the area ratio of the P-type doped polysilicon layer on the side of the first surface, thereby improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. In addition, when the extinction coefficient of the P-type doped polysilicon layer is within the above-mentioned range, it can prevent the occurrence of problems such as the electrode burning through the P-type doped polysilicon layer due to the low density of the P-type doped polysilicon layer due to the extinction coefficient of the P-type doped polysilicon layer being too small, thereby ensuring that the back contact battery has good working performance. In addition, it can also prevent the difficulty of selective etching of the P-type doped polysilicon layer and the doped silicon glass layer due to the high density of the P-type doped polysilicon layer due to the extinction coefficient of the P-type doped polysilicon layer being too large, further shortening the processing time of the doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. In addition, because the extinction coefficient of the P-type doped polysilicon layer is also related to its own doping concentration, when the extinction coefficient of the P-type doped polysilicon layer is within the above-mentioned range, the P-type doped polysilicon layer can also have a higher doping concentration, which is beneficial to improving the field passivation effect of the P-type doped polysilicon layer and reducing the contact resistance between the P-type doped polysilicon layer and the corresponding conductive material.

[0012] As a possible implementation solution, the second doped silicon layer includes an N-type doped polysilicon layer, and the extinction coefficient of the N-type doped polysilicon layer is greater than or equal to 0.01 and less than or equal to 1.5.

[0013] When the above technical solution is adopted, the extinction coefficient and density of the N-type doped polysilicon layer are relatively small compared to the P-type doped polysilicon layer. When the second doped silicon layer includes an N-type doped polysilicon layer, even if the second region on which the N-type doped polysilicon layer is disposed accounts for a relatively small area of ​​the first surface, resulting in a large amount of etching when the entire N-type doped polysilicon layer and the phosphosilicate glass layer are selectively etched, the etching difficulty of the N-type doped polysilicon layer and the phosphosilicate glass layer is relatively low, thereby ensuring a high manufacturing efficiency of the back-contact cell. The application principle of the beneficial effect of the extinction coefficient of the N-type doped polysilicon layer being greater than or equal to 0.01 and less than or equal to 1.5 is similar to the application principle of the beneficial effect of the extinction coefficient of the P-type doped polysilicon layer being greater than or equal to 0.01 and less than or equal to 1.5, and will not be repeated here.

[0014] As a possible implementation solution, the degree of crystallization of the second doped silicon layer is greater than that of the first doped silicon layer.

[0015] When the above technical solution is adopted, the density of the film of the doped silicon layer is related to its own degree of crystallization. Specifically, within a certain range, increasing the degree of crystallization of the doped silicon layer is conducive to improving the density of the doped silicon layer; on the contrary, reducing the degree of crystallization of the doped silicon layer is conducive to reducing the density of the doped silicon layer. In the above case, when the degree of crystallization of the second doped silicon layer is greater than that of the first doped silicon layer, the density of the film of the second doped silicon layer and the first doped silicon layer can be regulated by adjusting the degree of crystallization of the film layer, thereby regulating the density of the doped silicon glass layer formed by oxidizing part of the first doped silicon layer, reducing the difficulty of selective etching of the first doped silicon layer and the doped silicon glass layer, further shortening the processing time of the doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery.

[0016] As a possible implementation solution, the sum of the areas of the first region and the spacing region is S1, the sum of the areas of the second region and the spacing region is S2, and the ratio between S1 and S2 is greater than 1 and less than 2.

[0017] When the above technical solution is adopted, the ratio of the areas of S1 and S2 is within the above range, which helps prevent the second doped silicon layer arranged on the second region from occupying too large an area on the first surface due to the small ratio, ensuring that the PN junction has a larger junction area, which is conducive to achieving effective separation of carriers. In addition, it can also prevent the first doped silicon layer arranged on the first region from occupying too large an area on the first surface due to the large ratio, prevent the lateral transmission distance of carriers from being too long, and ensure that the second doped silicon layer has a higher carrier collection efficiency. At the same time, the size of the ratio will also affect the area ratio of the first doped silicon layer with a denser film layer and the second doped silicon layer with a relatively loose film layer on the side of the first surface, thereby affecting the etching capacity of the first doped silicon layer and the second doped silicon layer for selective etching, reducing the difference in the capacity of the two selective etchings, and eliminating the capacity bottleneck. Therefore, when the ratio is within the above range, it is also beneficial for the back contact battery to have both high conversion efficiency and manufacturing capacity, which is conducive to reducing costs and increasing efficiency.

[0018] As a possible implementation solution, the sum of the widths of the first region and the spacing region is W1, the sum of the widths of the second region and the spacing region is W2, and the ratio between W1 and W2 is greater than 1 and less than 2. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the ratio between S1 and S2 being greater than 1 and less than 2 described above, and will not be repeated here.

[0019] As a possible implementation scheme, the sum of the widths of a first region and a spacer region is W3, the sum of the widths of a second region and a spacer region is W4, and the ratio between W3 and W4 is greater than the ratio between S1 and S2. In this case, relative to the ratio between W3 and W4 being equal to the ratio between S1 and S2, when the ratio between W3 and W4 is greater than the ratio between S1 and S2, the ratio between W3 and W4 is relatively large, and / or the ratio between S1 and S2 is relatively small, thereby ensuring that the first doped silicon layer has a higher area ratio on one side of the first surface, further shortening the processing time of the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact cell, reducing production costs, and increasing the manufacturing capacity of the back contact cell.

[0020] As a possible implementation solution, the aspect ratio of the first doped silicon layer located on the first region is greater than the aspect ratio of the second doped silicon layer located on the second region. In this case, it is beneficial to increase the width of the first doped silicon layer located on the first region, increase the area ratio of the first doped silicon layer on the side of the first surface, further shorten the processing time of the denser doped silicon glass layer and the first doped silicon layer, improve the manufacturing efficiency of the back contact battery, reduce production costs, and increase the manufacturing capacity of the back contact battery. At the same time, if the first doped silicon layer is located at the emitter of the battery, it can also increase the area of ​​the PN junction region, which is beneficial to achieve effective separation of carriers, reduce the carrier recombination rate, and improve the conversion efficiency of the back contact battery.

[0021] As a possible implementation, the back-contact cell further includes a plurality of first collecting electrodes disposed on the first doped silicon layer, each first collecting electrode being in ohmic contact with the first doped silicon layer. The plurality of first collecting electrodes extend along a first direction and are spaced apart along a second direction, the first direction being different from the second direction. A second doped silicon layer is further disposed above a portion of the first doped silicon layer in the first region, with the second doped silicon layer in the first region being spaced apart from the first doped silicon layer and the first collecting electrodes.

[0022] When employing the above technical solution, in the actual manufacturing process, the second doped silicon layer is selectively etched throughout the entire second doped silicon layer, so that the second doped silicon layer in the back-contact cell is located only on a localized region of the first surface. Prior to the selective etching, the mask material formed on the side of the second doped silicon layer facing away from the semiconductor substrate is selectively treated using a process such as laser engraving, so that the untreated portion of the mask material forms a mask layer for protecting the second doped silicon layer. The formation range of the second doped silicon layer determines the range of mask material treatment required. Therefore, when the second doped silicon layer is not only located on the second region but also over a portion of the first doped silicon layer located on the first region, engraving of the second doped silicon layer located over the portion of the first doped silicon layer is unnecessary. This reduces the processing time for the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back-contact cell, reducing production costs, and increasing the manufacturing capacity of the back-contact cell. Furthermore, the second doped silicon layer located in the first region is spaced apart from the first doped silicon layer and the first collector electrode, preventing short circuits, reducing the risk of leakage, and ensuring high electrical reliability for the back-contact cell.

[0023] As a possible implementation scheme, the above-mentioned back-contact battery also includes a plurality of second collecting electrodes arranged on the second doped silicon layer, and each second collecting electrode is in ohmic contact with the second doped silicon layer. The plurality of second collecting electrodes extend along the first direction, and the second collecting electrodes and the first collecting electrodes are alternately spaced along the second direction. Among the plurality of second collecting electrodes, at least some of the second collecting electrodes are discontinuous second collecting electrodes. The second doped silicon layer located in the first region is arranged at the break of the discontinuous second collecting electrode. Among the plurality of first collecting electrodes, at least some of the first collecting electrodes are discontinuous first collecting electrodes, and the second doped silicon layer located in the first region is symmetrically arranged relative to the midline of the collecting electrode segment included in the discontinuous first collecting electrode in the second direction.

[0024] In the above technical solution, the first and second collecting electrodes are used to collect and conduct carriers of corresponding conductivity types within the first and second doped silicon layers, respectively. The formation ranges of the first and second collecting electrodes are proportional to their respective carrier collection capabilities. Furthermore, the intra-string interconnect, such as a soldering ribbon, extends generally along the second direction and is electrically connected to the first collecting electrode. It is electrically insulated from the discontinuous second collecting electrode of opposite polarity by the break in the discontinuous second collecting electrode. Furthermore, the intra-string interconnect, such as the soldering ribbon, is electrically connected to the first doped silicon layer via the first collecting electrode and does not directly contact the first doped silicon layer. Therefore, when the second doped silicon layer located in the first region is disposed at the break in the discontinuous second collecting electrode, not only can the processing time for the mask material and the second doped silicon layer be shortened by retaining the second doped silicon layer located on a portion of the first doped silicon layer, thereby improving the manufacturing capacity of back-contact cells, but it also does not affect the formation range of the first collecting electrode for collecting and conducting carriers of corresponding conductivity types within the first doped silicon layer, ensuring that the first collecting electrode has a high carrier collection capability and reducing the carrier recombination rate. In addition, the second doped silicon layer located in the first region is symmetrically arranged with respect to the midline of the collecting electrode segment included in the discontinuous first collecting electrode in the second direction. At this time, the two ends of the second doped silicon layer located in the first region along the first direction have roughly the same leakage distances from the edge of the first doped silicon layer and the edge of the second doped silicon layer located in the second region, respectively. This prevents a higher leakage risk on one side due to positional offset of the second doped silicon layer located in the first region at the disconnection point, thereby ensuring that the back-contact battery has a higher conversion efficiency.

[0025] As a possible implementation, along the second direction, the first surface includes a central region and edge regions on either side of the central region. The first and second collector electrodes located in the central region are either continuous first or continuous second collector electrodes, respectively, while the first and second collector electrodes located in the edge regions are either discontinuous first or discontinuous second collector electrodes, respectively. Furthermore, the back-contact cell further includes a first interconnect structure and a first busbar segment. The first busbar segment is disposed in the edge region and extends along the second direction. The discontinuous first collector electrode is electrically connected to the first busbar segment, while the discontinuous second collector electrode is disconnected at its intersection with the first busbar segment. The first interconnect structure is disposed at one end of the first busbar segment near the central region and is electrically connected to the first busbar segment. The second doped silicon layer located in the first region includes a first sub-doping portion and a second sub-doping portion. The first sub-doping portion is disposed below the first busbar segment, and the second sub-doping portion is disposed at least below the first interconnect structure. Along the first direction, the width of the second sub-doping portion is greater than the width of the first sub-doping portion.

[0026] As a possible implementation scheme, the width of the first sub-doping portion is greater than or equal to 0.3 times the width of the portion of the first doped silicon layer corresponding to below the first sub-doping portion, and is smaller than the width of the portion of the first doped silicon layer corresponding to below the first sub-doping portion; and / or, the width of the second sub-doping portion is greater than the width of the first interconnect structure, and is smaller than or equal to 0.95 times the width of the portion of the first doped silicon layer corresponding to below the second sub-doping portion.

[0027] When the above technical solution is adopted, along the first direction, when the width of the second sub-doping portion and / or the first sub-doping portion is within the above range, the width extension range of the first sub-doping portion and / or the second sub-doping portion at the corresponding disconnection point is larger, which is conducive to further shortening the processing time of the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery.

[0028] As a possible implementation, the second sub-doping portion is further disposed below the side of the first busbar segment proximate to the first interconnect structure, and / or the width of the second sub-doping portion and the width of the first sub-doping portion gradually decrease along the direction from the first busbar segment away from the first interconnect structure. In this case, it can be understood that along the first direction, the width of the first interconnect structure is greater than the width of the first busbar segment. To reduce the risk of leakage, the disconnection spacing of the discontinuous second electrode whose extended line intersects the first busbar segment and is proximate to the first interconnect structure is greater than the disconnection spacing of the discontinuous second electrode whose extended line intersects the first busbar segment and is distal to the first interconnect structure. Based on this, when the second sub-doping portion with a larger width is also disposed below the side of the first busbar segment proximate to the first interconnect structure, or when the width of the second sub-doping portion and the width of the first sub-doping portion gradually decrease along the direction from the first busbar segment away from the first interconnect structure, the larger disconnection spacing can be further utilized to further expand the arrangement range of the second doped silicon layer on the first region while preventing leakage, shorten the processing time of the denser doped silicon glass layer and the first doped silicon layer, and improve the manufacturing efficiency of the back-contact cell.

[0029] As a possible implementation solution, the back contact cell further includes an interconnection electrically connected to the first interconnection structure, and the width of the first sub-doped portion is greater than the width of the interconnection and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the first sub-doped portion. times; and / or, the width of the second sub-doped portion is greater than the width of the first interconnect structure and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the second sub-doped portion. times. In this case, the width of the first sub-doping portion and / or the second sub-doping portion is selected within the above corresponding ranges, which can not only maximize the use of the dead space at the collector electrode disconnection position and fully improve the manufacturing capacity of the back-contact battery, but also avoid the risk of leakage caused by the connection of the oppositely doped regions due to the excessive width of the first sub-doping portion and / or the second sub-doping portion, thereby improving the electrical reliability of the back-contact battery.

[0030] As a possible implementation scheme, along the second direction, the ratio of the sum of the lengths of all second sub-doping portions to the sum of the lengths of all first sub-doping portions is greater than or equal to 2:1 and less than or equal to 5:1. In this case, the length extension range of the first sub-doping portion and the second sub-doping portion at the corresponding disconnection point is relatively large, which is conducive to further shortening the processing time of the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back-contact battery, reducing production costs, and increasing the manufacturing capacity of the back-contact battery. In addition, it can also prevent the first sub-doping portion and the second sub-doping portion from being too large due to the first collecting electrode being too small, reducing the risk of leakage, and improving the electrical reliability of the back-contact battery.

[0031] In a second aspect, the present invention provides a photovoltaic module, which includes the back-contact cell provided by the first aspect and various implementations thereof.

[0032] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0034] Figure 1 A longitudinal cross-sectional view of the back contact battery structure provided by an embodiment of the present invention Figure 1 ;

[0035] Figure 2 A longitudinal cross-sectional view of the back contact battery structure provided by an embodiment of the present invention Figure 2 ;

[0036] Figure 3 A longitudinal cross-sectional view of the back contact battery provided in an embodiment of the present invention Figure 3 ;

[0037] Figure 4 A longitudinal cross-sectional view of the back contact battery structure provided by an embodiment of the present invention Figure 4 ;

[0038] Figure 5 A longitudinal cross-sectional view of the back contact battery provided in an embodiment of the present invention Figure 5 ;

[0039] Figure 6 A longitudinal cross-sectional view of the back contact battery structure provided by an embodiment of the present invention Figure 6 ;

[0040] Figure 7 Schematic diagram of the structural distribution relationship of the back contact battery on the first side provided by an embodiment of the present invention Figure 1 ;

[0041] Figure 8 Schematic diagram of the structural distribution relationship of the back contact battery on the first side provided by an embodiment of the present invention Figure 2 .

[0042] Figure numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is a spacing region, 15 is a first doped silicon layer, 16 is a second doped silicon layer, 17 is a first collecting electrode, 18 is a second collecting electrode, 19 is a first interconnection structure, 20 is a first bus electrode segment, 21 is a first sub-doped portion, 22 is a second sub-doped portion, 23 is an insulating layer, 24 is a first interface passivation layer, and 25 is a second interface passivation layer. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0044] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0045] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0047] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0048] A solar cell is a device that converts sunlight into electricity. A solar cell with both the positive and negative electrodes on the back of the cell is called a back-contact cell. Compared to a double-sided contact solar cell, the front of the back-contact cell is free of metal electrodes, allowing the light-facing side of the back-contact cell to utilize more light. Consequently, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological advancements in achieving high-efficiency crystalline silicon cells.

[0049] Among them, the existing back-contact battery generally includes a semiconductor substrate, a first doped silicon layer and a second doped silicon layer. The semiconductor substrate has a first surface and a second surface relative to each other. The first doped silicon layer and the second doped silicon layer are alternately distributed on one side of the first surface of the semiconductor substrate. In addition, the first doped silicon layer and the second doped silicon layer have opposite conductivity types, so as to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. The material of the first doped silicon layer includes polycrystalline silicon and / or single crystal silicon to improve the conductive properties and field passivation effect of the first doped silicon layer, which is conducive to improving the conversion efficiency of the back-contact battery. However, the manufacturing efficiency of the existing back-contact battery is low, which is not conducive to improving the production capacity of the back-contact battery.

[0050] Specifically, in the actual manufacturing process, in the process of forming the first doped silicon layer on a partial area of ​​the first surface of the semiconductor substrate, a whole layer of intrinsic silicon layer will be formed first, and the intrinsic silicon layer will be doped by diffusion and other processes to form a first doped silicon layer. At the same time, a doped silicon glass layer will also be formed on the side of the first doped silicon layer away from the semiconductor substrate. Then, it is necessary to completely remove at least the portion of the first doped silicon layer corresponding to the area where the second doped silicon layer is to be formed. Among them, in the existing manufacturing methods, a mask combined with wet etching method or a laser engraving combined with wet etching method is usually used to achieve the above-mentioned selective etching. The above-mentioned mask combined with wet etching method is to print a mask glue in the area that needs to be protected. When wet etching is performed, the area under the mask glue will be protected and retained, while the non-mask glue area will be etched by the chemical solution. The above-mentioned laser engraving combined with wet etching method is to use a laser to engrave the doped silicon glass layer formed on the first doped silicon layer according to the pattern. After wet etching, the area of ​​the first doped silicon layer corresponding to the laser engraving will be etched by the chemical solution, while the area of ​​the doped silicon glass layer that is not laser engraved has a higher density and can protect the first doped silicon layer underneath itself from the influence of the chemical solution, thereby forming a first doped silicon layer arranged on a local area on the back side of the battery.

[0051] Specifically, compared with the laser engraving combined with wet etching method, the mask-integrated wet etching method has a higher manufacturing efficiency. However, the mask-integrated wet etching method is limited by factors such as the composition of the mask glue and the stability of screen printing, and is currently not mass-produced. In the above-mentioned laser engraving combined with wet etching method, the laser engraving process benefits from the stability of the laser, making it a solution that can be mass-produced. However, when the density of the first doped silicon layer is high, the density of the doped silicon glass layer formed thereon is also relatively high. It is necessary to use a laser to completely ablate the doped silicon glass layer on the portion of the first doped silicon layer to be removed, so that the next step of wet etching will result in the complete removal of the exposed first doped silicon layer. At the same time, the laser used in the laser that can be applied to back-contact batteries is expensive, and the laser engraving pattern when manufacturing back-contact batteries is relatively complex. The corresponding engraving time for a single cell is long, resulting in low manufacturing efficiency of the back-contact battery and increased production costs, which is not conducive to improving the production capacity of the back-contact battery.

[0052] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back contact battery. Figure 1As shown, the back-contact cell includes: a semiconductor substrate 11, a first doped silicon layer 15, and a second doped silicon layer 16. The semiconductor substrate 11 includes a first surface and a second surface opposite to each other. The first surface has a first region 12 and a second region 13 spaced apart, and a spacer region 14 located between the first region 12 and the second region 13. The area of ​​the first region 12 in the first surface accounts for greater than or equal to 50% and less than or equal to 60%. The first doped silicon layer 15 is disposed on the first region 12. The material of the first doped silicon layer 15 includes polycrystalline silicon and / or single crystal silicon. The second doped silicon layer 16 is disposed on the second region 13. The conductivity type of the second doped silicon layer 16 is opposite to that of the first doped silicon layer 15. The extinction coefficient corresponding to the first doped silicon layer 15 is greater than the extinction coefficient corresponding to the second doped silicon layer 16.

[0053] It should be noted that, in actual application, the extinction coefficients of the first doped silicon layer and the second doped silicon layer can be measured and obtained by testing instruments such as ellipsometers. In the process of testing the extinction coefficient k of the first doped silicon layer and the second doped silicon layer, it is necessary to remove other film layers (such as doped silicon glass layer and / or surface passivation layer, etc.) located on the side of the first doped silicon layer away from the semiconductor substrate and the side of the second doped silicon layer away from the semiconductor substrate; and it is also necessary to measure under the same test conditions, especially different film layers that need to be compared in data need to be measured under the same test conditions to improve the accuracy of the measurement results and the accuracy of the comparison results. The specific test conditions can be: the test band is 220nm to 1000nm, for example: the test wavelength corresponding to the data range of the extinction coefficient of the first doped silicon layer and the second doped silicon layer is 632nm. The test position can be the position where the first doped silicon layer and the second doped silicon layer are set in the interconnection structure (such as the welding point).

[0054] When the above technical solution is adopted, Figure 1As shown, in the back-contact cell provided by an embodiment of the present invention, a first doped silicon layer 15 is disposed on a first region 12 of the first surface, and a second doped silicon layer 16 is disposed on a second region 13 of the first surface, and the first doped silicon layer 15 and the second doped silicon layer 16 have opposite conductivity types. Based on this, when the back-contact cell is in operation, electron and hole pairs generated by the semiconductor substrate 11 after absorbing photons are separated by the shunting action of the first doped silicon layer 15 located on the first region 12 and the second doped silicon layer 16 located on the second region 13, and one of the electrons and holes is collected and conducted away by the first doped silicon layer 15 located on the first region 12; the other electron and hole is collected and conducted away by the second doped silicon layer 16 located on the second region 13, forming a photocurrent. In addition, compared to amorphous silicon materials, polycrystalline silicon and single-crystalline silicon materials have higher conductivity and a higher degree of crystallization. Therefore, when the material of the first doped silicon layer 15 includes polycrystalline silicon and / or single-crystalline silicon, the conductivity and field passivation effect of the first doped silicon layer 15 can be improved, which is beneficial to improving the conversion efficiency of the back-contact cell. Secondly, when the material of the first doped silicon layer 15 includes polycrystalline silicon and / or single-crystalline silicon, during the actual manufacturing process of the first doped silicon layer 15, the corresponding process temperature of the first doped silicon layer 15 is relatively high. After the intrinsic silicon layer used to manufacture the first doped silicon layer 15 is doped using a doping process such as diffusion, it is easy to form a doped silicon glass layer on the first doped silicon layer 15. Based on this, after patterning, the doped silicon glass layer can serve as a mask layer in the subsequent selective etching process of the entire first doped silicon layer 15, playing a protective role. Moreover, there is no need to use additional deposition to form other mask layers, which is beneficial to improving the manufacturing efficiency of the back-contact cell. In the above process, since the extinction coefficient corresponding to the first doped silicon layer 15 is greater than the extinction coefficient corresponding to the second doped silicon layer 16, the first doped silicon layer 15 is relatively denser than the second doped silicon layer 16, and accordingly, etching the first doped silicon layer 15 at least on the second region 13 is more difficult. Secondly, the density of the doped silicon glass layer formed by oxidizing part of the first doped silicon layer 15 is also relatively large. Therefore, before selective etching, it is usually necessary to selectively process the denser doped silicon glass layer by laser engraving or other processes. , it is necessary to completely remove at least the portion of the doped silicon glass layer corresponding to the second region 13, thereby facilitating the subsequent complete removal of at least the second region 13 of the first doped silicon layer 15 under the protection of the untreated portion of the doped silicon glass layer, and retaining at least the portion of the first doped silicon layer 15 corresponding to the first region 12, thereby preventing the portion of the first doped silicon layer 15 with higher density located on the second region 13 from not being completely removed due to the influence of the doped silicon glass layer residue due to the presence of residues in the doped silicon glass layer, thereby reducing the risk of leakage.Furthermore, as can be seen from the above, the extent of the first region 12 on the first surface determines the formation range of the first doped silicon layer 15, thereby affecting the range of selective processing of the entire first doped silicon layer 15 and the entire doped silicon glass layer. Based on this, when the first region 12 on which the first doped silicon layer 15 is disposed accounts for greater than or equal to 50% and less than or equal to 60% of the area of ​​the first surface, the first doped silicon layer 15 in the back-contact cell also accounts for a larger area on one side of the first surface. Accordingly, when selectively processing the entire doped silicon glass layer by processes such as laser engraving, or selectively etching the first doped silicon layer 15 by processes such as wet etching, only the doped silicon glass layer and the first doped silicon layer 15 on the smaller area of ​​the first surface other than the first region 12 need to be removed. This shortens the processing time for the denser doped silicon glass layer and the first doped silicon layer 15, improves the manufacturing efficiency of the back-contact cell, reduces production costs, increases the manufacturing capacity of the back-contact cell, and reduces the risk of leakage in the second region 13. Furthermore, since the extinction coefficient of the second doped silicon layer 16 is smaller than that of the first doped silicon layer 15, its density is also relatively small. Therefore, even if the area of ​​the second region 13 on which the second doped silicon layer 16 is provided is relatively small in the first surface, resulting in a large amount of etching when the entire second doped silicon layer 16 is selectively etched, the etching difficulty of the second doped silicon layer 16 is relatively low, so a high manufacturing efficiency of the back contact battery can be guaranteed. In addition, the area ratios of the first region 12 and the second region 13 on the first surface respectively meet the above ranges. While improving the manufacturing capacity of the back contact battery, it is also possible to regulate the area ratios of the first doped silicon layer 15 and the second doped silicon layer 16 on one side of the first surface, and then regulate the area ratio of the PN junction region, thereby achieving effective shunting of carriers, so that the manufacturing capacity of the back contact battery and the effective collection of carriers are balanced, which is conducive to achieving cost reduction and efficiency improvement.

[0055] In actual application, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate. The semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0056] It is understood that the first surface of the semiconductor substrate corresponds to the back surface of the back-contact cell, and the second surface of the semiconductor substrate corresponds to the front surface of the back-contact cell. Furthermore, the specific locations of the first region, second region, and spacer region on the first surface can be determined based on the distribution of the first doped silicon layer and the second doped silicon layer included in the back-contact cell on the first surface, and are not specifically limited herein.

[0057] For example, Figure 1As shown, the first doped silicon layer 15 can be provided on the first region 12, and the second doped silicon layer 16 can be provided on the second region 13, and the first doped silicon layer 15 and the second doped silicon layer 16 are separated by the spacer region 14. In this case, one of the first region 12 and the second region 13 in the first surface corresponds to the N region, and the other corresponds to the P region. The spacer region 14 is the region between the N region and the P region in the first surface. Optionally, the first doped silicon layer 15 and the second doped silicon layer 16 both include doped polysilicon layers, such as a tunneling oxide layer passivated contact back contact cell (i.e., a TBC cell).

[0058] For example, Figure 2 As shown, the first doped silicon layer 15 can be disposed on the first region 12 and the spacer region 14. The second doped silicon layer 16 is disposed on the second region 13 and extends over the first doped silicon layer 15 located in the spacer region 14. In this case, the back contact cell may further include an insulating layer 23 located between the first doped silicon layer 15 and the second doped silicon layer 16 to reduce the risk of leakage between the first doped silicon layer 15 and the second doped silicon layer 16. In this case, one of the first region 12 and the second region 13 on the first surface corresponds to an N region, and the other corresponds to a P region. The spacer region 14 is the overlapping region of the first surface located between the N region and the P region. The material of the insulating layer 23 can include any non-conductive material such as silicon oxide, silicon nitride, aluminum oxide, and intrinsic silicon. Optionally, the first doped silicon layer 15 includes a doped polycrystalline silicon layer, and the second doped silicon layer 16 includes a doped amorphous silicon layer, such as a hybrid back contact cell that combines a tunneling oxide passivation contact structure with a heterogeneous contact structure.

[0059] From the above content, it can be seen that the area ratio of the second region and the spacing region in the first surface will affect the area ratio of the first doped silicon layer at least provided on the first region and the second doped silicon layer at least provided on the second region on one side of the first surface, respectively, thereby affecting the area ratio of the P region and the N region on one side of the first surface in the back contact battery, affecting the separation and collection of carriers. In addition, it will also affect the etching efficiency, etching capacity and leakage risk of at least the first doped silicon layer, the doped silicon glass layer and the second doped silicon layer in the actual manufacturing process. Therefore, the specific values ​​of the area ratios of the first region, the second region and the spacing distribution on the first surface can be determined based on the requirements for the conversion efficiency and manufacturing capacity of the back contact battery in the actual application scenario, as long as they can be used in the back contact battery provided in the embodiment of the present invention.

[0060] For example, the area of ​​the first region in the first surface may account for 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59% or 60%, etc.

[0061] For example, the second region may account for an area greater than or equal to 20% and less than or equal to 35% of the area of ​​the first surface. For example, the second region may account for an area of ​​20%, 21%, 22%, 23%, 24%, 25%, 28%, 30%, 32%, or 35% of the area of ​​the first surface.

[0062] Exemplarily, the area of ​​the spacing region in the first surface accounts for greater than or equal to 10% and less than or equal to 20%. For example, the area of ​​the spacing region in the first surface may account for 10%, 11%, 12%, 14%, 15%, 16%, 18%, or 20%.

[0063] For example, the sum of the areas of the first region and the spacer region is S1, and the sum of the areas of the second region and the spacer region is S2. The ratio between S1 and S2 can be greater than 1 and less than 2. The ratio between S1 and S2 can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.51, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 1.99, etc. In this case, the ratio of S1 to S2 is within the above range, which helps prevent the second doped silicon layer disposed on the second region from occupying too large an area of ​​the first surface due to a small ratio, ensures that the PN junction has a larger junction area when the conductivity type of the first doped silicon layer is opposite to that of the semiconductor substrate, and facilitates effective carrier separation. In addition, this ratio can also prevent the first doped silicon layer disposed on the first region from occupying too large an area of ​​the first surface due to a large ratio, thereby preventing the lateral carrier transmission distance from being too long and ensuring that the second doped silicon layer has a high carrier collection efficiency. At the same time, because the size of this ratio also affects the area ratio of the first doped silicon layer (with a denser film layer) and the second doped silicon layer (with a relatively loose film layer) on the side of the first surface, thereby affecting the etching capacity for selectively etching the first doped silicon layer and the second doped silicon layer, when this ratio is within the above range, it is also beneficial for the back-contact cell to have both high conversion efficiency and manufacturing capacity, thereby reducing costs and increasing efficiency.

[0064] It can be understood that, when the size of the semiconductor substrate is constant, the lengths of the first region and the second region are approximately the same (the length direction of the first region and the second region is approximately parallel to the series connection direction of different back contact batteries). Based on this, when the first region and the second region have different area proportions on the first surface, the widths of the first region and the second region are different; accordingly, the difference in the widths of the first region and the second region can refer to the difference in area proportions of the first region and the second region described above. Among them, the specific dimensions referred to by the widths of the first region and the second region can be determined based on the morphology of the first region and the second region. For example: when the first region and the second region are distributed in a strip-like manner, the widths of the first region and the second region refer to the widths of the strip-like regions included in the first region and the second region. For another example: when the first region and the second region are distributed in a finger-like manner, the widths of the first region and the second region may refer to the widths of the finger-like regions included in the first region and the second region. When the widths of the first region and the second region are unevenly distributed, the width refers to the average width.

[0065] For example, the sum of the widths of the first region and the spacing region is W1, and the sum of the widths of the second region and the spacing region is W2. The ratio between W1 and W2 may be greater than 1 and less than 2. For example, the ratio between W1 and W2 may be 1.1, 1.2, 1.3, 1.4, 1.5, 1.51, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 1.99. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect of the ratio between S1 and S2 being greater than 1 and less than 2 described above, and will not be repeated here.

[0066] Among them, the ratio between W1 and W2, and the ratio between S1 and S2 can be selected within the range of greater than 1 and less than 2. Among them, the ratio between W1 and W2 can be equal to the ratio between S1 and S2. The ratio between W3 and W4 can be greater than the ratio between S1 and S2. In this case, when the ratio between W3 and W4 is greater than the ratio between S1 and S2, the ratio between W3 and W4 is relatively large, and / or the ratio between S1 and S2 is relatively small, ensuring that the first doped silicon layer has a higher area ratio on one side of the first surface, further shortening the processing time of the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. For example, one side of the edge of the first surface has a P-type doped silicon layer, and the other three sides of the edge have an N-type doped silicon layer.

[0067] With respect to the first doped silicon layer and the second doped silicon layer, in terms of conductivity type, the conductivity type of the first doped silicon layer can be P-type, in which case the conductivity type of the second doped silicon layer is N-type; or the conductivity type of the first doped silicon layer is N-type, in which case the conductivity type of the second doped silicon layer is P-type. Secondly, the conductivity type of the first doped silicon layer can be opposite to that of the semiconductor substrate. In this case, the first doped silicon layer serves as the emitter region of the back-contact battery, and the area of ​​the first region in the first surface accounts for a relatively large proportion. This results in a relatively large area of ​​the emitter region disposed at least on the first region, which is beneficial for the effective separation and collection of carriers and improves the conversion efficiency of the back-contact battery.

[0068] In terms of materials, the material of the first doped silicon layer includes polycrystalline silicon and / or single crystal silicon. Specifically, the first doped silicon layer can be a doped polycrystalline silicon layer formed solely of polycrystalline silicon material; the first doped silicon layer can also be a doped single crystal silicon layer formed solely of single crystal silicon material; the first doped silicon layer can also be a doped crystalline silicon layer including both polycrystalline silicon material and single crystal silicon material. The distribution of the polycrystalline silicon material and the single crystal silicon material in the doped crystalline silicon layer can be determined according to actual needs and is not specifically limited here.

[0069] As for the second doped silicon layer, the crystal orientation of the second doped silicon layer can include at least one of single crystal, polycrystalline, microcrystalline, nanocrystalline or amorphous, as long as the extinction coefficient corresponding to the second doped silicon layer is less than the extinction coefficient corresponding to the first doped silicon layer.

[0070] Optionally, the first doped silicon layer and the second doped silicon layer may both be doped polysilicon layers. In this case, the conductivity type of the first doped silicon layer may be P-type, and the conductivity type of the second doped silicon layer may be N-type.

[0071] Optionally, the first doped silicon layer may be a doped polysilicon layer, and the second doped silicon layer may be a doped silicon layer whose material includes at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon. In this case, the back contact battery is a hybrid battery. Optionally, the conductivity type of the doped polysilicon layer may be N-type, and the conductivity type of the second doped silicon layer may be P-type; at this time, compared with P-type doped amorphous silicon, microcrystalline silicon or nanocrystalline silicon materials, the contact resistance between the P-type doped polysilicon material and the electrode is higher and the field passivation effect is poorer. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery.

[0072] From the perspective of formation position, Figure 1 and Figure 2 As shown, the first doped silicon layer 15 can be directly disposed on the semiconductor substrate 11. Alternatively, as shown in FIG. Figure 3As shown, the back contact cell may also include a first interface passivation layer 24, which is arranged between the semiconductor substrate 11 and the first doped silicon layer 15. In this case, the passivation contact structure composed of the first interface passivation layer 24 and the first doped silicon layer 15 has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the first region 12 of the first surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the back contact cell. The material and thickness of the first interface passivation layer 24 can be set according to actual needs and are not specifically limited here. For example, the material of the first interface passivation layer may include tunneling passivation materials such as silicon oxide, aluminum oxide or titanium oxide.

[0073] As for the second doped silicon layer, Figure 3 As shown, the second doped silicon layer 16 can be directly disposed on the second region 13. Alternatively, as shown in FIG. Figure 4 and Figure 5 As shown, the back contact battery can also include a second interface passivation layer 25, which is arranged between the semiconductor substrate 11 and the second doped silicon layer 16 (when the second doped silicon layer 16 also extends to above the first doped silicon layer 15 located in the spacing area 14, the second interface passivation layer 25 also extends from the second area 13 to between the first doped silicon layer 15 and the second doped silicon layer 16). In this case, the passivation contact structure composed of the second interface passivation layer 25 and the second doped silicon layer 16 can achieve selective collection of carriers and reduce the carrier recombination rate in the second area 13 of the first surface of the semiconductor substrate 11. The material and thickness of the second interface passivation layer 25 can be set according to the material of the second doped silicon layer 16 and actual needs, and are not specifically limited here. For example: when the material of the second doped silicon layer is doped polysilicon, the second interface passivation layer is a tunneling passivation layer. For another example, when the material of the second doped silicon layer includes at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon, the second interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer or a mixture of the three.

[0074] In terms of film properties, as mentioned above, the extinction coefficient corresponding to the first doped silicon layer is greater than that corresponding to the second doped silicon layer. Furthermore, the extinction coefficients of the doped silicon layers vary depending on the material used. The extinction coefficients of the first and second doped silicon layers can be determined based on the material requirements for the doped silicon layer in the actual application scenario, as well as the manufacturing capacity requirements for back-contact cells.

[0075] Exemplarily, when the first doped silicon layer includes a P-type doped polysilicon layer, the extinction coefficient of the P-type doped polysilicon layer may be greater than or equal to 0.01 and less than or equal to 1.5. Optionally, the extinction coefficient of the P-type doped polysilicon layer may be greater than or equal to 0.6 and less than or equal to 1.2. For example, the extinction coefficient of the P-type doped polysilicon layer may be 0.01, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1.0, 1.1, 1.2 or 1.5, etc. The extinction coefficient of the P-type doped polysilicon layer is also related to the density of the film layer itself. Specifically, within a certain range, the extinction coefficient of the P-type doped polysilicon layer is proportional to the density of the film layer itself. The density of the film layer will affect its own corrosion resistance to the etchant. It is understandable that the higher the density of the film layer, the lower the corrosion rate of the etchant on the film layer and the higher the etching difficulty. In this case, when the first doped silicon layer includes a P-type doped silicon layer, after the first doped silicon layer is formed, a doped silicon glass layer formed on the side of the first doped silicon layer facing away from the semiconductor substrate is doped with P-type impurities such as boron. Because P-type impurities such as boron have lower electron affinity than N-type impurities such as phosphorus, P-type impurities such as boron are less likely to accept electrons, further affecting the ease with which they are etched by the etchant. The doped silicon glass layer and the first doped silicon layer doped with P-type impurities such as boron are less likely to react with alkaline wet etching solutions, making them more difficult to etch. Based on this, when the first doped silicon layer includes a P-type doped polysilicon layer, the back-contact cell provided in an embodiment of the present invention can also shorten the processing time of the P-type doped polysilicon layer and the borosilicate glass layer by increasing the area ratio of the P-type doped polysilicon layer on the first side, thereby improving the manufacturing efficiency of the back-contact cell, reducing production costs, and increasing the manufacturing capacity of the back-contact cell. In addition, when the extinction coefficient of the P-type doped polysilicon layer is within the above-mentioned range, it can also prevent the occurrence of problems such as the electrode burning through the P-type doped polysilicon layer due to the low density of the P-type doped polysilicon layer due to the extinction coefficient of the P-type doped polysilicon layer being too small, thereby ensuring that the back contact battery has good working performance. It can also prevent the difficulty of selective etching of the P-type doped polysilicon layer and the doped silicon glass layer due to the high density of the P-type doped polysilicon layer due to the extinction coefficient of the P-type doped polysilicon layer being too large, further shortening the processing time of the doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. In addition, because the extinction coefficient of the P-type doped polysilicon layer is also related to its own doping concentration, when the extinction coefficient of the P-type doped polysilicon layer is within the above-mentioned range, it can also make the P-type doped polysilicon layer have a higher doping concentration, which is beneficial to improving the field passivation effect of the P-type doped polysilicon layer and reducing the contact resistance between the P-type doped polysilicon layer and the corresponding conductive material.

[0076] For example, when the second doped silicon layer includes an N-type doped polysilicon layer, the extinction coefficient of the N-type doped polysilicon layer may be greater than or equal to 0.01 and less than or equal to 1.5. Alternatively, the extinction coefficient of the N-type doped polysilicon layer may be greater than or equal to 0.05 and less than or equal to 0.3. For example, the extinction coefficient of the N-type doped polysilicon layer may be 0.01, 0.05, 0.08, 0.1, 0.12, 0.15, 0.18, 0.2, 0.22, 0.25, 0.28, 0.3, 0.5, 0.8, 1, 1.2, or 1.5. In this case, compared to the P-type doped polysilicon layer, the N-type doped polysilicon layer has a relatively small extinction coefficient and compactness. When the second doped silicon layer includes an N-type doped polysilicon layer, even if the second region on which the N-type doped polysilicon layer is disposed accounts for a relatively small proportion of the area of ​​the first surface, resulting in a large amount of etching when the entire N-type doped polysilicon layer and the phosphosilicate glass layer are selectively etched, the etching difficulty of the N-type doped polysilicon layer and the phosphosilicate glass layer is relatively low, thereby ensuring a high manufacturing efficiency of the back-contact cell. The application principle of the beneficial effect of the extinction coefficient of the N-type doped polysilicon layer being greater than or equal to 0.01 and less than or equal to 1.5 is similar to the application principle of the beneficial effect of the extinction coefficient of the P-type doped polysilicon layer being greater than or equal to 0.01 and less than or equal to 1.5, and will not be repeated here.

[0077] It should be noted that the extinction coefficients of the above-mentioned P-type doped polysilicon layer and N-type doped polysilicon layer can be selected within the range of greater than or equal to 0.01 and less than or equal to 1.5. This range of extinction coefficients is applicable to doped polysilicon layers doped only with elements of the three-five main groups, and is also applicable to a stacked structure formed by a doped polysilicon layer doped with elements of the three-five main groups and a doped polysilicon layer doped with C or N. Among them, the extinction coefficient of the doped polysilicon layer doped only with elements of the three-five main groups is greater than the extinction coefficient of the stacked structure formed by doped polysilicon layers doped with C or N and having the same conductivity type. The above-mentioned doped polysilicon layer doped with C or N refers to a doped polysilicon layer doped with B or P, and C and / or N at the same time.

[0078] Furthermore, in actual applications, the density of the doped silicon layer is related to its degree of crystallization. Specifically, within a certain range, increasing the degree of crystallization of the doped silicon layer improves the density of the doped silicon layer; conversely, decreasing the degree of crystallization of the doped silicon layer reduces the density of the doped silicon layer. In this case, the relationship and specific range between the degrees of crystallization of the first and second doped silicon layers can be determined based on the requirements for the extinction coefficients of the first and second doped silicon layers, and are not specifically limited here.

[0079] For example, the degree of crystallization of the second doped silicon layer can be greater than that of the first doped silicon layer. In this case, the film density of the second doped silicon layer and the first doped silicon layer can be regulated by adjusting the degree of crystallization of the film layer, thereby regulating the density of the doped silicon glass layer formed by oxidizing a portion of the first doped silicon layer, reducing the difficulty of selective etching of the first doped silicon layer and the doped silicon glass layer, further shortening the processing time of the doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of the back-contact cell, reducing production costs, and increasing the manufacturing capacity of the back-contact cell.

[0080] In terms of film layer dimensions, the aspect ratio of the first doped silicon layer located on the first region can be greater than the aspect ratio of the second doped silicon layer located on the second region. In this case, the width of the first doped silicon layer located on the first region is increased, and the area proportion of the first doped silicon layer on the first side is increased. This further shortens the processing time for the denser doped silicon glass layer and the first doped silicon layer, improving the manufacturing efficiency of back-contact cells, reducing production costs, and increasing the manufacturing capacity of back-contact cells. Furthermore, if the first doped silicon layer is located at the emitter of the cell, the area of ​​the PN junction region can be increased, facilitating effective carrier separation, reducing the carrier recombination rate, and improving the conversion efficiency of back-contact cells. The height direction of the first doped silicon layer and the second doped silicon layer refers to the thickness direction of the film layers themselves. The specific dimensions of the width of the first doped silicon layer located on the first region and the second doped silicon layer located on the second region can be referred to as the dimensions of the width of the first region and the second region described above, and will not be further elaborated here. Furthermore, the aspect ratio of the first doped silicon layer located on the first region can also be equal to or less than the aspect ratio of the second doped silicon layer located on the second region.

[0081] As for the second doped silicon layer, Figure 4 As shown, the second doped silicon layer 16 may be provided only on the second region 13 of the semiconductor substrate 11; or Figure 5 As shown, the second doped silicon layer 16 can be disposed on the second region 13 of the semiconductor substrate 11 and extend to above the portion of the first doped silicon layer 15 corresponding to the spacer region 14; or, as shown Figure 6As shown, the second doped silicon layer 16 is not only disposed on the second region 13 of the semiconductor substrate 11, but also disposed above a portion of the first doped silicon layer 15 located on the first region 12. Furthermore, the second doped silicon layer 16 located in the first region 12 is spaced apart from the first doped silicon layer 15. This means that the first doped silicon layer 15 has a dielectric layer on the side facing away from the semiconductor substrate 11, thereby isolating the first doped silicon layer 15 from the second doped silicon layer 16 located in the first region 12. In this case, in the actual manufacturing process, the entire second doped silicon layer 16 is selectively etched, so that the second doped silicon layer 16 in the back-contact cell is located only on a localized area of ​​the first surface. Prior to this selective etching, the mask material formed on the side of the second doped silicon layer 16 facing away from the semiconductor substrate 11 is selectively treated using a process such as laser engraving, so that the untreated portion of the mask material forms a mask layer for protecting the second doped silicon layer 16. It can be seen that the formation range of the second doped silicon layer 16 determines the range of mask material treatment required. Based on this, when the second doped silicon layer 16 is not only disposed on the second region 13 but also disposed above the portion of the first doped silicon layer 15 located on the first region 12, there is no need to carve the second doped silicon layer 16 located on the portion of the first doped silicon layer 15. This can shorten the processing time for the mask material and the second doped silicon layer 16, further improving the manufacturing efficiency of the back-contact cell, reducing production costs, and increasing the manufacturing capacity of the back-contact cell. At the same time, the second doped silicon layer 16 located in the first region 12 is spaced apart from the first doped silicon layer 15, which can prevent short circuits, reduce the risk of leakage, and ensure the high electrical reliability of the back-contact cell.

[0082] It is understandable that in actual application, Figure 7As shown, the back-contact cell may further include a plurality of first collecting electrodes 17 disposed on the first doped silicon layer 15. Each first collecting electrode 17 makes ohmic contact with the first doped silicon layer 15 to conduct carriers collected by the first doped silicon layer 15, thereby facilitating the formation of a photocurrent. The back-contact cell may further include a plurality of second collecting electrodes 18 disposed on the second doped silicon layer 16. Each second collecting electrode 18 makes ohmic contact with the second doped silicon layer 16 to conduct carriers collected by the second doped silicon layer 16 to facilitate the formation of a photocurrent. Specifically, the plurality of first collecting electrodes 17 and the plurality of second collecting electrodes 18 extend along a first direction, and the second collecting electrodes 18 and the first collecting electrodes 17 are alternately spaced along a second direction. The first direction is different from the second direction (the embodiments of the present invention do not specifically limit the directions to which the first and second directions refer. Optionally, if the surface of the semiconductor substrate is rectangular, one of the first and second directions may be parallel to the long side of the rectangle, and the other may be parallel to the short side of the rectangle). The second doped silicon layer 16 located in the first region 12 is spaced apart from the first collector electrode 17 to prevent leakage (specifically, the second doped silicon layer 16 located in the first region 12 can be spaced apart from the first collector electrode 17 by the insulating material of the surface passivation layer). The first collector electrode and the second collector electrode can be continuous first collector electrodes and continuous second collector electrodes, respectively. In this case, the same first collector electrode or the same second collector electrode located in the same row along the first direction has only one collector electrode with the same polarity.

[0083] Alternatively, the first collecting electrode and the second collecting electrode may be a discontinuous first collecting electrode and a discontinuous second collecting electrode, respectively. In this case, the same first collecting electrode or the same second collecting electrode located in the same row along the first direction has multiple spaced-apart collecting electrode segments of the same polarity. In this case, the back-contact battery may also include a first bus electrode and a second bus electrode extending along the second direction and alternately spaced along the first direction. The first bus electrode is electrically connected to the discontinuous first collecting electrode, and the first bus electrode is electrically insulated from the discontinuous second collecting electrode by a break in the discontinuous second collecting electrode. The second bus electrode is electrically connected to the discontinuous second collecting electrode, and the second bus electrode is electrically insulated from the discontinuous first collecting electrode by a break in the discontinuous first collecting electrode.

[0084] Or, if Figure 7As shown, along the second direction, the first surface includes a central region and edge regions located on both sides of the central region. The first collecting electrode 17 and the second collecting electrode 18 located on the central region are respectively a continuous first collecting electrode or a continuous second collecting electrode, and the first collecting electrode 17 and the second collecting electrode 18 located on the edge region are respectively a discontinuous first collecting electrode or a discontinuous second collecting electrode. In addition, the above-mentioned back-contact battery also includes a first interconnect structure 19 and a first bus electrode segment 20. The first bus electrode segment 20 is arranged on the edge region and extends along the second direction. The discontinuous first collecting electrode is electrically connected to the first bus electrode segment 20, and the discontinuous second collecting electrode is disconnected at the intersection with the first bus electrode segment 20. The first interconnect structure 19 is arranged at one end of the first bus electrode segment 20 close to the central region and is electrically connected to the first bus electrode segment 20. In this case, compared with the case where all the first collecting electrodes 17 and all the second collecting electrodes 18 are respectively discontinuous first collecting electrodes and discontinuous second collecting electrodes, when part of the first collecting electrodes 17 and part of the second collecting electrodes 18 are respectively continuous first collecting electrodes or continuous second collecting electrodes, the number of dead zones of the first doped silicon layer 15 and the second doped silicon layer 16 can be reduced, which is beneficial to improving the carrier collection efficiency and further improving the conversion efficiency of the back contact battery. In addition, in this case, the above-mentioned back contact battery may also include a second interconnect structure and a second bus electrode segment. The second bus electrode segment is arranged on the edge area and extends along the second direction. The discontinuous second collecting electrode is electrically connected to the second bus electrode segment, and the discontinuous first collecting electrode is disconnected at the intersection with the second bus electrode segment. The second interconnect structure is arranged at one end of the second bus electrode segment near the middle area and is electrically connected to the second bus electrode segment.

[0085] In addition, if Figure 7 As shown, it can be understood that when the second doped silicon layer 16 is also disposed above the portion of the first doped silicon layer 15 located on the first region 12, the first doped silicon layer 15 located in the first region 12 is provided with not only the second doped silicon layer 16 but also a first collector electrode 17 for collecting and conducting carriers. The carrier collection capability of the first collector electrode 17 is related to its formation range. Therefore, the specific position and setting range of the second doped silicon layer 16 above the first doped silicon layer 15 located in the first region 12 can be determined based on the requirements for the carrier collection capability of the first collector electrode 17 in actual application scenarios, the manufacturing capacity of the back-contact battery, and the actual manufacturing accuracy. No specific limitation is imposed here.

[0086] For example, Figure 7As shown, when at least some of the multiple second collecting electrodes 18 are discontinuous second collecting electrodes, the second doped silicon layer 16 located in the first region 12 can be disposed at the disconnection point of the discontinuous second collecting electrodes. In this case, the first collecting electrode 17 and the second collecting electrode 18 are used to collect and conduct carriers of corresponding conductivity types within the first doped silicon layer 15 and the second doped silicon layer 16, respectively. The formation range of the first collecting electrode 17 and the second collecting electrode 18 is proportional to their respective carrier collection capabilities. Furthermore, the intra-string interconnect, such as the soldering ribbon, extends substantially along the second direction and is electrically connected to the first collecting electrode 17, and is electrically insulated from the discontinuous second collecting electrode of opposite polarity by the disconnection point of the discontinuous second collecting electrode. At the same time, the intra-string interconnection parts such as the welding strip are electrically connected to the first doped silicon layer 15 through the first collecting electrode 17, and are not in direct electrical contact with the first doped silicon layer 15. Therefore, when the second doped silicon layer 16 located in the first region 12 is set at the disconnection point of the discontinuous second collecting electrode, it can not only shorten the processing time of the mask material and the second doped silicon layer 16 by retaining the second doped silicon layer 16 located on part of the first doped silicon layer 15, thereby improving the manufacturing capacity of the back contact battery, but also will not affect the formation range of the first collecting electrode 17 that collects and derives the corresponding conductive type carriers in the first doped silicon layer 15, thereby ensuring that the first collecting electrode 17 has a higher carrier collection ability and reduces the carrier recombination rate.

[0087] Specifically, such as Figure 7 As shown, if the second doped silicon layer 16 located in the first region can be disposed at the break in the discontinuous second collector electrode, the second doped silicon layer 16 located in the first region can be disposed at the center of the break along the first direction. Specifically, when at least some of the multiple first collector electrodes 17 are discontinuous first collector electrodes, the second doped silicon layer 16 located in the first region can be symmetrically disposed relative to the centerline of the collector electrode segment included in the discontinuous first collector electrode in the second direction. In this case, the leakage distances between the two ends of the second doped silicon layer 16 located in the first region and the edges of the first doped silicon layer 15 and the edges of the second doped silicon layer 16 located in the second region along the first direction are approximately the same, thereby preventing the risk of leakage on one side due to the positional offset of the second doped silicon layer 16 located in the first region at the break, thereby ensuring high conversion efficiency for the back-contact cell. Of course, the centerline of the second doped silicon layer 16 located in the first region along the second direction can also be offset by a certain distance relative to the centerline of the collector electrode segment included in the discontinuous first collector electrode in the second direction. The specific position of the disconnection point of the second doped silicon layer 16 located in the first region can be determined according to actual manufacturing accuracy and is not specifically limited here.

[0088] Among them, Figure 7As shown, when the back contact cell further includes the above-mentioned first interconnect structure 19 and the first bus electrode segment 20, the second doped silicon layer 16 located in the first region may include a first sub-doping portion 21 and a second sub-doping portion 22. The first sub-doping portion 21 is arranged below the first bus electrode segment 20, and the second sub-doping portion 22 is arranged at least below the first interconnect structure 19. In addition to isolating the first doped silicon layer 15 from the second doped silicon layer 16 located in the first region through the aforementioned dielectric layer, it is also necessary to form isolation between the second doped silicon layer 16 located in the first region and the electrode in the first region. The electrode in the first region includes any one of the first collector electrode, the first bus electrode segment 20 and the first interconnect structure 19, so as to ensure that the electrode in the first region fully collects carriers, while avoiding the formation of ohmic contact between the electrode in the first region and the second doped silicon layer 16 to cause leakage, thereby reducing the risk of hot spots.

[0089] Illustratively, the second doped silicon layer and the first collecting electrode located in the first region are spaced apart in the in-plane direction of the semiconductor substrate; no or very little ohmic contact is formed between the first sub-doped portion and the first bus electrode segment, and no or very little ohmic contact is formed between the second sub-doped portion and the first interconnect structure, for example, both the first bus electrode segment and the first interconnect structure use non-burn-through materials.

[0090] like Figure 7 and Figure 8 As shown, along the first direction, the width of the second sub-doped portion 22 is greater than the width of the first sub-doped portion 21. This fully utilizes the dead area of ​​the first busbar electrode segment 20 and the first doped silicon layer 15 beneath the first interconnect structure 19, thereby improving production capacity. Specifically, the width and length of the first sub-doped portion 21 and the second sub-doped portion 22 can be determined based on the size of the disconnection point, the manufacturing capacity of the back-contact cell in actual application scenarios, and the carrier collection capacity of the first collector electrode 17, and are not specifically limited here.

[0091] Exemplarily, the width of the first sub-doping portion may be greater than or equal to 0.3 times the width of the portion of the first doped silicon layer corresponding to the first sub-doping portion, and less than the width of the portion of the first doped silicon layer corresponding to the first sub-doping portion. And / or, the width of the second sub-doping portion is greater than the width of the first interconnect structure, and less than or equal to 0.95 times the width of the portion of the first doped silicon layer corresponding to the second sub-doping portion. In this case, along the first direction, when the width of the second sub-doping portion and / or the first sub-doping portion is within the above range, the width extension range of the first sub-doping portion and / or the second sub-doping portion at the corresponding disconnection point is larger, which is conducive to further shortening the processing time of the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery.

[0092] For example, the width of the first sub-doped portion may be greater than the width of the interconnect (such as a soldering ribbon) and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the first sub-doped portion. times; and / or, the width of the second sub-doped portion may be greater than the width of the first interconnect structure (such as a pad) and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the second sub-doped portion. times. In this configuration, the width of the first sub-doping portion and / or the second sub-doping portion is selected within the above corresponding ranges, which not only makes full use of the dead space at the disconnection position of the collector electrode, thereby fully improving the manufacturing capacity of the back-contact battery, but also avoids the risk of leakage caused by the connection of the oppositely doped regions due to the excessive width of the first sub-doping portion and / or the second sub-doping portion, thereby improving the electrical reliability of the back-contact battery.

[0093] For example, along the second direction, the width of the first sub-doped portion may be less than or equal to 2.4 mm. For example, the width of the first sub-doped portion may be 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, or 2.4 mm.

[0094] For example, along the second direction, the width of the second sub-doped portion may be less than or equal to 0.9 mm. For example, the width of the second sub-doped portion may be 0.1 mm, 0.2 mm, 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, or 0.9 mm.

[0095] Exemplarily, along the second direction, the ratio of the sum of the lengths of all the second sub-doping parts to the sum of the lengths of all the first sub-doping parts is greater than or equal to 2:1 and less than or equal to 5:1. For example, the ratio of the sum of the lengths of all the second sub-doping parts to the sum of the lengths of all the first sub-doping parts can be 2:1, 5:2, 3:1, 7:2, 4:1, 9:2 or 5:1, etc. In this case, the length extension range of the first sub-doping part and the second sub-doping part at the corresponding disconnection point is relatively large, which is conducive to further shortening the processing time of the mask material and the second doped silicon layer, further improving the manufacturing efficiency of the back contact battery, reducing production costs, and increasing the manufacturing capacity of the back contact battery. In addition, it can also prevent the first sub-doping part and the second sub-doping part from being too small in distance from the first collector electrode due to the excessive length, reduce the risk of leakage, and improve the electrical reliability of the back contact battery.

[0096] In addition, the location of the second sub-doped portion can be determined based on the disconnection spacing of the discontinuous second electrode where the extended line intersects the first busbar segment and is close to the first interconnection structure, and is not specifically limited here. Figure 7As shown, when the disconnection spacing of the discontinuous second electrode where the extension line intersects the first bus electrode segment 20 and is close to the first interconnect structure 19 is approximately the same as the disconnection spacing of the discontinuous second electrode where the extension line intersects the first bus electrode segment 20 and is away from the first interconnect structure 19, the second sub-doped portion 22 can be arranged only below the first interconnect structure 19.

[0097] Or, as Figure 8 As shown, the second sub-doped portion 22 can also be disposed below the side of the first busbar segment 20 near the first interconnect structure 19. In this case, it can be understood that along the first direction, the width of the first interconnect structure 19 is greater than the width of the first busbar segment 20. To reduce the risk of leakage, the disconnection spacing of the discontinuous second electrode whose extended line intersects the first busbar segment 20 and is close to the first interconnect structure 19 is greater than the disconnection spacing of the discontinuous second electrode whose extended line intersects the first busbar segment 20 and is away from the first interconnect structure 19. Based on this, when the wider second sub-doped portion 22 is also disposed below the side of the first busbar segment 20 near the first interconnect structure 19, the wider disconnection spacing can be further utilized to further expand the arrangement range of the second doped silicon layer 16 on the first region while preventing leakage, shortening the processing time of the denser doped silicon glass layer and the first doped silicon layer 15, and improving the manufacturing efficiency of the back-contact cell. The discontinuous second electrode whose extended line intersects the first busbar segment 20 and is close to the first interconnection structure 19 can be determined according to the requirements for preventing leakage in actual application scenarios and is not specifically limited here.

[0098] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes a back-contact cell provided by the first aspect and various implementations thereof.

[0099] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0100] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0101] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate comprising a first surface and a second surface opposite to each other; the first surface having a first region and a second region spaced apart from each other, and a spacer region between the first region and the second region; The first region accounts for an area of ​​the first surface that is greater than or equal to 50% and less than or equal to 60%; the sum of the widths of the first region and the spacing region is W1, the sum of the widths of the second region and the spacing region is W2, and the ratio of W1 to W2 is greater than 1 and less than 2; a first doped silicon layer, disposed on the first region; the material of the first doped silicon layer comprises polycrystalline silicon and / or single crystal silicon; the conductivity type of the first doped silicon layer is P type; A second doped silicon layer is disposed on the second region; the conductivity type of the second doped silicon layer is opposite to that of the first doped silicon layer; and the extinction coefficient corresponding to the first doped silicon layer is greater than the extinction coefficient corresponding to the second doped silicon layer.

2. The back contact battery according to claim 1, characterized in that The area of ​​the second region in the first surface accounts for greater than or equal to 20% and less than or equal to 35%; And / or, the area of ​​the spacing region in the first surface accounts for greater than or equal to 10% and less than or equal to 20%.

3. The back contact battery according to claim 1, characterized in that The first doped silicon layer includes a P-type doped polysilicon layer, and the extinction coefficient of the P-type doped polysilicon layer is greater than or equal to 0.01 and less than or equal to 1.5; And / or, the second doped silicon layer includes an N-type doped polysilicon layer, and an extinction coefficient of the N-type doped polysilicon layer is greater than or equal to 0.01 and less than or equal to 1.

5.

4. The back contact battery according to claim 1, characterized in that The crystallization degree of the second doped silicon layer is greater than the crystallization degree of the first doped silicon layer.

5. The back contact battery according to claim 1, characterized in that The sum of the areas of the first region and the spacer region is S1, the sum of the areas of the second region and the spacer region is S2, and a ratio between S1 and S2 is greater than 1 and less than 2.

6. The back contact battery according to claim 1, characterized in that The sum of the areas of the first region and the spacing region is S1, the sum of the areas of the second region and the spacing region is S2, the sum of the widths of one first region and one spacing region is W3, the sum of the widths of one second region and one spacing region is W4, and the ratio between W3 and W4 is greater than the ratio between S1 and S2.

7. The back contact battery according to claim 1, characterized in that The aspect ratio of the first doped silicon layer located on the first region is greater than the aspect ratio of the second doped silicon layer located on the second region.

8. The back contact battery according to claim 1, characterized in that The back-contact cell further includes a plurality of first collecting electrodes disposed on the first doped silicon layer, each of the first collecting electrodes being in ohmic contact with the first doped silicon layer; the plurality of first collecting electrodes extending along a first direction and spaced apart along a second direction, the first direction being different from the second direction; The second doped silicon layer is further disposed above a portion of the first doped silicon layer on the first region, and the second doped silicon layer located in the first region is spaced apart from the first doped silicon layer and the first collector electrode.

9. The back contact battery according to claim 8, characterized in that The back-contact cell further includes a plurality of second collecting electrodes disposed on the second doped silicon layer, each second collecting electrode being in ohmic contact with the second doped silicon layer; the plurality of second collecting electrodes extend along the first direction, and the second collecting electrodes and the first collecting electrodes are alternately spaced along the second direction; Among the multiple second collecting electrodes, at least some of the second collecting electrodes are discontinuous second collecting electrodes; the second doped silicon layer located in the first region is arranged at the disconnection point of the discontinuous second collecting electrode; among the multiple first collecting electrodes, at least some of the first collecting electrodes are discontinuous first collecting electrodes, and the second doped silicon layer located in the first region is symmetrically arranged with respect to the midline of the collecting electrode segment included in the discontinuous first collecting electrode in the second direction.

10. The back contact battery according to claim 9, characterized in that Along the second direction, the first surface includes a central region and edge regions located on both sides of the central region; the first collecting electrode and the second collecting electrode located on the central region are respectively a continuous first collecting electrode or a continuous second collecting electrode, and the first collecting electrode and the second collecting electrode located on the edge regions are respectively the discontinuous first collecting electrode or the discontinuous second collecting electrode; The back-contact battery also includes a first interconnect structure and a first bus electrode segment; the first bus electrode segment is arranged on the edge area and extends along the second direction; the discontinuous first collecting electrode is electrically connected to the first bus electrode segment, and the discontinuous second collecting electrode is disconnected at the intersection with the first bus electrode segment; the first interconnect structure is arranged at one end of the first bus electrode segment close to the middle area and is electrically connected to the first bus electrode segment; the second doped silicon layer located in the first area includes a first sub-doping portion and a second sub-doping portion; the first sub-doping portion is arranged below the first bus electrode segment, and the second sub-doping portion is arranged at least below the first interconnect structure; along the first direction, the width of the second sub-doping portion is greater than the width of the first sub-doping portion.

11. The back contact battery according to claim 10, characterized in that The width of the first sub-doped portion is greater than or equal to 0.3 times the width of the portion of the first doped silicon layer corresponding to below the first sub-doped portion, and is smaller than the width of the portion of the first doped silicon layer corresponding to below the first sub-doped portion; and / or, the width of the second sub-doped portion is greater than the width of the first interconnect structure and is less than or equal to 0.95 times the width of a portion of the first doped silicon layer corresponding to and below the second sub-doped portion; And / or, the second sub-doped portion is further arranged below a side of the first bus electrode segment close to the first interconnection structure; And / or, along a direction in which the first bus electrode segment moves away from the first interconnection structure, a width of the second sub-doped portion and a width of the first sub-doped portion gradually decrease.

12. The back contact battery according to claim 10, characterized in that The back contact cell further includes an interconnection electrically connected to the first interconnection structure, wherein the width of the first sub-doped portion is greater than the width of the interconnection and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the first sub-doped portion. times; And / or, the width of the second sub-doped portion is greater than the width of the first interconnect structure and less than or equal to the width of the portion of the first doped silicon layer corresponding to the lower portion of the second sub-doped portion. times.

13. The back contact battery according to claim 10, characterized in that Along the second direction, a ratio of the sum of lengths of all the second sub-doping portions to the sum of lengths of all the first sub-doping portions is greater than or equal to 2:1 and less than or equal to 5:

1.

14. A photovoltaic module, characterized in that: Comprising the back contact battery according to any one of claims 1 to 13.

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