Semiconductor test device

Abstract

A semiconductor test apparatus includes: a first node portion electrically connected to one end of a semiconductor switching device; a second node portion electrically connected to the other end of the semiconductor switching device; a first power supply for high-voltage and low-current, which generates a first voltage and a first current; a second power supply for a low voltage and a large current, the second power supply generating a second voltage lower than the first voltage and a second current larger than the first current; a first relay having a withstand voltage equal to or greater than the first voltage and electrically mounted between the first node portion and the first power source; a second relay having a withstand voltage equal to or greater than the second voltage and electrically mounted between the first node portion and the second power source; a third relay having a withstand voltage equal to or greater than the first voltage and connected in parallel with the second relay; and a fourth relay having a withstand voltage equal to or greater than the second voltage and connected in parallel with the second power source.

Description

Technical Field

[0001] This application claims priority based on Patent Application No. 2022-124695 filed in the Japan Patent Office on August 4, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor test device. Background Art

[0002] Patent document 1 discloses a semiconductor testing device for performing thermal resistance test, surge test, switching characteristic test, and continuous operation test of power semiconductor elements. Patent document 2 discloses a semiconductor testing device for testing the switching characteristic (dynamic characteristic) and saturation voltage (static characteristic) of power semiconductor elements.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-107432

[0006] Patent Document 2: Japanese Patent Application Publication No. 2012-229971 Summary of the invention

[0007] Problems to be solved by the invention

[0008] One embodiment provides a semiconductor test device capable of performing a high voltage and low current test and a low voltage and high current test on a semiconductor switch device.

[0009] Means for solving problems

[0010] One embodiment provides a semiconductor testing device, comprising: a first node portion, which is electrically connected to one end of a semiconductor switching device; a second node portion, which is electrically connected to the other end of the semiconductor switching device; a first power supply for high voltage and small current, which generates a first voltage and a first current; a second power supply for low voltage and large current, which generates a second voltage lower than the first voltage and a second current larger than the first current; a first relay, which has a withstand voltage greater than the first voltage and is electrically installed between the first node portion and the first power supply; a second relay, which has a withstand voltage greater than the second voltage and is electrically installed between the first node portion and the second power supply; a third relay, which has a withstand voltage greater than the first voltage and is connected in parallel with the second relay; and a fourth relay, which has a withstand voltage greater than the second voltage and is connected in parallel with the second power supply.

[0011] The above and other objects, features and effects will become more apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a circuit diagram showing the electrical structure of a semiconductor testing device according to one embodiment.

[0013] Figure 2 This is a circuit diagram showing the circuit operation of a semiconductor test device during a high voltage and low current test.

[0014] Figure 3 This is a circuit diagram showing the circuit operation of a semiconductor test device during a low voltage and high current test.

[0015] Figure 4 Yes means Figure 1 A top view of the semiconductor rectifier device shown.

[0016] Figure 5 It is along Figure 4 A cross-sectional view taken along line VV is shown.

[0017] Figure 6 It is a plan view showing an example of a semiconductor switch device (device under test).

[0018] Figure 7 It is along Figure 6 A cross-sectional view taken along line VII-VII is shown.

[0019] Figure 8 Yes means Figure 6 A top view of the internal structure of the semiconductor switching device is shown.

[0020] Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX is shown. DETAILED DESCRIPTION

[0021] The following is a detailed description of the implementation mode with reference to the accompanying drawings. The accompanying drawings are schematic diagrams and are not strictly illustrated, and the scales and the like may not be consistent. In addition, the same reference symbols are marked on the corresponding structures between the drawings, and repeated descriptions are omitted or simplified. For the structures whose descriptions are omitted or simplified, the descriptions before the omission or simplification shall apply.

[0022] When a phrase such as "substantially equal" is used in a description of a comparison target, the phrase includes not only a numerical value (method) equal to the numerical value (method) of the comparison target, but also a numerical error (method error) within a range of ±10% based on the numerical value (method) of the comparison target. In the embodiments, phrases such as "first", "second", and "third" are used, but they are symbols given to the names of each structure in order to clarify the order of description, and are not given to limit the names of each structure.

[0023] Figure 1 1 is a circuit diagram showing an electrical configuration of a semiconductor test device 1 according to an embodiment. The semiconductor test device 1 is a device for testing electrical characteristics of a semiconductor switch device SW as a device under test. The semiconductor test device 1 may also be referred to as a "characteristic test device" or a "semiconductor inspection device."

[0024] The semiconductor switch device SW is a semiconductor device including a transistor. The semiconductor switch device SW may include at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a BJT (Bipolar junction transistor).

[0025] The semiconductor switch device SW may include a Si-transistor including a Si (silicon) single crystal. The semiconductor switch device SW preferably includes a wide bandgap semiconductor-transistor including a single crystal of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), C (diamond), and the like.

[0026] The semiconductor switch device SW preferably has a SiC-transistor, which includes a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor. The semiconductor switch device SW is a SiC-MISFET (field effect transistor) in this embodiment. The semiconductor switch device SW may include a planar gate transistor or a trench gate transistor.

[0027] The semiconductor switch device SW is preferably a power semiconductor switch device (power transistor) having a first breakdown voltage VB1 of 500 V or more. The first breakdown voltage VB1 may be 3000 V or less.

[0028] The first breakdown voltage VB1 may have a value belonging to any range of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0029] The semiconductor switch device SW includes: a first terminal T1 (one end), a second terminal T2 (the other end) and a control terminal T3 (control end). In this embodiment, the first terminal T1, the second terminal T2 and the control terminal T3 are the drain terminal, the source terminal and the gate terminal of the MISFET. When the semiconductor switch device SW includes an IGBT, the first terminal T1, the second terminal T2 and the control terminal T3 are the collector terminal, the emitter terminal and the gate terminal of the IGBT. When the semiconductor switch device SW includes a BJT, the first terminal T1, the second terminal T2 and the control terminal T3 are the collector terminal, the emitter terminal and the base terminal of the BJT.

[0030] In this embodiment, the semiconductor switch device SW includes a body diode BD electrically connected to the first terminal T1 and the second terminal T2. The body diode BD includes an anode electrically connected to the second terminal T2 and a cathode electrically connected to the first terminal T1.

[0031] The semiconductor test device 1 includes a first node portion N1 (high potential application end) on one side (high potential side) and a second node portion N2 (low potential application end) on the other side (low potential side). In this embodiment, the second node portion N2 is connected to the ground potential (for example, zero potential). The first node portion N1 is electrically connected to the first terminal T1 of the semiconductor switch device SW. The second node portion N2 is electrically connected to the second terminal T2 of the semiconductor switch device SW. The first node portion N1 and the second node portion N2 are open-circuit ends except during testing, and are electrically connected to the first terminal T1 and the second terminal T2 of the semiconductor switch device SW during testing.

[0032] The semiconductor test device 1 includes: a first power supply P1 for high voltage and low current testing that generates a relatively high first voltage VH and a relatively small first current IL. In consideration of safety, the first power supply P1 is configured not to be high voltage and high current. The first power supply P1 has a first power switch S1 and is configured to be switchable between an on state and an off state. The first power supply P1 has a positive electrode on the side of the first node portion N1 and a negative electrode on the side of the second node portion N2.

[0033] The first power supply P1 applies the first voltage VH and the first current IL to the first node portion N1 when the first power switch S1 is turned on. That is, the first power supply P1 applies the first voltage VH and the first current IL to the first terminal T1 of the semiconductor switch device SW. In the high voltage and low current test, the leakage current Ioff as the off current flowing through the semiconductor switch device SW is measured in a state where a high voltage is applied to the semiconductor switch device SW in the off state.

[0034] The first voltage VH is preferably lower than the first breakdown voltage VB1 of the semiconductor switch device SW. The first voltage VH may be greater than or equal to 500 V. The first voltage VH may be less than or equal to 3000 V.

[0035] The first voltage VH may have a value belonging to any range of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0036] The first current IL is less than 1A. The first current IL is preferably less than 1A. The first current IL is particularly preferably greater than 0.01mA and less than 100mA. The first current IL may have a value belonging to any range of greater than 0.01mA and less than 0.05mA, greater than 0.05mA and less than 0.1mA, greater than 0.1mA and less than 0.5mA, greater than 0.5mA and less than 1mA, greater than 1mA and less than 5mA, greater than 5mA and less than 10mA, greater than 10mA and less than 25mA, greater than 25mA and less than 50mA, greater than 50mA and less than 75mA, and greater than 75mA and less than 100mA. The first current IL is preferably greater than 0.1mA and less than 5mA.

[0037] The semiconductor test device 1 includes: a second power supply P2 for low voltage and high current testing that generates a relatively low second voltage VL and a relatively large second current IH. Specifically, the second voltage VL is lower than the first voltage VH, and the second current IH is larger than the first current IL. In consideration of safety, the second power supply P2 is configured not to be a high voltage and a high current. The second power supply P2 has a second power switch S2, and is configured to be switchable between an on state and an off state. The second power supply P2 has a positive electrode on the side of the first node portion N1 and a negative electrode on the side of the second node portion N2.

[0038] The second power supply P2 applies the second voltage VL and the second current IH to the first node portion N1 when the second power switch S2 is turned on. That is, the second power supply P2 applies the second voltage VL and the second current IH to the first terminal T1 of the semiconductor switch device SW. In the low voltage and high current test, the on-resistance Ron of the semiconductor switch device SW is measured while a high current is applied to the semiconductor switch device SW in the on state.

[0039] The second voltage VL may be less than 100 V. The second voltage VL may be greater than 0.1 V. The second voltage VL may have a value belonging to any range of 0.1 V to 1 V, 1 V to 5 V, 5 V to 10 V, 10 V to 25 V, 25 V to 50 V, 50 V to 75 V, and 75 V to 100 V.

[0040] The second current IH may also be 1A or more. The second current IH is preferably greater than 1A. The second current IH may also be 100A or less. The second current IH may have a value belonging to any range of 1A or more and 5A or less, 5A or more and 10A or less, 10A or more and 25A or less, 25A or more and 50A or less, 50A or more and 75A or less, and 75A or more and 100A or less. The second current IH is particularly preferably 10A or more and 75A or less.

[0041] The semiconductor test device 1 includes: a first relay R1 electrically mounted between a first node portion N1 and a first power source P1. For example, the first relay R1 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and a contact (electromagnetic contact). The first relay R1 is composed of a high-voltage, low-current type relay capable of withstanding the load caused by the first power source P1. That is, the first relay R1 is configured not to become a high-voltage, high-current type relay in consideration of safety, as is the first power source P1.

[0042] The first relay R1 is configured to switch between a conducting state (on state) in which the first power source P1 is electrically connected to the first node portion N1, and a non-conducting state (off state) in which the first power source P1 is electrically disconnected from the first node portion N1. In the conducting state of the first relay R1, the first voltage VH and the first current IL of the first power source P1 are applied to the semiconductor switch device SW via the first node portion N1. In the non-conducting state of the first relay R1, the first voltage VH and the first current IL of the first power source P1 are blocked.

[0043] The first relay R1 has a first withstand voltage greater than the first voltage VH of the first power source P1. Thus, a failure of the first relay R1 caused by the voltage load of the first power source P1 is suppressed. Preferably, the first withstand voltage is greater than the first voltage VH. The first withstand voltage may also be greater than 1 times and less than 100 times the first voltage VH. Preferably, the first withstand voltage is less than 10 times the first voltage VH. The first withstand voltage may be greater than 500V and less than 3000V.

[0044] The first withstand voltage can have a value belonging to any range of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0045] The first relay R1 has a first rated current greater than the first current IL of the first power source P1. This prevents a failure of the first relay R1 caused by the current load of the first power source P1. The first rated current is preferably greater than the first current IL.

[0046] The first rated current may be greater than 1 and less than 100 times the first current IL. The first rated current is preferably less than 10 times the first current IL. The first rated current may also be less than 1A. The first rated current is preferably less than 1A. The first rated current is particularly preferably greater than 0.01 mA and less than 100 mA.

[0047] The first rated current may have a value belonging to any range of 0.01 mA to 0.05 mA, 0.05 mA to 0.1 mA, 0.1 mA to 0.5 mA, 0.5 mA to 1 mA, 1 mA to 5 mA, 5 mA to 10 mA, 10 mA to 25 mA, 25 mA to 50 mA, 50 mA to 75 mA, and 75 mA to 100 mA. The first rated current may also be 1 mA or more. The first rated current may also be 5 mA or less.

[0048] The semiconductor test device 1 includes: a second relay R2 electrically mounted between the first node portion N1 and the second power supply P2. For example, the second relay R2 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and a contact (electromagnetic contact). The second relay R2 is composed of a low withstand voltage and high current type relay capable of withstanding the load caused by the second power supply P2. That is, the second relay R2 is configured not to become a high voltage and high current in consideration of safety, as is the second power supply P2.

[0049] The second relay R2 is configured to switch between a conducting state (on state) in which the second power source P2 is electrically connected to the first node portion N1, and a non-conducting state (off state) in which the second power source P2 is electrically disconnected from the first node portion N1. In the conducting state of the second relay R2, the second voltage VL and the second current IH of the second power source P2 are applied to the semiconductor switch device SW via the first node portion N1. In the non-conducting state of the second relay R2, the second voltage VL and the second current IH of the second power source P2 are blocked.

[0050] The second relay R2 has a second withstand voltage greater than the second voltage VL of the second power supply P2. Thus, a failure of the second relay R2 caused by the voltage load of the second power supply P2 is suppressed. The second withstand voltage is preferably greater than the second voltage VL. The second withstand voltage may also be less than the first voltage VH of the first power supply P1 (the first withstand voltage of the first relay R1). The second withstand voltage may also be less than the first voltage VH of the first power supply P1 (the first withstand voltage of the first relay R1).

[0051] The second withstand voltage may also be more than 1 times and less than 100 times the second voltage VL. The second withstand voltage is preferably less than 10 times the second voltage VL. The second withstand voltage may be more than 0.1V and less than 100V. The second withstand voltage may have a value belonging to any range of more than 0.1V and less than 1V, more than 1V and less than 5V, more than 5V and less than 10V, more than 10V and less than 25V, more than 25V and less than 50V, more than 50V and less than 75V, and more than 75V and less than 100V. The second withstand voltage is preferably more than 1V. The second withstand voltage is particularly preferably more than 10V.

[0052] The second relay R2 has a second rated current greater than the second current IH of the second power supply P2. Thus, a malfunction of the second relay R2 caused by the current load of the second power supply P2 is suppressed. The second rated current is preferably greater than the second current IH. The second rated current may also be greater than 1 times and less than 100 times the second current IH. The second rated current is preferably less than 10 times the second current IH.

[0053] The second rated energizing current may also be 1A or more and 200A or less. The second rated energizing current is preferably greater than 1A. The second rated energizing current may have a value belonging to any range of 1A or more and 5A or less, 5A or more and 10A or less, 10A or more and 25A or less, 25A or more and 50A or less, 50A or more and 75A or less, 75A or more and 100A or less, 100A or more and 125A or less, 125A or more and 150A or less, 150A or more and 175A or less, and 175A or more and 200A or less. The second rated energizing current is preferably 10A or more.

[0054] The semiconductor test device 1 includes: a third relay R3 connected in parallel with the second relay R2. For example, the third relay R3 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and a contact (electromagnetic contact). The third relay R3 is composed of a high-voltage, low-current type relay that can withstand the load caused by the first power supply P1. That is, the third relay R3 is configured not to become a high voltage and a large current in consideration of safety, just like the first power supply P1.

[0055] The third relay R3 is configured to switch between a conducting state (on state) that short-circuits the second relay R2, and a non-conducting state (off state) that does not short-circuit the second relay R2. The third relay R3 has a third withstand voltage that is greater than the second voltage VL of the second power supply P2. That is, the third withstand voltage is greater than the second withstand voltage of the second relay R2. Thus, a failure of the third relay R3 caused by the voltage load of the second power supply P2 is suppressed. The third withstand voltage is particularly preferably greater than the second voltage VL of the second power supply P2 (the second withstand voltage of the second relay R2).

[0056] In this embodiment, the third relay R3 fixes the voltage between the terminals of the second relay R2 to zero voltage by short-circuiting the second relay R2, thereby protecting the second relay R2 from the voltage load caused by the first voltage VH of the first power supply P1. Therefore, the third withstand voltage is greater than the first voltage VH of the first power supply P1. As a result, the failure of the third relay R3 caused by the voltage load of the first power supply P1 is suppressed. The third withstand voltage is preferably greater than the first voltage VH.

[0057] The third withstand voltage may be greater than 1 time and less than 100 times the first voltage VH. The third withstand voltage is preferably less than 10 times the first voltage VH. The third withstand voltage may be greater than 500V and less than 3000V.

[0058] The third withstand voltage can have a value belonging to any range of 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, 2500V to 2750V, and 2750V to 3000V.

[0059] The third withstand voltage may be greater than or equal to the first withstand voltage of the first relay R1. The third withstand voltage may be less than the first withstand voltage. The third withstand voltage may be substantially equal to the first withstand voltage. In this case, the third relay R3 may be formed of the same type of relay as the first relay R1.

[0060] The third relay R3 has a third rated current greater than the first current IL of the first power source P1. Thus, a failure of the first relay R1 caused by the current load of the first power source P1 is suppressed. The third rated current is preferably greater than the first current IL. The third rated current is less than the second current IH of the second power source P2.

[0061] The third rated current may be more than 1 times and less than 100 times the first current IL. The third rated current is preferably less than 10 times the first current IL. The third rated current is particularly preferably less than 2 times the first current IL. The third rated current may also be less than 1A. The third rated current is preferably less than 1A. The third rated current is particularly preferably more than 0.01mA and less than 100mA.

[0062] The third rated current may have a value belonging to any range of 0.01 mA to 0.05 mA, 0.05 mA to 0.1 mA, 0.1 mA to 0.5 mA, 0.5 mA to 1 mA, 1 mA to 5 mA, 5 mA to 10 mA, 10 mA to 25 mA, 25 mA to 50 mA, 50 mA to 75 mA, and 75 mA to 100 mA. The third rated current may be 1 mA or more. The third rated current may be 5 mA or less.

[0063] The semiconductor test device 1 includes: a fourth relay R4 connected in parallel with the second power supply P2. For example, the fourth relay R4 may be an electromagnetic relay including an electromagnetic coil (electromagnet) and a contact (electromagnetic contact). The fourth relay R4 is composed of a low-voltage and high-current type relay that can withstand the load caused by the second power supply P2. That is, the fourth relay R4 is configured not to become a high voltage and a high current in consideration of safety, as is the case with the second power supply P2.

[0064] The fourth relay R4 is configured to switch between a conducting state (on state) that short-circuits the second power supply P2, and a non-conducting state (off state) that does not short-circuit the second power supply P2. The fourth relay R4 has a fourth withstand voltage that is greater than the second voltage VL of the second power supply P2. Thus, a failure of the fourth relay R4 caused by the voltage load of the second power supply P2 is suppressed. The fourth withstand voltage is preferably greater than the second voltage VL. The fourth withstand voltage may also be less than the first voltage VH of the first power supply P1 (the first withstand voltage of the first relay R1). The fourth withstand voltage may also be less than the first voltage VH of the first power supply P1 (the first withstand voltage of the first relay R1).

[0065] The fourth withstand voltage may be more than 1 times and less than 100 times the second voltage VL. The fourth withstand voltage is preferably less than 10 times the second voltage VL. The fourth withstand voltage may be more than 0.1V and less than 100V. The fourth withstand voltage may have a value belonging to any range of more than 0.1V and less than 1V, more than 1V and less than 5V, more than 5V and less than 10V, more than 10V and less than 25V, more than 25V and less than 50V, more than 50V and less than 75V, and more than 75V and less than 100V. The fourth withstand voltage is preferably more than 1V. The fourth withstand voltage is particularly preferably more than 10V.

[0066] The fourth withstand voltage may be greater than or equal to the second withstand voltage of the second relay R2. The fourth withstand voltage may be less than the second withstand voltage. The fourth withstand voltage may be substantially equal to the second withstand voltage. In this case, the fourth relay R4 may be formed of the same type of relay as the second relay R2.

[0067] The fourth relay R4 has a fourth rated current greater than the first current IL of the first power supply P1. The fourth rated current is greater than the first current IL. The fourth rated current is preferably greater than the second current IH of the second power supply P2. Thus, a malfunction of the fourth relay R4 caused by the current load of the second power supply P2 is suppressed. The fourth rated current is particularly preferably greater than the second current IH.

[0068] The fourth rated current may be 1 to 100 times the second current IH. The fourth rated current may be 10 to 100 times the second current IH. The fourth rated current may be 500 mA to 200 A.

[0069] The fourth rated current may have a value belonging to any range of 500 mA or more and 1 A or less, 1 A or more and 5 A or less, 5 A or more and 10 A or less, 10 A or more and 25 A or less, 25 A or more and 50 A or less, 50 A or more and 75 A or less, 75 A or more and 100 A or less, 100 A or more and 125 A or less, 125 A or more and 150 A or less, 150 A or more and 175 A or less, and 175 A or more and 200 A or less. The fourth rated current may be 1 A or more. The fourth rated current may also be greater than 1 A. The fourth rated current is preferably 10 A or less.

[0070] The semiconductor test device 1 includes: a semiconductor rectifier device D electrically mounted between a first node portion N1 and a second power source P2. The semiconductor rectifier device D may also be referred to as a "rectifier", "diode" or "protection diode". The semiconductor rectifier device D may include at least one of a pn junction diode, a pin junction diode, a Schottky barrier diode and a fast recovery diode.

[0071] The semiconductor rectifier D may include a Si diode including a Si single crystal. The semiconductor rectifier D preferably includes a wide bandgap semiconductor diode including a single crystal of a wide bandgap semiconductor. The semiconductor rectifier D particularly preferably includes a SiC diode including a SiC single crystal. In this embodiment, the semiconductor rectifier D includes a SiC Schottky barrier diode.

[0072] The semiconductor rectifier device D has a second breakdown voltage VB2 greater than the second voltage VL of the second power supply P2. The second breakdown voltage VB2 is preferably greater than the second voltage VL. The second breakdown voltage VB2 is preferably greater than the first voltage VH of the first power supply P1. The second breakdown voltage VB2 is particularly preferably greater than the first voltage VH.

[0073] The second breakdown voltage VB2 is preferably greater than the first breakdown voltage VB1 of the semiconductor switch device SW. The second breakdown voltage VB2 may be greater than the first breakdown voltage VB1. The second breakdown voltage VB2 may be greater than 500V. The second breakdown voltage VB2 may be less than 3000V.

[0074] The second breakdown voltage VB2 can have a value belonging to any range of above 500V and below 750V, above 750V and below 1000V, above 1000V and below 1250V, above 1250V and below 1500V, above 1500V and below 1750V, above 1750V and below 2000V, above 2000V and below 2250V, above 2250V and below 2500V, above 2500V and below 2750V, and above 2750V and below 3000V.

[0075] The semiconductor rectifier device D is electrically mounted between the second relay R2 and the second power supply P2. The semiconductor rectifier device D is mounted in a direction that is reverse biased relative to the voltage application direction of the first power supply P1. Specifically, the semiconductor rectifier device D includes: an anode electrically connected to the second power supply P2, and a cathode electrically connected to the second relay R2. From another perspective, in the semiconductor rectifier device D, the anode is electrically connected to the fourth relay R4, and the cathode is electrically connected to the third relay R3.

[0076] The semiconductor test device 1 includes a measuring unit MU electrically connected to the semiconductor switch device SW. For example, the measuring unit MU includes an ammeter for measuring the current flowing in the semiconductor switch device SW and a voltmeter for measuring the voltage between the terminals of the semiconductor switch device SW.

[0077] The ammeter can be assembled at a position capable of measuring the current of the semiconductor switch device SW. For example, the ammeter can be electrically installed between the first node portion N1 and the first terminal T1 of the semiconductor switch device SW. For example, the ammeter can also be electrically installed between the second node portion N2 and the second terminal T2 of the semiconductor switch device SW.

[0078] The voltmeter can be assembled at a position where the voltage between the terminals of the semiconductor switch device SW can be measured. For example, the voltmeter can also be connected between the first node portion N1 and the second node portion N2 (i.e., the first terminal T1 and the second terminal T2 of the semiconductor switch device SW). The measurement unit MU can be configured to measure the resistance value (on-resistance Ron) based on the voltage and current between the terminals.

[0079] The semiconductor test device 1 includes a drive unit DU electrically connected to a control terminal T3 of a semiconductor switch device SW. The drive unit DU includes a drive IC (gate drive circuit). The drive unit DU generates a control signal for controlling the on and off of the semiconductor switch device SW, and outputs the control signal to the control terminal T3 of the semiconductor switch device SW. The control signal includes an on signal for controlling the semiconductor switch device SW to be in an on state, and an off signal for controlling the semiconductor switch device SW to be in an off state.

[0080] The semiconductor test device 1 includes a control unit CU electrically connected to a first power source P1, a second power source P2, a first relay R1, a second relay R2, a third relay R3, a fourth relay R4, a drive unit DU, and a measurement unit MU. For example, the control unit CU includes a CPU, a memory (such as a ROM, a RAM, a nonvolatile memory, etc.), and an electronic circuit, and is configured to control the first power source P1, the second power source P2, the first relay R1, the second relay R2, the third relay R3, the fourth relay R4, the drive unit DU, and the measurement unit MU according to a predetermined program (process) stored in the memory.

[0081] The control unit CU is constructed as follows: when implementing a high voltage and low current test, the semiconductor switch device SW is controlled to be in an off state, the first power supply P1 is controlled to be in an on state, the second power supply P2 is controlled to be in an off state, the first relay R1 is controlled to be in a conducting state, the second relay R2 is controlled to be in a non-conducting state, the third relay R3 is controlled to be in a conducting state, and the fourth relay R4 is controlled to be in a conducting state.

[0082] The control unit CU is constructed as follows: when implementing a low voltage and high current test, the semiconductor switch device SW is controlled to be in an on state, the first power supply P1 is controlled to be in an off state, the second power supply P2 is controlled to be in an on state, the first relay R1 is controlled to be in a non-conducting state, the second relay R2 is controlled to be in a conducting state, the third relay R3 is controlled to be in a non-conducting state, and the fourth relay R4 is controlled to be in a non-conducting state.

[0083] Below, refer to Figure 2 and Figure 3 , a high voltage and low current test and a low voltage and high current test for the semiconductor switch device SW are explained. Figure 2 1 is a circuit diagram showing the circuit operation of the semiconductor test apparatus 1 during a high voltage and low current test. Figure 3 1 is a circuit diagram showing the circuit operation of the semiconductor test device 1 during a low voltage and high current test. Figure 2 and Figure 3 In the figure, for the sake of clarity, the energized parts are represented by bold lines, and the non-energized parts are represented by dotted lines.

[0084] High voltage and low current test (refer to Figure 2 ) and low voltage and high current test (refer to Figure 3 ) is arbitrary. Therefore, it is possible to perform a high voltage and low current test (see Figure 2 ) and then conduct a low voltage and high current test (refer to Figure 3 ), and can also be used in low voltage and high current tests (refer to Figure 3 ) and then conduct a high voltage and low current test (refer to Figure 2 ). High voltage and low current test (refer to Figure 2 ) can be performed once or multiple times. Low voltage and high current test (refer to Figure 3 ) can be implemented once or multiple times.

[0085] Reference Figure 2 , a high voltage and low current test is performed on the semiconductor switch device SW in the off state. When the high voltage and low current test is performed, the semiconductor switch device SW is controlled to be in the off state, the first power supply P1 (first power switch S1) is controlled to be in the on state, the second power supply P2 (second power switch S2) is controlled to be in the off state, the first relay R1 is controlled to be in the on state, the second relay R2 is controlled to be in the non-conducting state, the third relay R3 is controlled to be in the on state, and the fourth relay R4 is controlled to be in the on state.

[0086] Thus, a parallel circuit is formed in which the semiconductor switch device SW and the semiconductor rectifier device D are respectively connected in parallel to the first power supply P1. In this parallel circuit, the first voltage VH is applied to the semiconductor switch device SW in the off state, and a leakage current Ioff is generated in the semiconductor switch device SW from the first terminal T1 to the second terminal T2. The leakage current Ioff is measured by the measuring unit MU (ammeter). Here, the leakage current Ioff is measured in a voltage range less than the first breakdown voltage VB1 of the semiconductor switch device SW. The leakage current Ioff is smaller than the first current IL.

[0087] The third relay R3, the fourth relay R4 and the semiconductor rectifier device D constitute a protection circuit that protects the second relay R2 and the second power supply P2 from the load caused by the first power supply P1. The third relay R3 short-circuits the second relay R2 and fixes the voltage between the terminals of the second relay R2 to zero voltage. Therefore, the failure of the second relay R2 caused by the first voltage VH is suppressed.

[0088] On the other hand, the first voltage VH is applied to the third relay R3 as a load, but the third relay R3 has a third withstand voltage higher than the first voltage VH. Therefore, the failure of the third relay R3 caused by the first voltage VH is suppressed. The fourth relay R4 short-circuits the second power supply P2 in the disconnected state and fixes the voltage between the terminals of the second power supply P2 to the ground voltage. Therefore, the failure of the second power supply P2 caused by the first voltage VH is suppressed.

[0089] The semiconductor rectifier device D is electrically connected to the first node portion N1 via the third relay R3, and is electrically connected to the second node portion N2 via the fourth relay R4. The semiconductor rectifier device D is electrically installed between the third relay R3 and the fourth relay R4, and forms a voltage drop from the first voltage VH to the ground voltage toward the third relay R3 and the fourth relay R4. That is, the fourth relay R4 (the terminal voltage of the second power supply P2) is regarded as being fixed to zero voltage by the semiconductor rectifier device D.

[0090] The first voltage VH is applied to the semiconductor rectifier device D as a load, but the semiconductor rectifier device D has a second breakdown voltage VB2 that is higher than the first voltage VH. Therefore, the semiconductor rectifier device D does not fail due to the first voltage VH. In addition, the semiconductor rectifier device D does not break down due to the first voltage VH, so the current path between the third relay R3 and the fourth relay R4 is blocked by the semiconductor rectifier device D. As a result, the failure of the device caused by the breakdown of the semiconductor rectifier device D (for example, the failure of the second power supply P2, the third relay R3, the fourth relay R4, etc.) is suppressed.

[0091] In this method, the second relay R2 and the fourth relay R4 are of the low-voltage and high-current type and can have relatively large parasitic capacitance, but the current path is blocked between the second relay R2 and the fourth relay R4 by the semiconductor rectifier device D. Therefore, the deterioration of the detection accuracy of the leakage current Ioff caused by the parasitic capacitance of the second relay R2 and the parasitic capacitance of the fourth relay R4 is suppressed.

[0092] Reference Figure 3 , a low voltage and high current test is performed on the semiconductor switch device SW in the on state. When the low voltage and high current test is performed, the semiconductor switch device SW is controlled to be in the on state, the first power supply P1 (first power switch S1) is controlled to be in the off state, the second power supply P2 (second power switch S2) is controlled to be in the on state, the first relay R1 is controlled to be in the non-conducting state, the second relay R2 is controlled to be in the conducting state, the third relay R3 is controlled to be in the non-conducting state, and the fourth relay R4 is controlled to be in the non-conducting state.

[0093] Thus, a series circuit (closed circuit) including the second power supply P2, the second relay R2, the semiconductor rectifier device D, and the semiconductor switch device SW is formed (see the bold line). The series circuit does not include the first power supply P1, the first relay R1, the third relay R3, and the fourth relay R4 (see the dotted line). The second current IH (large current) from the second power supply P2 is given to the semiconductor switch device SW via the second relay R2 that allows large current and the semiconductor rectifier device D.

[0094] As a result, an on-current Ion (drain-source current) flows from the first terminal T1 toward the second terminal T2 in the semiconductor switch device SW. The on-resistance Ron of the semiconductor switch device SW is measured by the measuring unit MU. For example, the on-resistance Ron is calculated by dividing the voltage between the terminals of the semiconductor switch device SW and the on-current Ion of the semiconductor switch device SW (Ron=V1 / Ion). The first relay R1, the third relay R3, and the fourth relay R4 are in a non-conducting state, so a malfunction caused by the second current IH can be avoided.

[0095] As described above, the semiconductor test device 1 includes: a first node portion N1, a second node portion N2, a first power supply P1 for a high voltage and low current test, a second power supply P2 for a low voltage and high current test, a first relay R1, a second relay R2, a third relay R3, and a fourth relay R4. The first node portion N1 is configured to be electrically connected to one end of the semiconductor switch device SW. The second node portion N2 is configured to be electrically connected to the other end of the semiconductor switch device SW.

[0096] The first power supply P1 is configured to generate a first voltage VH and a first current IL. The second power supply P2 is configured to generate a second voltage VL lower than the first voltage VH and a second current IH larger than the first current IL. The first relay R1 has a first withstand voltage greater than the first voltage VH and is electrically installed between the first node portion N1 and the first power supply P1. The second relay R2 has a second withstand voltage greater than the second voltage VL and is electrically installed between the first node portion N1 and the second power supply P2.

[0097] The third relay R3 has a third withstand voltage greater than the first voltage VH and is connected in parallel with the second relay R2. The fourth relay R4 has a fourth withstand voltage greater than the second voltage VL and is connected in parallel with the second power supply P2. This structure can provide a semiconductor switch device SW that can be subjected to a high voltage and low current test (see Figure 2 ) and low voltage and high current test (refer to Figure 3 ) of a semiconductor testing device 1.

[0098] The semiconductor tester 1 preferably includes a semiconductor rectifier device D electrically mounted between the second power source P2 and the second relay R2. According to this configuration, the withstand voltage of the semiconductor rectifier device D can be used to protect the second power source P2 from the load caused by the first power source P1.

[0099] The semiconductor test device 1 is effective in testing power semiconductor devices used in a high load (high voltage and high current) environment. The semiconductor test device 1 is effective in testing wide bandgap semiconductor switch devices. The semiconductor test device 1 is particularly effective in testing SiC semiconductor switch devices.

[0100] The following indicates Figure 1 An example of one embodiment of a semiconductor rectifier device D is shown. Figure 4 Yes means Figure 1 A top view of a semiconductor rectifier device D is shown. Figure 5 It is along Figure 4 The cross-sectional view of the line VV is shown. Figure 4 and Figure 5 The semiconductor rectifier device D includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).

[0101] Chip 2 may be a Si chip including a Si single crystal. That is, semiconductor rectifier device D may also be a "Si semiconductor rectifier device". Chip 2 is preferably composed of a wide-bandgap semiconductor chip including a single crystal of a wide-bandgap semiconductor. That is, semiconductor rectifier device D is preferably a "wide-bandgap semiconductor rectifier device".

[0102] In this embodiment, chip 2 is a SiC chip including hexagonal SiC single crystal. That is, semiconductor rectifier device D is a "SiC semiconductor rectifier device". Hexagonal SiC single crystal has a variety of polymorphs including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example in which chip 2 includes 4H-SiC single crystal is shown, but the selection of other polymorphs is not excluded.

[0103] The chip 2 has: a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed into a quadrilateral shape when viewed from the top in the normal direction Z thereof (hereinafter referred to as "when viewed from the top"). The normal direction Z is also the thickness direction of the chip 2. The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.

[0104] In this case, it is preferred that the first principal surface 3 is formed by the silicon surface of the SiC single crystal, and the second principal surface 4 is formed by the carbon surface of the SiC single crystal. The first principal surface 3 and the second principal surface 4 may have an offset angle that is tilted at a predetermined angle in a predetermined offset direction relative to the c-plane. The offset direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The offset angle may exceed 0° and be less than 10°. The offset angle is preferably less than 5°.

[0105] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3, and are opposed to each other in a second direction Y intersecting (specifically, orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y, and are opposed to each other in the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0106] The semiconductor rectifier device D includes: an n-type first semiconductor region 6 formed in a region (surface portion) on the first main surface 3 side in the chip 2. The first semiconductor region 6 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is composed of an epitaxial layer (SiC epitaxial layer).

[0107] The semiconductor rectifier device D includes an n-type second semiconductor region 7 formed in a region (surface portion) on the second main surface 4 side in the chip 2. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 in the chip 2. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0108] In this embodiment, the second semiconductor region 7 is composed of a semiconductor substrate (SiC substrate). That is, the chip 2 has a stacked structure including a substrate and an epitaxial layer. The thickness of the second semiconductor region 7 can be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 can also be smaller than the thickness of the first semiconductor region 6. Of course, a method without the second semiconductor region 7 (semiconductor substrate) can also be adopted. That is, the chip 2 can have a single-layer structure composed of an epitaxial layer.

[0109] The semiconductor rectifier device D includes an n-type diode region 8 formed on the surface portion of the first main surface 3. In this embodiment, the diode region 8 is formed using the first semiconductor region 6. The diode region 8 is formed inside the first main surface 3 at a distance from the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3. The diode region 8 is formed in a polygonal shape (a quadrilateral shape in this embodiment) when viewed from above.

[0110] The semiconductor rectifier device D includes a p-type (second conductivity type) protection zone 9 formed on the surface of the first main surface 3. The protection zone 9 is formed on the surface of the first semiconductor region 6 at intervals from the periphery of the first main surface 3 to the inside. The protection zone 9 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) surrounding the diode region 8 when viewed from above. The protection zone 9 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the periphery side of the first main surface 3.

[0111] The semiconductor rectifier device D includes: a main surface insulating film 10 selectively covering the first main surface 3. The main surface insulating film 10 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 10 has a single-layer structure including a silicon oxide film. The main surface insulating film 10 preferably includes a silicon oxide film composed of an oxide of the chip 2.

[0112] The main surface insulating film 10 has a contact opening 11 that exposes the inner edge of the diode region 8 and the protection zone 9. The contact opening 11 can be formed into a polygonal shape (a quadrilateral in this embodiment) extending along the periphery of the diode region 8 (the inner edge of the protection zone 9) when viewed from above. The main surface insulating film 10 covers the first main surface 3 in a manner connected to the periphery of the first main surface 3. Of course, the main surface insulating film 10 can also cover the first main surface 3 from the periphery of the first main surface 3 to the inside at intervals in a manner that exposes the periphery of the first main surface 3.

[0113] The semiconductor rectifier device D includes a first polarity terminal 12 that forms a Schottky junction with the diode region 8. The first polarity terminal 12 is formed as an anode terminal (anode of the semiconductor rectifier device D). The first polarity terminal 12 enters the contact opening 11 from above the main surface insulating film 10 and is electrically connected to the inner edge of the diode region 8 and the protection region 9. The first polarity terminal 12 is arranged to be spaced inward from the periphery of the first main surface 3, and is formed in a polygonal shape (a quadrilateral shape in this embodiment) along the periphery of the first main surface 3 when viewed from above.

[0114] The first polarity terminal 12 has a stacked structure including a first electrode film 13 and a second electrode film 14 stacked in order from the first main surface 3. The first electrode film 13 is a Schottky barrier electrode film that forms a Schottky junction with the diode region 8. The material of the first electrode film 13 is arbitrary as long as a Schottky junction can be formed.

[0115] The first electrode film 13 may be composed of a metal film containing at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt) and gold (Au). Of course, the first electrode film 13 may also be composed of an alloy film containing at least one of these metal species. In this embodiment, the first electrode film 13 is composed of a Ti film.

[0116] The second electrode film 14 is composed of a Cu-based metal film or an Al-based metal film, and has a thickness greater than that of the first electrode film 13. The second electrode film 14 may also include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 14 has a single-layer structure composed of an AlCu alloy film.

[0117] The semiconductor rectifier device D includes an upper insulating film 15 covering the first polarity terminal 12. The upper insulating film 15 is preferably thicker than the first polarity terminal 12. The thickness of the upper insulating film 15 is preferably smaller than the thickness of the chip 2. The upper insulating film 15 is formed to be spaced inward from the periphery of the first main surface 3 and covers the periphery of the first polarity terminal 12. The upper insulating film 15 divides the pad opening 16 on the inner side of the chip 2 and divides the block 17 on the peripheral side of the chip 2.

[0118] The pad opening 16 exposes the inner side of the first polarity terminal 12. The pad opening 16 is formed into a polygonal shape (a quadrilateral in this embodiment) along the periphery of the first polarity terminal 12 when viewed from above. The block 17 extends along the periphery of the chip 2 to expose the main surface insulating film 10. Of course, in the case where the main surface insulating film 10 exposes the periphery of the first main surface 33, the block 17 can also expose the periphery of the first main surface 33.

[0119] In this embodiment, the upper insulating film 15 has a stacked structure including an inorganic insulating film 18 (inorganic film) and an organic insulating film 19 (organic film) stacked in sequence from the first polarity terminal 12 side. The inorganic insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 18 preferably includes an insulating material different from that of the main surface insulating film 10. In this embodiment, the inorganic insulating film 18 has a single-layer structure including a silicon nitride film. The inorganic insulating film 18 preferably has a thickness smaller than that of the first polarity terminal 12.

[0120] The organic insulating film 19 is thicker than the inorganic insulating film 18 and covers the inorganic insulating film 18. The organic insulating film 19 preferably has a thickness greater than that of the first polarity terminal 12. The organic insulating film 19 is preferably composed of a photosensitive resin film. The organic insulating film 19 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0121] The organic insulating film 19 may expose the inner edge of the inorganic insulating film 18 in the pad opening 16. The organic insulating film 19 may expose the outer edge of the inorganic insulating film 18 in the block 17. The organic insulating film 19 may expose one or both of the inner edge and the outer edge of the inorganic insulating film 18.

[0122] In this embodiment, the organic insulating film 19 exposes both the inner and outer edges of the inorganic insulating film 18 and defines the pad opening 16 and the block 17 together with the inorganic insulating film 18. Of course, the organic insulating film 19 may cover both the inner and outer edges of the inorganic insulating film 18.

[0123] The semiconductor rectifier device D includes a second polarity terminal 20 covering the second main surface 4. The second polarity terminal 20 is formed as a cathode terminal (cathode of the semiconductor rectifier device D). The second polarity terminal 20 is electrically connected to the second semiconductor region 7 exposed from the second main surface 4. The second polarity terminal 20 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0124] For example, the second polarity terminal 20 may have a stacked structure including a Ti film, a Ni film, and an Au film stacked in sequence from the second main surface 4 side. For example, the second polarity terminal 20 may have a stacked structure including an AlSi alloy film, a Ti film, a Ni film, and an Au film stacked in sequence from the second main surface 4 side. For example, the second polarity terminal 20 may have a stacked structure including a Ti film, a Ni film, an Au film, and an Ag film stacked in sequence from the second main surface 4 side.

[0125] The following indicates Figure 1 An example of one embodiment of the semiconductor switch device SW is shown. Figure 6 It is a plan view showing an example of a semiconductor switch device SW (device under test). Figure 7 It is along Figure 6 A cross-sectional view taken along line VII-VII is shown. Figure 8 Yes means Figure 6 FIG. 3 is a top view of the internal structure (transistor structure 38 ) of the semiconductor switch device SW shown. Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX is shown.

[0126] Reference Figure 6 to Figure 9 The semiconductor switch device SW includes a chip 32 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 32 may be a Si chip including a Si single crystal. That is, the semiconductor switch device SW may be a "Si semiconductor switch device". The chip 32 is preferably composed of a wide-gap semiconductor chip including a single crystal of a wide-gap semiconductor. That is, the semiconductor switch device SW is preferably a "wide-gap semiconductor switch device".

[0127] In this embodiment, the chip 32 is a SiC chip including a hexagonal SiC single crystal. That is, the semiconductor switch device SW is a "SiC semiconductor switch device". The hexagonal SiC single crystal has a variety of polymorphs including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example in which the chip 32 includes a 4H-SiC single crystal is shown, but the selection of other polymorphs is not excluded.

[0128] The chip 32 has: a first main surface 33 on one side, a second main surface 34 on the other side, and first to fourth side surfaces 35A to 35D connecting the first main surface 33 and the second main surface 34. The first main surface 33 and the second main surface 34 are formed into a quadrilateral shape when viewed from the normal direction Z thereof (hereinafter referred to as "when viewed from the top"). The normal direction Z is also the thickness direction of the chip 32. The first main surface 33 and the second main surface 34 are preferably formed by the c-plane of the SiC single crystal.

[0129] In this case, it is preferred that the first principal surface 33 is formed by the silicon surface of the SiC single crystal, and the second principal surface 34 is formed by the carbon surface of the SiC single crystal. The first principal surface 33 and the second principal surface 34 may have an offset angle that is tilted at a predetermined angle in a predetermined offset direction relative to the c-plane. The offset direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The offset angle may exceed 0° and be less than 10°. The offset angle is preferably less than 5°.

[0130] The first side surface 35A and the second side surface 35B extend in a first direction X along the first main surface 33, and are opposed to each other in a second direction Y intersecting (specifically, orthogonal to) the first direction X. The third side surface 35C and the fourth side surface 35D extend in the second direction Y, and are opposed to each other in the first direction X. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0131] The semiconductor switch device SW includes: an n-type first semiconductor region 36 formed in a region (surface portion) on the first main surface 33 side in the chip 32. The first semiconductor region 36 is electrically connected to the first node portion N1. The first semiconductor region 36 is formed in a layer extending along the first main surface 33 and exposed from the first main surface 33 and the first to fourth side surfaces 35A to 35D. In this embodiment, the first semiconductor region 36 is composed of an epitaxial layer (SiC epitaxial layer).

[0132] The semiconductor switch device SW includes an n-type second semiconductor region 37 formed in a region (surface portion) on the second main surface 34 side in the chip 32. The second semiconductor region 37 has a higher n-type impurity concentration than the first semiconductor region 36, and is electrically connected to the first semiconductor region 36 in the chip 32. The second semiconductor region 37 is formed in a layer extending along the second main surface 34, and is exposed from the second main surface 34 and the first to fourth side surfaces 35A to 35D.

[0133] In this embodiment, the second semiconductor region 37 is composed of a semiconductor substrate (SiC substrate). That is, the chip 32 has a stacked structure including a substrate and an epitaxial layer. The thickness of the second semiconductor region 37 can be greater than the thickness of the first semiconductor region 36. The thickness of the second semiconductor region 37 can be less than the thickness of the first semiconductor region 36. Of course, a method without the second semiconductor region 37 (semiconductor substrate) can also be adopted. That is, the chip 32 can also have a single-layer structure composed of an epitaxial layer.

[0134] The semiconductor switch device SW includes a transistor structure 38 formed on the first main surface 33. In the present embodiment, the transistor structure 38 is a trench gate type. The transistor structure 38 will be described in detail below.

[0135] The semiconductor switch device SW includes: a p-type body region 39 formed on the surface of the first main surface 33. The body region 39 forms a pn junction as a body diode BD with the first semiconductor region 36, and is electrically connected to the second node portion N2. The body region 39 may also be called a "base region" or a "channel region". The body region 39 is formed to be spaced apart from the bottom of the first semiconductor region 36 toward the first main surface 33 side, and extends in a layered manner on the surface of the first main surface 33. The body region 39 may also be formed on the inner side of the first main surface 33 at a distance from the periphery of the first main surface 33.

[0136] The semiconductor switch device SW includes an n-type source region 40 formed in the surface portion of the body region 39. The source region 40 is electrically connected to the second node portion N2. The source region 40 may be formed in the inner portion of the first main surface 33 at a distance from the periphery of the first main surface 33.

[0137] The source region 40 has a higher n-type impurity concentration than the first semiconductor region 36. The source region 40 is formed to be spaced from the bottom of the body region 39 toward the first main surface 33 and extends in a layered manner on the surface of the first main surface 33. The source region 40 forms a channel with the first semiconductor region 36 in the body region 39.

[0138] The semiconductor switch device SW includes: a plurality of first trench structures 41 formed on the first main surface 33. The first trench structure 41 is electrically connected to the drive unit DU and is given a control signal from the drive unit DU. The first trench structure 41 controls the inversion and non-inversion of the channel. The first trench structure 41 can also be called a "trench gate structure".

[0139] The first trench structure 41 penetrates the body region 39 and the source region 40 to reach the first semiconductor region 36. The plurality of first trench structures 41 may be arranged at intervals in the first direction X in a plan view, and each may be formed in a strip shape extending in the second direction Y. The plurality of first trench structures 41 are formed at intervals from the bottom of the first semiconductor region 36 toward the first main surface 33 side.

[0140] Each first trench structure 41 includes: a first trench 42, a first insulating film 43 and a first buried electrode 44. The first trench 42 is formed on the first main surface 33, dividing the wall surface of the first trench 42. The first insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film. In this embodiment, the first insulating film 43 has a single-layer structure including a silicon oxide film. The first insulating film 43 preferably includes a silicon oxide film composed of an oxide of the chip 32.

[0141] The first insulating film 43 covers the wall surface of the first trench 42. The first buried electrode 44 may include conductive polysilicon. The first buried electrode 44 is buried in the first trench 42 via the first insulating film 43. The first buried electrode 44 faces the channel via the first insulating film 43.

[0142] The semiconductor switch device SW includes: a plurality of second trench structures 45 formed on the first main surface 33. The plurality of second trench structures 45 are electrically connected to the second node portion N2. The second trench structure 45 may also be referred to as a "trench source structure". The plurality of second trench structures 45 are respectively formed in the region between two adjacent first trench structures 41.

[0143] The plurality of second trench structures 45 may be formed in a strip shape extending in the second direction Y in a plan view. The plurality of second trench structures 45 penetrate the body region 39 and the source region 40 to reach the first semiconductor region 36. The plurality of second trench structures 45 are formed to be spaced apart from the bottom of the first semiconductor region 36 toward the first main surface 33.

[0144] In this embodiment, the plurality of second groove structures 45 are formed deeper than the plurality of first groove structures 41. The depth of the second groove structure 45 can be greater than 1.5 times and less than 4 times (preferably less than 2.5 times) the depth of the first groove structure 41. Of course, the depth of the second groove structure 45 can also be substantially equal to the depth of the first groove structure 41.

[0145] Each second trench structure 45 includes a second trench 46, a second insulating film 47, and a second buried electrode 48. The second trench 46 is formed in the first main surface 33 and defines the wall surface of the second trench 46. The second insulating film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0146] In this embodiment, the second insulating film 47 has a single-layer structure including a silicon oxide film. The second insulating film 47 preferably includes a silicon oxide film composed of an oxide of the chip 32. The second insulating film 47 covers the wall surface of the second trench 46. The second buried electrode 48 may include conductive polysilicon. The second buried electrode 48 is buried in the second trench 46 via the second insulating film 47.

[0147] The semiconductor switch device SW includes: a plurality of p-type contact regions 49 formed in regions along the plurality of second trench structures 45 in the chip 32. Each contact region 49 has a higher p-type impurity concentration than the body region 39. Each contact region 49 covers the sidewalls and bottom wall of each second trench structure 45 and is electrically connected to the body region 39 at the surface portion of the first main surface 3.

[0148] The semiconductor switch device SW includes: a plurality of p-type well regions 50 formed in regions along the plurality of second trench structures 45 in the chip 32. Each well region 50 has a p-type impurity concentration higher than that of the body region 39 and lower than that of the contact region 49. Each well region 50 covers the corresponding second trench structure 45 via the corresponding contact region 49. Each well region 50 covers the sidewalls and bottom wall of each second trench structure 45 and is electrically connected to the body region 39 at the surface portion of the first main surface 3.

[0149] The semiconductor switch device SW includes: a main surface insulating film 51 that selectively covers the first main surface 33. In this embodiment, the main surface insulating film 51 includes a first main surface insulating film 52 and a second main surface insulating film 53. The first main surface insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first main surface insulating film 52 has a single-layer structure composed of a silicon oxide film. The first main surface insulating film 52 preferably includes a silicon oxide film composed of an oxide of the chip 32.

[0150] The first main surface insulating film 52 is connected to the first insulating film 43 and the second insulating film 47, and exposes the first buried electrode 44 and the second buried electrode 48. In this embodiment, the first main surface insulating film 52 covers the peripheral portion of the first main surface 33 in a manner connected to the peripheral edge of the first main surface 33. Of course, the main surface insulating film 51 can also expose the peripheral portion of the first main surface 33.

[0151] The second main surface insulating film 53 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the second main surface insulating film 53 includes a silicon oxide film. The second main surface insulating film 53 has a thickness greater than that of the first main surface insulating film 52 and covers the first main surface insulating film 52. The second main surface insulating film 53 covers the plurality of first trench structures 41 and the plurality of second trench structures 45.

[0152] In this embodiment, the second main surface insulating film 53 covers the peripheral portion of the first main surface 33 via the first main surface insulating film 52 in a manner connected to the peripheral portion of the first main surface 33. Of course, when the first main surface insulating film 52 exposes the peripheral portion of the first main surface 33, the second main surface insulating film 53 may also expose the peripheral portion of the first main surface 33.

[0153] The semiconductor switch device SW includes a gate terminal 54 disposed on the main surface insulating film 51. The gate terminal 54 is formed as a control terminal T3 of the semiconductor switch device SW. The gate terminal 54 has a stacked structure including a first electrode film 55 and a second electrode film 56 stacked in sequence from the first main surface 33 (main surface insulating film 51) side. The first electrode film 55 includes a Ti-based metal film. The first electrode film 55 may have a single-layer structure or a stacked structure including at least one of a Ti film and a TiN film.

[0154] The second electrode film 56 is composed of a Cu-based metal film or an Al-based metal film, and has a thickness greater than that of the first electrode film 55. The second electrode film 56 may also include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the second electrode film 56 has a single-layer structure composed of an AlCu alloy film.

[0155] In this embodiment, the gate terminal 54 is arranged in a region close to the central portion of one side (the third side surface 35C in this embodiment) of the first main surface 33 when viewed from above. The arrangement position of the gate terminal 54 is arbitrary. The gate terminal 54 may also be arranged at a corner of the first main surface 33 when viewed from above. The gate terminal 54 may also be arranged at the central portion of the first main surface 33 when viewed from above. In this embodiment, the gate terminal 54 is formed into a polygonal shape (specifically, a quadrilateral shape) when viewed from above.

[0156] The semiconductor switch device SW includes a source terminal 57 disposed on the main surface insulating film 51 at a distance from the gate terminal 54. The source terminal 57 is formed as a second terminal T2 of the semiconductor switch device SW. The source terminal 57 has a stacked structure including a first electrode film 55 and a second electrode film 56 stacked in sequence from the first main surface 33 (main surface insulating film 51) side, similarly to the gate terminal 54.

[0157] In this embodiment, the source terminal 57 is formed in a polygonal shape having a recessed portion along the gate terminal 54 when viewed from above. Of course, the source terminal 57 may also be formed in a quadrilateral shape when viewed from above. In the case where the gate terminal 54 is arranged in the central portion of the first main surface 33 when viewed from above, the source terminal 57 may also surround the gate terminal 54 when viewed from above. The source terminal 57 penetrates the main surface insulating film 51 and is electrically connected to the body region 39, the source region 40, and the plurality of second trench structures 45.

[0158] The semiconductor switch device SW includes a gate wiring 58 extending from a gate terminal 54 to the main surface insulating film 51. The gate wiring 58, like the gate terminal 54, has a stacked structure including a first electrode film 55 and a second electrode film 56 stacked in order from the first main surface 33 (main surface insulating film 51).

[0159] The gate wiring 58 extends along the first to fourth side surfaces 35A to 35D in a manner that surrounds the source terminal 57 (the inner side portion of the first main surface 33) from multiple directions when viewed from above. The gate wiring 58 is formed in a strip shape extending along the periphery of the first main surface 33 in a manner that intersects (specifically, is orthogonal to) the ends of the multiple first trench structures 41 when viewed from above. The gate wiring 58 penetrates the main surface insulating film 51 and is electrically connected to the multiple first trench structures 41.

[0160] The semiconductor switch device SW includes an upper insulating film 59 that selectively covers the gate terminal 54, the source terminal 57, and the gate wiring 58. The upper insulating film 59 is preferably thicker than the gate terminal 54 and the source terminal 57. The thickness of the upper insulating film 59 is preferably smaller than the thickness of the chip 32. The upper insulating film 59 is formed at intervals from the periphery of the first main surface 33 to the inside, and covers the periphery of the gate terminal 54, the periphery of the source terminal 57, and the entire area of ​​the gate wiring 58.

[0161] The upper insulating film 59 includes a gate pad opening 60 that exposes the inner portion of the gate terminal 54, and a source pad opening 61 that exposes the inner portion of the source terminal 57. In this embodiment, the gate pad opening 60 is divided into a polygonal shape (specifically, a quadrilateral shape) along the periphery of the gate terminal 54 when viewed from above. In this embodiment, the source pad opening 61 is divided into a polygonal shape along the periphery of the source terminal 57 when viewed from above.

[0162] The upper insulating film 59 defines a block 62 on the peripheral side of the chip 32. The block 62 extends along the periphery of the first main surface 33 to expose the main surface insulating film 51. Of course, when the main surface insulating film 51 exposes the peripheral portion of the first main surface 33, the block 62 may also expose the peripheral portion of the first main surface 33.

[0163] In this embodiment, the upper insulating film 59 has a stacked structure including an inorganic insulating film 63 (inorganic film) and an organic insulating film 64 (organic film) stacked in sequence from the first main surface 33 side. The inorganic insulating film 63 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film 63 preferably includes an insulating material different from that of the main surface insulating film 51. In this embodiment, the inorganic insulating film 63 has a single-layer structure including a silicon nitride film. The inorganic insulating film 63 preferably has a thickness smaller than that of the gate terminal 54 (source terminal 57).

[0164] The organic insulating film 64 is thicker than the inorganic insulating film 63 and covers the inorganic insulating film 63. The organic insulating film 64 preferably has a thickness greater than that of the gate terminal 54 (source terminal 57). The organic insulating film 64 is preferably composed of a photosensitive resin film. The organic insulating film 64 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0165] The organic insulating film 64 may expose the edge (gate side edge) of the inorganic insulating film 63 in the gate pad opening 60. The organic insulating film 64 may also expose the edge (source side edge) of the inorganic insulating film 63 in the source pad opening 61. The organic insulating film 64 may also expose the edge (street side edge) of the inorganic insulating film 63 in the block 62. Of course, the organic insulating film 64 may also cover the entire area of ​​the inorganic insulating film 63.

[0166] The organic insulating film 64 may expose at least one or all of the gate side edge portion, the source side edge portion, and the street side edge portion. In this embodiment, the organic insulating film 64 exposes all of the gate side edge portion, the source side edge portion, and the street side edge portion, and divides the gate pad opening 60, the source pad opening 61, and the street block 62 together with the inorganic insulating film 63. Of course, the organic insulating film 64 may also cover all of the gate side edge portion, the source side edge portion, and the street side edge portion.

[0167] The semiconductor switch device SW includes a drain terminal 65 covering the second main surface 34. The drain terminal 65 is formed as a first terminal T1 of the semiconductor switch device SW. The drain terminal 65 is formed as a drain electrode and is electrically connected to the second semiconductor region 37 exposed from the second main surface 34. The drain terminal 65 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0168] For example, the drain terminal 65 may have a stacked structure including a Ti film, a Ni film, and an Au film stacked in sequence from the second main surface 34 side. For example, the drain terminal 65 may also have a stacked structure including an AlSi alloy film, a Ti film, a Ni film, and an Au film stacked in sequence from the second main surface 34 side. For example, the drain terminal 65 may also have a stacked structure including a Ti film, a Ni film, an Au film, and an Ag film stacked in sequence from the second main surface 34 side.

[0169] The above embodiment has been described, but the embodiment can also be implemented in other ways. For example, in the above embodiment, a single semiconductor test device 1 is shown, but a semiconductor test module including a plurality of semiconductor test devices 1 can also be used. According to this module, a high voltage and low current test and a low voltage and high current test can be simultaneously performed on a plurality of semiconductor switch devices SW.

[0170] Regarding the semiconductor switch device SW (see Figure 6 to Figure 9), a p-type second semiconductor region 37 may be used instead of the n-type second semiconductor region 37. In this case, the semiconductor switch device SW includes an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET. The specific structure in this case is obtained by replacing the "source" of the MISFET with the "emitter" of the IGBT and replacing the "drain" of the MISFET with the "collector" of the IGBT in the above description.

[0171] In the above embodiments, the structure in which the first conductivity type is n-type and the second conductivity type is p-type is described. However, in each of the above embodiments, the structure in which the first conductivity type is p-type and the second conductivity type is n-type may also be adopted. The specific structure in this case is obtained by replacing the n-type region with the p-type region and the p-type region with the n-type region in the above description and the accompanying drawings.

[0172] The following are examples of features extracted from the specification and the accompanying drawings. The alphanumeric characters in parentheses indicate corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor test device" involved in the following clauses may also be referred to as a "characteristic test device" or a "semiconductor inspection device" as required.

[0173] [A1] A semiconductor test device (1), comprising: a first node portion (N1) electrically connected to one end (T1) of a semiconductor switch device (SW); a second node portion (N2) electrically connected to the other end (T2) of the semiconductor switch device (SW); a first power supply (P1) for high voltage and low current, which generates a first voltage (VH) and a first current (IL); a second power supply (P2) for low voltage and high current, which generates a second voltage (VL) lower than the first voltage (VH) and a second current (IH) larger than the first current (IL); a first relay (R1), It has a withstand voltage higher than the first voltage (VH) and is electrically installed between the first node portion (N1) and the first power supply (P1); a second relay (R2) has a withstand voltage higher than the second voltage (VL) and is electrically installed between the first node portion (N1) and the second power supply (P2); a third relay (R3) has a withstand voltage higher than the first voltage (VH) and is connected in parallel with the second relay (R2); and a fourth relay (R4) has a withstand voltage higher than the second voltage (VL) and is connected in parallel with the second power supply (P2).

[0174] [A2] The semiconductor testing device (1) according to A1, wherein:

[0175] When a high voltage and low current test is performed on the semiconductor switch device (SW), the first power supply (P1) is controlled to be in an on state, the second power supply (P2) is controlled to be in an off state, the first relay (R1) is controlled to be in a conducting state, the second relay (R2) is controlled to be in a non-conducting state, the third relay (R3) is controlled to be in a conducting state, and the fourth relay (R4) is controlled to be in a conducting state.

[0176] [A3] The semiconductor testing device (1) according to A1 or A2, wherein:

[0177] When a low voltage and high current test is performed on the semiconductor switch device (SW), the first power supply (P1) is controlled to be in an off state, the second power supply (P2) is controlled to be in an on state, the first relay (R1) is controlled to be in a non-conducting state, the second relay (R2) is controlled to be in a conducting state, the third relay (R3) is controlled to be in a non-conducting state, and the fourth relay (R4) is controlled to be in a non-conducting state.

[0178] [A4] The semiconductor testing device (1) according to any one of A1 to A3, wherein:

[0179] The first voltage (VH) is lower than a breakdown voltage (VB1) of the semiconductor switching device (SW).

[0180] [A5] The semiconductor testing device (1) according to any one of A1 to A4, wherein:

[0181] The first voltage (VH) is 500V or more.

[0182] [A6] The semiconductor testing device (1) according to any one of A1 to A5, wherein:

[0183] The first current (IL) is 1A or less.

[0184] [A7] The semiconductor testing device (1) according to A6, wherein:

[0185] The first current (IL) is less than 100 mA.

[0186] [A8] The semiconductor testing device (1) according to any one of A1 to A7, wherein:

[0187] The second voltage (VL) is 100V or less.

[0188] [A9] The semiconductor testing device (1) according to any one of A1 to A8, wherein:

[0189] The second current (IH) is 1A or more.

[0190] [A10] The semiconductor testing device (1) according to A9, wherein:

[0191] The second current (IH) is greater than or equal to 10A.

[0192] [A11] The semiconductor testing device (1) according to any one of A1 to A10, wherein:

[0193] The semiconductor switch device (SW) has a breakdown voltage (VB1) of 500V or more.

[0194] [A12] The semiconductor testing device (1) according to any one of A1 to A11, wherein:

[0195] The semiconductor switch device (SW) includes a wide bandgap semiconductor.

[0196] [A13] The semiconductor testing device (1) according to any one of A1 to A12, wherein:

[0197] The semiconductor switch device (SW) includes an insulated gate transistor.

[0198] [A14] The semiconductor testing device (1) according to A13, wherein:

[0199] The transistor is of trench gate type.

[0200] [A15] The semiconductor testing device (1) according to any one of A1 to A14, wherein:

[0201] The semiconductor testing device (1) further comprises: a semiconductor rectifier device (D) electrically installed between the second power source (P2) and the second relay (R2).

[0202] [A16] The semiconductor testing device (1) according to A15, wherein:

[0203] The semiconductor rectifier device (D) has a breakdown voltage (VB2) that is greater than or equal to the second voltage (VL).

[0204] [A17] The semiconductor testing device (1) according to A16, wherein:

[0205] The breakdown voltage (VB2) of the semiconductor rectifier device (D) is greater than or equal to the breakdown voltage (VB1) of the semiconductor switch device (SW).

[0206] [A18] The semiconductor testing device (1) according to A16 or A17, wherein:

[0207] The breakdown voltage (VB2) of the semiconductor rectifier device (D) is 500V or more.

[0208] [A19] The semiconductor testing device (1) according to any one of A15 to A18, wherein:

[0209] The semiconductor rectifying device (D) includes a wide bandgap semiconductor.

[0210] [A20] The semiconductor testing device (1) according to any one of A15 to A19, wherein:

[0211] The semiconductor rectifying device (D) includes a Schottky barrier diode.

[0212] The embodiments are described in detail above, but they are only specific examples to clarify the technical contents. Various technical ideas extracted from this specification are not limited to the order of description in the specification, the order of the embodiments, etc., and they can be combined appropriately.

[0213] Explanation of symbols

[0214] 1 Semiconductor test equipment

[0215] SW Semiconductor Switch Device

[0216] The first terminal (one end) of the semiconductor switch device T1

[0217] The second terminal (the other end) of the semiconductor switch device T2

[0218] Control terminals of the T3 semiconductor switching device

[0219] N1 First node

[0220] N2 Second node

[0221] P1 First Power Supply

[0222] VH First voltage

[0223] IL First current

[0224] P2 Second power supply

[0225] VL Second voltage

[0226] IH Second current

[0227] R1 First relay

[0228] R2 Second relay

[0229] R3 Third relay

[0230] R4 Fourth relay

[0231] D Semiconductor rectifier device

[0232] VB1 first breakdown voltage

[0233] VB2 second breakdown voltage.

Claims

1. A semiconductor testing device, comprising: a first node portion electrically connected to one end of the semiconductor switch device; a second node portion electrically connected to the other end of the semiconductor switch device; A first power supply for high voltage and low current, which generates a first voltage and a first current; a second power supply for low voltage and high current, which generates a second voltage lower than the first voltage and a second current larger than the first current; a first relay having a withstand voltage higher than the first voltage and electrically installed between the first node portion and the first power source; a second relay having a withstand voltage equal to or higher than the second voltage and electrically installed between the first node portion and the second power supply; a third relay having a withstand voltage higher than the first voltage and connected in parallel with the second relay; as well as The fourth relay has a withstand voltage higher than the second voltage and is connected in parallel with the second power supply.

2. The semiconductor testing device according to claim 1, wherein: When implementing a high voltage and low current test, the first power supply is controlled to be in an on state, the second power supply is controlled to be in an off state, the first relay is controlled to be in a conducting state, the second relay is controlled to be in a non-conducting state, the third relay is controlled to be in a conducting state, and the fourth relay is controlled to be in a conducting state.

3. The semiconductor testing device according to claim 1 or 2, wherein: When implementing a low voltage and high current test, the first power supply is controlled to be in an off state, the second power supply is controlled to be in an on state, the first relay is controlled to be in a non-conducting state, the second relay is controlled to be in a conducting state, the third relay is controlled to be in a non-conducting state, and the fourth relay is controlled to be in a non-conducting state.

4. The semiconductor testing device according to any one of claims 1 to 3, wherein: The first voltage is lower than a breakdown voltage of the semiconductor switching device.

5. The semiconductor testing device according to any one of claims 1 to 4, wherein: The first voltage is greater than 500V.

6. The semiconductor testing device according to any one of claims 1 to 5, wherein: The first current is less than 1A.

7. The semiconductor testing device according to claim 6, wherein: The first current is less than 100 mA.

8. The semiconductor testing device according to any one of claims 1 to 7, wherein: The second voltage is 100V or less.

9. The semiconductor testing device according to any one of claims 1 to 8, wherein: The second current is greater than 1A.

10. The semiconductor testing device according to claim 9, wherein: The second current is greater than 10A.

11. The semiconductor testing device according to any one of claims 1 to 10, wherein: The semiconductor switch device has a breakdown voltage of 500V or more.

12. The semiconductor testing device according to any one of claims 1 to 11, wherein: The semiconductor switch device includes a wide bandgap semiconductor.

13. The semiconductor testing device according to any one of claims 1 to 12, wherein: The semiconductor switching device includes an insulated gate transistor.

14. The semiconductor testing device according to claim 13, wherein: The transistor is of trench gate type.

15. The semiconductor testing device according to any one of claims 1 to 14, wherein: The semiconductor testing device further includes: a semiconductor rectifying device electrically installed between the second power source and the second relay.

16. The semiconductor testing device according to claim 15, wherein: The semiconductor rectifier device has a breakdown voltage equal to or higher than the second voltage.

17. The semiconductor testing device according to claim 16, wherein: The breakdown voltage of the semiconductor rectifier device is greater than or equal to the breakdown voltage of the semiconductor switch device.

18. The semiconductor testing device according to claim 16 or 17, wherein: The breakdown voltage of the semiconductor rectifier device is 500V or more.

19. The semiconductor testing device according to any one of claims 15 to 18, wherein: The semiconductor rectifying device includes a wide bandgap semiconductor.

20. The semiconductor testing device according to any one of claims 15 to 19, wherein: The semiconductor rectifying device includes a Schottky barrier diode.

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