Display substrate and display device

Abstract

A display substrate comprises a substrate (10) and a gate drive circuit arranged on the substrate (10), the gate drive circuit comprises: a plurality of cascaded shift register circuits (GOA), each shift register circuit (GOA) comprises: a plurality of NOT gate circuits, each NOT gate circuit comprises: a first control transistor and a second control transistor, the first control transistor and the second control transistor have different transistor types. The arrangement modes of transistors of at least two NOT gate circuits in a plurality of NOT gate circuits of the shift register circuit (GOA) are different.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 21, 2023, with application number 202310907887.1 and invention name “Display substrate, driving method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device.

[0007] On the one hand, this embodiment provides a display substrate, comprising: a substrate and a gate driving circuit arranged on the substrate, the gate driving circuit including a multi-stage shift register circuit, the shift register circuit including an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor including a first bottom gate layer, a first top gate layer, and an active layer at least partially located between the first bottom gate layer and the first top gate layer; the oxide switching transistor including a second bottom gate layer, a second top gate layer, and an active layer at least partially located between the second bottom gate layer and the second top gate layer; the first bottom gate layer and the second bottom gate layer are independent of each other; the first bottom gate layer and the first top gate layer are coupled; the second bottom gate layers of at least some of the oxide switching transistors in the plurality of oxide switching transistors are coupled.

[0008] In some exemplary embodiments, all second bottom gate layers included in the plurality of oxide switching transistors are coupled.

[0009] In some exemplary embodiments, the multiple oxide switching transistors are divided into at least two transistor groups, each transistor group includes at least one oxide switching transistor; the second bottom gate layers of the multiple oxide switching transistors belonging to the same transistor group are coupled; and the second bottom gate layers of the oxide switching transistors belonging to different transistor groups are independent of each other.

[0010] In some exemplary embodiments, the shift register circuit includes a plurality of functional modules, and oxide switching transistors in the same functional module are divided into the same transistor group.

[0011] In some exemplary embodiments, the second bottom gate layer included in the oxide switching transistors in the at least some of the oxide switching transistors extends along a first direction or a second direction, where the first direction intersects the second direction. The display substrate further includes at least one bottom gate connection portion coupled to the second bottom gate layer included in the corresponding oxide switching transistor.

[0012] In some exemplary embodiments, the at least some oxide switching transistors are divided into a first transistor group and a second transistor group. The display substrate includes a first bottom gate connection portion and a second bottom gate connection portion, the first bottom gate connection portion being coupled to the second bottom gate layer included in the oxide switching transistors in the first transistor group, and the second bottom gate connection portion being coupled to the second bottom gate layer included in the oxide switching transistors in the second transistor group. The first bottom gate connection portion and the second bottom gate connection portion are coupled via a first conductive connection portion; alternatively, the first bottom gate connection portion and the second bottom gate connection portion are independent of each other.

[0013] In some exemplary embodiments, the first bottom gate connection portion and the second bottom gate layer to which it is coupled are connected as an integral structure, and the second bottom gate connection portion and the second bottom gate layer to which it is coupled are connected as an integral structure. The first bottom gate connection portion and the second bottom gate connection portion are provided in the same layer and the same material, and the first bottom gate connection portion and the first conductive connection portion are provided in different layers.

[0014] In some exemplary embodiments, the display substrate further includes: a second gate metal layer and a first source-drain metal layer; the first bottom gate connection portion is located in the second gate metal layer, and the first conductive connection portion is located in the first source-drain metal layer.

[0015] In some exemplary embodiments, when the first bottom gate connection portion and the second bottom gate connection portion are independent of each other, the display substrate further includes: a first signal line and a second signal line, the first signal line is coupled to the first bottom gate connection portion, and the second signal line is coupled to the second bottom gate connection portion.

[0016] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of at least a portion of the oxide switching transistors in the previous shift register circuit is coupled to the second bottom gate layer of at least a portion of the oxide switching transistors in the next shift register circuit; or, the second bottom gate layer of the oxide switching transistor in the previous shift register circuit is independent of the second bottom gate layer of the oxide switching transistor in the next shift register circuit.

[0017] In some exemplary embodiments, the second bottom gate layer of at least part of the oxide switching transistors in the previous shift register circuit and the second bottom gate layer of at least part of the oxide switching transistors in the next shift register circuit are connected as an integrated structure.

[0018] In some exemplary embodiments, the second bottom gate layer of at least a portion of the oxide switching transistors in the previous shift register circuit is coupled to the second bottom gate layer of at least a portion of the oxide switching transistors in the next shift register circuit through a second conductive connection portion, and the second conductive connection portion is arranged in a different layer from the second bottom gate layer.

[0019] In some exemplary embodiments, the shift register circuit further includes: a light-shielding layer and a plurality of low-temperature polysilicon transistors, wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of the low-temperature polysilicon transistor on the substrate; and at least a portion of the light-shielding layer of the shift register circuit is coupled.

[0020] In some exemplary embodiments, the light shielding layer included in at least a portion of the shift register circuit is coupled via a third conductive connection portion, and the third conductive connection portion is provided in a different layer from the light shielding layer.

[0021] In some exemplary embodiments, the display substrate further includes a nineteenth conductive connection portion, the nineteenth conductive connection portion being coupled to the first bottom gate layer and the first top gate layer, respectively.

[0022] On the other hand, this embodiment provides a display device, including the display substrate as described above.

[0023] On the other hand, this embodiment provides a driving method for a display substrate, which is used to drive the display substrate as described above. The driving method includes: providing the same signal to the first bottom gate layer and the first top gate layer to control the oxide output transistor to be turned on or off; independently providing signals to the second bottom gate layer and the second top gate layer of the oxide switching transistor, wherein the second bottom gate layers of at least some of the multiple oxide switching transistors are coupled to receive the same signal.

[0024] On the other hand, this embodiment provides a display substrate, comprising: a substrate and a gate drive circuit disposed on the substrate, the gate drive circuit comprising: a plurality of cascaded shift register circuits, the shift register circuit comprising: a plurality of NOT gate circuits, the NOT gate circuit comprising: a first control transistor and a second control transistor, the first control transistor and the second control transistor being of different transistor types; a gate of the first control transistor connected to a gate of the second control transistor, serving as a first input of the NOT gate circuit; a second electrode of the first control transistor connected to a second electrode of the second control transistor, serving as an output of the NOT gate circuit; a first electrode of the first control transistor serving as a second input of the NOT gate circuit; a first electrode of the second control transistor serving as a third input of the NOT gate circuit, the second and third inputs of the NOT gate circuit being configured to receive different voltage signals. At least two of the plurality of NOT gate circuits in the shift register circuit have transistors arranged differently.

[0025] In some exemplary embodiments, at least one NOT gate circuit among the plurality of NOT gate circuits satisfies one of the following:

[0026] The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit extend in the same direction, and the arrangement direction of the first control transistor and the second control transistor is the same as the extending direction of the active layer;

[0027] The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit extend in the same direction, and the arrangement direction of the first control transistor and the second control transistor intersects with the extending direction of the active layer;

[0028] The extension directions of the active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit intersect, and the arrangement direction of the first control transistor and the second control transistor is the same as the extension direction of the active layer of the first control transistor or the second control transistor.

[0029] In some exemplary embodiments, the multiple NOT gate circuits include at least: a first NOT gate circuit and a second NOT gate circuit; the output end of the first NOT gate circuit is connected to the output end of the second NOT gate circuit; the first NOT gate circuit and the second NOT gate circuit are adjacent in the second direction; the transistor arrangement of the first NOT gate circuit is the same as the transistor arrangement of the second NOT gate circuit; the active layer of the first control transistor of the first NOT gate circuit and the active layer of the first control transistor of the second NOT gate circuit are an integrated structure connected to each other.

[0030] In some exemplary embodiments, the second input terminal of the first NOT circuit is connected to the first voltage line via a first transfer transistor, and the second input terminal of the second NOT circuit is connected to the first voltage line via a second transfer transistor. The first transfer transistor, the second transfer transistor, and the first control transistor are of the same transistor type. The active layers of the first control transistor of the first NOT circuit, the first control transistor of the second NOT circuit, the first transfer transistor, and the second transfer transistor are interconnected as an integrated structure, and the orthographic projection of the integrated structure on the substrate is C-shaped or ring-shaped.

[0031] In some exemplary embodiments, the third input terminal of the first NOT circuit is connected to the second voltage line via a third transfer transistor, and the third input terminal of the second NOT circuit is connected to the second voltage line via a fourth transfer transistor. The third transfer transistor, the fourth transfer transistor, and the second control transistor are of the same transistor type. The gate of the third transfer transistor is connected to the gate of the second transfer transistor, and the gate of the fourth transfer transistor is connected to the gate of the first transfer transistor. The active layer of the second control transistor of the first NOT circuit and the active layer of the third transfer transistor are interconnected as a single unit; the active layer of the second control transistor of the second NOT circuit and the active layer of the fourth transfer transistor are interconnected as a single unit.

[0032] In some exemplary embodiments, the plurality of NOT circuits further include a third NOT circuit, wherein a first input terminal of the third NOT circuit is connected to output terminals of the first NOT circuit and the second NOT circuit, and an output terminal of the third NOT circuit is connected to a first input terminal of the second NOT circuit. The third NOT circuit is adjacent to the second NOT circuit in the second direction; and the transistor arrangement of the third NOT circuit is the same as that of the second NOT circuit.

[0033] In some exemplary embodiments, the first input terminal of the third NOT circuit is connected to an integrated structure of active layers of the first control transistor of the first NOT circuit and the first control transistor of the second NOT circuit.

[0034] In some exemplary embodiments, the second electrode of the first control transistor of the third NOT gate circuit and the second electrode of the second control transistor are connected to the gate of the first control transistor of the second NOT gate circuit through different conductive connection portions, and the gate of the second control transistor of the second NOT gate circuit and the second electrode of the second control transistor of the third NOT gate circuit are connected to the gate of the first control transistor of the second NOT gate circuit through the same conductive connection portion.

[0035] In some exemplary embodiments, the plurality of NOT circuits further include: a fourth NOT circuit; a first input terminal of the fourth NOT circuit is connected to the gate of the second transfer transistor, and an output terminal of the fourth NOT circuit is connected to the gate of the first transfer transistor; the transistor arrangement of the fourth NOT circuit is different from the transistor arrangements of the first NOT circuit and the second NOT circuit; the fourth NOT circuit is located on the same side of the first NOT circuit and the second NOT circuit in a first direction; the first direction intersects the second direction.

[0036] In some exemplary embodiments, the first input terminal of the fourth NOT gate circuit of the 2i-1th stage shift register circuit of the gate drive circuit is connected to the first clock signal line, and the first input terminal of the fourth NOT gate circuit of the 2ith stage shift register circuit of the gate drive circuit is connected to the second clock signal line, where i is an integer greater than 0.

[0037] In some exemplary embodiments, the shift register circuit further includes a NAND gate circuit; the NAND gate circuit is connected to at least one NOT gate circuit. The NAND gate circuit includes a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor; the third and fourth control transistors are of the same transistor type, and the fifth and sixth control transistors are of the same transistor type. The gates of the third and fifth control transistors are connected, serving as a first input of the NAND gate circuit; the gates of the fourth and sixth control transistors are connected, serving as a second input of the NAND gate circuit; the first electrode of the third control transistor is connected to the first electrode of the fourth control transistor, serving as a third input of the NAND gate circuit; the second electrode of the third control transistor, the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor are connected, serving as an output of the NAND gate circuit; the first electrode of the fifth control transistor is connected to the second electrode of the sixth control transistor; and the first electrode of the sixth control transistor serves as a fourth input of the NAND gate circuit. The third and fourth inputs of the NAND gate circuit are configured to receive different voltage signals. The third control transistor and the fourth control transistor are located between the fifth control transistor and the sixth control transistor.

[0038] In some exemplary embodiments, the sixth control transistor, the fourth control transistor, the third control transistor and the fifth control transistor are arranged sequentially along the second direction; the gate of the sixth control transistor, the gate of the fourth control transistor, the gate of the third control transistor and the gate of the fifth control transistor are arranged alternately in the second direction.

[0039] In some exemplary embodiments, the active layer of the third control transistor and the active layer of the fourth control transistor are interconnected as an integral structure, and an orthographic projection of the integral structure on the substrate is C-shaped or ring-shaped.

[0040] In some exemplary embodiments, the plurality of NOT gate circuits include a fifth NOT gate circuit and a sixth NOT gate circuit. The input terminal of the sixth NOT gate circuit is connected to the output terminal of the fifth NOT gate circuit, and the output terminal of the sixth NOT gate circuit is connected to the second input terminal of the NAND gate circuit. The fifth NOT gate circuit is adjacent to the sixth NOT gate circuit in a first direction; the fifth NOT gate circuit and the sixth NOT gate circuit are located on the same side of the NAND gate circuit in a second direction; and the first direction intersects the second direction. The transistor arrangement of the fifth NOT gate circuit is the same as that of the sixth NOT gate circuit.

[0041] In some exemplary embodiments, the first control transistor of the fifth NOT gate circuit and the first control transistor of the sixth NOT gate circuit are aligned in the first direction, and the second control transistor of the fifth NOT gate circuit and the second control transistor of the sixth NOT gate circuit are aligned in the first direction.

[0042] In some exemplary embodiments, the plurality of NOT gate circuits further include a seventh NOT gate circuit. The input of the seventh NOT gate circuit is connected to the output of the NAND gate circuit, and the output of the seventh NOT gate circuit serves as a drive output of the shift register circuit. The first control transistor and the second control transistor of the seventh NOT gate circuit are arranged along a second direction, with the first control transistor adjacent to the NAND gate circuit in the first direction, and the first direction intersecting the second direction.

[0043] In some exemplary embodiments, the shift register circuit includes at least: a cascade signal generating circuit, a gating circuit, a voltage maintaining circuit, an output control circuit, and an output circuit; the cascade signal generating circuit includes at least one NOT gate circuit, the output circuit includes at least one NOT gate circuit, the voltage maintaining circuit includes at least one NOT gate circuit, and the output control circuit includes a NAND gate circuit. The cascade signal generating circuit is connected to a cascade input terminal and a cascade output terminal, and is configured to perform a shift operation on a cascade signal provided by a previous-stage shift register circuit received at the cascade input terminal, and to provide a cascade signal of the current-stage shift register circuit to the cascade output terminal. The gating circuit is connected to the gating input terminal, the cascade input terminal, the cascade output terminal, and a third node, and is configured to write the gating input signal provided by the gating input terminal to the third node under the control of the cascade output terminal and the cascade input terminal. The voltage maintaining circuit is connected to the third node, the cascade input terminal, a clock signal terminal, and a fifth node, and is configured to control the potential of the fifth node under the control of the third node, the cascade input terminal, and the clock signal terminal. The output control circuit is connected to the cascade output terminal, the fifth node, and the sixth node, and is configured to perform a NAND operation on the potentials of the cascade output terminal and the fifth node to control the potential of the sixth node. The output circuit is connected to the sixth node and the drive output terminal, and is configured to invert the potential of the sixth node to output a drive signal. The output control circuit is located between the cascade signal generation circuit and the output circuit in a first direction, the gating circuit is adjacent to the cascade signal generation circuit in a second direction, and the voltage maintaining circuit is located between the gating circuit and the output circuit in the first direction and adjacent to the output control circuit in the second direction; the first direction intersects the second direction.

[0044] In some exemplary embodiments, the shift register circuit further includes an initialization circuit connected to an initialization control terminal, the third node, and the cascade output terminal, and configured to initialize the third node and the cascade output terminal under control of the initialization control terminal. The initialization circuit is located on a side of the gating circuit away from the voltage maintaining circuit in the first direction and is adjacent to the cascade signal generating circuit in the second direction.

[0045] In some exemplary embodiments, the gating circuit includes a seventeenth transistor and an eighteenth transistor; the seventeenth and eighteenth transistors are of different transistor types. The gate of the seventeenth transistor is connected to the cascade output terminal, the first electrode of the seventeenth transistor is connected to the gating input terminal, and the second electrode of the seventeenth transistor is connected to the first electrode of the eighteenth transistor; the gate of the eighteenth transistor is connected to the cascade input terminal, and the second electrode of the eighteenth transistor is connected to the third node. The seventeenth and eighteenth transistors are arranged sequentially along the second direction, and the eighteenth transistor is adjacent to the cascade signal generating circuit in the second direction.

[0046] In some exemplary embodiments, the first control transistor is a low-temperature polysilicon transistor, and the second control transistor is an oxide transistor.

[0047] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the base. The first semiconductor layer includes at least an active layer of the first control transistor. The first conductive layer includes at least a gate of the first control transistor. The second conductive layer includes at least a bottom gate of the second control transistor. The second semiconductor layer includes at least an active layer of the second control transistor. The third conductive layer includes at least a top gate of the second control transistor. The fourth conductive layer includes at least a plurality of conductive connection portions connected to the first and second control transistors. The fifth conductive layer includes at least a signal line connected to the shift register circuit.

[0048] In some exemplary embodiments, the shift register circuit includes a plurality of oxide transistors, including an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor is connected to a driver output terminal. The bottom gate of the oxide output transistor is independently provided from the bottom gates of the plurality of oxide switching transistors, and the bottom gate of the oxide output transistor is connected to a top gate. The bottom gates of at least some of the plurality of oxide switching transistors are interconnected and integrally formed.

[0049] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0050] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0051] Summary of the Figures

[0052] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0053] FIG1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0054] FIG2 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0055] 3 is a partial cross-sectional schematic diagram of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0056] FIG4 is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0057] FIG5 is a schematic diagram of the display substrate after the first semiconductor layer is formed in FIG4 ;

[0058] FIG6A is a schematic diagram of the display substrate after the first conductive layer is formed in FIG4 ;

[0059] FIG6B is a schematic diagram of the first conductive layer in FIG6A ;

[0060] FIG7A is a schematic diagram of the display substrate after the second conductive layer is formed in FIG4 ;

[0061] FIG7B is a schematic diagram of the second conductive layer in FIG7A ;

[0062] FIG8A is a schematic diagram of the display substrate after the second semiconductor layer is formed in FIG4 ;

[0063] FIG8B is a schematic diagram of the second semiconductor layer in FIG8A ;

[0064] FIG9A is a schematic diagram of the display substrate after forming the third conductive layer in FIG4 ;

[0065] FIG9B is a schematic diagram of the third conductive layer in FIG9A ;

[0066] 10A and 10B are schematic diagrams of the display substrate after the fifth insulating layer is formed in FIG. 4 ;

[0067] FIG11 is a schematic diagram of the fourth conductive layer in FIG4 ;

[0068] FIG12 is a schematic diagram of a display substrate after forming a seventh insulating layer according to at least one embodiment of the present disclosure;

[0069] FIG13A is a schematic diagram of a display substrate after forming a fifth conductive layer according to at least one embodiment of the present disclosure;

[0070] FIG13B is a schematic diagram of the fifth conductive layer in FIG13A;

[0071] FIG14 is a schematic diagram showing the connection of a bottom gate connection portion according to at least one embodiment of the present disclosure;

[0072] FIG15 is another partial schematic top view of a display substrate according to at least one embodiment of the present disclosure;

[0073] FIG16A is a schematic diagram of the display substrate after the first semiconductor layer is formed in FIG15 ;

[0074] FIG16B is a schematic diagram of the display substrate after the first conductive layer is formed in FIG15 ;

[0075] FIG16C is a schematic diagram of the fourth conductive layer in FIG15;

[0076] FIG17 is another partial schematic top view of a display substrate according to at least one embodiment of the present disclosure;

[0077] FIG18A is a schematic diagram of the display substrate after forming the fourth conductive layer in FIG17;

[0078] FIG18B is a schematic diagram showing connections between the shift register circuit in FIG17 and the first clock signal line and the second clock signal line;

[0079] FIG19 is a schematic diagram illustrating the connection of bottom gate connecting portions of adjacent shift register circuits according to at least one embodiment of the present disclosure;

[0080] FIG20 is another schematic diagram illustrating the connection of bottom gate connection portions of adjacent shift register circuits according to at least one embodiment of the present disclosure;

[0081] FIG21 is another connection diagram of the bottom gate connection portion of the shift register circuit according to at least one embodiment of the present disclosure;

[0082] FIG22A is a schematic diagram of the bottom gate structure in FIG21 ;

[0083] 22B and 22C are schematic diagrams showing the connection relationship of the bottom gate connecting portion in FIG. 21 ;

[0084] FIG23 is a schematic diagram of a light shielding layer according to at least one embodiment of the present disclosure;

[0085] FIG24 is another schematic diagram of a light shielding layer according to at least one embodiment of the present disclosure;

[0086] FIG. 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0087] Details

[0088] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0089] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0090] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0091] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0092] In this specification, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," and "coupled" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meanings of these terms in this disclosure based on the specific circumstances.

[0093] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0094] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0095] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0096] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0097] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0098] In this disclosure, "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" includes both completely identical and substantially the same, and "substantially the same" means that the difference in value is within 10%.

[0099] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0100] The rapid development of OLED display technology has led to a multitude of requirements for display products, including high resolution, narrow bezels, and low power consumption. Partial refresh technology (for example, a portion of the screen refreshes at a high frequency while another portion refreshes at a low frequency) has attracted considerable attention due to its significant benefits in reducing power consumption. Display products using partial refresh technology have a relatively complex gate drive circuit structure, necessitating solutions such as achieving improved drive stability and rationally planning the gate drive circuit's footprint to accommodate narrow bezels.

[0101] This embodiment provides a display substrate and a display device, which can effectively improve the driving stability of the gate driving circuit while reducing power consumption, and can reasonably plan the installation space of the gate driving circuit to save space while taking into account the narrowing of the frame.

[0102] This embodiment provides a display substrate, comprising: a substrate and a gate drive circuit disposed on the substrate. The gate drive circuit comprises: a plurality of cascaded shift register circuits (also referred to as shift register units). The shift register circuit comprises: a plurality of NOT gate circuits. The NOT gate circuit comprises: a first control transistor and a second control transistor, the first control transistor and the second control transistor being of different transistor types. The gate of the first control transistor is connected to the gate of the second control transistor, serving as the first input of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor, serving as the output of the NOT gate circuit; the first electrode of the first control transistor serves as the second input of the NOT gate circuit; and the first electrode of the second control transistor serves as the third input of the NOT gate circuit. The second input and third input of the NOT gate circuit are configured to receive different voltage signals. At least two of the plurality of NOT gate circuits in the shift register circuit have different transistor arrangements.

[0103] In this example, the transistor arrangement of the NOT circuit may include at least one of the following: the positional relationship between the first control transistor and the second control transistor of the NOT circuit, and the relationship between the extension directions of the active layers of the first control transistor and the second control transistor of the NOT circuit. The different transistor arrangements of at least two NOT circuits may include: different positional relationships between the transistors of at least two NOT circuits, such as two transistors of one NOT circuit arranged along a first direction and two transistors of another NOT circuit arranged along a second direction; or different extension directions between the active layers of the transistors of at least two NOT circuits, such as two transistors of one NOT circuit extending in the same direction and two transistors of another NOT circuit extending in intersecting directions; or different positional relationships between the transistors and extension directions of the active layers of at least two NOT circuits, such as two transistors of one NOT circuit arranged along a first direction and the extension directions of the active layers of the two transistors extending in the same direction and two transistors of another NOT circuit arranged along a second direction and the extension directions of the active layers of the two transistors extending in intersecting directions. This embodiment is not limited to this.

[0104] In some examples, the first control transistor may be a low-temperature polysilicon transistor, and the second control transistor may be an oxide transistor. For example, the first control transistor may be a P-type transistor, and the second control transistor may be an N-type transistor. However, this embodiment is not limited to this. In other examples, the second control transistor may be a low-temperature polysilicon transistor, and the first control transistor may be an oxide transistor.

[0105] In some examples, the NOT gate circuit may include: a first input terminal, a second input terminal, a third input terminal, and an output terminal. For example, the second input terminal may receive a first voltage signal, the third input terminal may receive a second voltage signal, and the first voltage signal may be greater than the second voltage signal. This embodiment is not limited to this.

[0106] The display substrate provided in this embodiment can realize a local refresh function by providing a shift register circuit including multiple NOT gate circuits, thereby effectively reducing the power consumption of the display substrate; by adopting different arrangements of transistors of at least two NOT gate circuits of the shift register circuit, occupied space can be saved, thereby facilitating reasonable planning of the setting space of the shift register circuit while taking into account the narrowing of the frame.

[0107] In some exemplary embodiments, at least one NOT gate circuit among the plurality of NOT gate circuits of the shift register circuit may satisfy one of the following:

[0108] The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit extend in the same direction, and the arrangement direction of the first control transistor and the second control transistor is the same as the extending direction of the active layer;

[0109] The active layer of the first control transistor and the active layer of the second control transistor in the NOT gate circuit extend in the same direction, and the arrangement direction of the first control transistor and the second control transistor intersects with the extending direction of the active layer;

[0110] The active layers of the first and second control transistors in the NOT gate circuit extend in intersecting directions, and the first and second control transistors are arranged in the same direction as the active layers of the first or second control transistors. This example utilizes multiple NOT gate structure designs to save space, thereby facilitating the rational planning of the shift register circuit's layout while also minimizing borders.

[0111] The solution of this embodiment is illustrated below through some examples.

[0112] In some examples, the display substrate may include a display area and a non-display area. For example, the non-display area may be a peripheral area located outside the display area. However, this embodiment is not limited to this. For example, the non-display area may be located between adjacent display areas.

[0113] In some examples, the display area may include multiple sub-pixels. A pixel unit within the display area may include three sub-pixels, and the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0114] In some examples, a sub-pixel may include: a pixel circuit (also referred to as a sub-pixel driving circuit) and a light-emitting element connected to the pixel circuit. The shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or in a square pattern. However, this embodiment is not limited to this.

[0115] In some examples, the display area may include at least: a plurality of pixel circuits arranged in an array (i.e., including a plurality of rows of pixel circuits and a plurality of columns of pixel circuits), a plurality of gate lines extending along a first direction (for example, including: a scan line, a reset signal line, a light-emitting control line), and a plurality of data lines and power lines extending along a second direction. The plurality of rows of pixel circuits may be arranged along the second direction, and each row of pixel circuits may include a plurality of pixel circuits arranged along the first direction. The first direction and the second direction may be located in the same plane, and the first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. For example, the first direction may include a horizontal direction, and the second direction may include a vertical direction.

[0116] In some examples, the pixel circuit can be configured to drive the connected light-emitting element. For example, the pixel circuit can be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0117] In some examples, the pixel circuit may include a first type transistor and a second type transistor. The transistor types of the first type transistor and the second type transistor are different. For example, the first type transistor may be a P-type transistor, and the second type transistor may be an N-type transistor. The second type transistor may be, for example, an oxide thin film transistor, and the first type transistor may be, for example, a low temperature polysilicon thin film transistor. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). Low temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low temperature polycrystalline oxide (LTPO+Oxide) display substrate can take advantage of the advantages of both, achieve low frequency driving, reduce power consumption, and improve display quality.

[0118] In some examples, the non-display area may be provided with a timing controller, a data driving circuit, and a gate driving circuit. Among them, the gate driving circuit may be respectively provided on opposite sides of the display area, for example, on the left and right sides of the display area (such as the left border area and the right border area included in the peripheral area); the timing controller and the data driving circuit may be provided on one side of the display area, such as the lower side of the display area (such as the lower border area included in the peripheral area). However, this embodiment is not limited to this. In some examples, the gate driving circuit may be located in the display area.

[0119] In some examples, a data driver circuit can provide data signals to sub-pixels in a display area via data lines. A timing controller can provide drive signals to the data driver circuit and the gate driver circuit. The operations of the gate driver circuit and the data driver circuit can be controlled by the timing controller. The timing controller can provide grayscale data specifying the grayscale to be displayed in the sub-pixel to the data driver circuit. The data driver circuit can provide a data signal with a potential corresponding to the grayscale data of the sub-pixel to the sub-pixel in the row selected by the gate driver circuit via the data line.

[0120] In some examples, the display substrate may include multiple gate drive circuits, such as a gate drive circuit for outputting a scan signal, a gate drive circuit for outputting a light-emitting control signal, and the like. For example, the gate drive circuit for outputting a scan signal may provide a scan signal to a sub-pixel via a scan line, and provide a reset signal to the sub-pixel via a reset signal line; the gate drive circuit for outputting a light-emitting control signal may provide a light-emitting control signal to the sub-pixel via a light-emitting control line. Each gate drive circuit may include multiple cascaded shift register circuits. The output end of each stage of the shift register circuit may be respectively connected to multiple pixel circuits in a corresponding row of pixel circuits, and configured to provide a drive signal (e.g., a scan signal) to the pixel circuit in that row.

[0121] FIG1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. FIG1 may be an equivalent circuit diagram of an n-th stage shift register circuit. Here, n may be a positive integer greater than 1. In some examples, as shown in FIG1 , the shift register circuit provided in this embodiment may include: a cascade signal generating circuit 101, a gating circuit 102, an output control circuit 103, an output circuit 104, a voltage maintaining circuit 105, and an initialization circuit 106.

[0122] In some examples, the cascade signal generating circuit 101 can be electrically connected to a cascade input terminal (also referred to as a first scan signal input terminal) NS(n-1), a clock signal terminal (also referred to as a first clock signal input terminal) CK, a first voltage input terminal (also referred to as a first level signal input terminal) VGH, a second voltage input terminal (also referred to as a second voltage signal input terminal) VGL, and a cascade output terminal (also referred to as a second scan signal input terminal) NS(n), and is configured to perform a shift operation on a cascade signal provided by the n-1th stage shift register circuit received by the cascade input terminal NS(n-1), and output the cascade signal of the nth stage shift register circuit to the cascade output terminal NS(n). The cascade input terminal of the current stage shift register circuit (e.g., the nth stage shift register circuit) is connected to the cascade output terminal of the previous stage shift register circuit (e.g., the n-1th stage shift register circuit). The cascade signal generating circuit 101 of the current level shift register circuit (for example, the nth level shift register circuit) can utilize the cascade signal output by the previous level shift register circuit (for example, the n-1th level shift register circuit) to generate the cascade signal of the current level shift register circuit and provide it to the cascade input end of the next level shift register circuit (for example, the n+1th level shift register circuit).

[0123] In some examples, the gating circuit 102 can be connected to the gating input terminal (also referred to as the shielding signal input terminal) VCT, the cascade input terminal NS(n-1), the cascade output terminal NS(n) and the third node N3, and configured to write the gating input signal provided by the gating input terminal VCT to the third node N3 under the control of the cascade input terminal NS(n-1) and the cascade output terminal NS(n).

[0124] In some examples, the voltage maintenance circuit 105 can be connected to the first voltage input terminal VGH, the second voltage input terminal VGL, the clock signal terminal CK, the cascade input terminal NS(n-1), the third node N3, and the fifth node N5, and is configured to control the potential of the fifth node N5 under the control of the third node N3, the cascade input terminal NS(n-1), and the clock signal terminal CK. The voltage maintenance circuit 105 can be configured to stabilize the gate input signal provided by the gate input terminal VCT and compensate for the transmission loss of the gate input signal.

[0125] In some examples, the output control circuit 103 can be connected to the cascade output terminal NS(n), the fifth node N5, the sixth node N6, the first voltage input terminal VGH, and the second voltage input terminal VGL, and configured to perform a NAND operation on the potentials of the cascade output terminal NS(n) and the fifth node N5 to control the potential of the sixth node N6.

[0126] In some examples, the output circuit 104 can be connected to the sixth node N6, the drive output terminal (also known as the gate drive signal output terminal) NO(n), the first voltage input terminal VGH and the second voltage input terminal VGL, and is configured to invert the potential of the sixth node N6 and output a drive signal.

[0127] In some examples, the initialization circuit 106 can be connected to the initial control terminal (also referred to as the second clock signal input terminal) NCX, the cascade output terminal NS(n), the first voltage input terminal VGH and the third node N3, and is configured to initialize the cascade output terminal NS(n) and the third node N3 under the control of the initial control terminal NCX.

[0128] In some examples, the first voltage input terminal VGH can continuously provide a high-level first voltage signal, and the second voltage input terminal VGL can continuously provide a low-level second voltage signal. The first voltage signal can be greater than the second voltage signal. The first voltage input terminal VGH can be connected to a first voltage line that transmits the first voltage signal, and the second voltage input terminal VGL can be connected to a second voltage line that transmits the second voltage signal. However, this embodiment is not limited to this.

[0129] The “high level” and “low level” mentioned herein are relative, and the voltage values ​​of the “high level” and the “low level” are not limited.

[0130] In some examples, the cascade signal generation circuit 101 may include: a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit. The first control circuit and the second control circuit may be inverter circuits including transmission gates, and the third control circuit and the fourth control circuit may be inverter circuits. The first control circuit, the second control circuit, and the third control circuit are all connected to the second node N2, and the first control circuit, the second control circuit, and the fourth control circuit are all connected to the first node N1.

[0131] In some examples, the first control circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 and the second transistor T2 are of the same transistor type, the third transistor T3 and the fourth transistor T4 are of the same transistor type, and the transistor type of the second transistor T2 is different from the transistor type of the third transistor T3. The first transistor T1 and the second transistor T2 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0132] In some examples, the gate of the first transistor T1 is connected to the first node N1, the first electrode of the first transistor T1 is connected to the first voltage input terminal VGH, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The gate of the second transistor T2 is connected to the cascode input terminal NS(n-1), and the second electrode of the second transistor T2 is connected to the second node N2. The gate of the third transistor T3 is connected to the cascode input terminal NS(n-1), the second electrode of the third transistor T3 is connected to the second node N2, and the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4. The gate of the fourth transistor T4 is connected to the clock signal terminal CK, and the first electrode of the fourth transistor T4 is connected to the second voltage input terminal VGL.

[0133] In some examples, the second control circuit may include: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The fifth transistor T5 and the sixth transistor T6 are of the same transistor type, the seventh transistor T7 and the eighth transistor T8 are of the same transistor type, and the sixth transistor T6 and the seventh transistor T7 are of different transistor types. The fifth transistor T5 and the sixth transistor T6 may be P-type transistors, and the seventh transistor T7 and the eighth transistor T8 may be N-type transistors.

[0134] In some examples, the gate of the fifth transistor T5 is connected to the clock signal terminal CK, the first electrode of the fifth transistor T5 is connected to the first voltage input terminal VGH, and the second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6. The gate of the sixth transistor T6 is connected to the cascade output terminal NS(n), and the second electrode of the sixth transistor T6 is connected to the second node N2. The gate of the seventh transistor T7 is connected to the cascade output terminal NS(n), the second electrode of the seventh transistor T7 is connected to the second node N2, and the first electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8. The gate of the eighth transistor T8 is connected to the first node N1, and the first electrode of the eighth transistor T8 is connected to the second voltage input terminal VGL.

[0135] In some examples, the third control circuit may include: a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 and the tenth transistor T10 may be of different transistor types. The ninth transistor T9 may be a P-type transistor, and the tenth transistor T10 may be an N-type transistor. The gate of the ninth transistor T9 is connected to the second node N2, the first electrode of the ninth transistor T9 is connected to the first voltage input terminal VGH, and the second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 are both connected to the cascade output terminal NS(n). The gate of the tenth transistor T10 is connected to the second node N2, and the first electrode of the tenth transistor T10 is connected to the second voltage input terminal VGL.

[0136] In some examples, the fourth control circuit may include a twenty-seventh transistor T27 and a twenty-eighth transistor T28. The twenty-seventh transistor T27 and the twenty-eighth transistor T28 are of different transistor types. The twenty-seventh transistor T27 may be a P-type transistor, and the twenty-eighth transistor T28 may be an N-type transistor. The gate of the twenty-seventh transistor T27 is connected to the clock signal terminal CK, the first electrode of the twenty-seventh transistor T27 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-seventh transistor T27 and the second electrode of the twenty-eighth transistor T28 are both connected to the first node N1. The gate of the twenty-eighth transistor T28 is connected to the clock signal terminal CK, and the first electrode of the twenty-eighth transistor T28 is connected to the second voltage input terminal VGL.

[0137] In some examples, the gating circuit 102 may include a seventeenth transistor T17 and an eighteenth transistor T18. The seventeenth transistor T17 and the eighteenth transistor T18 may be of different transistor types. The seventeenth transistor T17 may be a P-type transistor, and the eighteenth transistor T18 may be an N-type transistor. The gate of the seventeenth transistor T17 is connected to the cascode output terminal NS(n), the first electrode of the seventeenth transistor T17 is connected to the gating input terminal VCT, and the second electrode of the seventeenth transistor T17 is connected to the first electrode of the eighteenth transistor T18. The gate of the eighteenth transistor T18 is connected to the cascode input terminal NS(n-1), and the second electrode of the eighteenth transistor T18 is connected to the third node N3.

[0138] In some examples, a low-level signal is provided at the cascade output terminal NS(n), the seventeenth transistor T17 is turned on, a high-level signal is provided at the cascade input terminal NS(n-1), the eighteenth transistor T18 is turned on, and the gating input signal provided by the gating input terminal VCT can be written to the third node N3. A high-level signal is provided at the cascade output terminal NS(n), the seventeenth transistor T17 is turned off, or a low-level signal is provided at the cascade input terminal NS(n-1), the eighteenth transistor T18 is turned off, and the gating input signal provided by the gating input terminal VCT cannot be written to the third node N3. The gating circuit of this example implements gating input signal transmission by simultaneously turning on two signals (the cascade signals of the previous stage and the current stage shift register circuit), and can obtain the gating input signal state within a high-low frequency switching cycle.

[0139] In some examples, the output control circuit 103 may include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, and a twenty-fourth transistor T24. The twenty-first transistor T21 and the twenty-second transistor T22 are of the same transistor type, and the twenty-third transistor T23 and the twenty-fourth transistor T24 are of the same transistor type. The twenty-first transistor T21 and the twenty-second transistor T22 may be P-type transistors, and the twenty-third transistor T23 and the twenty-fourth transistor T24 may be N-type transistors. The gate of the twenty-first transistor T21 is connected to the cascade output terminal NS(n), the first electrode of the twenty-first transistor T21 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-first transistor T21 is connected to the sixth node N6. The gate of the twenty-second transistor T22 is connected to the fifth node N5, the first electrode of the twenty-second transistor T22 is connected to the first voltage input terminal VGH, and the second electrode of the twenty-second transistor T22 is connected to the sixth node N6. The gate of the twenty-third transistor T23 is connected to the cascade output terminal NS(n), the second electrode of the twenty-third transistor T23 is connected to the sixth node N6, and the first electrode of the twenty-third transistor T23 is connected to the second electrode of the twenty-fourth transistor T24. The gate of the twenty-fourth transistor T24 is connected to the fifth node N5, and the first electrode of the twenty-fourth transistor T24 is connected to the second voltage input terminal VGL.

[0140] In some examples, the output circuit 104 may include a nineteenth transistor T19 and a twentieth transistor T20. The nineteenth transistor T19 and the twentieth transistor T20 are of different transistor types. The nineteenth transistor T19 may be a P-type transistor, and the twentieth transistor T20 may be an N-type transistor. The gate of the nineteenth transistor T19 is connected to the sixth node N6, the first electrode of the nineteenth transistor T19 is connected to the first voltage input terminal VGH, and the second electrode of the nineteenth transistor T19 and the second electrode of the twenty-first transistor T20 are both connected to the driving output terminal NO(n). The gate of the twentieth transistor T20 is connected to the sixth node N6, and the first electrode of the twentieth transistor T20 is connected to the second voltage input terminal VGL.

[0141] In some examples, the voltage maintaining circuit 105 may include a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a twenty-fifth transistor T25, and a twenty-sixth transistor T26. The twelfth transistor T12, the fourteenth transistor T14, and the twenty-fifth transistor T25 are of the same transistor type, for example, P-type transistors; the thirteenth transistor T13, the fifteenth transistor T15, and the twenty-sixth transistor T26 are of the same transistor type, for example, N-type transistors.

[0142] In some examples, the gate of the twelfth transistor T12 is connected to the third node N3, the first electrode of the twelfth transistor T12 is connected to the first voltage input terminal VGH, and the second electrode of the twelfth transistor T12 is connected to the fourth node N4. The gate of the thirteenth transistor T13 is connected to the third node N3, the second electrode of the thirteenth transistor T13 is connected to the fourth node N4, and the first electrode of the thirteenth transistor T13 is connected to the second voltage input terminal VGL. The gate of the fourteenth transistor T14 is connected to the fourth node N4, the first electrode of the fourteenth transistor T14 is connected to the first voltage input terminal VGH, and the second electrode of the fourteenth transistor T14 is connected to the fifth node N5. The gate of the fifteenth transistor T15 is connected to the fourth node N4, the second electrode of the fifteenth transistor T15 is connected to the fifth node N5, and the first electrode of the fifteenth transistor T15 is connected to the second voltage input terminal VGL. The gate of the twenty-fifth transistor T25 is connected to the cascode input terminal NS(n-1), the first electrode of the twenty-fifth transistor T25 is connected to the third node N3, and the second electrode of the twenty-fifth transistor T25 is connected to the fifth node N5. A gate of the twenty-sixth transistor T26 is connected to the clock signal terminal CK, a first electrode of the twenty-sixth transistor T26 is connected to the third node N3, and a second electrode of the twenty-sixth transistor T26 is connected to the fifth node N5.

[0143] In some examples, because P-type transistors experience threshold voltage loss when transmitting low voltages and N-type transistors experience threshold voltage loss when transmitting high voltages, the absolute value of the potential at the third node N3 decreases. The twelfth to fifteenth transistors T12 to T15 can be used to control the absolute value of the potential at the third node N3 to increase, thereby better controlling the on / off of corresponding transistors in the output circuit 104. The twenty-fifth and twenty-sixth transistors T25 and T26 can control the disconnection between the third node N3 and the fifth node N5 when the seventeenth and eighteenth transistors T17 and T18 of the gating circuit 102 are both turned on, to avoid affecting the potential writing of the third node N3.

[0144] In some examples, the initialization circuit 106 may include an eleventh transistor T11 and a sixteenth transistor T16. The eleventh transistor T11 and the sixteenth transistor T16 are of the same transistor type, for example, both are P-type transistors. The gate of the eleventh transistor T11 is connected to the initial control terminal NCX, the first electrode of the eleventh transistor T11 is connected to the first voltage input terminal VGH, and the second electrode of the eleventh transistor T11 is connected to the cascade output terminal NS(n). The gate of the sixteenth transistor T16 is connected to the initial control terminal NCX, the first electrode of the sixteenth transistor T16 is connected to the first voltage input terminal VGH, and the second electrode of the sixteenth transistor T16 is connected to the third node N3.

[0145] In some examples, when the cascade input terminal NS(n-1) provides a high voltage signal and the cascade output terminal NS(n) outputs a low voltage signal, if the selection input terminal VCT outputs a low voltage signal, then when the cascade output terminal NS(n) outputs a high voltage signal, the output terminal NO(n) is driven to output a low voltage signal; when the cascade input terminal NS(n-1) provides a high voltage signal and the cascade output terminal NS(n) outputs a low voltage signal, if the selection input terminal VCT outputs a high voltage signal, then when the cascade output terminal NS(n) outputs a high voltage signal, the output terminal NO(n) is driven to output a high voltage signal.

[0146] In some examples, the first node N1 may be a connection point of the first transistor T1, the eighth transistor T8, the twenty-seventh transistor T27, and the twenty-eighth transistor T28. The second node N2 may be a connection point of the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10. The third node N3 may be a connection point of the eighteenth transistor T18, the sixteenth transistor T16, the twelfth transistor T12, the thirteenth transistor T13, the twenty-fifth transistor T25, and the twenty-sixth transistor T26. The fourth node N4 may be a connection point of the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15. The fifth node N5 may be a connection point of the fourteenth transistor T14, the fifteenth transistor T15, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-second transistor T22, and the twenty-fourth transistor T24. The sixth node N6 may be a connection point of the twenty-first transistor T21 , the twenty-second transistor T22 , the twenty-third transistor T23 , the nineteenth transistor T19 , and the twentieth transistor T20 .

[0147] In this example, the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5, and the sixth node N6 do not represent actual components but rather represent junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to junctions of related electrical connections in the circuit diagram.

[0148] In some examples, the drive signal provided by the drive output terminal NO(n) of the shift register circuit of this example can be configured to be transmitted to the gate of an N-type transistor in a pixel circuit within the display area, serving as a control signal for controlling whether the N-type transistor in the pixel circuit is turned on. For example, by controlling the conduction or disconnection of the N-type transistor in the pixel circuit, the pixel brightness can be refreshed. Therefore, when it is desired to prevent some pixels from being refreshed, it is sufficient to ensure that the N-type transistor in the pixel circuit is disconnected.

[0149] In some examples, the shift register circuit of this example may include twenty-eight transistors, including fifteen P-type transistors and thirteen N-type transistors. The P-type transistors may be low-temperature polysilicon transistors, including a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a fourteenth transistor T14, a sixteenth transistor T16, a seventeenth transistor T17, a nineteenth transistor T19, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-fifth transistor T25, and a twenty-seventh transistor T27. The N-type transistors may be oxide transistors, including a third transistor T3, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a tenth transistor T10, a thirteenth transistor T13, a fifteenth transistor T15, an eighteenth transistor T18, a twentieth transistor T20, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-sixth transistor T26, and a twenty-eighth transistor T28. The multiple oxide transistors of the shift register circuit of this example may include: an oxide output transistor and multiple oxide switching transistors. The oxide output transistor may include a twentieth transistor T20, and the multiple oxide switching transistors may include a third transistor T3, a fourth transistor T4, a seventh transistor T7, an eighth transistor T8, a tenth transistor T10, a thirteenth transistor T13, a fifteenth transistor T15, an eighteenth transistor T18, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-sixth transistor T26, and a twenty-eighth transistor T28.

[0150] In some examples, the shift register circuit may include multiple NOT gate circuits (also referred to as inverting circuits or inverters). The multiple NOT gate circuits of the shift register circuit may include, for example, a first NOT gate circuit to a seventh NOT gate circuit. Each NOT gate circuit may include: a first control transistor and a second control transistor, the first control transistor and the second control transistor having different transistor types, such as the first control transistor may be a P-type transistor, the second control transistor may be an N-type transistor, and the P-type transistor and the N-type transistor work in a complementary manner. For example, the NOT gate circuit may be a complementary metal oxide semiconductor (CMOS) tube formed by a P-type transistor and an N-type transistor that appear in a pair and work in a complementary manner.

[0151] In some examples, the gate of a first control transistor in a NOT gate circuit is connected to the gate of a second control transistor, serving as the first input of the NOT gate circuit; the second electrode of the first control transistor is connected to the second electrode of the second control transistor, serving as the output of the NOT gate circuit; the first electrode of the first control transistor serves as the second input of the NOT gate circuit; and the first electrode of the second control transistor serves as the third input of the NOT gate circuit. The second and third inputs of the NOT gate circuit can be configured to receive different voltage signals.

[0152] In some examples, as shown in FIG1 , the first control transistor of the first NOT circuit may be the second transistor T2, and the second control transistor may be the third transistor T3. The first control transistor of the second NOT circuit may be the sixth transistor T6, and the second control transistor may be the seventh transistor T7. The first control transistor of the third NOT circuit may be the ninth transistor T9, and the second control transistor may be the tenth transistor T10. The first control transistor of the fourth NOT circuit may be the twenty-seventh transistor T27, and the second control transistor may be the twenty-eighth transistor T28. The first control transistor of the fifth NOT circuit may be the twelfth transistor T12, and the second control transistor may be the thirteenth transistor T13. The first control transistor of the sixth NOT circuit may be the fourteenth transistor T14, and the second control transistor may be the fifth transistor T15. The first control transistor of the seventh NOT circuit may be the nineteenth transistor T19, and the second control transistor may be the twentieth transistor T20. The cascade signal generating circuit 101 may include four NOT circuits (i.e., the first NOT circuit to the fourth NOT circuit). The voltage maintaining circuit 105 may include two NOT circuits (i.e., the fifth NOT circuit and the sixth NOT circuit). The output circuit 104 may include a NOT gate circuit (ie, a seventh NOT gate circuit).

[0153] In some examples, the shift register circuit may include a NAND gate circuit. The NAND gate circuit may include: a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor. The third and fourth control transistors may be of the same transistor type, for example, P-type transistors; the fifth and sixth control transistors may be of the same transistor type, for example, N-type transistors. The gates of the third and fifth control transistors are connected, serving as the first input of the NAND gate circuit; the gates of the fourth and sixth control transistors are connected, serving as the second input of the NAND gate circuit; the first electrode of the third control transistor and the first electrode of the fourth control transistor are connected, serving as the third input of the NAND gate circuit; the second electrode of the third control transistor, the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor are connected, serving as the output of the NAND gate circuit; the first electrode of the fifth control transistor is connected to the second electrode of the sixth control transistor; and the first electrode of the sixth control transistor serves as the fourth input of the NAND gate circuit. The third and fourth inputs of the NAND gate circuit may be configured to receive different voltage signals.

[0154] In some examples, as shown in FIG1 , the third control transistor of the NAND gate circuit may be a twenty-first transistor T21 , the fourth control transistor may be a twenty-second transistor T22 , the fifth control transistor may be a twenty-third transistor T23 , and the sixth control transistor may be a twenty-fourth transistor T24 .

[0155] In some examples, the third input terminal can be connected to a high-level first voltage signal, and the fourth input terminal can be connected to a low-level second voltage signal. When the first input terminal of the NAND gate circuit receives a high-level signal and the second input terminal receives a high-level signal, the output terminal of the NAND gate circuit can output a low-level signal; when the first input terminal of the NAND gate circuit receives a high-level signal and the second input terminal receives a low-level signal, the output terminal of the NAND gate circuit can output a high-level signal; when the first input terminal of the NAND gate circuit receives a low-level signal and the second input terminal receives a high-level signal, the output terminal of the NAND gate circuit can output a high-level signal; when the first input terminal of the NAND gate circuit receives a low-level signal and the second input terminal receives a low-level signal, the output terminal of the NAND gate circuit can output a high-level signal. The output control circuit 103 of this example may include a NAND gate circuit.

[0156] The shift register circuit of this embodiment includes 28 transistors and no capacitors, enabling partial refresh of the display area. This example can control the strobe input signal provided by the strobe input terminal VCT to update a portion of the display screen, thereby reducing power consumption. Alternatively, partial display updates can achieve ultra-low power consumption in OLED display products such as wearable devices, mobile terminals, and notebook computers (NBs).

[0157] FIG2 is a schematic diagram of a gate drive circuit of at least one embodiment of the present disclosure. In some examples, as shown in FIG2 , the gate drive circuit may include a plurality of cascaded shift register circuits (e.g., GOA (1) to GOA (4)). The cascade output terminal of the n-1th stage shift register circuit GOA (n-1) is connected to the cascade input terminal of the nth stage shift register circuit GOA (n). Except for the last stage shift register circuit, the cascade signal provided by the cascade output terminal of each stage shift register circuit can be used as an input signal of the cascade input terminal of the next stage shift register circuit. Wherein, n can be an integer greater than 1. The cascade input terminal of the first stage shift register circuit can be connected to the start signal line STV.

[0158] In some examples, the clock signal terminal of the 2i-1th stage shift register circuit can be connected to the first clock signal line CKL, and the clock signal terminal of the 2ith stage shift register circuit can be connected to the second clock signal line CBL. Wherein, i can be an integer greater than 0. The first voltage input terminal VGH of each stage shift register circuit can be connected to the first voltage line VH, the second voltage input terminal VGL of each stage shift register circuit can be connected to the second voltage line VL, the selection input terminal VCT of each stage shift register circuit can be connected to the selection input signal line VT, and the initial control terminal NCX of each stage shift register circuit can be connected to the initial control signal line NX. The selection input signal line VT can provide a selection input signal, and the selection input signal can be a pulse signal.

[0159] Figure 3 is a partial cross-sectional schematic diagram of the display region of a display substrate according to at least one embodiment of the present disclosure. Figure 3 illustrates the stacking order of the display substrate's film layers. In some examples, as shown in Figure 3 , in a direction perpendicular to the display substrate, the display substrate may include: a base (also referred to as a substrate substrate) 10, and a circuit structure layer 20, a light-emitting structure layer 30, and an encapsulation structure layer 40 sequentially disposed on the base 10.

[0160] In some examples, the circuit structure layer 20 may include: a buffer layer BF, a first semiconductor layer (also referred to as a polysilicon active layer) PY1, a first insulating layer (also referred to as a first gate insulating layer) GI1, a first conductive layer (also referred to as a first gate metal layer) GT1, a second insulating layer (also referred to as a second gate insulating layer) GI2, a second conductive layer (also referred to as a second gate metal layer) GT2, a third insulating layer (also referred to as a third gate insulating layer) GI3, a second semiconductor layer (also referred to as an oxide active layer) PY2, a fourth insulating layer (also referred to as a fourth gate insulating layer) GI4, a third conductive layer (also referred to as a third gate metal layer) GT3, a fifth insulating layer (also referred to as an interlayer insulating layer) ILD, a fourth conductive layer (also referred to as a first source / drain metal layer) SD1, a sixth insulating layer (also referred to as a passivation layer) PVX, a seventh insulating layer (also referred to as a first planarizing layer) PLN1, a fifth conductive layer (also referred to as a second source / drain metal layer) SD2, and an eighth insulating layer (also referred to as a second planarizing layer) PLN2, which are sequentially disposed on the substrate 10. However, this embodiment is not limited thereto. In other examples, the sixth insulating layer PVX may be omitted, or the sixth insulating layer PVX may be located between the seventh insulating layer and the fifth conductive layer.

[0161] In some examples, the light-emitting structure layer 30 may include an anode layer ANO, a pixel definition layer (also referred to as a pixel defining layer) PDL, a light-emitting functional layer EL, and a cathode layer CATH. The anode layer ANO may include an anode of a light-emitting element. The pixel definition layer PDL may be formed with a plurality of pixel openings that expose the anode layer ANO. The light-emitting functional layer EL may be disposed within the pixel openings and connected to the anode within the anode layer ANO. The cathode layer CATH may be connected to the light-emitting functional layer EL.

[0162] In some examples, the encapsulation structure layer 40 may include: a first encapsulation layer CVD1, a second encapsulation layer IJP, and a third encapsulation layer CVD2. The first encapsulation layer CVD1 and the third encapsulation layer CVD2 may be made of inorganic materials, and the second encapsulation layer IJP may be made of organic materials. The second encapsulation layer IJP may be disposed between the first encapsulation layer CVD1 and the third encapsulation layer CVD2, forming an inorganic material / organic material / inorganic material stacked structure, which can prevent external moisture from entering the light-emitting structure layer 30. In some possible implementations, the display substrate may further include other film layers, such as a touch structure layer and a color filter layer, which are not limited in this embodiment.

[0163] Figure 4 is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 4 illustrates a top view of a shift register circuit of the display substrate. The equivalent circuit of the shift register circuit of this example may be as shown in Figure 1 .

[0164] In some examples, as shown in FIG4 , the outer contour of a single shift register circuit can be substantially rectangular within a plane parallel to the display substrate. The cascade signal generating circuit 101, the output control circuit 103, and the output circuit 104 can be arranged sequentially along a first direction X, and the initialization circuit 106, the gating circuit 102, and the voltage maintaining circuit 105 can be arranged sequentially along the first direction X. The initialization circuit 106 is adjacent to the cascade signal generating circuit 101 in a second direction Y, the gating circuit 102 is adjacent to the cascade signal generating circuit 101 in the second direction Y, a portion of the voltage maintaining circuit 105 is adjacent to the cascade signal generating circuit 101 in the second direction Y, and another portion is adjacent to the output control circuit 103 in the second direction Y. The initialization circuit 106, the gating circuit 102, and the voltage maintaining circuit 105 are located on the same side of the cascade signal generating circuit 101 in the second direction Y. A portion of the output circuit 104 is adjacent to the output control circuit 103 in the first direction X, and another portion is adjacent to the voltage maintaining circuit 105 in the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X may be perpendicular to the second direction Y. The arrangement of the shift register circuit in this example can save space and facilitate the realization of a narrow frame.

[0165] In some examples, as shown in FIG4 , within a plane parallel to the display substrate, the output end of the first NOT gate circuit (including the second transistor T2 and the third transistor T3) is connected to the output end of the second NOT gate circuit (including the sixth transistor T6 and the seventh transistor T7), and the first NOT gate circuit and the second NOT gate circuit are adjacent in the second direction Y. The first NOT gate circuit may be located on one side of the second NOT gate circuit in the second direction Y. The transistor arrangement of the first NOT gate circuit may be the same as the transistor arrangement of the second NOT gate circuit. The third transistor T3 and the second transistor T2 in the first NOT gate circuit may be arranged sequentially along the first direction X, and the seventh transistor T7 and the sixth transistor T6 in the second NOT gate circuit may be arranged sequentially along the first direction X. The third transistor T3 and the seventh transistor T7 may be arranged substantially aligned in the second direction Y, and the second transistor T2 and the sixth transistor T6 may be arranged substantially aligned in the second direction Y.

[0166] In some examples, the second input terminal of the first NOT circuit is connected to the first transistor T1 (serving as the first transfer transistor), and the third input terminal of the first NOT circuit is connected to the fourth transistor T4 (serving as the third transfer transistor); the second input terminal of the second NOT circuit is connected to the fifth transistor T5 (serving as the second transfer transistor), and the third input terminal of the second NOT circuit is connected to the eighth transistor T8 (serving as the fourth transfer transistor). The first transistor T1 can be located on one side of the second transistor T2 in the first direction X, and the fourth transistor T4 can be located on the side of the third transistor T3 in the opposite direction of the first direction X. The fifth transistor T5 can be located on one side of the sixth transistor T6 in the first direction X, and the eighth transistor T8 can be located on the side of the seventh transistor T7 in the opposite direction of the first direction X. The first transistor T1 and the fifth transistor T5 can be arranged substantially aligned in the second direction Y, and the fourth transistor T4 and the eighth transistor T8 can be arranged substantially aligned in the second direction Y.

[0167] In some examples, the third NOT gate circuit (including the ninth transistor T9 and the tenth transistor T10) is adjacent to the second NOT gate circuit in the second direction Y. The third NOT gate circuit can be located on a side of the second NOT gate circuit in the opposite direction of the second direction Y. The transistor arrangement of the third NOT gate circuit can be the same as the transistor arrangement of the second NOT gate circuit. The tenth transistor T10 and the ninth transistor T9 can be arranged sequentially along the first direction X. The ninth transistor T9 and the sixth transistor T6 can be arranged substantially aligned in the second direction Y, and the tenth transistor T10 and the seventh transistor T7 can be arranged substantially aligned in the second direction Y.

[0168] In some examples, the fourth NOT gate circuit (including the twenty-seventh transistor T27 and the twenty-eighth transistor T28) can be located on a side of the first NOT gate circuit and the second NOT gate circuit in a direction opposite to the first direction X. The transistor arrangement of the fourth NOT gate circuit can be different from the transistor arrangement of the first NOT gate circuit, the second NOT gate circuit, and the third NOT gate circuit. The twenty-seventh transistor T27 and the twenty-eighth transistor T28 can be arranged sequentially along the second direction Y.

[0169] In some examples, the NAND gate circuit (including the twenty-first transistor T21 to the twenty-fourth transistor T24) can be located on one side of the first NOT gate circuit and the second NOT gate circuit in the first direction X, and on the side of the seventh NOT gate circuit (including the nineteenth transistor T19 and the twentieth transistor T20) in the opposite direction of the first direction X. The NAND gate circuit is adjacent to the fifth NOT gate circuit (including the twelfth transistor T12 and the thirteenth transistor T13) and the sixth NOT gate circuit (including the fourteenth transistor T14 and the fifteenth transistor T15) in the second direction Y. The four transistors within the NAND gate circuit can be arranged sequentially along the second direction Y.

[0170] In some examples, the fifth NOT gate circuit and the sixth NOT gate circuit may be adjacent to each other in the first direction X. The sixth NOT gate circuit may be located on one side of the fifth NOT gate circuit in the first direction X. The transistor arrangement of the fifth NOT gate circuit may be the same as the transistor arrangement of the sixth NOT gate circuit. The twelfth transistor T12 and the thirteenth transistor T13 may be arranged sequentially along the second direction Y, and the fourteenth transistor T14 and the fifteenth transistor T15 may be arranged sequentially along the second direction Y. Furthermore, the twelfth transistor T12 and the fourteenth transistor T14 may be adjacent to and aligned in the first direction X; and the thirteenth transistor T13 and the fifteenth transistor T15 may be adjacent to and aligned in the first direction X.

[0171] In some examples, the nineteenth transistor T19 and the twentieth transistor T20 of the seventh NOT gate circuit may be arranged sequentially along the second direction Y. The nineteenth transistor T19 may be located on one side of the twentieth transistor T20 along the second direction Y. The nineteenth transistor T19 may be adjacent to the NAND gate circuit in the first direction X, and the twentieth transistor T20 may be adjacent to the sixth NOT gate circuit in the first direction.

[0172] In some examples, the seventeenth transistor T17 and the eighteenth transistor T18 included in the gating circuit 102 can be arranged sequentially along the second direction Y. The eighteenth transistor T18 can be located on one side of the seventeenth transistor T17 in the second direction Y. The sixteenth transistor T16 included in the initialization circuit 106 can be located on one side of the eighteenth transistor T18 in the opposite direction of the first direction X. The eleventh transistor T11 included in the initialization circuit 106 can be approximately located on one side of the sixteenth transistor T16 in the opposite direction of the second direction Y. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 included in the voltage maintaining circuit 105 can be arranged sequentially along the first direction X. The twenty-fifth transistor T25 can be located on one side of the gating circuit 102 in the first direction X, the twenty-sixth transistor T26 can be located on one side of the twenty-fifth transistor T25 in the first direction X, and the fifth NOT gate circuit can be located on one side of the twenty-sixth transistor T26 in the first direction X. The twenty-sixth transistor T26 can be arranged substantially aligned with the thirteenth transistor T13 of the fifth NOT gate circuit in the first direction.

[0173] The preparation process of the display substrate is exemplified below. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0174] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary of the projection of A, or that the boundary of the projection of A overlaps with the boundary of the projection of B. In this example, the shape of A refers to the shape of the orthographic projection of A on the substrate.

[0175] The manufacturing process of the display substrate of this exemplary embodiment may include the following steps: The manufacturing process of the circuit structure layer is taken as an example for description.

[0176] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0177] (2) Forming a first semiconductor layer. In some examples, a buffer film and a first semiconductor film are sequentially deposited on a substrate, and the first semiconductor film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0178] FIG5 is a schematic diagram of the display substrate after the first semiconductor layer is formed in FIG4. In some examples, as shown in FIG5, the first semiconductor layer of the display substrate may include at least active layers of multiple P-type transistors of the shift register circuit, such as the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 35 of the fifth transistor T5, the active layer 36 of the sixth transistor T6, the active layer 39 of the ninth transistor T9, the active layer 311 of the eleventh transistor T11, the active layer 312 of the twelfth transistor T12, the active layer 314 of the fourteenth transistor T14, the active layer 316 of the sixteenth transistor T16, the active layer 317 of the seventeenth transistor T17, the active layer 319 of the nineteenth transistor T19, the active layer 321 of the twenty-first transistor T21, the active layer 322 of the twenty-second transistor T22, the active layer 325 of the twenty-fifth transistor T25, and the active layer 327 of the twenty-seventh transistor T27.

[0179] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region of the first type transistor may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. For example, the first region of the active layer may be interpreted as a first electrode of the transistor, and the second region of the active layer may be interpreted as a second electrode of the transistor. Portions of the active layer between the transistors may be interpreted as wiring doped with impurities, which may be used to electrically connect the transistors. This embodiment is not limited to this.

[0180] In some examples, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 can be sequentially connected to form an integrated structure. The shape of the integrated structure can be approximately C-shaped. The second region of the active layer 31 of the first transistor T1 can also serve as the first region of the active layer 32 of the second transistor T2, the second region of the active layer 32 of the second transistor T2 can also serve as the second region of the active layer 36 of the sixth transistor T6, and the first region of the active layer 36 of the sixth transistor T6 can also serve as the second region of the active layer 35 of the fifth transistor T5.

[0181] In some examples, the active layer 311 of the eleventh transistor T11 may be shaped substantially like a strip extending along the first direction X, and the active layer 316 of the sixteenth transistor T16 may be shaped substantially like a strip extending along the second direction Y. The active layer 311 of the eleventh transistor T11 and the active layer 316 of the sixteenth transistor T16 may be connected to each other as an integrated structure, and the shape of the integrated structure may be substantially L-shaped. The first region of the active layer 311 of the eleventh transistor T11 may also serve as the first region of the active layer 316 of the sixteenth transistor T16.

[0182] In some examples, the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22 may extend at least along the first direction X. The active layer 321 of the twenty-first transistor T21 and the active layer 322 of the second transistor T22 may be an interconnected integral structure, and the shape of the integral structure may be substantially C-shaped. The second region of the active layer 321 of the twenty-first transistor T21 may also serve as the second region of the active layer 322 of the twenty-second transistor T22. The opening of the integral structure of the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 may face the opening of the integral structure of the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the second transistor T22.

[0183] In some examples, the active layer 39 of the ninth transistor T9 can be shaped roughly like a strip extending along the second direction Y, and is located on the side of the integrated structure of the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 in the opposite direction of the second direction Y.

[0184] In some examples, the active layer 312 of the twelfth transistor T12 may be shaped substantially like a strip extending along the first direction X. The active layer 314 of the fourteenth transistor T14 may be shaped substantially like a strip extending along the first direction X. The active layer 312 of the twelfth transistor T12 and the active layer 314 of the fourteenth transistor T14 may be adjacent to each other in the first direction X and may be aligned in the first direction X. The active layer 312 of the twelfth transistor T12 may be located on one side of the twenty-fifth transistor T25 in the first direction X, and the active layer 314 of the fourteenth transistor T14 may be located on one side of the active layer 312 of the twelfth transistor T12 in the first direction X.

[0185] In some examples, the active layer 317 of the seventeenth transistor T17 may be shaped substantially like a strip extending along the first direction X. The active layer 317 of the seventeenth transistor T17 may be located between the active layer 311 of the eleventh transistor T11 and the active layer 325 of the twenty-fifth transistor T25 in the first direction X.

[0186] In some examples, the active layer 319 of the nineteenth transistor T19 may be substantially rectangular in shape and located on one side of the integrated structure of the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22 in the first direction X.

[0187] In some examples, the active layer 325 of the twenty-fifth transistor T25 may be shaped substantially like a strip extending along the second direction Y. The active layer 325 of the twenty-fifth transistor T25 may be located on one side of the active layer 317 of the seventeenth transistor T17 in the first direction X.

[0188] In some examples, the active layer 327 of the twenty-seventh transistor T27 may be shaped substantially like a strip extending along the second direction Y. The active layer 327 of the twenty-seventh transistor T27 may be located on one side of the integrated structure of the active layer 311 of the eleventh transistor T11 and the active layer 316 of the sixteenth transistor T16 in the second direction Y, and may be located on one side of the integrated structure of the active layers 31, 32, 36, and 35 in the opposite direction to the first direction X.

[0189] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.

[0190] Fig. 6A is a schematic diagram of the display substrate after the first conductive layer is formed in Fig. 4. Fig. 6B is a schematic diagram of the first conductive layer in Fig. 6A. In some examples, as shown in Figures 6A and 6B, the first conductive layer of the display substrate may include at least: gates of multiple P-type transistors of the shift register circuit (for example, including: the gate 21 of the first transistor T1, the gate 22 of the second transistor T2, the gate 25 of the fifth transistor T5, the gate 26 of the sixth transistor T6, the gate 29 of the ninth transistor T9, the gate 211 of the eleventh transistor T11, the gate 212 of the twelfth transistor T12, the gate 214 of the fourteenth transistor T14, the gate 216 of the sixteenth transistor T16, the gate 217 of the seventeenth transistor T17, the gate 219 of the nineteenth transistor T19, the gate 221 of the twenty-first transistor T21, the gate 222 of the twenty-second transistor T22, the gate 225 of the twenty-fifth transistor T25, and the gate 227 of the twenty-seventh transistor T27), and a plurality of connecting electrodes (for example, including the first connecting electrode 401 and the second connecting electrode 402).

[0191] In some examples, the gate 21 of the first transistor T1 may be shaped approximately like an N. The gate 22 of the second transistor T2 may be shaped approximately like a strip extending along the second direction Y. The gate 25 of the fifth transistor T5 may be shaped approximately like a strip extending along the second direction Y. The gate 26 of the sixth transistor T6 may be shaped approximately like a J. The gate 29 of the ninth transistor T9 may be shaped approximately like a strip extending along the first direction X. The gate 211 of the eleventh transistor T11 may be shaped approximately like a strip extending along the second direction Y. The gate 212 of the twelfth transistor T12 and the gate 214 of the fourteenth transistor T14 may be shaped approximately like a strip extending along the second direction Y. The gate 216 of the sixteenth transistor T16 may be shaped approximately like a strip extending along the first direction X. The gate 217 of the seventeenth transistor T17 may be shaped approximately like a J. The gate 219 of the nineteenth transistor T19 may be shaped approximately like comb teeth. The gate 221 of the twenty-first transistor T21 may be shaped substantially like a combination of an L-shape and an N-shape. The gate 222 of the twenty-second transistor T22 may be shaped substantially like a zigzag line extending along the second direction Y. The gate 225 of the twenty-fifth transistor T25 may be shaped substantially like a combination of an N-shape and an L-shape. The gate 227 of the twenty-seventh transistor T27 may be shaped substantially like a strip extending along the first direction X.

[0192] In some examples, the gate 211 of the eleventh transistor T11 and the gate 216 of the sixteenth transistor T16 may be connected to each other as an integral structure. The nineteenth transistor T19 may be a tri-gate transistor to prevent and reduce leakage current. However, this embodiment is not limited to this.

[0193] In some examples, the first connection electrode 401 may be shaped substantially like a dumbbell extending along the second direction Y. The first connection electrode 401 may be located on one side of the gate 21 of the second transistor T2 and the gate 25 of the fifth transistor T5 in the first direction X, and on one side of the gate 211 of the twenty-first transistor T21 in the opposite direction of the first direction X.

[0194] In some examples, the second connection electrode 402 may be shaped substantially like a dumbbell extending along the second direction Y. The second connection electrode 402 may be located on one side of the gate 216 of the sixteenth transistor T16 in the second direction Y.

[0195] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer.

[0196] Fig. 7A is a schematic diagram of the display substrate after the second conductive layer is formed in Fig. 4. Fig. 7B is a schematic diagram of the second conductive layer in Fig. 7A. In some examples, as shown in Figures 7A and 7B, the second conductive layer of the display substrate may include at least: bottom gates of multiple N-type transistors of the shift register circuit (for example, including: the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 520 of the twentieth transistor T20, the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, the bottom gate 526 of the twenty-sixth transistor T26, and the bottom gate 528 of the twenty-eighth transistor T28), a bottom gate connection portion 60 (for example, including a first bottom gate connection portion 601 and a second bottom gate connection portion 602), and an output electrode 61. In this example, the bottom gate of the transistor may also be referred to as a bottom gate layer, and the top gate of the transistor may also be referred to as a top gate layer.

[0197] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, the bottom gate 513 of the thirteenth transistor T13, and the bottom gate 515 of the fifteenth transistor T15 can be shaped substantially like a strip extending along the second direction Y. The bottom gate 510 of the tenth transistor T10, the bottom gate 518 of the eighteenth transistor T18, and the bottom gate 526 of the twenty-sixth transistor T26 can be shaped substantially like a strip extending along the first direction X. The bottom gate 520 of the twentieth transistor T20 can be shaped substantially like comb teeth.

[0198] In some examples, the bottom gate 53 of the third transistor T3 and the bottom gate 57 of the seventh transistor T7 can be connected to each other as an integral structure. The bottom gate 54 of the fourth transistor T4 and the bottom gate 58 of the eighth transistor T8 can be connected to each other as an integral structure. The bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, and the bottom gate 523 of the twenty-third transistor T23 can be connected via a first bottom gate connection portion 601.

[0199] In some examples, the first bottom gate connection portion 601 may include: a first line segment extending along the first direction X, a second line segment extending along the third direction, a third line segment extending along the first direction X, a fourth line segment extending along the second direction Y, a fifth line segment extending along the first direction X, a first extension segment, and a second extension segment. The first line segment, the second line segment, the third line segment, the fourth line segment, and the fifth line segment may be connected in sequence, and the fourth line segment and the fifth line segment may be located on one side of the third line segment in the second direction Y. The first line segment may be connected to the first extension segment and the second extension segment extending in the second direction Y, and the second extension segment may be located on one side of the first extension segment. The third direction may be parallel to the plane containing the first direction X and the second direction Y and intersect both the first direction X and the second direction Y.

[0200] In some examples, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, and the bottom gate 57 of the seventh transistor T7 can be located on one side of the first line segment in the second direction Y and directly connected to the first line segment; the bottom gate 518 of the eighteenth transistor T18 and the bottom gate 510 of the tenth transistor T10 can be located on a side of the first line segment in the opposite direction of the second direction Y, and the bottom gate 518 of the eighteenth transistor T18 can be connected to the first line segment through a first extension segment, and the bottom gate 510 of the tenth transistor T10 can be connected to the first line segment through a second extension segment; the bottom gate 523 of the twenty-third transistor T23 can be located on a side of the fifth line segment in the opposite direction of the second direction Y and directly connected to the fifth line segment.

[0201] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, the bottom gate 523 of the twenty-third transistor T23, and the first bottom gate connecting portion 601 can be an integrated structure connected to each other. This example does not limit the shape of the first bottom gate connecting portion; for example, the first bottom gate connecting portion can adopt other irregular structures.

[0202] In some examples, the second bottom gate connection portion 602 may include a sixth segment extending along the second direction Y, a seventh segment extending along the third direction, and an eighth segment extending along the first direction X, wherein the sixth segment, the seventh segment, and the eighth segment are sequentially connected.

[0203] In some examples, the bottom gate 526 of the twenty-sixth transistor T26 can be located on a side of the sixth line segment opposite to the first direction X and connected to the sixth line segment. The bottom gate 524 of the twenty-fourth transistor T24 can be located on a side of the eighth line segment opposite to the second direction Y and connected to the eighth line segment. The bottom gate 513 of the thirteenth transistor T13 and the bottom gate 515 of the fifteenth transistor T15 can be located on a side of the eighth line segment opposite to the second direction Y and connected to the eighth line segment.

[0204] In some examples, the bottom gate 526 of the twenty-sixth transistor T26, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 524 of the twenty-fourth transistor T24, and the second bottom gate connection portion 602 can be an integrated structure connected to each other. This example does not limit the shape of the second bottom gate connection portion. For example, the second bottom gate connection portion can adopt other irregular structures.

[0205] In this example, by providing a bottom gate connection portion, the bottom gate connection of the corresponding plurality of N-type transistors can be achieved, and this helps to reduce the layout difficulty of the shift register circuit.

[0206] In some examples, the output electrode 61 may be in the shape of a strip extending at least along the first direction X. The output electrode 61 may be located on one side of the bottom gate 520 of the twentieth transistor T20 in the first direction X. The output electrode 61 may serve as a driving output terminal of the shift register circuit to transmit a driving signal to a pixel circuit in the display area.

[0207] In some examples, the orthographic projection of the second conductive layer on the substrate may not overlap with the orthographic projections of the first semiconductor layer and the first conductive layer on the substrate to reduce the impact on the P-type transistor.

[0208] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0209] FIG8A is a schematic diagram of the display substrate after forming the second semiconductor layer in FIG4 . FIG8B is a schematic diagram of the second semiconductor layer in FIG8A . In some examples, as shown in FIG8A and FIG8B , the second semiconductor layer of the display substrate may include at least active layers of multiple N-type transistors of the shift register circuit (e.g., active layer 33 of the third transistor T3, active layer 34 of the fourth transistor T4, active layer 37 of the seventh transistor T7, active layer 38 of the eighth transistor T8, active layer 310 of the tenth transistor T10, active layer 313 of the thirteenth transistor T13, active layer 315 of the fifteenth transistor T15, active layer 318 of the eighteenth transistor T18, active layer 320 of the twentieth transistor T20, active layer 323 of the twenty-third transistor T23, active layer 324 of the twenty-fourth transistor T24, active layer 326 of the twenty-sixth transistor T26, and active layer 328 of the twenty-eighth transistor T28).

[0210] In some examples, the active layer 33 of the third transistor T3 and the active layer 34 of the fourth transistor T4 may be an interconnected integral structure, and the integral structure may be in a strip shape extending along the first direction X. The integral structure may be located between the active layer 327 of the twenty-seventh transistor T27 and the active layer 32 of the second transistor T2 in the first direction X. The first region of the active layer 33 of the third transistor T3 may also serve as the second region of the active layer 34 of the fourth transistor T4.

[0211] In some examples, the active layer 37 of the seventh transistor T7, the active layer 38 of the eighth transistor T8, and the active layer 328 of the twenty-eighth transistor T28 may be sequentially connected as an integral structure, and the integral structure may be in the shape of a strip extending along the first direction X. The integral structure may be located on a side of the active layer 36 of the sixth transistor T6 opposite to the first direction X and aligned with the active layer 36 of the sixth transistor T6 in the first direction X. The first region of the active layer 37 of the seventh transistor T7 may also serve as the second region of the active layer 38 of the eighth transistor T8, and the first region of the active layer 38 of the eighth transistor T8 may also serve as the first region of the active layer 328 of the twenty-eighth transistor T28. The active layer 328 of the twenty-eighth transistor T28 may be located on a side of the active layer 327 of the twenty-seventh transistor T27 opposite to the second direction Y.

[0212] In some examples, the active layer 310 of the tenth transistor T10, the active layer 318 of the eighteenth transistor T18, and the active layer 326 of the twenty-sixth transistor T26 may be shaped substantially like strips extending along the second direction Y. The active layer 310 of the seventh transistor T10 may be located on a side of the active layer 39 of the ninth transistor T9 in a direction opposite to the first direction X and aligned with the active layer 39 in the first direction X. The active layer 318 of the eighteenth transistor T18 may be located on a side of the active layer 317 of the seventeenth transistor T17 in the second direction Y. The active layer 318 of the eighteenth transistor T18 and the active layer 310 of the tenth transistor T10 may be staggered along the second direction Y. The active layer 326 of the twenty-sixth transistor T26 may be located on a side of the active layer 325 of the twenty-fifth transistor T25 in the first direction X.

[0213] In some examples, the active layer 313 of the thirteenth transistor T13, the active layer 315 of the fifteenth transistor T15, the active layer 324 of the twenty-fourth transistor T24, and the active layer 323 of the twenty-third transistor T23 may be substantially strip-shaped and extend along the first direction X. The active layer 313 of the thirteenth transistor T13 may be located on one side of the active layer 312 of the twelfth transistor T12 in the second direction Y. The active layer 315 of the fifteenth transistor T15 may be located on one side of the active layer 314 of the fourteenth transistor T14 in the second direction Y. The active layer 313 of the thirteenth transistor T13 and the active layer 315 of the fifteenth transistor T15 are adjacent to and aligned in the first direction X. The active layer 324 of the twenty-fourth transistor T24 may be located between the active layer 322 of the twenty-second transistor T22 and the active layer 315 of the fifteenth transistor T15 in the second direction Y. The active layer 323 of the twenty-third transistor T23 may be located at one side of the active layer 321 of the twenty-first transistor T21 in the second direction Y.

[0214] In some examples, the active layer 320 of the twentieth transistor T20 may be substantially rectangular in shape. The active layer 320 of the twentieth transistor T20 may be located on a side of the active layer 319 of the nineteenth transistor T19 in the opposite direction of the second direction Y and aligned with the active layer 319 in the second direction Y.

[0215] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate having the aforementioned pattern formed thereon, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer.

[0216] FIG9A is a schematic diagram of the display substrate after forming the third conductive layer in FIG4 . FIG9B is a schematic diagram of the third conductive layer in FIG9A . In some examples, as shown in FIG9A and FIG9B , the third conductive layer of the display substrate may include at least the top gates of a plurality of N-type transistors of the shift register circuit (e.g., the top gate 23 of the third transistor T3, the top gate 24 of the fourth transistor T4, the top gate 27 of the seventh transistor T7, the top gate 28 of the eighth transistor T8, the top gate 210 of the tenth transistor T10, the top gate 213 of the thirteenth transistor T13, the top gate 215 of the fifteenth transistor T15, the top gate 218 of the eighteenth transistor T18, the top gate 220 of the twentieth transistor T20, the top gate 223 of the twenty-third transistor T23, the top gate 224 of the twenty-fourth transistor T24, the top gate 226 of the twenty-sixth transistor T26, and the top gate 228 of the twenty-eighth transistor T28).

[0217] In some examples, the top gate 23 of the third transistor T3 may be substantially F-shaped. The top gate 24 of the fourth transistor T4 may be substantially L-shaped. The top gate 27 of the seventh transistor T7 and the top gate 28 of the eighth transistor T8 may be substantially L-shaped. The top gate 210 of the tenth transistor T10 may be substantially stripe-shaped extending along the first direction X. The top gate 213 of the thirteenth transistor T13 and the top gate 215 of the fifteenth transistor T15 may be substantially L-shaped. The top gate 218 of the eighteenth transistor T18 may be substantially stripe-shaped extending along the first direction X. The top gate 223 of the twenty-third transistor T23 and the top gate 224 of the twenty-fourth transistor T24 may be substantially stripe-shaped extending along the second direction Y. The top gate 226 of the twenty-sixth transistor T26 may be substantially zigzag-shaped extending along the first direction X. The top gate 228 of the twenty-eighth transistor T28 may be substantially stripe-shaped extending along the second direction Y. The top gate 220 of the twentieth transistor T20 may have a substantially comb-teeth shape.

[0218] In some examples, the orthographic projection of the overlapping region of the top gate of the N-type transistor and the active layer on the substrate can be located within the orthographic projection of the overlapping region of the bottom gate of the N-type transistor and the active layer on the substrate. In this example, by setting the bottom gate of the N-type transistor, the characteristics of the N-type transistor can be adjusted to achieve better transistor performance.

[0219] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating film can be patterned by two patterning processes, wherein a first group of vias can be formed in the fifth insulating layer by the first patterning process, and a second group of vias can be formed in the fifth insulating layer by the second patterning process. For example, the first group of vias can expose portions of the surfaces of the first semiconductor layer, the first conductive layer, and the second conductive layer, and the second group of vias can expose portions of the surfaces of the second semiconductor layer and the third conductive layer.

[0220] Figures 10A and 10B are schematic diagrams of the display substrate after the fifth insulating layer is formed in Figure 4. Figure 10A illustrates a first group of via holes in the fifth insulating layer, and Figure 10B illustrates a second group of via holes in the fifth insulating layer.

[0221] In some examples, as shown in FIG10A , the first group of vias in the fifth insulating layer of the display substrate may include: first through twenty-sixth vias V1 to V26, twenty-eighth through V28 to V50, and fifty-first through V51 to V55. The fifth, fourth, third, second, and first insulating layers within the first through-holes V1 to V26 may be removed to expose a portion of the surface of the first semiconductor layer; the fifth, fourth, third, and second insulating layers within the twenty-eighth through-holes V28 to V50 may be removed to expose a portion of the surface of the first conductive layer; and the fifth, fourth, and third insulating layers within the fifty-first through V51 to V55 may be removed to expose a portion of the surface of the second conductive layer.

[0222] In some examples, as shown in FIG10B , the second group of vias in the fifth insulating layer of the display substrate may include: the sixty-first via V61 to the eighty-fourth via V84, and the ninety-first via V91 to the one-hundred-and-fourth via V104. The fifth insulating layer and the fourth insulating layer within the sixty-first via V61 to the eighty-fourth via V84 may be removed to expose a portion of the surface of the second semiconductor layer; and the fifth insulating layer within the ninety-first via V91 to the one-hundred-and-fourth via V104 may be removed to expose a portion of the surface of the third conductive layer.

[0223] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer.

[0224] FIG11 is a schematic diagram of the fourth conductive layer in FIG4. In some examples, as shown in FIG4 and FIG11, the fourth conductive layer of the display substrate may include at least an input electrode 62 and a plurality of conductive connection portions (e.g., including a first conductive connection portion D1, a fourth conductive connection portion D4, a third conductive connection portion D39).

[0225] In some examples, the input electrode 62 can be substantially rectangular. The input electrode 62 can be located on one side of the twenty-seventh transistor T27 in the second direction Y. The input electrode 62 can be connected to one end of the top gate 23 of the third transistor T3 through the ninety-first via V91. The input electrode 62 can serve as a cascade input terminal of the current stage shift register circuit and be connected to the cascade output terminal of the previous stage shift register circuit.

[0226] In some examples, the shape of the first conductive connection portion D1 can be substantially dumbbell-shaped and extend along the second direction Y. The first conductive connection portion D1 can be located between the cascade signal generating circuit 101 and the output control circuit 103. One end of the first conductive connection portion D1 can be connected to the first bottom gate connection portion 601 through a fifty-second via V52 (e.g., connected to the connection position of the third and fourth segments of the first bottom gate connection portion 601), and the other end can be connected to the second bottom gate connection portion 602 through a fifty-third via V53 (e.g., connected to the connection position of the seventh and eighth segments of the second bottom gate connection portion 602).

[0227] In some examples, the shape of the fourth conductive connection portion D4 can be roughly a combination of a T-shape and an L-shape. The fourth conductive connection portion D4 can be adjacent to the eleventh transistor T11 and the sixteenth transistor T16 in the first direction X. The fourth conductive connection portion D4 of the shift register circuit at this stage can serve as the cascade output terminal of the shift register circuit at this stage and be connected to the input electrode 62 of the shift register circuit at the next stage. For example, the fourth conductive connection portion D4 of the shift register circuit at this stage and the input electrode 62 of the shift register circuit at the next stage can be an integrated structure connected to each other. The fourth conductive connection portion D4 can be connected to the second connection electrode 402 through the forty-fifth via V45, can also be connected to the active layer 311 of the eleventh transistor T11 through the eleventh via V11, and can also be connected to the gate 217 of the seventeenth transistor T17 through the forty-second via V42.

[0228] In some examples, the fifth conductive connection portion D5 may be shaped substantially like a dumbbell extending along the third direction. One end of the fifth conductive connection portion D5 may be connected to the first region of the active layer 327 of the twenty-seventh transistor T27 through a fifth via V5. The other end of the fifth conductive connection portion D5 may be connected to a first transmission line 711 formed subsequently and located in the fifth conductive layer.

[0229] In some examples, the shape of the sixth conductive connection portion D6 can be substantially L-shaped. The sixth conductive connection portion D6 can be located on one side of the fifth conductive connection portion D5 in the first direction X. One end of the sixth conductive connection portion D6 can be connected to the top gate 24 of the fourth transistor T4 through the ninety-third via V93, can be connected to the top gate 228 of the twenty-eighth transistor T28 through the ninety-fourth via V94, and can be connected to the gate 227 of the twenty-seventh transistor T27 through the thirty-fifth via V35. The other end of the sixth conductive connection portion D6 can be connected to a second clock signal line CBL formed later on the fifth conductive layer.

[0230] In some examples, the seventh conductive connection portion D7 may be shaped substantially like a dumbbell extending along the second direction Y. The seventh conductive connection portion D7 may be located on a side of the sixth conductive connection portion D6 opposite to the second direction Y. One end of the seventh conductive connection portion D7 may be connected to the first region of the active layer 34 of the fourth transistor T4 via a sixty-first via V61, and the other end may be connected to the first region of the active layer 38 of the eighth transistor T8 via a sixty-fourth via V64. The seventh conductive connection portion D7 may be connected to a fifth transmission line 715 formed subsequently and located on the fifth conductive layer.

[0231] In some examples, the eighth conductive connection portion D8 may be shaped substantially like a zigzag line extending along the first direction X. The eighth conductive connection portion D8 may be located on one side of the seventh conductive connection portion D7 in the first direction X. One end of the eighth conductive connection portion D8 may be connected to the gate 25 of the fifth transistor T5 through a thirty-second via V32. The other end of the eighth conductive connection portion D8 may be connected to a second clock signal line CBL formed later and located on the fifth conductive layer.

[0232] In some examples, the ninth conductive connection portion D9 may be shaped substantially like a dumbbell extending along the first direction X. The ninth conductive connection portion D9 may be located on one side of the eighth conductive connection portion D8 in the second direction Y. The ninth conductive connection portion D9 may be connected to the second region of the active layer 32 of the second transistor T2 through the second via V2, and may also be connected to the second region of the active layer 33 of the third transistor T3 through the sixty-second via V62.

[0233] In some examples, the tenth conductive connection portion D10 may be shaped substantially like a strip extending along the first direction X. The tenth conductive connection portion D10 may be located on one side of the ninth conductive connection portion D9 in the second direction Y. One end of the tenth conductive connection portion D10 may be connected to the gate 22 of the second transistor T2 through a thirty-first via V31, and may also be connected to the top gate 23 of the third transistor T3 through a ninety-second via V92. The other end may be connected to one end of the first connection electrode 401 through a thirty-sixth via V36. The other end of the first connection electrode 401 may be connected to one end of the eleventh conductive connection portion D11 through a thirty-seventh via V37.

[0234] In some examples, the eleventh conductive connection portion D11 may be shaped like a dumbbell extending along the second direction Y. The eleventh conductive connection portion D11 may be located on a side of the first conductive connection portion D1 in a direction opposite to the first direction X. The other end of the eleventh conductive connection portion D11 may be connected to the gate 225 of the twenty-fifth transistor T25 through a fortieth via V40.

[0235] In some examples, the shape of the twelfth conductive connection portion D12 can be substantially L-shaped. The twelfth conductive connection portion D12 can be located on one side of the first conductive connection portion D1 in the first direction X. One end of the twelfth conductive connection portion D12 can be connected to the first region of the active layer 323 of the twenty-third transistor T23 through the seventy-sixth via V76, and the other end can be connected to the second region of the active layer 324 of the twenty-fourth transistor T24 through the seventy-eighth via V78.

[0236] In some examples, the thirteenth conductive connection portion D13 may be shaped substantially like a strip extending along the first direction X. The thirteenth conductive connection portion D13 may be located on one side of the twelfth conductive connection portion D12 in the first direction X. One end of the thirteenth conductive connection portion D13 may be connected to the gate 221 of the twenty-first transistor T21 through a twenty-eighth via V28, and the other end may be connected to the top gate 223 of the twenty-third transistor T23 through a one-hundred-and-third via V103.

[0237] In some examples, the fourteenth conductive connection portion D14 may be shaped substantially like a strip extending along the first direction X. The fourteenth conductive connection portion D14 may be located on one side of the twelfth conductive connection portion D12 in the first direction X. The fourteenth conductive connection portion D14 may be connected to the first bottom gate connection portion 601 (e.g., the fifth line segment of the first bottom gate connection portion 601) through a fifty-first via V51. The fourteenth conductive connection portion D14 may be connected to a seventh transmission line 717 formed subsequently and located in the fifth conductive layer.

[0238] In some examples, the shape of the fifteenth conductive connection portion D15 can be a special-shaped structure, for example, a T-shaped or L-shaped connection structure. The fifteenth conductive connection portion D15 can be located on a side of the fourteenth conductive connection portion D14 in a direction opposite to the second direction Y. One end of the fifteenth conductive connection portion D15 can be connected to the second region of the active layer 321 of the twenty-first transistor T21 through the twentieth via V20, and can also be connected to the second region of the active layer 322 of the twenty-second transistor T22 through the twenty-second via V22. The other end can be connected to the second region of the active layer 323 of the twenty-third transistor T23 through the seventy-seventh via V77, and can also be connected to the gate 219 of the nineteenth transistor T19 through the forty-sixth via V46.

[0239] In some examples, the sixteenth conductive connection portion D16 may be substantially in the shape of a strip extending along the first direction X. The sixteenth conductive connection portion D16 may be located on one side of the fourteenth conductive connection portion D14 in the first direction X. The sixteenth conductive connection portion D16 may be connected to the first region of the active layer 319 of the nineteenth transistor T19 through a plurality (e.g., four) of laterally arranged twenty-third vias V23.

[0240] In some examples, the shape of the seventeenth conductive connection portion D17 can be substantially stepped. The seventeenth conductive connection portion D17 can be located on one side of the fifteenth conductive connection portion D15 in the first direction X. One end of the seventeenth conductive connection portion D17 can be connected to the first region of the active layer 322 of the twenty-second transistor T22 through a twenty-first via V21, and the other end can be connected to another first region of the active layer 319 of the nineteenth transistor T19 through a plurality (e.g., four) of laterally arranged twenty-fifth vias V25.

[0241] In some examples, the eighteenth conductive connection portion D18 may be shaped substantially like a strip extending along the first direction X. The eighteenth conductive connection portion D18 may be located on a side of the fifteenth conductive connection portion D15 in a direction opposite to the second direction Y. One end of the eighteenth conductive connection portion D18 may be connected to the gate 222 of the twenty-second transistor T22 through a forty-eighth via V48, and the other end may be connected to the top gate 224 of the twenty-fourth transistor T24 through a one-hundred-second via V102.

[0242] In some examples, the shape of the nineteenth conductive connection portion D19 can be substantially L-shaped. The nineteenth conductive connection portion D19 can be located on one side of the eighteenth conductive connection portion D18 in the first direction X. The nineteenth conductive connection portion D19 can be connected to the bottom gate 520 of the twentieth transistor T20 through the fifty-fourth via V54, can be connected to the top gate 220 of the twentieth transistor T20 through the one hundred and fourth via V104, and can be connected to the gate 219 of the nineteenth transistor T19 through the forty-seventh via V47. The top gate 220 of the twentieth transistor T20 and the gate 219 of the nineteenth transistor T19 can be electrically connected via the nineteenth conductive connection portion D19, and the gate 219 of the nineteenth transistor T19, the second electrode of the twenty-first transistor T21, the second electrode of the twenty-second transistor T22, and the second electrode of the twenty-third transistor T23 can be electrically connected via the fifteenth conductive connection portion D15. Therefore, the fifteenth conductive connection portion D15, the gate 219 of the nineteenth transistor T19, and the nineteenth conductive connection portion D19 can be connected as a sixth node N6.

[0243] In some examples, the shape of the twentieth conductive connection portion D20 can be substantially a zigzag line extending along the first direction X. The twentieth conductive connection portion D20 can be located on one side of the nineteenth conductive connection portion D19 in the opposite direction of the second direction Y. One end of the twentieth conductive connection portion D20 can be connected to the first region of the active layer 324 of the twenty-fourth transistor T24 through the seventy-ninth via V79, and the other end can be connected to the first first region of the active layer 320 of the twentieth transistor T20 through a plurality (e.g., four) of eighty-first vias V81 arranged laterally. The twentieth conductive connection portion D20 can be connected to the eighth transmission line 718 located in the fifth conductive layer, which is formed later.

[0244] In some examples, the shape of the twenty-first conductive connection portion D21 may be substantially comb-shaped. The twenty-first conductive connection portion D21 may be located on one side of the twentieth conductive connection portion D20 in the first direction X. The twenty-first conductive connection portion D21 can be connected to the second region of the active layer 319 of the nineteenth transistor T19 through a plurality of (for example, four) twenty-fourth vias V24 arranged laterally, can also be connected to another second region of the active layer 319 of the nineteenth transistor T19 through a plurality of (for example, four) twenty-sixth vias V26 arranged laterally, can also be connected to the first second region of the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eightieth vias V80 arranged laterally, can also be connected to the second second region of the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eightieth vias V82 arranged laterally, can also be connected to the third second region of the active layer 320 of the twentieth transistor T20 through a plurality of (for example, four) eightieth vias V84 arranged laterally, and can also be connected to the output electrode 61 through two fifty-fifth vias V55 arranged laterally.

[0245] In some examples, the twenty-second conductive connection portion D22 can be shaped substantially like a strip extending along the first direction X. The twenty-second conductive connection portion D22 can be located on a side of the twenty-first conductive connection portion D21 in a direction opposite to the first direction X. The twenty-second conductive connection portion D22 can be connected to the second first region of the active layer 320 of the twentieth transistor T20 via four eighty-third vias V83 arranged laterally. The twenty-second conductive connection portion D22 can be connected to an eighth transmission element 718 formed subsequently and located on the fifth conductive layer.

[0246] In some examples, the twenty-third conductive connection portion D23 can be substantially T-shaped. The twenty-third conductive connection portion D23 can be located on a side of the twenty-second conductive connection portion D22 opposite to the first direction X. The twenty-third conductive connection portion D23 can be connected to the second region of the active layer 313 of the thirteenth transistor T13 through the seventy-third via V73, can be connected to the second region of the active layer 312 of the twelfth transistor T12 through the seventeenth via V17, can be connected to the gate 214 of the fourteenth transistor T14 through the thirtieth via V30, and can be connected to the top gate 215 of the fifteenth transistor T15 through the one-hundred-first via V101. The second electrode of the twelfth transistor T12, the second electrode of the thirteenth transistor T13, the gate of the fourteenth transistor T14, and the gate of the fifteenth transistor T15 can be electrically connected via the twenty-third conductive connection portion D23, and the twenty-third conductive connection portion D23 can serve as the fourth node N4.

[0247] In some examples, the twenty-fourth conductive connection portion D24 can be substantially n-shaped. The twenty-fourth conductive connection portion D24 can be located on a side of the first conductive connection portion D1 opposite to the second direction Y. The twenty-fourth conductive connection portion D24 can be connected to the first region of the active layer 313 of the thirteenth transistor T13 through the seventy-second via V72, and can also be connected to the first region of the active layer 315 of the fifteenth transistor T15 through the seventy-fourth via V74. The twenty-fourth conductive connection portion D24 can be connected to a sixth transmission line 716 formed later and located on the fifth conductive layer.

[0248] In some examples, the shape of the twenty-fifth conductive connection portion D25 can be substantially L-shaped. The twenty-fifth conductive connection portion D25 can be located on a side of the twenty-first conductive connection portion D21 in a direction opposite to the first direction X. The twenty-fifth conductive connection portion D25 can be connected to the gate 222 of the twenty-second transistor T22 through the forty-ninth via V49, can be connected to the second region of the active layer 314 of the fourteenth transistor T14 through the nineteenth via V19, can be connected to the second region of the active layer 325 of the twenty-fifth transistor T25 through the thirteenth via V13, can be connected to the second region of the active layer 315 of the fifteenth transistor T15 through the seventy-fifth via V75, and can be connected to the second region of the active layer 326 of the twenty-sixth transistor T26 through the seventy-first via V71. The gate of the twenty-second transistor T22, the second electrode of the fourteenth transistor T14, the second electrode of the fifteenth transistor T15, the second electrode of the twenty-fifth transistor T25 and the second electrode of the twenty-sixth transistor T25 can be connected through the twenty-fifth conductive connection portion D25, and the gate of the twenty-fourth transistor T24 and the gate of the twenty-second transistor T22 can be connected through the eighteenth conductive connection portion D18. Therefore, the eighteenth conductive connection portion D18, the gate of the twenty-second transistor T22 and the twenty-fifth conductive connection portion D25 can be connected in sequence as the fifth node N5.

[0249] In some examples, the shape of the twenty-sixth conductive connection portion D26 can be substantially stepped. The twenty-sixth conductive connection portion D26 can be located between the twenty-fifth conductive connection portion D25 and the twenty-third conductive connection portion D23 in the second direction Y. The twenty-sixth conductive connection portion D26 can be connected to the first region of the active layer 312 of the twelfth transistor T12 through the sixteenth via V16, and can also be connected to the first region of the active layer 314 of the fourteenth transistor T14 through the eighteenth via V18. The twenty-sixth conductive connection portion D26 can be connected to the second transmission line 712 located in the fifth conductive layer, which is formed later.

[0250] In some examples, the twenty-seventh conductive connection portion D27 can be substantially L-shaped. The twenty-seventh conductive connection portion D27 can be located between the eighth conductive connection portion D8 and the eleventh conductive connection portion D11 in the first direction X. The twenty-seventh conductive connection portion D27 can be connected to the first region of the active layer 31 of the first transistor T1 through the first via V1, can be connected to the first region of the active layer 35 of the fifth transistor T5 through the third via V3, and can be connected to the first region of the active layer 39 of the ninth transistor T9 through the eighth via V8. The twenty-seventh conductive connection portion D27 can be connected to a second imaginary transmission line 712 formed later and located in the fifth conductive layer.

[0251] In some examples, the shape of the twenty-eighth conductive connection portion D28 can be substantially a zigzag line extending along the first direction X. The twenty-eighth conductive connection portion D28 can be located on a side of the twenty-third conductive connection portion D23 in a direction opposite to the first direction X. The twenty-eighth conductive connection portion D28 can be connected to the gate 212 of the twelfth transistor T12 through the twenty-ninth via V29, can be connected to the top gate 213 of the thirteenth transistor T13 through the one-hundredth via V100, can be connected to the first region of the active layer 326 of the twenty-sixth transistor T26 through the seventieth via V70, can be connected to the first region of the active layer 325 of the twenty-fifth transistor T25 through the twelfth via V12, can be connected to the second region of the active layer 316 of the sixteenth transistor T16 through the ninth via V9, and can be connected to the second region of the active layer 318 of the eighteenth transistor T18 through the sixty-eighth via V68. The gate of the twelfth transistor T12, the gate of the thirteenth transistor T13, the first electrode of the twenty-fifth transistor T25, the first electrode of the twenty-sixth transistor T26, the second electrode of the sixteenth transistor T16, and the second electrode of the eighteenth transistor T18 can be electrically connected through a twenty-eighth conductive connection portion D28, and the twenty-eighth conductive connection portion D28 can serve as a third node N3.

[0252] In some examples, the twenty-ninth conductive connection portion D29 can be substantially dumbbell-shaped. The twenty-ninth conductive connection portion D29 can be located on a side of the twenty-fifth conductive connection portion D25 in a direction opposite to the first direction X. The twenty-ninth conductive connection portion D29 can be connected to the first region of the seventeenth transistor T17 via the fifteenth via V15. The twenty-ninth conductive connection portion D29 can serve as a gate input terminal of the shift register circuit at this stage. The twenty-ninth conductive connection portion D29 can be connected to a gate input signal line VT formed later on the fifth conductive layer.

[0253] In some examples, the shape of the 30th conductive connection portion D30 can be substantially rectangular. The 30th conductive connection portion D30 can be located on one side of the 28th conductive connection portion D28 in the opposite direction of the second direction Y. The 30th conductive connection portion D30 can be connected to the top gate 218 of the 18th transistor T18 through the 98th via V98, and can also be connected to the gate 225 of the 25th transistor T25 through the 41st via V41.

[0254] In some examples, the shape of the thirty-first conductive connection portion D31 can be substantially rectangular. The thirty-first conductive connection portion D31 can be located on a side of the twenty-ninth conductive connection portion D29 in a direction opposite to the second direction Y. The thirty-first conductive connection portion D31 can be connected to the gate 226 of the twenty-sixth transistor T26 through the ninety-ninth via V99. The thirty-first conductive connection portion D31 can be connected to a second clock signal line CBL formed later on the fifth conductive layer.

[0255] In some examples, the shape of the thirty-second conductive connection portion D32 may be substantially a dumbbell extending along the second direction Y. The thirty-second conductive connection portion D32 may be located on a side of the twenty-ninth conductive connection portion D29 in a direction opposite to the first direction X. The thirty-second conductive connection portion D32 may be connected to the first region of the active layer 318 of the eighteenth transistor T18 through the sixty-ninth via V69, and may also be connected to the second region of the active layer 317 of the seventeenth transistor T17 through the fourteenth via V14.

[0256] In some examples, the shape of the thirty-third conductive connection portion D33 can be substantially a zigzag line extending along the first direction X. The thirty-third conductive connection portion D33 can be located on one side of the twenty-eighth conductive connection portion D28 along the second direction Y. The thirty-third conductive connection portion D33 can be connected to the first region of the active layer 310 of the tenth transistor T10 through the sixty-seventh via V67. The thirty-third conductive connection portion D33 can be connected to a fifth transmission line 715 formed subsequently and located in the fifth conductive layer.

[0257] In some examples, the shape of the thirty-fourth conductive connection portion D34 can be substantially rectangular. The thirty-fourth conductive connection portion D34 can be located between the fourth conductive connection portion D4 and the thirty-second conductive connection portion D32 in the first direction X. The thirty-fourth conductive connection portion D34 can be connected to the first region of the active layer 316 of the sixteenth transistor T16 through the tenth via V10. The thirty-fourth conductive connection portion D34 can be connected to the first transmission line 711 formed later and located in the fifth conductive layer.

[0258] In some examples, the shape of the thirty-fifth conductive connection portion D35 can be substantially L-shaped. The thirty-fifth conductive connection portion D35 can be located on a side of the twenty-seventh conductive connection portion D27 in a direction opposite to the first direction X. The thirty-fifth conductive connection portion D35 can be connected to the gate 26 of the sixth transistor T6 through the thirty-third via V33, can be connected to the second region of the active layer 39 of the ninth transistor T9 through the seventh via V7, and can be connected to the gate 221 of the twenty-first transistor T21 through the thirty-ninth via V39.

[0259] In some examples, the shape of the thirty-sixth conductive connection portion D36 can be substantially rectangular. The thirty-sixth conductive connection portion D36 can be located on a side of the fourth conductive connection portion D4 in a direction opposite to the first direction X. The thirty-sixth conductive connection portion D36 can be connected to the gate 216 of the sixteenth transistor T16 through a forty-third via V43. The thirty-sixth conductive connection portion D36 can serve as an initial control terminal of the shift register circuit at this stage and be connected to an initial control signal line NX formed subsequently on the fifth conductive layer.

[0260] In some examples, the shape of the thirty-seventh conductive connection portion D37 can be substantially L-shaped. The thirty-seventh conductive connection portion D37 can be located on one side of the thirty-third conductive connection portion D33 in the second direction Y. The thirty-seventh conductive connection portion D37 can be connected to the second connection electrode 402 through the forty-fourth via V44, can be connected to the second region of the active layer 310 of the tenth transistor T10 through the sixty-sixth via V66, can be connected to the gate 27 of the seventh transistor T7 through the ninety-sixth via V96, and can be connected to the gate 26 of the sixth transistor T6 through the thirty-fourth via V34. The gate of the sixth transistor T6, the gate of the seventh transistor T7, and the second electrode of the tenth transistor T10 are connected through the thirty-seventh conductive connection portion D37, the gate of the sixth transistor T6, the second electrode of the ninth transistor T9, and the gate of the twenty-first transistor T21 can be connected through the thirty-fifth conductive connection portion D35, the gate of the twenty-first transistor T21 and the gate of the twenty-third transistor T23 can be connected through the thirteenth conductive connection portion D13, the thirty-seventh conductive connection portion D37 can be connected to the fourth conductive connection portion D4 through the second connection electrode 402, and the fourth conductive connection portion D4 is connected to the second electrode of the eleventh transistor T11, thereby achieving the connection between the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twenty-first transistor T21 and the twenty-third transistor T23 are all connected to the cascade output end.

[0261] In some examples, the shape of the thirty-eighth conductive connection portion D38 can be substantially U-shaped. The thirty-eighth conductive connection portion D38 can be located on a side of the seventh conductive connection portion D7 in a direction opposite to the first direction X. The thirty-eighth conductive connection portion D38 can be connected to the gate 21 of the first transistor T1 through the fiftieth via V50, can be connected to the second region of the active layer 27 of the twenty-seventh transistor T27 through the sixth via V6, can be connected to the gate 28 of the eighth transistor T8 through the ninety-fifth via V95, and can be connected to the second region of the active layer 328 of the twenty-eighth transistor T28 through the sixty-fifth via V65. The gate of the first transistor T1, the gate of the eighth transistor T8, the second electrode of the twenty-seventh transistor T27, and the second electrode of the twenty-eighth transistor T28 can be connected through the thirty-eighth conductive connection portion D38, and the thirty-eighth conductive connection portion D38 can serve as the first node N1.

[0262] In some examples, the shape of the thirty-ninth conductive connection portion D39 can be substantially I-shaped. The thirty-ninth conductive connection portion D39 can be located between the thirty-seventh conductive connection portion D37 and the thirty-fifth conductive connection portion D35. The thirty-ninth conductive connection portion D39 can be connected to the top gate 210 of the tenth transistor T10 through the ninety-seventh via V97, can be connected to the gate 29 of the ninth transistor T9 through the thirty-eighth via V38, can be connected to the second region of the active layer 36 of the sixth transistor T6 through the fourth via V4, and can be connected to the second region of the active layer 37 of the seventh transistor T7 through the sixty-third via V63. The second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, the gate of the ninth transistor T9 and the gate of the tenth transistor T10 can be connected through the thirty-ninth conductive connection portion D39, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 can be connected through the ninth conductive connection portion D9, the second electrode of the second transistor T2 and the second electrode of the sixth transistor T6 can be connected through the active layer 22 of the second transistor T2 and the active layer 26 of the sixth transistor T6 as an integrated structure, and the integrated structure of the active layer 22 of the second transistor T2 and the active layer 26 of the sixth transistor T6, the ninth conductive connection portion D9 and the thirty-ninth conductive connection portion D39 can be connected as the second node N2.

[0263] (9) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate having the aforementioned pattern, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. Subsequently, a seventh insulating film is applied, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer.

[0264] Figure 12 is a schematic diagram of a display substrate after forming the seventh insulating layer according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 12, the seventh insulating layer of the display substrate is provided with a plurality of vias, such as vias 111 through 127. The seventh and sixth insulating layers within vias 111 through 127 can be removed, exposing a portion of the surface of the fourth conductive layer.

[0265] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern formed thereon, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer.

[0266] FIG13A is a schematic diagram of a display substrate after forming a fifth conductive layer according to at least one embodiment of the present disclosure. FIG13B is a schematic diagram of the fifth conductive layer in FIG13A.

[0267] In some examples, as shown in Figures 13A and 13B, the fifth conductive layer of the display substrate may include at least: multiple signal lines, such as: a first clock signal line CKL, a second clock signal line CBL, a selection input signal line VT, an initial control signal line NX, and multiple transmission lines (for example, including a first transmission line 711, a second transmission line 712, a third transmission line 713, a fourth transmission line 714, a fifth transmission line 715, a sixth transmission line 716, a seventh transmission line 717 and an eighth transmission line 718).

[0268] In some examples, the first clock signal line CKL, the second clock signal line CBL, the strobe input signal line VT, the initial control signal line NX, and the plurality of transmission lines may all be in the shape of bars extending along the second direction Y. In the first direction X, the initial control signal line NX, the first transmission line 711, the fifth transmission line 715, the second small clock signal line CBL, the strobe input signal line VT, the first clock signal line CKL, the second transmission line 712, the sixth transmission line 716, the seventh transmission line 717, the third transmission line 713, the fourth transmission line 714, and the eighth transmission line 718 may be arranged in sequence.

[0269] In some examples, the initial control signal line NX may be connected to the thirty-sixth conductive connection portion D36 through the one-hundred-and-seventeenth via hole V117 , thereby providing an initial control signal to the initial control terminal of the shift register circuit.

[0270] In some examples, the strobe input signal line VT may be located between the second clock signal line CBL and the second clock signal line CKL in the first direction X. The strobe input signal line VT may be connected to the twenty-ninth conductive connection portion D29 through the one-hundred-nineteenth via V119 to provide a strobe input signal to the strobe input terminal of the shift register circuit.

[0271] In some examples, the line widths of the second clock signal line CBL and the first clock signal line CKL can be substantially the same, and the line width can be greater than the line widths of the remaining traces, which can reduce the transmission resistance of the clock signal. In this example, the clock signal terminal of the n-th stage (for example, n can be equal to 2i) shift register circuit can be connected to the second clock signal line CBL. The second clock signal line CBL can be connected to the sixth conductive connection portion D6 through the 112th via V112 to provide a clock signal to the fourth transistor T4, the 27th transistor T27, and the 28th transistor T28; it can also be connected to the eighth conductive connection portion D8 through the 114th via V114 to provide a clock signal to the fifth transistor T5; it can also be connected to the thirty-first conductive connection portion D31 through the 118th via V118 to provide a clock signal to the 26th transistor T26. The first clock signal line CKL can be connected to the clock signal terminal of the n-1th stage shift register circuit.

[0272] In some examples, the voltage signals transmitted by the first transmission line 711, the second transmission line 712, the third transmission line 713, and the fourth transmission line 714 can be greater than the voltage signals transmitted by the fifth transmission line 715, the sixth transmission line 716, the seventh transmission line 717, and the eighth transmission line 718. For example, the first transmission line 711, the second transmission line 712, the third transmission line 713, and the fourth transmission line 714 can all serve as first voltage lines, transmitting a first voltage signal; and the fifth transmission line 715, the sixth transmission line 716, the seventh transmission line 717, and the eighth transmission line 718 can all serve as second voltage lines, transmitting a second voltage signal. However, this embodiment is not limited to this. In other examples, the fifth transmission line 715, the sixth transmission line 716, and the eighth transmission line 718 can transmit the same voltage signal, and the seventh transmission line 717 can transmit a different voltage signal than the fifth transmission line 715.

[0273] In some examples, the first transmission line 711 can be connected to the fifth conductive connection portion D5 through the 111th via V111 to achieve electrical connection with the 27th transistor T27; it can also be connected to the 34th via V34 through the 127th via V127 to achieve connection with the 11th transistor T11 and the 16th transistor T16.

[0274] In some examples, the second transmission line 712 can be connected to the twenty-seventh conductive connection portion D27 through the one hundred and thirteenth via V113 to achieve connection with the first transistor T1 and the fifth transistor T5; it can also be connected to the twenty-sixth conductive connection portion D26 through the one hundred and twentieth via V120 to achieve connection with the twelfth transistor T12 and the fourteenth transistor T14.

[0275] In some examples, the third transmission line 713 can be connected to the sixteenth conductive connection portion D16 through the one hundred and twenty-third via V123, and can also be connected to the seventeenth conductive connection portion D17 through the one hundred and twenty-fourth via V124, thereby being connected to the nineteenth transistor T19, the twenty-first transistor T21 and the twenty-second transistor T22.

[0276] In some examples, the fourth transmission line 714 may be adjacent to the third transmission line 713 in the first direction X, for example, located on one side of the third transmission line 713 in the first direction X. The fourth transmission line 714 may not be connected to the n-th stage (n may be equal to 2i) shift register circuit, and may be connected to the n-1-th stage shift register circuit.

[0277] In some examples, the fifth transmission line 715 can be adjacent to the first transmission line 711 in the first direction X, for example, located on one side of the first transmission line 711 in the first direction X. The fifth transmission line 715 can be connected to the seventh conductive connection portion D7 through the 115th via V115 to achieve connections with the fourth transistor T4, the eighth transistor T8, and the twenty-eighth transistor T28; and can also be connected to the thirty-third conductive connection portion D33 through the 116th via V116 to achieve connection with the tenth transistor T10.

[0278] In some examples, the sixth transmission line 716 may be adjacent to the second transmission line 712 in the first direction X, for example, located on one side of the second transmission line 712 in the first direction X. The sixth transmission line 716 may be connected to the twenty-fourth conductive connection portion D24 through the one hundred and twenty-first via hole V121 to achieve connection with the thirteenth transistor T13 and the fifteenth transistor T15.

[0279] In some examples, the seventh transmission line 717 may be adjacent to the third transmission line 713 and the sixth transmission line 716 in the first direction X. For example, the seventh transmission line 717 may be located on one side of the third transmission line 713 in the opposite direction of the first direction X, and on one side of the sixth transmission line 716 in the first direction X. The distance between the seventh transmission line 717 and the sixth transmission line 716 may be greater than the distance between the seventh transmission line 717 and the third transmission line 713. The seventh transmission line 717 may be connected to the fourteenth conductive connection portion D14 through the one-hundred-and-twenty-second via hole V122, thereby being connected to the first bottom gate connection portion 601.

[0280] In some examples, the eighth transmission line 718 may be located on one side of the fourth transmission line 714 in the first direction X. The eighth transmission line 718 may be connected to the twentieth conductive connection portion D20 through the one-hundred-twenty-fifth via hole V125 to achieve connection with the twentieth transistor T20 and the twenty-fourth transistor T24; and may also be connected to the twenty-second conductive connection portion D22 through the one-hundred-twenty-sixth via hole V126 to achieve connection with the twentieth transistor T20.

[0281] In some examples, while a shift register circuit is formed on a display substrate, a pixel circuit can be formed in a display area. For example, the first semiconductor layer of the display area may include: an active layer of a first type transistor (e.g., a P-type transistor) of the pixel circuit, the first conductive layer of the display area may include: a gate of the first type transistor of the pixel circuit and a first plate of a storage capacitor, the second conductive layer of the display area may include: a second plate of the storage capacitor of the pixel circuit and a bottom gate of the second type transistor, the second semiconductor layer of the display area may include: an active layer of a second type transistor (e.g., an N-type transistor) of the pixel circuit, the third conductive layer of the display area may include: a top gate of the second type transistor of the pixel circuit, the fourth conductive layer of the display area may include at least: connection electrodes of multiple transistors of the pixel circuit, and the fifth conductive layer of the display area may include at least: a data line and a power line connected to the pixel circuit. This embodiment is not limited to this.

[0282] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The sixth insulating layer and the seventh insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0283] The structure and fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed as needed. The fabrication process of this exemplary embodiment can be implemented using currently available fabrication equipment and is well compatible with existing fabrication processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0284] In this example, the gate of the second transistor T2 and the gate of the third transistor T3 of the first NOT gate circuit are connected to receive the same signal, the second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected through the ninth conductive connection portion D9 located in the fourth conductive layer, the first electrode of the second transistor T2 can be connected to the first transistor T1 through the active layer integrated structure located in the first semiconductor layer, and the first electrode of the third transistor T3 can be connected to the fourth transistor T4 through the active layer integrated structure located in the second semiconductor layer. By designing the active layers of the second transistor T2 and the first transistor T1 as an interconnected integrated structure, and the active layers of the third transistor T3 and the fourth transistor T4 as an interconnected integrated structure, circuit space can be saved.

[0285] In this example, the gate of the sixth transistor T6 and the gate of the seventh transistor T7 of the second NOT gate circuit are connected to receive the same signal. The second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 are connected via a thirty-ninth conductive connection portion D39 located on the fourth conductive layer. The first electrode of the sixth transistor T6 can be connected to the fifth transistor T5 via an integrated active layer structure located on the first semiconductor layer, and the first electrode of the seventh transistor T7 can be connected to the eighth transistor T8 via an integrated active layer structure located on the second semiconductor layer. By designing the active layers of the sixth transistor T6 and the fifth transistor T5 as an integrated structure connected to each other, and the active layers of the seventh transistor T7 and the eighth transistor T8 as an integrated structure connected to each other, circuit space can be saved. The thirty-ninth conductive connection portion D39 and the ninth conductive connection portion D9 can be connected via the integrated structure of the active layers of the second transistor T2 and the sixth transistor T6 located on the first semiconductor layer, which can facilitate the rational arrangement of the conductive connection portions of the fourth conductive layer.

[0286] In this example, the gates of the ninth transistor T9 and the tenth transistor T10 of the third NOT circuit can both be connected to the thirty-ninth conductive connection portion D39 to achieve connections with the output terminals of the first NOT circuit and the second NOT circuit. The third NOT circuit can be connected in series with the first NOT circuit and the second NOT circuit. The second electrode of the ninth transistor T9 can be connected to the thirty-fifth conductive connection portion D35 located on the fourth conductive layer, and the second electrode of the tenth transistor T10 can be connected to the thirty-seventh conductive connection portion D37 located on the fourth conductive layer. The thirty-seventh conductive connection portion D37 and the thirty-fifth conductive connection portion D35 can be connected via the gate 26 of the sixth transistor T6 located on the first conductive layer. The thirty-seventh conductive connection portion D37 can be connected to the second connection electrode 402 located on the first conductive layer. The second electrode of the ninth transistor T9 and the second electrode of the tenth transistor T10 can be connected in sequence by jumpering via the thirty-fifth conductive connection portion D35 located on the fourth conductive layer, the gate 26 of the sixth transistor T6 located on the first conductive layer, the thirty-seventh conductive connection portion D37 located on the fourth conductive layer, and the second connection electrode 402 located on the first conductive layer before being connected to the other transistors. The first electrode of the ninth transistor T9 can be connected to the second transmission line 712 located on the fifth conductive layer via the twenty-seventh conductive connection portion D27 located on the fourth conductive layer to receive the first voltage signal. The first electrode of the tenth transistor T10 can be connected to the fifth transmission line 715 located on the fifth conductive layer via the thirty-third conductive connection portion D33 located on the fourth conductive layer to receive the second voltage signal. The transistor arrangement and connection method of the NOT gate circuit of this example can advantageously save space.

[0287] In this example, the second electrode of the twelfth transistor T12 and the second electrode of the thirteenth transistor T13 of the fifth NOT circuit, and the gate of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 of the sixth NOT circuit can be connected via a twenty-third conductive connection portion D23 located on the fourth conductive layer. The fifth NOT circuit can be connected in series with the sixth NOT circuit.

[0288] In this example, the active layer 32 of the second transistor T2 and the active layer 33 of the third transistor T3 of the first NOT gate circuit extend in the same direction, for example, both extend along the first direction X. The active layer 32 of the second transistor T2 and the active layer 33 of the third transistor T3 are arranged sequentially along the first direction X, and can be arranged substantially in a straight line. The arrangement direction of the second transistor T2 and the third transistor T3 of the first NOT gate circuit can be the same as the direction in which the active layers extend, that is, they can be arranged sequentially along the first direction X.

[0289] In this example, the active layer 36 of the sixth transistor T6 and the active layer 37 of the seventh transistor T7 of the second NOT gate circuit extend in the same direction, for example, both extend along the first direction X. The active layer 36 of the sixth transistor T6 and the active layer 37 of the seventh transistor T7 are arranged sequentially along the first direction X, and can be arranged substantially in a straight line. The arrangement direction of the sixth transistor T6 and the seventh transistor T7 of the second NOT gate circuit can be the same as the direction in which the active layers extend, that is, they can be arranged sequentially along the first direction X.

[0290] In this example, the active layer 39 of the ninth transistor T9 and the active layer 310 of the tenth transistor T10 of the third NOT gate circuit can extend in the same direction, for example, both extending along the first direction X. The active layer 39 of the ninth transistor T9 and the active layer 310 of the tenth transistor T10 are arranged sequentially along the first direction X, and can be arranged substantially in a straight line. The arrangement direction of the ninth transistor T9 and the tenth transistor T10 of the third NOT gate circuit can be the same as the direction in which the active layers extend, that is, they are arranged sequentially along the first direction X.

[0291] In this example, the active layer 327 of the twenty-seventh transistor T27 of the fourth NOT circuit extends along the second direction Y, and the active layer 328 of the twenty-eighth transistor T28 extends along the first direction X, with the two extending in intersecting directions. The active layer 327 of the twenty-seventh transistor T27 and the active layer 328 of the twenty-eighth transistor T28 can be arranged in a substantially L-shape. The twenty-seventh transistor T27 and the second eighth transistor T28 of the fourth NOT circuit can be arranged in the second direction Y, which can be substantially the same as the extending direction of the active layer 327 of the twenty-seventh transistor T27.

[0292] In this example, the active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 of the fifth NOT gate circuit extend in the same direction, for example, both extend along the first direction X; the active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 are arranged sequentially along the second direction Y. The active layer 312 of the twelfth transistor T12 and the active layer 313 of the thirteenth transistor T13 can be arranged in parallel. The arrangement direction of the twelfth transistor T12 and the thirteenth transistor T13 of the fifth NOT gate circuit can intersect with the extension direction of the active layers, for example, they are arranged sequentially along the second direction Y.

[0293] In this example, the active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 of the sixth NOT gate circuit extend in the same direction, for example, both extend along the first direction X; the active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 are arranged sequentially along the second direction Y. The active layer 314 of the fourteenth transistor T14 and the active layer 315 of the fifteenth transistor T15 can be arranged in parallel. The arrangement direction of the fourteenth transistor T14 and the fifteenth transistor T15 of the sixth NOT gate circuit can intersect with the extension direction of the active layers, for example, being arranged sequentially along the second direction Y.

[0294] This example provides a variety of arrangements of transistors in a NOT gate circuit. Combining the various arrangements can help save space and facilitate narrowing the frame.

[0295] In this example, the twenty-first transistor T21 and the twenty-second transistor T22 of the NAND gate circuit can be located between the twenty-third transistor T23 and the twenty-fourth transistor T24. The top gate 223 of the twenty-third transistor T23, the gate 221 of the twenty-first transistor T21, the gate 222 of the twenty-second transistor T22, and the top gate 224 of the twenty-fourth transistor T24 can be arranged along the second direction Y and staggered to save space. The arrangement of the NAND gate circuit in this example can save space for the NAND gate circuit.

[0296] The display substrate provided by this exemplary embodiment can save the space occupied by the shift register circuit by designing the layout of the shift register circuit on the basis of realizing partial refresh, which is conducive to realizing a display substrate with a narrow frame.

[0297] FIG14 is a schematic diagram of the connection of the bottom gate connection portion of at least one embodiment of the present disclosure. FIG14 illustrates the second conductive layer and a partial structure connected to the bottom gate connection portion. In some examples, as shown in FIG14 , the first bottom gate connection portion 601 can be connected to the second bottom gate connection portion 602 via the first conductive connection portion D1 located in the fourth conductive layer. The first bottom gate connection portion 601 can also be connected to the seventh transmission line 717 via the fourteenth conductive connection portion D14 located in the fourth conductive layer, for example, to receive a second voltage signal. The top gate 320 of the twentieth transistor T20 can be connected to the bottom gate 320 via the nineteenth conductive connection portion D19 located in the fourth conductive layer.

[0298] In this example, the bottom gate 520 and the top gate 320 of the twentieth transistor T20 are connected so that the same control signal can be written to the top gate 320 and the bottom gate 520 of the twentieth transistor T20, thereby simultaneously controlling the on / off state of the twentieth transistor T20. Furthermore, the bottom gates of the remaining N-type transistors are independently controlled from the bottom gate of the twentieth transistor T20 serving as the output transistor, thereby ensuring that the remaining N-type transistors do not interfere with the twentieth transistor T20 serving as the output transistor, thereby improving the stability of the drive signal output by the shift register circuit.

[0299] FIG15 is another partial top view of a display substrate according to at least one embodiment of the present disclosure. FIG16A is a schematic diagram of the display substrate after forming the first semiconductor layer in FIG15 . FIG16B is a schematic diagram of the display substrate after forming the first conductive layer in FIG15 . FIG16C is a schematic diagram of the fourth conductive layer in FIG15 .

[0300] In some examples, as shown in Figures 15 to 16C, the active layer 31 of the first transistor T1, the active layer 32 of the second transistor T2, the active layer 36 of the sixth transistor T6, and the active layer 35 of the fifth transistor T5 can be interconnected as an integrated structure, and the shape of the integrated structure can be annular, such as a rectangular ring. In particular, the second region of the active layer 31 of the first transistor T1 can also serve as the first region of the active layer 32 of the second transistor T2, the second region of the active layer 32 of the second transistor T2 can also serve as the second region of the active layer 36 of the sixth transistor T6, the first region of the active layer 36 of the sixth transistor T6 can also serve as the second region of the active layer 35 of the fifth transistor T5, and the first region of the active layer 31 of the first transistor T1 can also serve as the first region of the active layer 35 of the fifth transistor T5.

[0301] In some examples, the active layer 321 of the twenty-first transistor T21 and the active layer 322 of the twenty-second transistor T22 may be interconnected as an integrated structure, and the shape of the integrated structure may be substantially annular, such as a rectangular ring. The second region of the active layer 321 of the twenty-first transistor T21 may also serve as the second region of the active layer 322 of the twenty-second transistor T22, and the first region of the active layer 321 of the twenty-first transistor T21 may also serve as the first region of the active layer of the twenty-second transistor T22.

[0302] In some examples, the twenty-seventh conductive connection portion D27 located in the fourth conductive layer can be simultaneously connected to the first region of the active layer 31 of the first transistor T1 and the first region of the active layer 35 of the fifth transistor T5 through a single via to achieve access to the same signal. The fifteenth conductive connection portion D15 located in the fourth conductive layer can be simultaneously connected to the first region of the active layer 321 of the twenty-first transistor T21 and the first region of the active layer 322 of the twenty-second transistor T22 through a single via to achieve access to the same signal.

[0303] In this example, for a plurality of transistors whose first electrodes are connected to each other and whose second electrodes are also connected to each other, a ring channel structure design can be adopted to reduce the number of holes.

[0304] Figure 17 is another partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 18A is a schematic diagram of the display substrate after the fourth conductive layer is formed in Figure 17. Figure 18B is a schematic diagram of the connection between the shift register circuit in Figure 17 and the first clock signal line and the second clock signal line. Figure 17 illustrates two cascaded shift register circuits GOA(n-1) and GOA(n), where n can be 2i and i can be an integer greater than 0.

[0305] In some examples, as shown in Figures 17, 18A, and 18B, the shift register circuit GOA(n-1) can be connected to the first clock signal line CKL, and the shift register circuit GOA(n) can be connected to the second clock signal line CBL. The eighth conductive connection portion D8 of the shift register circuit GOA(n-1) located on the fourth conductive layer can be substantially rectangular in shape, can be connected to the first clock signal line CKL, and can be connected to the gate of the fifth transistor T5. The sixth conductive connection portion D6 of the shift register circuit GOA(n-1) located on the fourth conductive layer can extend to one side of the tenth conductive connection portion D10 in the second direction Y and be connected to the first clock signal line CKL. The sixth conductive connection portion D6 can be connected to the gate of the twenty-seventh transistor T27, the gate of the twenty-eighth transistor T28, and the gate of the first transistor T1. The top gate 226 of the twenty-sixth transistor T26 of the shift register circuit GOA(n-1) can be in the shape of a strip extending along the first direction X. The top gate 226 of the twenty-sixth transistor T26 can be connected to the thirty-first conductive connection portion D31 located on the fourth conductive layer. The thirty-first conductive connection portion D31 can be in the shape of a strip extending along the second direction Y and located between the twenty-eighth conductive connection portion D28 and a portion of the twenty-fifth conductive connection portion D25 in the second direction Y. The thirty-first conductive connection portion D31 of the shift register circuit GOA(n-1) can be connected to the first clock signal line CKL. The connection between the shift register circuit GOA(n) and the second clock signal line CBL can be described in the previous embodiment and will not be repeated here.

[0306] In this example, a first clock signal line CKL is configured to provide a clock signal to the odd-numbered shift register circuits, and a second clock signal line CBL is configured to provide a clock signal to the even-numbered shift register circuits. Within a single shift register circuit, a fourth NOT gate circuit (including a twenty-seventh transistor T27 and a twenty-eighth transistor T28) inverts the received clock signal to generate an inverted clock signal. This configuration reduces coupling between the clock signals provided by the first clock signal line CKL and the second clock signal line CBL, thereby ensuring the stability of the drive signal output by the shift register circuit.

[0307] In some examples, the shift register circuit GOA(n-1) can be connected to the fourth transmission line 714, and the shift register circuit GOA(n) can be connected to the third transmission line 713. The third transmission line 713 and the fourth transmission line 714 can be configured to transmit the same first voltage signal. The sixteenth conductive connection portion D16 and the seventeenth conductive connection portion D17 of the shift register circuit GOA(n-1) located on the fourth conductive layer can be connected to the fourth transmission line 714 located on the fifth conductive layer.

[0308] The layout design of the shift register circuit of this example is conducive to saving space and facilitating wiring layout. The structure of the shift register circuit GOA(n) and the remaining structure of the shift register circuit GOA(n-1) of this example can be referred to the description of the previous embodiment, so they are not repeated here.

[0309] Figure 19 is a schematic diagram of the connection of the bottom gate connection parts of adjacent shift register circuits of at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the first bottom gate connection part 601 of the shift register circuit GOA(n-1) can be connected to the second bottom gate connection part 602 through the first conductive connection part D1 located in the fourth conductive layer, and can also be connected to the seventh transmission line 717 located in the fifth conductive layer through the fourteenth conductive connection part D14. The seventh transmission line 717 can be connected to the first bottom gate connection part of the shift register circuit GOA(n). The bottom gate connection parts of adjacent shift register circuits can be connected through the seventh transmission line 717 located in the fifth conductive layer. In this example, adjacent shift register circuits can be connected to the same signal line (i.e., the seventh transmission line 717) to access the same signal. The remaining structure of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0310] FIG20 is another schematic diagram illustrating the connection of bottom gate connections between adjacent shift register circuits according to at least one embodiment of the present disclosure. In some examples, as shown in FIG20 , the first bottom gate connection 601 of each shift register circuit can be connected to the second bottom gate connection 602 via the first conductive connection D1 located in the fourth conductive layer. The bottom gate 515 of the fifteenth transistor T15 of the shift register circuit GOA(n-1) can be connected to the first bottom gate connection 601 of the shift register circuit GOA(n) via the fifth connection electrode 405. The bottom gate 515 of the fifteenth transistor T15, the bottom gate of the thirteenth transistor T13, the bottom gate 524 of the twenty-fourth transistor T24, the bottom gate 526 of the twenty-sixth transistor T26, the second bottom gate connection 602, the fifth connection electrode 405, and the first bottom gate connection 601 of the shift register circuit GOA(n) of the shift register circuit GOA(n-1) can be interconnected as an integrated structure. The arrangement of the bottom gates and bottom gate connecting portions of adjacent shift register circuits in this example does not require additional drilling, which simplifies the process flow. The remaining structures of this example can be referred to the description of the aforementioned embodiment, so they will not be repeated here.

[0311] Figure 21 is another schematic diagram illustrating the connection of the bottom gate connection portion of a shift register circuit according to at least one embodiment of the present disclosure. Figure 21 illustrates a portion of the structure of two adjacent shift register circuits. Figure 22A is a schematic diagram illustrating the structure of the bottom gate in Figure 21. Figures 22B and 22C are schematic diagrams illustrating the connection relationship of the bottom gate connection portion in Figure 21.

[0312] In some examples, as shown in Figures 21 to 22C, the second conductive layer of the display substrate may include at least: a bottom gate 53 of the third transistor T3 of the shift register circuit, a bottom gate 54 of the fourth transistor T4, a bottom gate 57 of the seventh transistor T7, a bottom gate 58 of the eighth transistor T8, a bottom gate 510 of the tenth transistor T10, a bottom gate 513 of the thirteenth transistor T13, a bottom gate 515 of the fifteenth transistor T15, a bottom gate 518 of the eighteenth transistor T18, a bottom gate 520 of the twentieth transistor T20, a bottom gate 523 of the twenty-third transistor T23, a bottom gate 524 of the twenty-fourth transistor T24, a bottom gate 525 of the twenty-fifth transistor T25, a bottom gate 526 of the twenty-sixth transistor T26, and a bottom gate 528 of the twenty-eighth transistor T28.

[0313] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 525 of the twenty-fifth transistor T25, the bottom gate 526 of the twenty-sixth transistor T26, and the bottom gate 528 of the twenty-eighth transistor T28 may be connected via the first bottom gate connection portion 601.

[0314] In some examples, the first bottom gate connection portion 601 may include a first line segment extending along the first direction X, a second line segment extending along the third direction, a third line segment extending along the first direction X, a fourth line segment extending along the second direction Y, and a fifth line segment extending along the first direction X, as well as a first extension segment and a second extension segment extending along the second direction Y. The first line segment, the second line segment, the third line segment, the fourth line segment, and the fifth line segment may be connected in sequence, and the fourth line segment and the fifth line segment may be located on one side of the third line segment in a direction opposite to the second direction Y. The first line segment may be connected to the first extension segment and the second extension segment extending along the second direction Y, and the second extension segment may be located on one side of the first extension segment.

[0315] In some examples, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, and the bottom gate 57 of the seventh transistor T7 can be located on one side of the first line segment in the second direction Y and directly connected to the first line segment; the bottom gate 54 of the fourth transistor T4 can be connected to the first line segment via the bottom gate 58 of the eighth transistor T8, and the bottom gate 53 of the third transistor T3 can be connected to the first line segment via the bottom gate 57 of the seventh transistor T7. The bottom gate 518 of the eighteenth transistor T18 and the bottom gate 510 of the tenth transistor T10 can be located on one side of the first line segment opposite to the second direction Y, and the bottom gate 518 of the eighteenth transistor T18 can be connected to the first line segment via the first extension segment, while the bottom gate 510 of the tenth transistor T10 can be connected to the first line segment via the second extension segment. The bottom gate 526 of the twenty-sixth transistor T26 can be located on one side of the fourth line segment opposite to the first direction X and directly connected to the fourth line segment. The bottom gate 513 of the thirteenth transistor T13 and the bottom gate 515 of the fifteenth transistor T15 may be located at one side of the fifth line segment in the second direction Y and directly connected to the fifth line segment.

[0316] In some examples, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 528 of the twenty-eighth transistor T28, the bottom gate 58 of the eighth transistor T8, the bottom gate 57 of the seventh transistor T7, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 510 of the tenth transistor T10, the bottom gate 526 of the twenty-sixth transistor T26, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, and the first bottom gate connection portion 601 can be an integrated structure connected to each other.

[0317] In some examples, the bottom gate 523 of the twenty-third transistor T23 and the bottom gate 524 of the twenty-fourth transistor T24 may be connected via a second bottom gate connection portion 602. The second bottom gate connection portion 602 may be substantially strip-shaped and extend along the third direction. For example, the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, and the second bottom gate connection portion 602 may be an integrated structure connected to each other.

[0318] In some examples, as shown in FIG22B , the fourth conductive layer of the display substrate may include at least a third connection electrode 403 and a fourth connection electrode 404. The third connection electrode 403 may be shaped substantially like a strip extending along the first direction X. The third connection electrode 403 may be connected to an extension of the bottom gate 523 of the twenty-third transistor T23. The fourth connection electrode 404 may be located on a side of the bottom gate 513 of the thirteenth transistor T13 opposite to the second direction and aligned with the bottom gate 513 in the second direction Y. The fourth connection electrode 404 may be shaped substantially like a strip extending along the second direction Y. The fourth connection electrode 404 may be connected to the first bottom gate connection portion 601.

[0319] In some examples, as shown in FIG22C , the fifth conductive layer of the display substrate may include at least a seventh transmission line 717 and a ninth transmission line 719. The seventh transmission line 717 may be located on one side of the ninth transmission line 719 in the first direction X. For example, the ninth transmission line 719 may be located between the sixth transmission line and the seventh transmission line 717, or the ninth transmission line 719 and the sixth transmission line may be integrally formed. The seventh transmission line 717 may be connected to the third connection electrode 403 to provide a voltage signal to the bottom gate 523 of the twenty-third transistor T23, the bottom gate 524 of the twenty-fourth transistor T24, and the second bottom gate connection 602. The ninth transmission line 719 may be connected to the fourth connection electrode 404 to provide a voltage signal to the first bottom gate connection 601 and the bottom gate to which it is connected.

[0320] In some examples, the seventh transmission line 717 and the ninth transmission line 719 can be configured to transmit the same voltage signal, such as the second voltage signal. However, this embodiment is not limited to this. In other examples, the seventh transmission line 717 and the ninth transmission line 719 can transmit different voltage signals.

[0321] In this example, the N-type transistors other than the second transistor T20 serving as the output transistor are divided into two groups, and the bottom gates of the two groups of N-type transistors are independently set, thereby reducing the risk of electrostatic discharge (ESD) that may be caused by connecting the entire surface of the N-type transistors of multiple shift register circuits.

[0322] Figure 23 is a schematic diagram of a light-shielding layer according to at least one embodiment of the present disclosure. In some examples, the display substrate may further include a light-shielding layer (BSM) located on the side of the first semiconductor layer closest to the substrate. The orthographic projection of the light-shielding layer (BSM) on the substrate may at least partially overlap with the orthographic projection of the first semiconductor layer on the substrate. The light-shielding layer (BSM) may at least partially overlap with the orthographic projection of the active layer of the low-temperature polysilicon transistor of the shift register circuit on the substrate. For example, the light-shielding layer (BSM) may cover the orthographic projection of the active layer of multiple low-temperature polysilicon transistors of the shift register circuit on the substrate.

[0323] In some examples, the display substrate may include multiple gate drive circuits, such as a gate drive circuit for providing a light emission control signal, a gate drive circuit for providing a control signal to an N-type transistor in a pixel circuit, and a gate drive circuit for providing a control signal to a P-type transistor in a pixel circuit. Each gate drive circuit may include multiple shift register circuits connected in cascade.

[0324] In some examples, the multiple gate drive circuits can be divided into multiple circuit areas, and the multiple circuit areas can be arranged in sequence along the second direction Y. Two circuit areas 81a and 81b are illustrated in Figure 23. Each circuit area (for example, circuit area 81a) may include: a first area 801, a second area 802, and a third area 803 arranged in sequence along the first direction X. The shift register circuit provided in the first area 801 may be a shift register circuit included in a gate drive circuit for providing a light-emitting control signal. The shift register circuit provided in the second area 802 may be a shift register circuit included in a gate drive circuit for providing a control signal to an N-type transistor of a pixel circuit. The shift register circuit provided in the third area 803 may be a gate drive circuit for providing a control signal to a P-type transistor of a pixel circuit. The shift register circuit provided in the aforementioned embodiment may be provided in the second area 802.

[0325] In some examples, as shown in Figure 23, the shading layers BSM corresponding to the first area 801, the second area 802, and the third area 803 can be interconnected integrated structures, and the shading layers BSM in adjacent circuit areas can be interconnected integrated structures, thereby forming a mesh-like integrated structure of the shading layer BSM in the entire display substrate.

[0326] Figure 24 is another schematic diagram of the light-shielding layer of at least one embodiment of the present disclosure. In some examples, as shown in Figure 24, the light-shielding layers in adjacent circuit areas 81a and 81b can be connected by a third conductive connection portion D3. The third conductive connection portion D3 can be roughly a trace extending along the second direction Y. The third conductive connection portion D3 can be connected to the light-shielding layer BSM in the first area of ​​the circuit area to achieve signal transmission of the light-shielding layer BSM in the second direction Y. The light-shielding layers in the first area, the second area and the third area of ​​each circuit area can be an integrated structure connected to each other. For example, the third conductive connection portion D3 can be located in the fifth conductive layer. The setting method of the light-shielding layer in this example can reduce the ESD risk that may be generated by the full-surface connection of the light-shielding layer BSM in multiple shift register circuits. The relevant description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0327] This embodiment provides a display substrate, comprising: a substrate and a gate drive circuit disposed on the substrate. The gate drive circuit includes a multi-stage shift register circuit, which includes an oxide output transistor (e.g., the twentieth transistor T20 in FIG. 1 ) and a plurality of oxide switching transistors (e.g., the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the thirteenth transistor T13, the fifteenth transistor T15, the eighteenth transistor T18, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-sixth transistor T26, and the twenty-eighth transistor T28 in FIG. 1 ). The oxide output transistor includes a first bottom gate layer (e.g., the bottom gate 520 of the twentieth transistor T20 ), a first top gate layer (e.g., the top gate 220 of the twentieth transistor T20 ), and an active layer at least partially located between the first bottom gate layer and the first top gate layer (e.g., the active layer 320 of the twentieth transistor T20 ). The oxide switching transistor includes a second bottom gate layer, a second top gate layer, and an active layer at least partially located between the second bottom gate layer and the second top gate layer. The first bottom gate layer and the second bottom gate layer are independent of each other; the first bottom gate layer is coupled to the first top gate layer; and the second bottom gate layers of at least some of the oxide switching transistors are coupled.

[0328] In some examples, the first bottom gate layer and the second bottom gate layer are independent of each other, and the first bottom gate layer and the second bottom gate layer can be connected to the same or different signals. The first bottom gate layer is coupled to the first top gate layer, and the first bottom gate layer and the first top gate layer are connected to the same signal. The second bottom gate layers of at least some of the oxide switching transistors in the plurality of oxide switching transistors are coupled, and the coupled second bottom gate layers are connected to the same signal.

[0329] In some examples, the first bottom gate layer in the oxide output transistor and the second bottom gate layer in the oxide switching transistor are both provided in the same layer and made of the same material as the second gate metal layer (i.e., the aforementioned second conductive layer). The first top gate layer in the oxide output transistor and the second top gate layer in the oxide switching transistor are both provided in the same layer and made of the same material as the third gate metal layer (i.e., the aforementioned third conductive layer). The active layer in the oxide output transistor and the active layer in the oxide switching transistor are both provided in the same layer and made of the same material as the oxide active layer (i.e., the aforementioned second semiconductor layer).

[0330] In the display substrate provided in this embodiment, a shift register circuit is provided, including an oxide output transistor and a plurality of oxide switching transistors. The oxide transistor has the property of low power consumption, and the shift register circuit can realize local refresh, that is, a part of the area on the screen (for example: the animation area) displays high-frequency refresh, and another part of the area (for example: the text area) displays low-frequency refresh, thereby effectively reducing the power consumption of the display substrate.

[0331] In the display substrate provided by this embodiment, the first bottom gate layer of the oxide output transistor is coupled to the first top gate layer, so that the first bottom gate layer and the first top gate layer of the oxide output transistor can be written with the same control signal (for example, the signal conducted by other transistors), and simultaneously control the conduction or cutoff of the oxide output transistor; moreover, the first bottom gate layer of the oxide output transistor and the second bottom gate layer of the oxide switching transistor are set to be independent of each other, so that the oxide switching transistor and the oxide output transistor can be separately and independently controlled, which can ensure that the oxide switching transistor and the oxide output transistor do not interfere with each other, thereby improving the stability of the driving signal output by the shift register circuit in the display substrate.

[0332] In the display substrate provided in this embodiment, by coupling the second bottom gate layers of at least some of the oxide switching transistors in a plurality of oxide switching transistors and connecting them to the same signal, the characteristics of at least some of the oxide switching transistors can be adjusted simultaneously, achieving better transistor performance. Furthermore, the above arrangement allows for the provision of only one signal line, which can provide signals to all second bottom gate layers included in at least some of the oxide switching transistors, thereby reducing the complexity of the shift register circuit and, in turn, the difficulty of layout of the display substrate. Furthermore, by providing independent second top gate layers for the plurality of oxide switching transistors, the on / off control of the oxide switching transistors can be achieved through the second top gate layers of the oxide switching transistors, thereby ensuring the normal operation performance of the shift register circuit.

[0333] In some exemplary embodiments, all the second bottom gate layers included in the plurality of oxide switching transistors may be coupled. The arrangement of this example can adjust the characteristics of all oxide switching transistors at the same time to achieve better transistor performance. Moreover, the arrangement of this example can only set up one signal line, that is, it can provide signals to all the second bottom gate layers included in all oxide switching transistors, which is conducive to reducing the complexity of the shift register circuit and thereby reducing the layout difficulty of the display substrate. Moreover, the second top gate layers of the plurality of oxide switching transistors are set to be independent of each other, and the second top gate layer of the oxide switching transistor can be used to control the conduction or cutoff of the oxide switching transistor, which can ensure the normal operation performance of the shift register circuit.

[0334] In some exemplary embodiments, the plurality of oxide switching transistors may be divided into at least two transistor groups. Each transistor group may include at least one oxide switching transistor. The second bottom gate layers of the plurality of oxide switching transistors in the same transistor group may be coupled. The second bottom gate layers of the oxide switching transistors in different transistor groups may be independent of each other.

[0335] In some examples, the shift register circuit may include multiple functional modules, and oxide switch transistors in the same functional module may be grouped into the same transistor group. The functional modules may include a series-connected NOT gate structure, a parallel-connected structure, or a series-parallel structure. This embodiment is not limited to this.

[0336] In some examples, the second bottom gate layer in the same transistor group receives the same signal, while the second bottom gate layers in different transistor groups receive different signals. For example, as shown in Figure 1, the output terminals of the first NOT gate circuit and the second NOT gate circuit are connected, and the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 can be divided into one transistor group. The third NOT gate circuit and the first NOT gate circuit form a NOT gate series structure, and the third NOT gate circuit and the second NOT gate circuit form a NOT gate series structure, so that the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 can be divided into one transistor group. The fifth NOT gate circuit and the sixth NOT gate circuit form a NOT gate series structure, so that the twelfth transistor T12 and the thirteenth transistor T13, and the fourteenth transistor T14 and the fifteenth transistor T15 can be divided into one transistor group. The twenty-seventh transistor T27 and the twenty-eighth transistor T28 of the fourth NOT gate circuit can be divided into one transistor group. The seventeenth transistor T17 and the eighteenth transistor T18 can form a gating circuit and can be divided into one transistor group. The twenty-fifth transistor T25 and the twenty-sixth transistor T26 can form a transmission gate structure and can be divided into a transistor group. The twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23 and the twenty-fourth transistor T24 form a NAND gate circuit and can be divided into a transistor group. The first transistor T1, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11 and the sixteenth transistor T16 are all independent transistors that act as switches. In this example, by coupling the second bottom gate layers of the oxide switch transistors belonging to the same functional module and connecting to the same signal, characteristic adjustment can be achieved simultaneously to achieve better transistor performance; moreover, the above-mentioned setting method can make the characteristics of the oxide switch transistors belonging to different functional modules independently adjustable.

[0337] In some exemplary embodiments, the second bottom gate layer included in at least some of the oxide switching transistors may extend along a first direction or a second direction, with the first direction intersecting the second direction, for example, the first direction being perpendicular to the second direction. The display substrate may further include: at least one bottom gate connection portion, the bottom gate connection portion being coupled to the second bottom gate layer included in the corresponding oxide switching transistor. For example, the display substrate may include a first bottom gate connection portion 601 and a second bottom gate connection portion 602. The arrangement of this example ensures that the bottom gate connection portion couples the second bottom gate layers included in the corresponding plurality of oxide switching transistors, and also helps reduce the layout difficulty of the shift register circuit.

[0338] In some example embodiments, at least some of the oxide switching transistors may be divided into a first transistor group and a second transistor group. The display substrate includes a first bottom gate connection portion 601 and a second bottom gate connection portion 602. The first bottom gate connection portion 601 can be coupled to the second bottom gate layer included in multiple oxide switching transistors in the first transistor group (for example, the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 523 of the twenty-third transistor T23, and the bottom gate 528 of the twenty-eighth transistor T28 shown in Figure 14). The second bottom gate connection portion 602 can be coupled to the second bottom gate layer included in multiple oxide switching transistors in the second transistor group (for example, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 524 of the twenty-fourth transistor T24, and the bottom gate 526 of the twenty-sixth transistor T26 shown in Figure 14). The first bottom gate connection portion 601 and the second bottom gate connection portion 602 may be coupled via a first conductive connection portion D1 (as shown in FIG. 14 ).

[0339] In some examples, the first bottom gate connection portion 601 and the second bottom gate layer to which it is coupled can be an integral structure connected to each other, and the second bottom gate connection portion 602 and the second bottom gate layer to which it is coupled can be an integral structure connected to each other. The first bottom gate connection portion 601 and the second bottom gate connection portion 602 can be provided in the same layer and the same material, and the first bottom gate connection portion 601 and the first conductive connection portion D1 can be provided in different layers. For example, the first bottom gate connection portion 601 can be located in the second gate metal layer (i.e., the aforementioned second conductive layer), and the first conductive connection portion D1 can be located in the first source-drain metal layer (i.e., the aforementioned fourth conductive layer). In some examples, the orthographic projection of the second bottom gate layer on the substrate may not overlap with the orthographic projection of the first gate metal layer (i.e., the aforementioned first conductive layer) on the substrate, and the orthographic projection of the first conductive connection portion D1 on the substrate may overlap with the orthographic projection of the first gate metal layer on the substrate.

[0340] In some example embodiments, at least some of the oxide switching transistors may be divided into a first transistor group and a second transistor group.The display substrate may include a first bottom gate connection portion 601 and a second bottom gate connection portion 602 . The first bottom gate connection portion 601 is coupled to the second bottom gate layer of the oxide switching transistors in the first transistor group (e.g., the bottom gate 53 of the third transistor T3, the bottom gate 54 of the fourth transistor T4, the bottom gate 57 of the seventh transistor T7, the bottom gate 58 of the eighth transistor T8, the bottom gate 510 of the tenth transistor T10, the bottom gate 513 of the thirteenth transistor T13, the bottom gate 515 of the fifteenth transistor T15, the bottom gate 518 of the eighteenth transistor T18, the bottom gate 526 of the twenty-sixth transistor T26, and the bottom gate 528 of the twenty-eighth transistor T28, as shown in FIG22A ). The second bottom gate connection portion 602 is coupled to the second bottom gate layer of the oxide switching transistors in the second transistor group (e.g., the bottom gate 523 of the twenty-third transistor T23 and the bottom gate 524 of the twenty-fourth transistor T24, as shown in FIG22A ). The first bottom gate connection portion 601 and the second bottom gate connection portion 602 may be independent of each other.

[0341] In some examples, when the first bottom gate connection portion 601 and the second bottom gate connection portion 602 are independent of each other, the display substrate may further include a first signal line (i.e., the ninth transmission line 719 shown in Figures 21 and 22C) and a second signal line (i.e., the seventh transmission line 717 shown in Figures 21 and 22C). The first signal line is coupled to the first bottom gate connection portion 601 and is configured to provide a first signal to the first bottom gate connection portion 601; the second signal line is coupled to the second bottom gate connection portion 602 and is configured to provide a second signal to the second bottom gate connection portion 602. The method of this example can achieve independent adjustment of the characteristics of the oxide switching transistors in different transistor groups.

[0342] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of the oxide switching transistor in the previous shift register circuit and the second bottom gate layer of the oxide switching transistor in the next shift register circuit can be independent of each other. This exemplary configuration enables independent control of the second bottom gate layers in two adjacent shift register circuits.

[0343] In some exemplary embodiments, in two adjacent shift register circuits, the second bottom gate layer of at least part of the oxide switching transistor in the previous shift register circuit can be coupled to the second bottom gate layer of at least part of the oxide switching transistor in the next shift register circuit. In the configuration of this example, the voltage signal of the second bottom gate layer can be connected to the lower frame area of ​​the display substrate. For example, as shown in Figure 20, the second bottom gate layer of at least part of the oxide switching transistor in the previous shift register circuit and the second bottom gate layer of at least part of the oxide switching transistor in the next shift register circuit can form an integrated structure. For example, as shown in Figure 20, the second bottom gate layer of at least part of the oxide switching transistor in the previous shift register circuit and the second bottom gate layer of at least part of the oxide switching transistor in the next shift register circuit are both arranged in the same layer and the same material as the second gate metal layer in the display substrate. The configuration of this example does not require additional drilling, which can simplify the manufacturing process.

[0344] In some exemplary embodiments, the second bottom gate layer of at least a portion of the oxide switching transistors in the previous shift register circuit can be coupled to the second bottom gate layer of at least a portion of the oxide switching transistors in the next shift register circuit via a second conductive connection (i.e., the seventh transmission line 717 shown in FIG19 ), and the second conductive connection is disposed in a different layer from the second bottom gate layer. In some examples, in the previous shift register circuit, the orthographic projection of the second conductive connection on the substrate overlaps with the orthographic projection of the first transfer pattern (i.e., the fourteenth conductive connection D14 shown in FIG19 ) on the substrate, and in this overlap, the second conductive connection is coupled to the first transfer pattern via a via; the orthographic projection of the first transfer pattern on the substrate overlaps with the orthographic projection of the bottom gate connection in the previous shift register circuit on the substrate, and in this overlap, the first transfer pattern is coupled to the bottom gate connection in the previous shift register circuit via a via. In some examples, the second conductive connection can be located in the second source / drain metal layer (i.e., the aforementioned fifth conductive layer). This example reduces the risk of electrostatic discharge (ESD) that may be caused by the full-surface connection of the second bottom gate layers in multiple shift register circuits by setting the second bottom gate layer of at least part of the oxide switching transistors in the previous shift register circuit and coupling it with the second bottom gate layer of at least part of the oxide switching transistors in the next shift register circuit through a second conductive connection portion.

[0345] In some exemplary embodiments, the shift register circuit may further include: a light shielding layer BSM (as shown in Figures 23 and 24), and a plurality of low-temperature polysilicon transistors (for example, including the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the fourteenth transistor T14, the sixteenth transistor T16, the seventeenth transistor T17, the nineteenth transistor T19, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-fifth transistor T25, and the twenty-seventh transistor T27 shown in Figure 1). The orthographic projection of the light shielding layer BSM on the substrate may at least partially overlap with the orthographic projection of the active layer of the low-temperature polysilicon transistor on the substrate. The light shielding layer BSM of at least a portion of the shift register circuit (for example, the shift register circuit provided in circuit regions 81a and 81b in Figure 23) is coupled to each other.

[0346] In some examples, at least part of the light shielding layer BSM of the shift register circuit can be coupled through a third conductive connection portion D3 (as shown in FIG24 ), and the third conductive connection portion D3 can be provided in a different layer from the light shielding layer BSM. For example, the thirteenth conductive connection portion D3 can be located in the fifth conductive layer. In some examples, the shift register circuit can further include a second transfer pattern, wherein in the previous stage shift register circuit, the orthographic projection of the third conductive connection portion D3 on the substrate has an overlapping area with the orthographic projection of the second transfer pattern on the substrate, and in this overlapping area, the third conductive connection portion D3 and the second transfer pattern are coupled through a via; the orthographic projection of the second transfer pattern on the substrate has an overlapping area with the orthographic projection of the light shielding layer BSM in the previous stage shift register circuit on the substrate, and in this overlapping area, the second transfer pattern is coupled to the light shielding layer BSM in the previous stage shift register circuit through a via. In this example, by setting the light-shielding layer BSM of at least part of the shift register circuit to be coupled through the third conductive connection part, and the third conductive connection part D3 and the light-shielding layer BSM are set in different layers, the ESD risk that may be caused by the full-surface connection of the light-shielding layer BSM in multiple shift register circuits can be reduced.

[0347] The description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be repeated here.

[0348] This embodiment also provides a method for driving a display substrate, which is used to drive the display substrate as described above. The driving method includes: providing the same signal to the first bottom gate layer and the first top gate layer to control the oxide output transistor to be turned on or off; independently providing signals to the second bottom gate layer and the second top gate layer of the oxide switching transistor, wherein the second bottom gate layers of at least some of the oxide switching transistors in the multiple oxide switching transistors are coupled to receive the same signal.

[0349] By using the driving method provided in this embodiment to drive the display substrate, the same control signal can be written into the first bottom gate layer and the first top gate layer of the oxide output transistor, and the on or off of the oxide output transistor can be controlled simultaneously. Moreover, by setting the first bottom gate layer and the second bottom gate layer to be independent of each other, the oxide switching transistor and the oxide output transistor can be controlled separately and independently, thereby ensuring that the oxide switching transistor and the oxide output transistor do not interfere with each other, and improving the stability of the driving signal output by the shift register circuit in the display substrate. Moreover, by using the driving method provided in this embodiment to drive the display substrate, the characteristics of at least some of the oxide switching transistors can be adjusted simultaneously to achieve better transistor performance. The remaining description of this embodiment can refer to the description of the previous embodiment, so it will not be repeated here.

[0350] Figure 25 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 25 , this embodiment provides a display device 91 comprising a display substrate 910. Display substrate 910 may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. Display device 91 may be any product or component with a display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.

[0351] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate and a gate driving circuit disposed on the substrate, the gate driving circuit comprising a multi-stage shift register circuit, the shift register circuit comprising an oxide output transistor and a plurality of oxide switch transistors; The oxide output transistor includes a first bottom gate layer, a first top gate layer, and an active layer at least partially located between the first bottom gate layer and the first top gate layer; The oxide switch transistor includes a second bottom gate layer, a second top gate layer, and an active layer at least partially located between the second bottom gate layer and the second top gate layer; The first bottom gate layer and the second bottom gate layer are independent of each other; the first bottom gate layer and the first top gate layer are coupled; and the second bottom gate layers of at least some of the oxide switching transistors in the plurality of oxide switching transistors are coupled.

2. The display substrate according to claim 1, wherein: All second bottom gate layers included in the plurality of oxide switch transistors are coupled to each other.

3. The display substrate according to claim 1, wherein: The plurality of oxide switch transistors are divided into at least two transistor groups, each transistor group including at least one oxide switch transistor; The second bottom gate layers of the plurality of oxide switch transistors belonging to the same transistor group are coupled; the second bottom gate layers of the oxide switch transistors belonging to different transistor groups are independent of each other.

4. The display substrate according to claim 3, wherein: The shift register circuit includes a plurality of functional modules, and the oxide switch transistors belonging to the same functional module are divided into the same transistor group.

5. The display substrate according to claim 2 or 3, wherein: The second bottom gate layer included in the oxide switch transistor in the at least part of the oxide switch transistors extends along a first direction or a second direction, and the first direction intersects with the second direction; The display substrate further includes: at least one bottom gate connection portion, wherein the bottom gate connection portion is coupled to the second bottom gate layer included in the corresponding oxide switch transistor.

6. The display substrate according to claim 5, wherein: The at least partially oxide switch transistors are divided into a first transistor group and a second transistor group; The display substrate comprises: a first bottom gate connection portion and a second bottom gate connection portion, the first bottom gate connection portion is coupled to the second bottom gate layer included in the oxide switch transistor in the first transistor group, and the second bottom gate connection portion is coupled to the second bottom gate layer included in the oxide switch transistor in the second transistor group; The first bottom gate connection portion and the second bottom gate connection portion are coupled via a first conductive connection portion; or, the first bottom gate connection portion and the second bottom gate connection portion are independent of each other.

7. The display substrate according to claim 6, wherein: The first bottom gate connection portion and the second bottom gate layer coupled thereto are an integrated structure connected to each other, and the second bottom gate connection portion and the second bottom gate layer coupled thereto are an integrated structure connected to each other; The first bottom gate connection portion and the second bottom gate connection portion are provided in the same layer and the same material, and the first bottom gate connection portion and the first conductive connection portion are provided in different layers.

8. The display substrate according to claim 7, wherein: The display substrate further includes: a second gate metal layer and a first source-drain metal layer; the first bottom gate connection portion is located in the second gate metal layer, and the first conductive connection portion is located in the first source-drain metal layer.

9. The display substrate according to claim 6, wherein: When the first bottom gate connection portion and the second bottom gate connection portion are independent of each other, the display substrate further includes: a first signal line and a second signal line, the first signal line is coupled to the first bottom gate connection portion, and the second signal line is coupled to the second bottom gate connection portion.

10. The display substrate according to any one of claims 1 to 9, wherein: In the adjacent two-stage shift register circuit: The second bottom gate layer of at least part of the oxide switch transistor in the previous stage shift register circuit is coupled to the second bottom gate layer of at least part of the oxide switch transistor in the next stage shift register circuit; or, The second bottom gate layer of the oxide switch transistor in the previous shift register circuit is independent of the second bottom gate layer of the oxide switch transistor in the next shift register circuit.

11. The display substrate according to claim 10, wherein: The second bottom gate layer of at least part of the oxide switch transistor in the previous stage shift register circuit and the second bottom gate layer of at least part of the oxide switch transistor in the next stage shift register circuit are interconnected as an integrated structure.

12. The display substrate according to claim 10, wherein: The second bottom gate layer of at least part of the oxide switching transistor in the previous shift register circuit is coupled to the second bottom gate layer of at least part of the oxide switching transistor in the next shift register circuit through a second conductive connection portion, and the second conductive connection portion is arranged in a different layer from the second bottom gate layer.

13. The display substrate according to claim 1, wherein: The shift register circuit also includes: a light shielding layer and a plurality of low-temperature polysilicon transistors, wherein the orthographic projection of the light shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of the low-temperature polysilicon transistor on the substrate; at least part of the light shielding layer of the shift register circuit is coupled.

14. The display substrate according to claim 13, wherein: The light shielding layer included in at least part of the shift register circuit is coupled via a third conductive connection portion, and the third conductive connection portion is arranged in a different layer from the light shielding layer.

15. The display substrate according to claim 1, further comprising: A nineteenth conductive connection portion is respectively coupled to the first bottom gate layer and the first top gate layer.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for driving a display substrate, for driving the display substrate according to any one of claims 1 to 15, the driving method comprising: The same signal is provided to the first bottom gate layer and the first top gate layer to control the oxide output transistor to be turned on or off; and signals are independently provided to the second bottom gate layer and the second top gate layer of the oxide switching transistor, wherein the second bottom gate layers of at least some of the multiple oxide switching transistors are coupled to receive the same signal.

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