Variable delay FIR filter for reflection equalization

Abstract

In an example, a circuit (200) includes a first signal path (212) including a first filter (202A) having a first number of taps and having an input and an output. The circuit (200) also includes a combiner (208) having first and second inputs, the first input coupled to the output of the first filter (202A). The circuit (200) includes a second signal path (214A) coupled to the input of the first filter (202A) and the second input of the combiner (208). The second signal path (214A) includes a gain component (206A), a delay component (204A) coupled to the gain component (206A), and a second filter (202B) having a second number of taps and coupled to the delay component (204A).

Description

Background Art

[0001] High-speed data converters convert analog signals into digital signals, or vice versa. Data converters can be used to provide analog signals to or receive analog signals from a destination across a transmission line. Impedance mismatches typically occur at electrical interfaces, such as where a transmission cable is coupled to a connector. Impedance mismatches can cause standing waves to be generated, resulting in frequency ripples, which can degrade the quality of the analog signal. One solution to equalize the ripple is to filter the data signal, such as by a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. Summary of the invention

[0002] In at least one example of the present specification, a circuit includes a first signal path, the first signal path including a first filter having a first number of taps and having an input and an output. The circuit also includes a combiner having first and second inputs, the first input coupled to the output of the first filter. The circuit includes a second signal path, the second signal path coupled to the input of the first filter and the second input of the combiner. The second signal path includes a gain component, a delay component coupled to the gain component, and a second filter having a second number of taps and coupled to the delay component.

[0003] In at least one example of the present specification, a circuit includes a first filter having a first number of taps and having an input and an output. The circuit also includes a combiner having first and second inputs, the first input being coupled to the output of the first filter. The circuit includes a second filter having a second number of taps. The circuit also includes a gain component having an input coupled to the input of the first filter and having an output. The circuit includes a delay component having an input coupled to the output of the gain component and having an output, wherein the second filter has an input coupled to the output of the delay component, and wherein the second filter has an output coupled to the second input of the combiner. The circuit also includes a digital-to-analog converter having an input coupled to the output of the combiner.

[0004] In at least one example of the present specification, a circuit includes a first filter having a first number of taps and having an input and an output. The circuit includes a combiner having first and second inputs, the first input being coupled to the output of the first filter. The circuit also includes a second filter having a second number of taps and having an input coupled to the input of the first filter and having an output. The circuit includes a delay component having an input coupled to the output of the second filter and having an output. The circuit also includes a gain component having an input coupled to the output of the delay component and having an output coupled to the second input of the combiner. The circuit includes an analog-to-digital converter having an output coupled to the input of the first filter.

[0005] In at least one example of the present specification, a circuit includes a first filter having a first number of taps and having an input and an output. The circuit includes a first combiner having first and second inputs, the first input coupled to the output of the first filter. The circuit also includes a second filter having a second number of taps. The circuit includes a first gain component having an input coupled to the input of the first filter and having an output. The circuit also includes a first delay component having an input coupled to the output of the first gain component and having an output, wherein the second filter has an input coupled to the output of the first delay component, and wherein the second filter has an output coupled to the second input of the first combiner. The circuit includes a digital-to-analog converter having an input coupled to the output of the first combiner. The circuit also includes a third filter having a third number of taps and having an input and an output. The circuit includes a second combiner having first and second inputs, the first input coupled to the output of the third filter. The circuit also includes a fourth filter having a fourth number of taps and having an input coupled to the input of the third filter and having an output. The circuit includes a second delay component having an input coupled to the output of the fourth filter and having an output. The circuit also includes a second gain component having an input coupled to the output of the second delay component and having an output coupled to the second input of the second combiner. The circuit includes an analog-to-digital converter having an output coupled to the input of the third filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1is a block diagram of an example system with a variable delay FIR filter.

[0007] Figure 2 is a block diagram of an example circuit with a delay equalization path.

[0008] Figure 3A , 3B and 3C are example graphs of frequency domain response for cable response and standing waves.

[0009] Figure 4 is an example graph of the frequency domain response for a FIR filter.

[0010] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0011] Data converters such as analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) convert signals for use or transmission in various applications. Signal processing is performed on the signal to optimize transmission, correct errors or distortion, or detect components within the signal. A digital signal is a digital sequence of samples representing a continuous variable in a domain such as time, space, or frequency. A digital signal is represented as a pulse train, where the pulse train contains samples of the signal. A digital signal can be filtered using an FIR filter. A FIR filter is a filter whose impulse response has a finite duration because it settles to zero in a finite time. An N-order FIR filter includes an N-stage delay line with N+1 taps. Integer-valued N delay elements are coupled in series and are configured to receive samples of a digital signal.

[0012] In one example, the N delay elements of the delay line are implemented with registers or shift registers. The taps of the filter are tapped into the delay line between the N delay elements and receive samples as they pass through the delay line. When the samples are received by the taps, each of the N+1 taps performs a multiplication operation on each of the samples, where each sample is multiplied by a coefficient. The FIR filter produces an output sequence that is a sum (e.g., accumulation) of multiplication operations. Digital hardware performs multiplication and accumulation operations. The FIR filter is designed to have a specific response by selecting the order N, the number of taps, and the coefficients of the multiplication operations performed by the taps. FIR filter design can take into account many factors, including bandwidth, sharpness of response, speed, area, hardware complexity, accuracy, available computing power, etc.

[0013] The signal may pass through a transmission medium, such as a cable. The transmission medium herein is referred to as a path or signal path. The path or signal path may include a cable, a wire, a trace, a conductor, or any other medium for transmitting an electrical signal. The cable may connect one component to another component via an interface at each end of the cable. The signal may also pass through other interfaces, such as when the output of one component (e.g., a DAC) is coupled to another component (e.g., a connector). Impedance mismatches at these interfaces may cause reflections. Multiple interfaces with impedance mismatches may cause standing waves to be generated in the transmission medium. Standing waves cause frequency ripples over the signal bandwidth, which reduces the quality of the signal.

[0014] One solution to flatten the ripple is to use a single FIR filter on the digital signal before or after conversion from the analog domain, where the FIR filter is designed to have an inverse response to the ripple. However, the length of the digital filter increases with the length of the transmission medium and / or with the number of digital samples (e.g., as the speed of the data converter increases). Therefore, for high-speed data converters, such as 64 gigasamples per second (GSPS) data converters, the filter requires multiple taps. Each FIR tap contains a multiplication / accumulation digital function to perform the above-mentioned multiplication and addition operations, so more FIR taps require more silicon area, power, and computation time.

[0015] In the example herein, instead of using one large FIR filter to flatten the ripple, multiple filters with delays are implemented. The incoming digital signal passes through the main path and one or more parallel delay equalization paths (also referred to herein as delay reflection equalization paths). The main path includes an FIR filter that filters the digital signal. Each delay equalization path includes a gain circuit (also referred to herein as a gain component), a variable integer sample delay (e.g., a shift register, which is also referred to herein as a delay component) and an FIR filter. The variable integer sample delay is used to delay each sample of the digital signal based on the delay of a specific reflection without performing multiplication on the signal. Due to the time it takes for the digital signal to pass through various cables and signal paths in the system and then be reflected back, the reflection is delayed. The variable integer sample delay is designed to delay the sample of the digital signal by a certain amount of time in each delay equalization path. Each variable integer sample delay is designed to have a specific delay based on the reflection delay. Therefore, the output of the FIR filter in the delay equalization path produces a signal that compensates or eliminates the reflection when the reflection is received later.

[0016] In an example, a delay equalization path with an FIR filter is included for each reflection of a digital signal. As described above, the delay in the delay equalization path matches the delay of the corresponding reflection. In some examples, the digital signal is scaled in the delay equalization path because the reflection is smaller than the complete signal. Scaling the signal allows a lower resolution in the filter tap in the delay equalization path. For example, a smaller signal can be represented by fewer bits (e.g., lower resolution) in the filter tap compared to a larger signal. By reducing the signal, fewer bits are required to represent the result of the multiplication and accumulation operations performed on the digital samples of the signal as described above. Because the signal is reduced, the total noise (e.g., floor noise) in the signal is also reduced proportionally. The example described herein with multiple smaller FIR filters is more effective than a large FIR filter. Variable integer sample delays (e.g., delay components) are easier to implement than a large number of FIR taps to be implemented in a large FIR filter. Moreover, the FIR filter may have a reduced tap coefficient resolution away from the center of the FIR filter. In some examples, instead of or in addition to the FIR filter, an IIR filter is used.

[0017] In some instances, the delay is a fractional value and therefore not exactly an integer number of samples (e.g., a delay of 10.5 samples is required). In this case, the variable integer sample delay provides a delay equal to an integer number of samples (e.g., 10 samples). For the remainder of the delay, the fractional portion (e.g., 0.5 samples) is provided by the N delay elements in the FIR filter, as described above. The N delay elements within the FIR filter are designed to provide fractional delay values.

[0018] Figure 1 1 is a block diagram of a system 100 having one or more variable delay FIR filters in various examples herein. System 100 represents a test environment in which digital signals are transmitted to and received from a device for testing. However, the examples herein are implemented in systems other than test environments. For example, a variable delay FIR filter as described herein can filter reflections caused by signals transmitted to and from a processor or controller embodied in an integrated circuit through traces or wires.

[0019] The system 100 includes an instrument card 102 coupled to a test board 104. The test board 104 includes a device under test (DUT) 106. The DUT 106 is any electronic device that is tested using a setup similar to the system 100, such as a microprocessor, a controller, or a radio frequency transceiver. The instrument card 102 is coupled to the test board 104 via cables 108A and 108B (collectively referred to as cables 108). Two cables 108 are shown in the system 100, but there are any number of cables 108 in other examples. The instrument card 102 includes a DAC 110 having a DAC input 112 and a DAC output 114, a variable delay filter 116, an ADC 120 having an ADC input 122 and an ADC output 124, and a variable delay filter 126. The output of the variable delay filter 116 is coupled to the DAC input 112. An input signal path 118 provides a digital signal to the input of the variable delay filter 116. A signal path is any cable, conductor, trace, wire, or other medium that transmits an electrical signal. A signal path is also referred to herein as a path. An input of the variable delay filter 126 is coupled to the ADC output 124. The variable delay filter 126 provides an output signal at its output to an output signal path 128. The components in the instrument card 102 may be embodied in analog hardware, digital hardware, and / or in an integrated circuit.

[0020] The system 100 also includes connectors 130A, 130B, 130C, and 130D (collectively, connectors 130). The connectors 130 couple the cables 108 to other components, such as the instrument card 102 and / or the test board 104. In this example, the connector 130A couples the cable 108A to the instrument card 102, that is, to the DAC output 114. The connector 130B couples the cable 108A to the test board 104, that is, to the input of the DUT 106. The connector 130C couples the cable 108B to the instrument card 102, that is, to the ADC input 122. The connector 130D couples the cable 108B to the test board 104, that is, to the output of the DUT 106.

[0021] In operation, a digital signal is provided to the instrument card 102 via an input signal path 118. The digital signal is filtered by a variable delay filter 116. The details and operation of the variable delay filter 116 are described below. The filtered digital signal is provided to the DAC 110 via a DAC input 112. The output signal of the DAC 110 is provided to the DUT 106 via a cable 108A. The DUT 106 receives the signal and may provide an output signal in response, which is received by the ADC 120 via a cable 108B. In another example, the DUT 106 generates a signal and provides the signal to the ADC 120. The ADC 120 provides the digital signal to the variable delay filter 126 via an ADC output 124. The variable delay filter 126 provides an output signal via an output signal path 128. The output signal is analyzed to test the operation of the DUT 106.

[0022] Delays are introduced through signal paths (also referred to as paths) in the system 100. Delays represent signal propagation delays between components of the system 100, such as due to impedance mismatches between components that may cause ripples in the signal, as described above. A plurality of potential delays 132 (collectively referred to as delays 132, or individually referred to as delays 132) are shown in the system 100. Delays 132A, 132B, 132C, 132D, 132E, and 132F are shown, but other delays 132 may also exist in the system 100, such as delays 132 internal to a component. Each of the delays 132 represents a different delay experienced by the signal as it propagates through the system 100.

[0023] Delay 132A is the delay along the path between DAC 110 and connector 130A. Delay 132B is the delay along the path between connector 130A and connector 130B (e.g., the delay caused by cable 108A). Delay 132C is the delay between connector 130B and DUT 106. Delay 132D is the delay between DUT 106 and connector 130D. Delay 132E is the delay between connectors 130C and 130D (e.g., the delay caused by cable 108B). Delay 132F is the delay between connector 130C and ADC 120.

[0024] Each delay 132 and other delays 132 not shown can produce reflections, which cause standing waves in the signal transmitted in the system 100, which produces frequency-dependent ripples in the signal. Variable delay filters 116 and 126 include components that mitigate such ripples. For example, variable delay filters 116 and 126 include different delay equalization paths for each delay in the system 100. Each of the delay equalization paths includes a gain component, a variable integer sample delay (also referred to as a delay or delay component), and an FIR filter with a specific number of taps. The FIR filter is a programmable FIR filter in some instances, or an IIR in other instances. The variable integer sample delay delays the timing of the sample of the input digital signal to match the time when the reflection associated with the corresponding delay equalization path arrives at the variable delay filter. The gain component scales the signal because the reflection is usually smaller than the size of the complete input signal. Appropriate tap coefficients are also selected for each FIR filter to filter the ripples in the signal.

[0025] Figure 2 is a block diagram of an example circuit 200 that represents a portion of an instrument card 102 of the system 100. The circuit 200 includes an example delay equalization path. More specifically, Figure 2 1 and 120 are coupled to the DAC 110 and the ADC 120, respectively. Figure 1 1 and 126. The example variable delay filter 116 includes a first (or main) signal path 212 and three delay equalization paths 214A, 214B, and 214C. Similarly, the example variable delay filter 126 includes a second signal path 216 and three delay equalization paths 218A, 218B, and 218C. In other examples, different numbers of delay equalization paths are useful. Delay equalization paths may also be referred to as paths or signal paths in this article.

[0026] The first signal path 212 includes an N-tap FIR filter 202A, where N is an integer representing the number of taps in the FIR filter. In one example, N is 40 taps in the FIR filter 202A. Delay equalization path 214A includes a gain component 206A, a delay 204A, and a P-tap FIR filter 202B, where P is an integer representing the number of taps in the FIR filter. Delay equalization path 214B includes a gain component 206B, a delay 204B, and a P-tap FIR filter 202C. Delay equalization path 214C includes a gain component 206C, a delay 204C, and a P-tap FIR filter 202D.

[0027] Similarly, second signal path 216 includes N-tap FIR filter 202E. In one example, N is 40 taps in FIR filter 202E. Delay equalization path 218A includes P-tap FIR filter 202F, delay 204D, and gain component 206D. Delay equalization path 218B includes P-tap FIR filter 202G, delay 204E, and gain component 206E. Delay equalization path 218C includes P-tap FIR filter 202H, delay 204F, and gain component 206F.

[0028] FIR filters 202A-202H are collectively referred to as FIR filters 202. Delays 204A-204F are referred to as delays 204. Gain components 206A-206F are referred to as gain components 206. Input signal path 118 is coupled to the inputs of gain components 206A-206C and the input of FIR filter 202A. The outputs of FIR filters 202A-202D are coupled to the input of combiner 208. In this example, combiner 208 has first and second inputs. The outputs of gain components 206D-206F and the output of FIR filter 202E are coupled to the input of combiner 210. In this example, combiner 210 has first and second inputs. The output of combiner 208 is coupled to the DAC input 112 of DAC 110. The ADC output 124 of ADC 120 is coupled to the inputs of FIR filters 202E-202H. The output of combiner 210 is coupled to output signal path 128.

[0029] In some instances, FIR filter 202, delay 204 and gain component 206 are hardware components. FIR filter 202 is configured to filter digital signal to compensate for some interference, standing wave, reflection or undesirable response in digital signal. FIR filter 202 is implemented in digital hardware in one instance and includes register, multiplier and accumulator as described above. In some instances, each delay 204 is a shift register or FIFO (first in, first out) component. Delay 204 is configured to delay digital signal by an integer number of samples of digital signal (e.g., M1 samples, M2 samples, etc.). Therefore, delay 204 stores samples of incoming digital signal and then releases samples at a later time to match the timing of reflection, wherein reflection is caused by digital signal of various paths traveling through system 100. Delay 204 may be located before or after FIR filter 202 in delay equalization path 214 or 218. In some instances, each gain component 206 is a digital multiplier or bit shifter, or any other circuit system that amplifies or reduces digital signal. Furthermore, the gain component 206 may be located before or after the FIR filter 202 .

[0030] In example operation, a digital signal is received via the input signal path 118. The first signal path 212 provides the digital signal to the DAC 110. The first signal path 212 includes an N-tap FIR filter 202A. In this example, N is any integer representing the number of taps in the FIR filter 202A. The entire input digital signal passes through each of the main path (the first signal path 212) and one or more delay equalization paths 214. Therefore, each path receives the entire input digital signal and then scales, filters, and / or delays the input digital signal provided by the components in the corresponding path.

[0031] The first delay equalization path 214A comprises a gain component 206A, a delay 204A and a P-tap FIR filter 202B, wherein P is an integer representing the number of taps in the FIR filter 202B. In one example, P is 20 taps in the FIR filter 202B. The value of the tap coefficients in the gain component 206A, the delay 204A (e.g., M1 samples, wherein M1 is the number of digital samples by which the signal is delayed), the number of taps P in the FIR filter and the FIR filter 202B are selected to compensate for the specific reflection of the signal caused by one of the delays 132. In order to select these variables and design the components in the system 100, a test digital signal is transmitted through the system 100 and reflections, standing waves and other interferences are measured. Reflections and interferences are generated by the physical components (e.g., cables, connectors, etc.) of the system 100. The FIR filter is designed to compensate for these reflections based on the size and delay of the reflections.

[0032] For example, delay 132B ( Figure 1 108A) may produce a standing wave in the signal caused by cable 108A. The first delay equalization path 214A may compensate for this standing wave by providing an opposite response to this standing wave caused by delay 132B. In this example, each delay equalization path 214 and 218 is designed to compensate for a specific reflection or other interference in this particular system. If system 100 is changed or modified (e.g., by replacing a cable), the test is performed again and the filter is modified to compensate for the reflection caused by the new component in system 100.

[0033] The second delay equalization path 214B comprises a gain component 206B, a delay 204B and a P tap FIR filter 202C. The value of the tap coefficient in the value of the gain component 206B, the delay 204B (e.g., M2 samples), the number of taps P and the P tap FIR filter 202C are selected to compensate for the specific reflection of the signal caused by one of the delays 132. In an example, the value of the number of taps P and the tap coefficient in the P tap FIR filter 202C is different from the value of the number of taps P and the tap coefficient in the P tap FIR filter 202B. In an example, P is 20 taps in the FIR filter 202C, but P can be any other number of taps, such as 16, 18 or 22 taps. Moreover, the gain amount provided by the gain component 206B and the delay length provided by the delay 204B can be different from the gain and delay of these corresponding components found in the first delay equalization path 214A. The gain amount and the delay length in each delay equalization path 214 are designed to compensate for the specific reflection of the signal.

[0034] The third delay equalization path 214C includes a gain component 206C, a delay 204C, and a P-tap FIR filter 202D. The value of the tap coefficient in the gain component 206C, the delay 204C (e.g., M3 samples), the number of taps P, and the P-tap FIR filter 202D are selected to compensate for the specific reflection of the signal caused by one of the delays 132. The number of taps P and the value of the tap coefficient in the P-tap FIR filter 202D may be different from the number of taps P and the tap coefficient in the P-tap FIR filter 202B or the P-tap FIR filter 202C. The gain amount provided by the gain component 206C and the delay length provided by the delay 204C may also be different from the gain and delay of these corresponding components found in the first delay equalization path 214A or the second delay equalization path 214B.

[0035] Delay equalization paths 214 and 218 (described below) are configured to compensate for Figure 1 Any number of delay equalization paths 214 or 218 may be generated. The signals generated by delay equalization paths 214A, 214B, and 214C are combined at combiner 208 with the signal from first signal path 212, and the combined signal is then provided to DAC 110 at DAC input 112. DAC 110 then sends the signal to a DAC such as Figure 1 The DUT 106 shown and described above, or in other examples, to any other component or device.

[0036] In some instances, an IIR filter is used instead of a FIR filter 202. In a FIR filter, the impulse response becomes zero in a finite time period. However, an IIR filter uses internal feedback, so the IIR filter operates in an infinite time period. The feedback in the IIR filter considers past output samples, while the FIR filter has no feedback and only considers past and current input samples. FIR filters are generally more stable and easier to implement than IIR filters. FIR filters have a linear phase response, while IIR filters have a nonlinear phase response. However, IIR filters are generally faster than FIR filters and use less memory space.

[0037] Circuit 200 includes a second signal path 216 and an ADC 120 coupled to three delay equalization paths 218. In an example, ADC 120 receives a signal from DUT 106 via cable 108B. The signal arriving at ADC 120 may have multiple standing waves or ripples caused by delays 132D, 132E, and / or 132F. The filter 202 and delay equalization paths 218 coupled to ADC 120 compensate for these ripples or reflections. As an example, ADC 120 sends the signal to N-tap FIR filter 202E via second signal path 216. N is any integer and may be a different value from N in N-tap FIR filter 202A.

[0038] Delay equalization paths 218A, 218B, and 218C are paths coupled to ADC 120 that receive signals from second signal path 216 and operate similarly to delay equalization paths 214A, 214B, and 214C described above. First delay equalization path 218A includes gain component 206D, delay 204D, and P-tap FIR filter 202F. The value of gain component 206D, delay 204D (e.g., M1 samples), number of taps P, and the value of the tap coefficient in P-tap FIR filter 202F are selected to compensate for the specific reflection of the signal caused by delay 132. The value of the number of taps P and the tap coefficient in P-tap FIR filter 202F may be different from the value of the number of taps P and the tap coefficient in P-tap FIR filter 202B, 202C, or 202D. As an example, delay 132E ( Figure 1 ) creates a standing wave in the signal caused by the cable 108B coupling the DUT 106 to the ADC 120. The first delay equalization path 218A compensates for this standing wave caused by the delay 132E.

[0039] The second delay equalization path 218B includes a gain component 206E, a delay 204E, and a P-tap FIR filter 202G. The value of the tap coefficient in the gain component 206E, the delay 204E (e.g., M2 samples), the number of taps P, and the P-tap FIR filter 202G are selected to compensate for the specific reflection of the signal caused by the delay 132. The number of taps P and the value of the tap coefficient in the P-tap FIR filter 202G may be different from the number of taps P and the value of the tap coefficient in the other P-tap FIR filters 202. The gain amount provided by the gain component 206E and the delay length provided by the delay 204E may also be different from the gain and delay of these corresponding components found in the first delay equalization path 218A.

[0040] The third delay equalization path 218C includes a gain component 206F, a delay 204F, and a P-tap FIR filter 202H. The value of the gain component 206F, the delay 204F (e.g., M3 samples), the number of taps P, and the value of the tap coefficient in the P-tap FIR filter 202H are selected to compensate for the specific reflection of the signal caused by the delay 132. The value of the number of taps P and the tap coefficient in the P-tap FIR filter 202H may be different from the value of the number of taps P and the tap coefficient in the other P-tap FIR filters 202. The gain amount provided by the gain component 206F and the delay length provided by the delay 204F may also be different from the gain and delay of these corresponding components found in the first delay equalization path 218A or the second delay equalization path 218B.

[0041] The signals generated by delay equalization paths 218A, 218B, and 218C are combined at combiner 210 with the signal from second signal path 216, and the combined signal is then provided to output signal path 128. The combined signal is then processed by any suitable system, processor, or controller ( Figure 2 The example delay equalization paths 214 and 218 described herein operate to remove or compensate for standing waves caused by the delay 132 in the system 100.

[0042] In the examples described herein, the use of delay equalization paths 214 and 218 instead of a single large filter reduces the number of FIR taps in the system. As described above, taps require silicon area, power, and computation time. For example, in the example of a 64GSPS data converter, the fully programmable FIR filter has approximately 640 taps, while in some examples, the FIR filters 202 each have approximately 20 taps. Therefore, the delay path with a smaller FIR filter provides large area and computational savings while still compensating for reflections in the system as well as the fully programmable FIR filter or better than the fully programmable FIR filter. Moreover, the FIR filter 202 that filters the reflections has a reduced tap coefficient resolution away from the center peak of the reflection. For a fully programmable FIR filter, all tap coefficients require full resolution because the location of the center peak of the signal is unknown. The full resolution of all tap coefficients requires higher silicon area and power. Lower coefficient resolution allows fewer bits to be multiplied to implement the filter, which reduces hardware area and power consumption. In one example, a system (e.g. Figure 2 In the example of a 64 GSPS data converter, the fully programmable FIR filter has 640 taps. In another example, the fully programmable FIR filter has 16 coefficient bits for each tap. Thus, a system with 100 taps would have 1600 bits; a system with 200 taps would have 3200 bits, etc.

[0043] Figures 3A to 3C are graphs of the frequency domain response for cable response and standing waves in various examples herein. Figures 3A to 3C In each of , the x-axis represents the frequency in gigahertz (GHz), and the y-axis represents the amplitude of the signal. Figures 3A to 3C The waveforms shown in are examples and may be different in other systems.

[0044] Figure 3A 3 is a graph 300 including a waveform 302. In one example, the waveform 302 represents the response of a cable transmitting a signal. The waveform 302 shows the magnitude of the response decreasing as the frequency increases. Figure 3B 3 is a graph 320 including a waveform 322. In one example, the waveform 322 represents ripples caused by standing waves in the cable. The waveform 322 also loses amplitude as the frequency increases. As described above, the standing waves represented by the waveform 322 are reflected back to other components, such as the DAC 110 or the ADC 120.

[0045] Figure 3C302 and 322. Waveform 342 shows a small ripple and a gradual decrease in amplitude as frequency increases. Waveform 342 shows a signal without any equalization. In the example herein, equalization is performed to compensate for waveform 342. As an example, Figure 2 The filter compensation waveform 302 in the first signal path 212 in the delay equalization path 214A is shown in FIG. 3 , and the filter compensation waveform 322 in the delay equalization path 214A is shown in FIG. 3 . When the filters on these paths are combined with the filters and paths for other standing waves, all standing waves and cable responses are compensated in the system, as described above with respect to FIG. Figure 2 described.

[0046] Figure 4 400 is a graph of the frequency domain response of the FIR filter in various examples herein. In the graph 400, the x-axis represents the multiple of the frequency of the sampling rate (Fs) of the ADC (e.g., *Fs) and the y-axis represents the amplitude. The graph 400 represents the Nyquist zone between 0 and 0.5 times the sampling rate Fs, where the frequency response is unique. The graph 400 includes three waveforms 402, 404 and 406.

[0047] The waveform 402 in the graph 400 shows an example cable response or delay response. In this cable response, the amplitude of the signal transmitted by the cable decreases as the frequency increases, which is shown as the waveform 402 decreasing from left to right. In one example, the waveform 402 is described above with respect to Figure 4 C. To counteract this cable response, the composite response of the FIR filter is designed to compensate for the dip in waveform 402. These FIR filters include all of the FIR filters 202 in the system. Therefore, as shown in waveform 404, the composite response of the FIR filter 202 in the example circuit 200 increases as frequency increases.

[0048] Waveform 406 is a combination of waveforms 402 and 404. If FIR filter 202 filters the signal to compensate for the cable response (and other delays), the amplitude of the drop relative to frequency is removed. Waveform 406 is the result of a signal where FIR filter 202 is designed to compensate for the specific delay in the system represented by waveform 402. Waveform 406 is a mostly flat response, indicating that the composite FIR filter response represented by waveform 404 has compensated for the delay in this example.

[0049] In the examples herein, instead of using one large FIR filter to flatten the ripple, multiple filters with delays are implemented. The incoming digital signal passes through the main path and one or more parallel delay equalization paths. A delay equalization path with an FIR filter can be added for each reflection found in the digital signal. The examples described herein with multiple FIR filters are more effective than one large FIR filter. Variable integer sample delays are easier to implement than a large number of FIR taps. Moreover, the FIR filter has a reduced tap coefficient resolution away from the center of the FIR filter. Savings in area and power consumption are achieved by some examples described herein.

[0050] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in the first instance, device A is directly connected to device B; or (b) in the second instance, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intermediate component C, so device B is controlled by device A via the control signal provided by device A.

[0051] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0052] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0053] In this specification, unless otherwise specified, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter. Modifications may be made in the described examples, and other examples may be within the scope of the claims.

Claims

1. A circuit comprising: a first signal path comprising a first filter having a first number of taps and having an input and an output; a combiner having first and second inputs, said first input being coupled to said output of said first filter; as well as a second signal path coupled to the input of the first filter and to the second input of the combiner, the second signal path comprising: Gain components; a delay component coupled to the gain component; as well as A second filter has a second number of taps and is coupled to the delay component.

2. The circuit of claim 1 , wherein the gain component is a first gain component and the delay component is a first delay component, the circuit further comprising a third signal path coupled to the input of the first filter and the second input of the combiner, the third signal path comprising: a second gain component; a second delay component coupled to the second gain component; and A third filter has a third number of taps and is coupled to the second delay component. 3 . The circuit of claim 1 , wherein the second signal path is configured to compensate for reflections of digital signals in the circuit. 4 . The circuit of claim 3 , wherein the gain component is configured to scale the digital signal based on a magnitude of the reflection.

5. The circuit of claim 3, wherein the delay component is configured to delay the digital signal based on a delay of the reflection.

6. The circuit of claim 1, further comprising a digital-to-analog converter having an input coupled to an output of the combiner.

7. The circuit of claim 6, wherein: the gain component having an input coupled to the input of the first filter and having an output; The delay component has an input coupled to the output of the gain component and has an output; and The second filter has an input coupled to the output of the delay component and has an output coupled to the second input of the combiner.

8. The circuit of claim 1, further comprising an analog-to-digital converter having an output coupled to the input of the first filter.

9. The circuit of claim 8, wherein: the second filter having an input coupled to the input of the first filter and having an output; The delay component has an input coupled to the output of the second filter and has an output; and The gain component has an input coupled to the output of the delay component and has an output coupled to the second input of the combiner.

10. The circuit of claim 1, wherein the first filter and the second filter are finite impulse response filters.

11. The circuit of claim 1, wherein the first filter and the second filter are infinite impulse response filters.

12. A circuit comprising: a first filter having a first number of taps and having an input and an output; a combiner having first and second inputs, said first input being coupled to said output of said first filter; a second filter having a second number of taps; a gain component having an input coupled to the input of the first filter and having an output; a delay component having an input coupled to the output of the gain component and having an output, wherein the second filter has an input coupled to the output of the delay component, and wherein the second filter has an output coupled to the second input of the combiner; as well as a digital-to-analog converter having an input coupled to the output of the combiner.

13. The circuit of claim 12, wherein the second filter, gain component, and delay component are configured to compensate for reflections of digital signals in the circuit.

14. The circuit of claim 13, wherein the gain component is configured to scale the digital signal based on a magnitude of the reflection.

15. The circuit of claim 13, wherein the delay component is configured to delay the digital signal based on a delay of the reflection.

16. The circuit of claim 12, wherein the first filter and the second filter are finite impulse response filters.

17. A circuit comprising: a first filter having a first number of taps and having an input and an output; a combiner having first and second inputs, said first input being coupled to said output of said first filter; a second filter having a second number of taps and having an input coupled to the input of the first filter and having an output; a delay component having an input coupled to the output of the second filter and having an output; a gain component having an input coupled to the output of the delay component and having an output coupled to the second input of the combiner; as well as An analog-to-digital converter has an output coupled to the input of the first filter.

18. The circuit of claim 17, wherein the second filter, gain component, and delay component are configured to compensate for reflections of digital signals in the circuit.

19. The circuit of claim 18, wherein the gain component is configured to scale the digital signal based on a magnitude of the reflection.

20. The circuit of claim 18, wherein the delay component is configured to delay the digital signal based on a delay of the reflection.

21. The circuit of claim 17, wherein the first filter and the second filter are finite impulse response filters.

22. A circuit comprising: a first filter having a first number of taps and having an input and an output; a first combiner having first and second inputs, the first input coupled to the output of the first filter; a second filter having a second number of taps; a first gain component having an input coupled to the input of the first filter and having an output; a first delay component having an input coupled to the output of the first gain component and having an output, wherein the second filter has an input coupled to the output of the first delay component, and wherein the second filter has an output coupled to the second input of the first combiner; a digital-to-analog converter having an input coupled to the output of the first combiner; a third filter having a third number of taps and having an input and an output; a second combiner having first and second inputs, said first input being coupled to said output of said third filter; a fourth filter having a fourth number of taps and having an input coupled to the input of the third filter and having an output; a second delay component having an input coupled to the output of the fourth filter and having an output; a second gain component having an input coupled to the output of the second delay component and having an output coupled to the second input of the second combiner; as well as An analog-to-digital converter has an output coupled to the input of the third filter.

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