Track circuit and its method, device and medium for checking frequency shift signal

Abstract

The present invention discloses a track circuit, a method, a device and a medium for back-checking a frequency-shift signal. The back-checking method includes: obtaining a first count value of a first frequency-shift square wave, and determining whether the frequency of the first frequency-shift square wave meets a first requirement according to the first count value; obtaining a second count value of a second frequency-shift square wave, and determining whether the frequency of the second frequency-shift square wave meets a second requirement according to the second count value; obtaining a third count value of the frequency-shift signal output by the transformer, and determining whether the frequency of the frequency-shift signal output by the transformer meets a third requirement according to the third count value; when the frequency of the first frequency-shift square wave meets the first requirement, the frequency of the second frequency-shift square wave meets the second requirement, and the frequency of the frequency-shift signal output by the transformer meets the third requirement, determining that the frequency-shift signal is correct. The technical solution of the present invention realizes the back-check of the correctness of the frequency-shift signal in multiple aspects to improve the correctness of the frequency-shift signal, thereby improving the track safety.

Description

Technical Field

[0001] The present invention relates to the field of digital signal technology, and in particular to a track circuit, a method, a device and a medium for detecting the frequency shift signal in the track circuit backwards. Background Art

[0002] In a communication coding track circuit, the main function of the transmitter is to generate a sinusoidal wave signal with continuous phase and frequency modulation according to the carrier frequency and low frequency configuration. The sinusoidal wave signal is sent into the rail through the configurable tap of the transformer to generate a transmit signal with a flexibly adjustable amplitude, so as to realize the inspection of the idle / occupied state of the section where the track circuit is located. Therefore, the correctness of the transmit signal sent into the rail is crucial for track safety.

[0003] At present, the backward inspection of the transmit signal includes the amplitude inspection of the backward inspection tap of the transformer and the frequency inspection of the frequency shift square wave inside the Field-Programmable Gate Array (FPGA). The inspection accuracy of the correctness of the transmit signal sent into the rail is relatively low. Summary of the Invention

[0004] The present invention provides a track circuit, a method, a device and a medium for detecting the frequency shift signal in the track circuit backwards, so as to solve the defects of the prior art, realize the backward inspection of the correctness of the frequency shift signal in multiple aspects, improve the correctness of the frequency shift signal, and further improve the track safety.

[0005] In a first aspect, the present invention provides a method for detecting the frequency shift signal in the track circuit backwards, including:

[0006] Obtaining a first count value of a first frequency shift square wave, and determining whether the frequency of the first frequency shift square wave meets a first requirement according to the first count value;

[0007] Obtaining a second count value of a second frequency shift square wave, and determining whether the frequency of the second frequency shift square wave meets a second requirement according to the second count value; the first frequency shift square wave forms a first frequency shift sine wave through a digital-to-analog converter, and the first frequency shift sine wave forms a second frequency shift square wave through a zero-crossing detection circuit;

[0008] Obtaining a third count value of the frequency shift signal output by the transformer, and determining whether the frequency of the frequency shift signal output by the transformer meets a third requirement according to the third count value;

[0009] When the frequency of the first frequency shift square wave meets the first requirement, the frequency of the second frequency shift square wave meets the second requirement, and the frequency of the frequency shift signal output by the transformer meets the third requirement, it is determined that the frequency shift signal is correct.

[0010] Optionally, when the frequency of the first frequency-shifted square wave does not meet the first requirement, the frequency of the second frequency-shifted square wave does not meet the second requirement, or the frequency of the frequency-shifted signal output by the transformer does not meet the third requirement, it is determined that the frequency-shifted signal is incorrect.

[0011] Optionally, it is characterized in that obtaining a first count value of the first frequency-shifted square wave and determining whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value includes:

[0012] Under the excitation of a first fixed clock signal, a first register is used to count the first frequency-shifted square wave to obtain the first count value;

[0013] According to the first count value and a first table, determine a first upper side frequency and a first lower side frequency of the first frequency-shifted square wave;

[0014] According to the first upper side frequency and the first lower side frequency, determine whether the frequency of the first frequency-shifted square wave meets the first requirement.

[0015] Optionally, determining whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first upper side frequency and the first lower side frequency includes:

[0016] According to the first upper side frequency, the first lower side frequency, and 5 continuously collected first count values, determine a first switching point value of the upper and lower side frequencies;

[0017] According to two adjacent first switching point values and the first count values between the two first switching point values, determine a cumulative count result between the two adjacent first switching point values, and record it as a first cumulative count value;

[0018] According to 5 continuously collected first count values, the first switching point value, and the first cumulative count value, determine a first carrier frequency and a first low frequency of the first frequency-shifted square wave;

[0019] According to the first carrier frequency and the first low frequency, determine whether the frequency of the first frequency-shifted square wave meets the first requirement.

[0020] Optionally, determining whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first carrier frequency and the first low frequency includes:

[0021] When the absolute value of the difference between the first carrier frequency and the expected value of the carrier frequency is less than or equal to the first carrier frequency value, and the absolute value of the difference between the first low frequency and the expected value of the low frequency is less than or equal to the first low frequency value, it is determined that the frequency of the first frequency-shifted square wave meets the first requirement.

[0022] Optionally, obtaining a second count value of the second frequency-shifted square wave, and determining whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second count value, includes:

[0023] Under the excitation of a second fixed clock signal, using a second register to count the second frequency-shifted square wave to obtain the second count value;

[0024] According to the second count value and a second table, determining a second upper sideband frequency and a second lower sideband frequency of the second frequency-shifted square wave;

[0025] According to the second upper sideband frequency and the second lower sideband frequency, determining whether the frequency of the second frequency-shifted square wave meets the second requirement.

[0026] Optionally, determining whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second upper sideband frequency and the second lower sideband frequency, includes:

[0027] According to the second upper sideband frequency, the second lower sideband frequency, and 5 continuously collected second count values, determining a second switching point value of the second upper sideband frequency and the second lower sideband frequency;

[0028] According to two adjacent second switching point values and the second count value between the two second switching point values, determining a cumulative count result between the two adjacent second switching point values, and recording it as a second cumulative count value;

[0029] According to 5 continuously collected second count values, the second switching point value, and the second cumulative count value, determining a second carrier frequency and a second low frequency of the second frequency-shifted square wave;

[0030] According to the second carrier frequency and the second low frequency, determining whether the frequency of the second frequency-shifted square wave meets the second requirement.

[0031] Optionally, determining whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second carrier frequency and the second low frequency, includes:

[0032] When the absolute value of the difference between the second carrier frequency and the expected value of the carrier frequency is less than or equal to the second carrier frequency value, and the absolute value of the difference between the second low frequency and the expected value of the low frequency is less than or equal to the second low frequency value, determining that the frequency of the second frequency-shifted square wave meets the second requirement.

[0033] Optionally, obtaining a third count value of the frequency-shifted signal output by the transformer, and determining whether the frequency of the frequency-shifted signal output by the transformer meets a third requirement according to the third count value, includes:

[0034] After attenuating the frequency-shifted signal output by the transformer, sample and count the frequency-shifted signal output by the transformer at a set frequency to obtain the three count values;

[0035] According to the latest obtained preset number of the third count values, determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

[0036] Optionally, according to the latest obtained preset number of the third count values, determining whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement includes:

[0037] Form an N×N matrix M1 with every N 2 of the third count values;

[0038] Generate an N×2 signal basis matrix B with a single-frequency f1; the first column elements of the signal basis matrix B are 100×sin(2×π×i / 8192×f1 + π / 6), and the second column elements of the signal basis matrix B are 100×cos(2×π×i / 8192×f1 + π / 6); where i takes integers between [0,7] in sequence, the range of the single-frequency f1 is: fc - 25Hz ≤ f1 ≤ fc + 25Hz, the accuracy of f1 is 0.1Hz, and fc is the expected carrier frequency value;

[0039] According to the matrix M1 and the signal basis matrix B, determine the signal basis projection matrix T1;

[0040] According to the signal basis projection matrix T1, determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

[0041] Optionally, according to the matrix M1 and the signal basis matrix B, determining the signal basis projection matrix T1 includes:

[0042] Perform singular value decomposition on the autocorrelation matrix M3 of the matrix M1 to obtain the U matrix;

[0043] Take the last 5-row submatrix of the transpose matrix of the U matrix as the matrix U3;

[0044] Multiply the matrix U3 and the signal basis matrix B to obtain the signal basis projection matrix T1.

[0045] Optionally, according to the signal basis projection matrix T1, determining whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement includes:

[0046] Sum the squares of each element in the signal basis projection matrix T1 to obtain the signal basis projection error D;

[0047] Based on the signal base projection error D, determine the projection error D1 at the upper sideband timing and the projection error D2 at the lower sideband timing;

[0048] Based on the projection error D1 at the upper sideband timing and the projection error D2 at the lower sideband timing, determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

[0049] In a second aspect, the present invention provides a frequency-shifted signal feedback detection device for an orbital circuit, which is characterized by comprising:

[0050] A first acquisition and judgment module, configured to acquire a first count value of a first frequency-shifted square wave, and based on the first count value, determine whether the frequency of the first frequency-shifted square wave meets the first requirement;

[0051] A second acquisition and judgment module, configured to acquire a second count value of a second frequency-shifted square wave, and based on the second count value, determine whether the frequency of the second frequency-shifted square wave meets the second requirement; the first frequency-shifted square wave forms a first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave forms a second frequency-shifted square wave through a zero-crossing detection circuit;

[0052] A third acquisition and judgment module, configured to acquire a third count value of the frequency-shifted signal output by the transformer, and based on the third count value, determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement;

[0053] A determination module, configured to determine that the frequency-shifted signal is correct when the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

[0054] In a third aspect, the present invention provides an orbital circuit, comprising:

[0055] At least one processor;

[0056] And a memory communicatively connected to the at least one processor; wherein, the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method described in any one of the above.

[0057] In a fourth aspect, the present invention provides a computer storage medium, which stores computer instructions for causing a processor to implement the method described in any one of the above when executed.

[0058] The technical solution of the present invention is to obtain the first count value of the first frequency-shifted square wave, and determine whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value. The first frequency-shifted square wave forms the first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave forms the second frequency-shifted square wave through a zero-crossing detection circuit. By obtaining the second count value of the second frequency-shifted square wave, it is determined whether the frequency of the second frequency-shifted square wave meets the second requirement. By obtaining the third count value of the frequency-shifted signal output by the transformer, it is determined whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement. Thus, when the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, it is determined that the frequency-shifted signal is correct. In this way, the correctness of the frequency-shifted signal is back-checked in multiple aspects, improving the correctness of the frequency-shifted signal and further improving the track safety.

[0059] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0061] Figure 1 It is a flowchart of a method for back-checking the frequency-shifted signal of a track circuit provided in Embodiment 1 of the present invention;

[0062] Figure 2 It is a flowchart of a method for back-checking the frequency-shifted signal of a track circuit provided in Embodiment 2 of the present invention;

[0063] Figure 3 It is a flowchart of a method for back-checking the frequency-shifted signal of a track circuit provided in Embodiment 3 of the present invention;

[0064] Figure 4 It is a schematic structural diagram of a device for back-checking the frequency-shifted signal of a track circuit provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0066] It should be noted that the terms "first", "second", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0067] Embodiment 1

[0068] Figure 1 The figure is a flowchart of a method for back-checking the frequency-shift signal of a track circuit provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation of determining the correctness of the frequency-shift signal of the track circuit. This method can be executed by a frequency-shift signal back-checking device of the track circuit. The back-checking device can be implemented in the form of hardware and / or software, and the back-checking device can be configured in a processor. As Figure 1 shown, the method includes:

[0069] S110. Obtain the first count value of the first frequency-shift square wave, and determine whether the frequency of the first frequency-shift square wave meets the first requirement according to the first count value.

[0070] Among them, the generation method of the track circuit frequency-shift signal is that the FPGA generates a first-frequency square wave with high-precision phase continuity according to the carrier frequency and the low frequency. Then, the first frequency-shift square wave is converted into a frequency-shift sine wave through a configurable filter chip MAX260 or a digital-to-analog converter. After the frequency-shift sine wave is amplified by a signal amplifier, a frequency-shift signal with different voltage levels is formed according to actual needs through a transformer with an externally configurable turns ratio, and finally the frequency-shift signal is output to the rail to realize the inspection of the idle / occupied state of the section where the track circuit is located.

[0071] In an alternative embodiment, the FPGA adds the upper sideband control word and the lower sideband control word (the switching frequency between the upper sideband control word and the lower sideband controller is the low frequency) to the phase control word register under the excitation of a fixed clock, such as a 36.48 MHz fixed clock. The phase control word determines the input address of the look-up table, and the most significant bit (0 or 1) of the data output by the look-up table forms the first frequency-shifted square wave. The data output by the look-up table is directly or sampled and then used as the input of the digital-to-analog converter, so that the digital-to-analog converter forms a frequency-shifted sine wave.

[0072] The first count value of the first frequency-shifted square wave can be understood as the frequency value obtained by counting the first frequency-shifted square wave under the excitation of the clock signal each time. Since the FPGA generates the first frequency-shifted square wave according to the carrier frequency and the low frequency, the frequency of the first frequency-shifted square wave should correspond to the carrier frequency and the low frequency. The first requirement is set according to the accuracy requirement of the first frequency-shifted square wave and the accuracy of the track circuit, and the first requirement is related to the carrier frequency and the low frequency. Therefore, according to the first count value of the first frequency-shifted square wave, it can be determined whether the frequency of the first frequency-shifted square wave meets the first requirement. When the first count value meets the first requirement, it indicates that the frequency of the first frequency-shifted square wave output by the FPGA is correct. On the contrary, when the first count value does not meet the first requirement, it indicates that the frequency of the first frequency-shifted square wave output by the FPGA is incorrect. At this time, the transformer is stopped from outputting the frequency-shifted signal to ensure the safety of the track.

[0073] S120. Obtain the second count value of the second frequency-shifted square wave, and determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second count value.

[0074] Among them, the first frequency-shifted square wave forms the first frequency-shifted sine wave through the digital-to-analog converter, and the first frequency-shifted sine wave forms the second frequency-shifted square wave through the zero-crossing detection circuit. Specifically, the input end of the digital-to-analog converter is electrically connected to the output end of the FPGA, and the output end of the digital-to-analog converter is electrically connected to the input end of the FPGA through the zero-crossing detection circuit, so that the first frequency-shifted square wave formed by the FPGA forms the first frequency-shifted sine wave through the digital-to-analog converter, and the first frequency-shifted sine wave is reshaped into the second frequency-shifted square wave through the zero-crossing detection circuit.

[0075] The second count value of the second frequency-shifted square wave can be understood as the frequency value obtained by counting the second frequency-shifted square wave under the excitation of the clock signal each time. Since the FPGA generates the first frequency-shifted square wave based on the carrier frequency and the low frequency, and the second frequency-shifted square wave is converted from the first frequency-shifted square wave, the frequency of the second frequency-shifted square wave should also correspond to the carrier frequency and the low frequency. The second requirement is set according to the accuracy requirement of the second frequency-shifted square wave and the accuracy of the track circuit, and the second requirement is related to the carrier frequency and the low frequency. Therefore, according to the second count value of the second frequency-shifted square wave, it can be determined whether the frequency of the second frequency-shifted square wave meets the second requirement. When the second count value meets the second requirement, it indicates that the frequency of the second frequency-shifted square wave is correct, that is, the frequency of the first frequency-shifted sine wave output by the digital-to-analog converter is correct. On the contrary, when the second count value does not meet the second requirement, it indicates that the frequency of the second frequency-shifted square wave is incorrect, that is, the frequency of the first frequency-shifted sine wave output by the digital-to-analog converter is incorrect. At this time, the transformer is stopped from outputting the frequency-shifted signal to ensure the safety of the track.

[0076] S130. Obtain the third count value of the frequency-shifted signal output by the transformer, and determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the third count value.

[0077] Among them, the output terminal of the digital-to-analog converter is also electrically connected to the transformer. The output side of the transformer includes a tap with a variable ratio that can be configured by external wiring and a feedback tap with a fixed ratio. The tap with a variable ratio that can be configured by external wiring is electrically connected to the track circuit to output a frequency-shifted signal to the track. The feedback tap with a fixed ratio is electrically connected to the AD pin of the central processing unit (CPU) through an attenuation circuit, so that the CPU can count the frequency-shifted signal output by the feedback tap of the transformer.

[0078] The third count value of the frequency-shifted signal output by the transformer can be understood as the frequency value obtained by counting the frequency-shifted signal output by the transformer under the excitation of the clock signal each time. Since the FPGA generates the first frequency-shifted square wave based on the carrier frequency and the low frequency, the first frequency-shifted square wave is converted into the first frequency-shifted sine wave by the analog-to-digital converter, and the first frequency-shifted sine wave is output as a frequency-shifted signal after passing through the transformer. Therefore, the frequency of the frequency-shifted signal output by the transformer should correspond to the carrier frequency and the low frequency. The third requirement is set according to the accuracy requirement of the frequency-shifted signal and the accuracy of the track circuit, and the third requirement is related to the carrier frequency and the low frequency. Therefore, according to the third count value of the frequency-shifted signal output by the transformer, it can be determined whether the frequency-shifted signal output by the transformer meets the third requirement. When the frequency-shifted signal output by the transformer meets the third requirement, it indicates that the frequency of the frequency-shifted signal output by the transformer is correct. On the contrary, when the frequency-shifted signal output by the transformer does not meet the third requirement, it indicates that the frequency of the frequency-shifted signal output by the transformer is incorrect. At this time, the transformer is stopped from outputting the frequency-shifted signal to ensure the safety of the track.

[0079] S140. When the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, it is determined that the frequency-shifted signal is correct.

[0080] Optionally, when the frequency of the first frequency-shifted square wave does not meet the first requirement, the frequency of the second frequency-shifted square wave does not meet the second requirement, or the frequency of the frequency-shifted signal output by the transformer does not meet the third requirement, it is determined that the frequency-shifted signal is incorrect.

[0081] Specifically, obtain the first count value of the first frequency-shifted square wave, and determine whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value. Obtain the second count value of the second frequency-shifted square wave, and determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second count value. Obtain the third count value of the frequency-shifted signal output by the transformer, and determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the third count value. When the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, it indicates that the frequency-shifted signal sent by the track circuit is correct. When the frequency of the first frequency-shifted square wave does not meet the first requirement, the frequency of the second frequency-shifted square wave does not meet the second requirement, or the frequency of the frequency-shifted signal output by the transformer does not meet the third requirement, that is, when at least one of the frequency of the first frequency-shifted square wave, the frequency of the second frequency-shifted square wave, and the frequency of the frequency-shifted signal output by the transformer does not meet the corresponding requirement, it is determined that the frequency-shifted signal is incorrect.

[0082] In this embodiment, by obtaining the first count value of the first frequency-shifted square wave to determine whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value, the first frequency-shifted square wave forms the first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave forms the second frequency-shifted square wave through a zero-crossing detection circuit. By obtaining the second count value of the second frequency-shifted square wave to determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second count value, and by obtaining the third count value of the frequency-shifted signal output by the transformer to determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement, so when the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, it is determined that the frequency-shifted signal is correct. In this way, the correctness of the frequency-shifted signal is back-checked from multiple aspects, the correctness of the frequency-shifted signal is improved, and thus the track safety is improved.

[0083] Embodiment 2

[0084] Figure 2This is a flowchart of a method for detecting the frequency shift signal of a track circuit provided in the second embodiment of the present invention. On the basis of the above embodiment, this embodiment further adds steps on how to obtain the first count value and determine whether the frequency of the first frequency shift square wave meets the requirements according to the first count value, how to obtain the second count value and determine whether the frequency of the second frequency shift square wave meets the requirements according to the second count value, and how to obtain the third count value and determine whether the frequency of the frequency shift signal output by the transformer meets the requirements. As Figure 2 shown, the method specifically includes:

[0085] S210. Under the excitation of the first fixed clock signal, use the first register to count the first frequency shift square wave to obtain the first count value.

[0086] Among them, the first fixed clock signal can be, but is not limited to, generated by a 40MHz independent clock. The first register can be, but is not limited to, a 16-bit register. It should be noted that each time the first fixed clock signal is excited, the first register counts the first frequency shift square wave once to obtain a first count value. Since the first fixed clock signal excites the first frequency shift square wave at a fixed time period, the first register can obtain multiple first count values.

[0087] S220. According to the first count value and the first table, determine the first upper sideband frequency and the first lower sideband frequency of the first frequency shift square wave.

[0088] Among them, the upper sideband frequency and the lower sideband frequency refer to the frequency components of the modulation signal. The upper sideband frequency is above the carrier frequency, and the lower sideband frequency is below the carrier frequency. The first table (Table 1) records the first upper sideband frequency range and the first lower sideband frequency range of the first frequency shift square wave at different carrier frequencies. Therefore, according to the first count value and the first table, the first upper sideband frequency and the first lower sideband frequency of the first frequency shift square wave can be determined. Among them, in Table 1, 1700-1 is the carrier frequency of 1701.4Hz, 1700-2 is the carrier frequency of 1698.7Hz, 2000-1 is the carrier frequency of 2001.4Hz, 2000-2 is the carrier frequency of 1998.7Hz, 2300-1 is the carrier frequency of 2301.4Hz, 2300 is the carrier frequency of 2298.7Hz, 2600-1 is the carrier frequency of 2601.4Hz, and 2600-2 is the carrier frequency of 2598.7Hz. The lower limit of Range 1 to the upper limit of Range 1 is the first upper sideband frequency range, and the lower limit of Range 2 to the upper limit of Range 2 is the first lower sideband frequency range.

[0089] Table 1. The first table

[0090]

[0091] S230. According to the first upper sideband frequency and the first lower sideband frequency, determine whether the frequency of the first frequency shift square wave meets the first requirement.

[0092] Among them, based on the first upper side frequency and the first lower side frequency, the upper and lower side frequency switching point and the first count value between the upper and lower side frequency switching points can be determined. Furthermore, it can be determined whether the frequency of the first frequency-shifted square wave meets the first requirement. Herein, the upper and lower side frequency switching point can be understood as the first count value collected when switching from the first upper side frequency to the first lower side frequency, or the first count value collected when switching from the first lower side frequency to the first upper side frequency.

[0093] Specifically, under the excitation of the first fixed clock signal, the first register obtains multiple first count values at a fixed time period. Based on each first count value, by looking up the first table, the first upper side frequency and the first lower side frequency of the first frequency-shifted square wave are determined. There are also multiple first upper side frequencies and first lower side frequencies. Based on the first upper side frequencies and first lower side frequencies obtained at different time periods, it is determined whether the frequency of the first frequency-shifted square wave meets the first requirement.

[0094] Optionally, determining whether the frequency of the first frequency-shifted square wave meets the first requirement based on the first upper side frequency and the first lower side frequency includes: determining the first switching point value of the switching point of the upper and lower side frequencies according to the first upper side frequency, the first lower side frequency, and 5 continuously collected first count values; determining the cumulative count result between two adjacent first switching point values according to two adjacent first switching point values and the first count value between these two first switching point values, and recording it as the first cumulative count value; determining the first carrier frequency and the first low frequency of the first frequency-shifted square wave according to the 5 continuously collected first count values, as well as the first switching point value and the first cumulative count value; and determining whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first carrier frequency and the first low frequency.

[0095] Among them, under the excitation of the first fixed clock, the 5 continuously collected first count values can reflect the waveform of the first frequency-shifted square wave. Exemplarily, among the 5 continuously collected first count values, all 5 first count values may be the upper side frequency, or some first count values are the upper side frequency, some first count values are the lower side frequency, and some first count values are neither the upper side frequency nor the lower side frequency, that is, the first switching point value of the upper and lower side frequencies, or all 5 first count values are the lower side frequency. Therefore, the first switching point value of the switching point of the upper and lower side frequencies is determined according to the first upper side frequency, the first lower side frequency, and the 5 continuously collected first count values.

[0096] In an optional embodiment, the specific method for determining the first carrier frequency and the first low frequency of the first frequency-shifted square wave according to the 5 continuously collected first count values, as well as the first switching point value and the first cumulative count value is as follows:

[0097] The three consecutive first switching point values are the first first switching point value, the second first switching point value, and the third first switching point value respectively.

[0098] The calculation method of the first carrier frequency is as follows: The first carrier frequency = (the first cumulative count value between the first first switching point value and the second first switching point value / the accumulation times of the first cumulative count value between the first first switching point value and the second first switching point value + the first cumulative count value between the second first switching point value and the third first switching point value / the accumulation times of the first cumulative count value between the second first switching point value and the third first switching point value) × the frequency of the first fixed clock / 2.

[0099] When the first first switching point value and the third first switching point value are the upper sideband and lower sideband switching points, and the second first switching point value is the lower sideband and upper sideband switching point, the calculation method of the first low frequency is as follows:

[0100] The first low frequency = [(the first first switching point value - the lower limit of range 1) / (the lower limit of range 2 - the lower limit of range 1) × the lower limit of range 2 + the second first switching point value + the first cumulative count value between the first first switching point value and the second first switching point value + the first cumulative count value between the second first switching point value and the third first switching point value + (the lower limit of range 2 - the third first switching point value) / (the lower limit of range 2 - the lower limit of range 1) × the lower limit of range 1] × the frequency of the first fixed clock.

[0101] When the first first switching point value and the third first switching point value are the lower sideband and upper sideband switching points, and the second first switching point value is the upper sideband and lower sideband switching point, the calculation method of the first low frequency is as follows:

[0102] The first low frequency = [(the lower limit of range 2 - the first first switching point value) / (the lower limit of range 2 - the lower limit of range 1) × the lower limit of range 1 + the second first switching point value + the first cumulative count value between the first first switching point value and the second first switching point value + the first cumulative count value between the second first switching point value and the third first switching point value + (the third first switching point value - the lower limit of range 1) / (the lower limit of range 2 - the lower limit of range 1) × the lower limit of range 2] × the frequency of the first fixed clock.

[0103] Optionally, according to the first carrier frequency and the first low frequency, determine whether the frequency of the first frequency-shifted square wave meets the first requirement, including: when the absolute value of the difference between the first carrier frequency and the expected carrier frequency value is less than or equal to the first carrier frequency value, and the absolute value of the difference between the first low frequency and the expected low frequency value is less than or equal to the first low frequency value, determine that the frequency of the first frequency-shifted square wave meets the first requirement.

[0104] In an optional embodiment, when the absolute value of the difference between the first carrier frequency and the expected carrier frequency value is greater than the first carrier frequency value, or the absolute value of the difference between the first low frequency and the expected low frequency value is greater than the first low frequency value, determine that the frequency of the first frequency-shifted square wave does not meet the first requirement.

[0105] Among them, the expected carrier frequency value is the carrier frequency code obtained by the track circuit. Exemplarily, the carrier frequency is one of the eight carrier frequencies: 1701.4Hz, 1698.7Hz, 2001.4Hz, 1998.7Hz, 2301.4Hz, 2298.7Hz, 2601.4Hz, and 2598.7Hz. The expected low-frequency value is the low-frequency code obtained by the track circuit. Exemplarily, it is one of the eighteen low frequencies: 10.3Hz, 11.4Hz, 12.5Hz, 13.6Hz, 14.7Hz, 15.8Hz, 16.9Hz, 18.0Hz, 19.1Hz, 20.2Hz, 21.3Hz, 22.4Hz, 23.5Hz, 24.6Hz, 25.7Hz, 26.8Hz, 27.9Hz, and 29Hz. The first carrier frequency value is set according to the expected carrier frequency value, the accuracy of the track circuit, etc. Exemplarily, the first carrier frequency value is 0.05Hz. The first low-frequency value is set according to the expected low-frequency value, the accuracy of the track circuit, etc. Exemplarily, the first low-frequency value is 0.03Hz.

[0106] In a specific embodiment, under the excitation of a 40 MHz fixed clock signal, the first frequency-shifted square wave output by the FPGA is counted, and the counting result is stored in a 16-bit register, that is, the first count value is stored in a 16-bit register. The range of the first count value is 0 to 32768. The highest bit of the 16-bit register represents the update flag bit. When each first count value is acquired, the update flag bit is toggled. The CPU of the track circuit queries the counting result of the 16-bit register at a frequency of 8192 Hz. Since the reading frequency of the CPU (8192 Hz) is much higher than the frequency of the first fixed clock signal (40 MHz), there will be duplicates in the counting results read by the CPU, that is, multiple identical first count values are continuously read. Therefore, the highest bit of the counting result read by the CPU is the update flag bit. When the update flag bit read by the CPU is different from the currently recorded update flag bit, it indicates that the counting result read by the CPU is valid data, that is, the first count value. Since the carrier frequency encoding is known, when the first count value, that is, the lower 15 bits of the read valid data, is between the lower limit and the upper limit of Range 1 in the first table (Table 1), the first count value is considered to be the upper sideband frequency. When the first count value, that is, the lower 15 bits of the read valid data, is between the lower limit and the upper limit of Range 2 in the first table (Table 1), the first count value is considered to be the lower sideband frequency. Five buffers H1 - H5 are set in the CPU. Each buffer H is used to store a first count value. A buffer Q is set to record the first count value of the latest upper and lower sideband switching point, that is, the first switching point value. An accumulative counter S is set to record the cumulative counting result between two adjacent first switching point values, that is, the first cumulative count value. When a new first count value is captured, the last buffer H5 is used to record the newly captured first count value, and the positions of buffers H1, H2, H3, and H4 are used to save the results of buffers H2, H3, H4, and H5.After each update of the buffer, the following judgments and operations are performed: If the first count values of the first two (H1, H2) are between the upper limit and the lower limit of range 1 (upper side frequency), and the first count values of the last two (H4, H5) are between the upper limit and the lower limit of range 2 (lower side frequency), then the first count value recorded in the third buffer H3 is the upper and lower side frequency switching point, that is, the first switching point. After locking the upper and lower side frequency switching point, save the upper and lower side frequency switching point to buffer Q1, and update the cumulative count result of the cumulative counter S. Then, the carrier frequency and low frequency of the first frequency-shifted square wave can be calculated using Q1, S, and H1~H5. By comparing the carrier frequency with the expected carrier frequency value and comparing the low frequency with the expected low frequency value, when the carrier frequency error is greater than 0.05 Hz (the first carrier frequency value) and the low frequency error is greater than 0.03 Hz (the first carrier frequency value), it is considered that the frequency of the first frequency-shifted square wave does not meet the first requirement, that is, the back-check fails. At this time, stop the output of the power output signal, lock the upper and lower side frequency switching point, after completing the clearing of the carrier frequency and low frequency, update the count result of buffer H3 to Q1, reset the cumulative counter S to the sum of buffer H4 and buffer H5, and start a new round of real-time back-check calculation.

[0107] In an optional embodiment, in addition to performing frequency back-check on the first frequency-shifted square wave, CRC32 check is also performed on the content of the look-up table to prevent the input signal of the digital-to-analog converter from not meeting the expectation due to errors in the look-up table.

[0108] S240. Under the excitation of the second fixed clock signal, use the second register to count the second frequency-shifted square wave to obtain the second count value.

[0109] Among them, the second fixed clock signal can be but is not limited to being generated by a 40 MHz independent clock. The first register can be but is not limited to a 16-bit register. It should be noted that the second fixed clock signal is not limited to being the same as the first fixed clock signal, and the second register is not limited to being the same as the first register, as long as the core inventive point of the present invention can be achieved.

[0110] It should also be noted that each time the second fixed clock signal is excited, the second register counts the second frequency-shifted square wave once to obtain a second count value. Since the second fixed clock signal excites the second frequency-shifted square wave at a fixed time period, the second register can obtain multiple second count values.

[0111] S240. Determine the second upper side frequency and the second lower side frequency of the second frequency-shifted square wave according to the second count value and the second table.

[0112] Among them, the second table (Table 2) records the second upper frequency range and the second lower frequency range of the second frequency-shifted square wave at different carrier frequencies. Thus, according to the second count value and the second table, the second upper frequency and the second lower frequency of the second frequency-shifted square wave can be determined. Among them, the range from the lower limit of Range 3 to the upper limit of Range 3 is the second upper frequency range, and the range from the lower limit of Range 4 to the upper limit of Range 4 is the second lower frequency range.

[0113] Table 2. Second Table

[0114]

[0115] S260. Determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second upper frequency and the second lower frequency.

[0116] Among them, according to the second upper frequency and the second lower frequency, the second count value between the upper and lower frequency switching points and the upper and lower frequency switching points can be determined, and further, whether the frequency of the second frequency-shifted square wave meets the second requirement can be determined. Among them, the upper and lower frequency switching points can be understood as the second count value collected when switching from the second upper frequency to the second lower frequency, or the second count value collected when switching from the second lower frequency to the second upper frequency.

[0117] Specifically, under the excitation of the second fixed clock signal, the second register obtains multiple second count values at a fixed time period. According to each second count value, the second table is searched to determine the second upper frequency and the second lower frequency of the second frequency-shifted square wave. There are also multiple second upper frequencies and second lower frequencies. According to the second upper frequencies and second lower frequencies obtained in different time periods, it is determined whether the frequency of the second frequency-shifted square wave meets the second requirement.

[0118] Optionally, determining whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second upper frequency and the second lower frequency includes: determining the second switching point value of the second upper frequency and the second lower frequency according to the second upper frequency, the second lower frequency, and 5 continuously collected second count values; determining the cumulative count result between two adjacent second switching point values according to the two adjacent second switching point values and the second count value between the two second switching point values, and recording it as the second cumulative count value; determining the second carrier frequency and the second low frequency of the second frequency-shifted square wave according to the 5 continuously collected second count values, the second switching point value, and the second cumulative count value; determining whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second carrier frequency and the second low frequency.

[0119] Among them, under the excitation of the second fixed clock, the five continuously collected second count values can feedback the waveform of the second frequency-shifted square wave. Exemplarily, all five second count values among the continuously collected five second count values may be the upper side frequencies, or some second count values are the upper side frequencies, some second count values are the lower side frequencies, and some second count values are neither the upper side frequencies nor the lower side frequencies, that is, the second switching point value of the upper and lower side frequencies, or all five second count values are the lower side frequencies. Therefore, according to the second upper side frequency, the second lower side frequency, and the five continuously collected second count values, the second switching point value of the switching point of the upper and lower side frequencies is determined.

[0120] In an optional embodiment, the specific method for determining the second carrier frequency and the second low frequency of the second frequency-shifted square wave according to the five continuously collected second count values, the second switching point value, and the second cumulative count value is as follows:

[0121] The three consecutive second switching point values are the first second switching point value, the second second switching point value, and the third second switching point value respectively.

[0122] The calculation method of the second carrier frequency is as follows: Second carrier frequency = (Second cumulative count value between the first second switching point value and the second second switching point value / Accumulation times of the second cumulative count value between the first second switching point value and the second second switching point value + Second cumulative count value between the second second switching point value and the third second switching point value / Accumulation times of the second cumulative count value between the second second switching point value and the third second switching point value) × Frequency of the second fixed clock / 2.

[0123] When the first second switching point value and the third second switching point value are the upper side frequency and lower side frequency switching points, and the second second switching point value is the lower side frequency and upper side frequency switching point, the calculation method of the second low frequency is as follows:

[0124] Second low frequency = [(First second switching point value - Lower limit of range 3) / (Lower limit of range 4 - Lower limit of range 3) × Lower limit of range 4 + Second second switching point value + Second cumulative count value between the first second switching point value and the second second switching point value + Second cumulative count value between the second second switching point value and the third second switching point value + (Lower limit of range 4 - Third second switching point value) / (Lower limit of range 4 - Lower limit of range 3) × Lower limit of range 3] × Frequency of the second fixed clock.

[0125] When the first second switching point value and the third second switching point value are the lower side frequency and upper side frequency switching points, and the second second switching point value is the upper side frequency and lower side frequency switching point, the calculation method of the second low frequency is as follows:

[0126] Second low frequency = [(Lower limit of range 4 - First and second switching point value) / (Lower limit of range 4 - Lower limit of range 3) × Lower limit of range 3 + Second and second switching point value + Second cumulative count value between first and second switching point value and second and second switching point value + Second cumulative count value between second and second switching point value and third and second switching point value + (Third and second switching point value - Lower limit of range 3) / (Lower limit of range 4 - Lower limit of range 3) × Lower limit of range 4] × Frequency of second fixed clock.

[0127] Optionally, determine whether the frequency of the second frequency - shifted square wave meets the second requirement according to the second carrier frequency and the second low frequency, including: when the absolute value of the difference between the second carrier frequency and the expected carrier frequency value is less than or equal to the second carrier frequency value, and the absolute value of the difference between the second low frequency and the expected low frequency value is less than or equal to the second low frequency value, determine that the frequency of the second frequency - shifted square wave meets the second requirement.

[0128] In an alternative embodiment, when the absolute value of the difference between the second carrier frequency and the expected carrier frequency value is greater than the second carrier frequency value, or when the absolute value of the difference between the second low frequency and the expected low frequency value is less than or equal to the second low frequency value, determine that the frequency of the second frequency - shifted square wave does not meet the second requirement.

[0129] Among them, the second carrier frequency value is set according to the expected carrier frequency value and the accuracy of the track circuit, etc. Exemplarily, the second carrier frequency value is 0.15 Hz. The second low frequency value is set according to the expected low frequency value and the accuracy of the track circuit, etc. Exemplarily, the second low frequency value is 0.2 Hz.

[0130] In an exemplary embodiment, under the excitation of a 40 MHz fixed clock signal, the second frequency-shifted square wave is counted, and the counting result is stored in a 16-bit register, that is, the second count value is stored in a 16-bit register. The range of the second count value is 0 to 32768. The highest bit of the 16-bit register represents the update flag bit. When each second count value is acquired, the update flag bit is toggled. The CPU of the track circuit queries the counting result of the 16-bit register at a frequency of 8192 Hz. Since the reading frequency of the CPU (8192 Hz) is much higher than the frequency of the first fixed clock signal (40 MHz), there will be duplicates in the counting results read by the CPU, that is, multiple consecutive identical second count values are read. Therefore, the highest bit of the counting result read by the CPU is the update flag bit. When the update flag bit read by the CPU is different from the currently recorded update flag bit, it indicates that the counting result read by the CPU is valid data, that is, the second count value. Since the carrier frequency encoding is known, when the second count value, that is, the lower 15 bits of the read valid data, is between the lower limit and the upper limit of range 3 of the second table (Table 2), the second count value is considered to be the upper sideband frequency. When the second count value, that is, the lower 15 bits of the read valid data, is between the lower limit and the upper limit of range 4 of the second table (Table 2), the second count value is considered to be the lower sideband frequency. Five buffers H’1 - H’5 are set in the CPU. Each buffer H’ is used to store a second count value. A buffer Q’ is set to record the second count value of the latest upper and lower sideband frequency switching point, that is, the second switching point value. An accumulative counter S’ is set to record the cumulative counting result between two adjacent second switching point values, that is, the second cumulative count value. When a new second count value is captured, the last buffer H’5 is used to record the newly captured second count value, and the positions of buffers H’1, H’2, H’3, and H’4 are used to save the results of buffers H’2, H’3, H’4, and H’5.After each update of the buffer, the following judgments and operations are performed: If the first two (H’1, H’2) second count values are between the upper limit and the lower limit of range 3 (upper side frequency), and the last two (H’4, H’5) second count values are between the upper limit and the lower limit of range 4 (lower side frequency), then the second count value recorded in the third buffer H’3 is the upper and lower side frequency switching point, that is, the second switching point. After locking the upper and lower side frequency switching point, save the upper and lower side frequency switching point to buffer Q’1, and update the cumulative count result of the cumulative counter S’. Then, the carrier frequency and low frequency of the second frequency-shifted square wave can be calculated using Q’1, S’, and H’1~H’5. By comparing the carrier frequency with the expected carrier frequency value and comparing the low frequency with the expected low frequency value, when the carrier frequency error is greater than 0.15 Hz (the second carrier frequency value) and the low frequency error is greater than 0.2 Hz (the second carrier frequency value), it is considered that the frequency of the second frequency-shifted square wave does not meet the second requirement, that is, the back-check fails. At this time, stop the output of the power output signal, lock the upper and lower side frequency switching point, after completing the clearing of the carrier frequency and low frequency, update the count result of buffer H’3 to Q’1, reset the cumulative counter S’ to the sum of buffer H’4 and buffer H’5, and start a new round of real-time back-check calculation.

[0131] S270. After attenuating the voltage of the frequency-shifted signal output by the transformer, sample and count the frequency-shifted signal output by the transformer at a set frequency to obtain a third count value.

[0132] Among them, the frequency-shifted signal output by the transformer is output to the attenuation circuit through the back-check tap, and the attenuation circuit attenuates the voltage of the frequency-shifted signal output by the transformer. Exemplarily, the voltage of the frequency-shifted signal after voltage attenuation is 0 - 3.3V. In an exemplary embodiment, the set frequency is 8192 Hz.

[0133] Specifically, the output terminal of the attenuation circuit is electrically connected to the AD pin of the CPU, and the CPU samples the frequency-shifted signal after voltage attenuation at a set frequency to obtain a third count value.

[0134] S280. Determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the latest obtained preset number of third count values.

[0135] Among them, the preset number is set according to the requirement for the accuracy of the frequency-shifted signal. The larger the preset number, the higher the correctness of the back-check result, and the smaller the preset number, the lower the correctness of the back-check result. In an exemplary embodiment, the preset number is 1280.

[0136] S290. When the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, determine that the frequency-shifted signal is correct.

[0137] In this embodiment, under the excitation of the first fixed clock signal, the first register is used to count the first frequency-shifted square wave to obtain a first count value. Then, based on the first count value and the first table, the first upper side frequency and the first lower side frequency of the first frequency-shifted square wave are determined. Thus, according to the first upper side frequency and the first lower side frequency, it is determined whether the frequency of the first frequency-shifted square wave meets the first requirement. Also, under the excitation of the second fixed clock signal, the second register is used to count the second frequency-shifted square wave to obtain a second count value. Then, based on the second count value and the second table, the second upper side frequency and the second lower side frequency of the second frequency-shifted square wave are determined. Thus, according to the second upper side frequency and the second lower side frequency, it is determined whether the frequency of the second frequency-shifted square wave meets the second requirement. When checking the frequencies of the first frequency-shifted square wave and the second frequency-shifted square wave, the time required is short, and the storage space required is small, which can save signal storage space and improve the real-time performance and robustness of the check result. Furthermore, it is beneficial to further improve the safety performance of the track circuit.

[0138] Embodiment III

[0139] Figure 3 The flowchart of a method for checking the frequency of a frequency-shifted signal of a track circuit provided in Embodiment III of the present invention. On the basis of the above embodiment, this embodiment further adds steps for determining whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement. As Figure 3 shown, the method specifically includes:

[0140] S310. Obtain the first count value of the first frequency-shifted square wave, and determine whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value.

[0141] S320. Obtain the second count value of the second frequency-shifted square wave, and determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second count value.

[0142] Among them, the first frequency-shifted square wave forms a first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave forms a second frequency-shifted square wave through a zero-crossing detection circuit.

[0143] S330. Form an N×N matrix M1 with every N 2 third count values among a preset number of third count values.

[0144] Among them, N can be 8, and the preset number is a multiple of N 2 . Every N2 third count values forming an N×N matrix M1 can form an N×N matrix M1 in the principle of row-first order.

[0145] S340. Generate an N×2 signal basis matrix B with a single-frequency f1.

[0146] The first column elements of the signal basis matrix B are 100×sin(2×π×i / 8192×f1+π / 6), and the second column elements of the signal basis matrix B are 100×cos(2×π×i / 8192×f1+π / 6); where i takes integers in the range of [0,7] in sequence, the range of the single-frequency f1 is: fc - 25Hz ≤ f1 ≤ fc + 25Hz, the accuracy of f1 is 0.1Hz, and fc is the expected value of the carrier frequency.

[0147] S350. Determine the signal basis projection matrix T1 according to the matrix M1 and the signal basis matrix B.

[0148] Optionally, determining the signal basis projection matrix T1 according to the matrix M1 and the signal basis matrix B includes: performing singular value decomposition on the autocorrelation matrix M3 of the matrix M1 to obtain the U matrix; taking the last 5-row submatrix of the transpose matrix of the U matrix as the matrix U3; multiplying the matrix U3 and the signal basis matrix B to obtain the signal basis projection matrix T1.

[0149] S360. Determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the signal basis projection matrix T1.

[0150] Optionally, determining whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the signal basis projection matrix T1 includes: performing a cumulative sum of the squares of the elements in the signal basis projection matrix T1 to obtain the signal basis projection error D; determining the projection error D1 at the upper sideband timing and the projection error D2 at the lower sideband timing according to the signal basis projection error D; determining whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the projection error D1 at the upper sideband timing and the projection error D2 at the lower sideband timing.

[0151] In a specific embodiment, the voltage of the transformer's back-check tap is attenuated to 0 - 3.3V by an attenuation circuit and output to the AD pin of the CPU. The CPU counts the signal at a frequency of 8192Hz. The recording length of the counting buffer is 1280, that is, the buffer is used to record a preset number of the latest third count values. Among them, every 64 third count values form an 8×8 matrix M1 according to the principle of row-major order. After transposing matrix M1, matrix M2 is formed. Matrix M2 and matrix M1 are multiplied to obtain the autocorrelation matrix M3. The autocorrelation matrix M3 is subjected to singular value decomposition to obtain the U matrix, the S matrix, and the V matrix. A signal basis matrix B of 8×2 is generated using the single-frequency f1. The first column elements of B are 100×sin(2×π×i / 8192×f1 + π / 6), and the second column elements of B are 100×cos(2×π×i / 8192×f1 + π / 6), where i takes integers between [0, 7] in sequence. The range of the single-frequency f1 is: fc - 25Hz ≤ f1 ≤ fc + 25Hz, the accuracy of f1 is 0.1Hz, and fc is the expected value of the carrier frequency. Therefore, there are 500 such signal basis matrices B. After transposing the U matrix, matrix U2 is formed. The size of the sub-matrix U3 of the last 5 rows of U2 is 5×8. Matrix U3 and the signal basis matrix B are multiplied to obtain the signal basis projection matrix T1. The sum of the squares of 10 elements in T1 is accumulated to obtain the signal basis projection error D. Since there are 500 signal basis matrices B, 500 projection errors D are also obtained. When the projection error D1 of the upper center carrier frequency signal basis is at the minimum value and the absolute value of D1 is less than the set value Y1, the time sub-gap corresponding to the upper center carrier frequency signal basis is considered the upper sideband timing. When the projection error D2 of the lower center carrier frequency signal basis is at the minimum value and the absolute value of D2 is less than the set value Y2, the time sub-gap of the signal basis is considered the lower sideband timing. After adopting the above method, the above buffer can be calculated 20 times per round (i.e., 1280 / 64). Therefore, the minimum effective error D3 of the upper sideband (select the minimum error among the upper sideband timings of 20 calculations) and the minimum effective error D4 of the lower sideband (select the minimum error among the lower sideband timings of 20 calculations) can be obtained. When both D3 and D4 are less than the preset value Y3, the back-check is considered valid, otherwise the back-check is considered failed. Among them, the set values Y1, Y2, and Y3 are determined according to the accuracy requirements for the frequency shift signal of the track circuit. The set values Y1, Y2, and Y3 can be the same or different.

[0152] S370. When the frequency of the first frequency shift square wave meets the first requirement, the frequency of the second frequency shift square wave meets the second requirement, and the frequency of the frequency shift signal output by the transformer meets the third requirement, it is determined that the frequency shift signal is correct.

[0153] In this embodiment, by taking a preset number of third count values every N 2A third count value forms an N×N matrix M1 and a signal basis matrix B of N×2 is generated with a single-frequency f1, and operations are performed on the matrix M1 and the signal basis matrix B to obtain a signal basis projection matrix T1, and further a projection error D1 at the upper sideband timing and a projection error D2 at the lower sideband timing are obtained. Thus, according to the projection error D1 at the upper sideband timing and the projection error D2 at the lower sideband timing, it is determined whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement, so that when the frequency of the frequency-shifted signal output by the transformer is back-checked, the required time is short and the required storage space is small, the signal storage space can be saved, and the real-time performance and robustness of the back-check result are improved, which is further beneficial to improving the safety performance of the track circuit.

[0154] Embodiment 4

[0155] This embodiment provides a frequency-shifted signal back-check device for a track circuit. The device can be implemented in the form of hardware and / or software and can be integrated into a processor. Figure 4 It is a schematic structural diagram of the frequency-shifted signal back-check device for a track circuit provided in Embodiment 4 of the present invention, as Figure 4 shown. The device includes:

[0156] A first acquisition and judgment module 410 is configured to acquire a first count value of a first frequency-shifted square wave and determine whether the frequency of the first frequency-shifted square wave meets the first requirement according to the first count value.

[0157] A second acquisition and judgment module 420 is configured to acquire a second count value of a second frequency-shifted square wave and determine whether the frequency of the second frequency-shifted square wave meets the second requirement according to the second count value.

[0158] Wherein, the first frequency-shifted square wave forms a first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave forms a second frequency-shifted square wave through a zero-crossing detection circuit;

[0159] A third acquisition and judgment module 430 is configured to acquire a third count value of the frequency-shifted signal output by the transformer and determine whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement according to the third count value;

[0160] A determination module 440 is configured to determine that the frequency-shifted signal is correct when the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

[0161] The frequency-shifted signal back-check device for a track circuit provided in the embodiment of the present invention can execute the frequency-shifted signal back-check device method for a track circuit provided in any embodiment of the present invention, has corresponding functional modules and beneficial effects for executing the method, and the same parts can be referred to the above description.

[0162] Embodiment 5

[0163] Based on the same inventive concept, this embodiment further provides a track circuit, which includes at least one processor and a memory communicatively connected to the at least one processor. Among them, the memory stores a computer program executable by the at least one processor. When the computer program is executed by the at least one processor, the at least one processor is enabled to execute the frequency shift signal feedback method of the track circuit provided in any embodiment of the present invention.

[0164] Since when the computer program of the track circuit provided in this embodiment is executed by the at least one processor, the at least one processor is enabled to execute the frequency shift signal feedback method of the track circuit provided in any embodiment of the present invention. Therefore, the track circuit provided in this embodiment has the corresponding functional modules and beneficial effects of the execution method, and the same parts can be referred to the above description.

[0165] Embodiment Six

[0166] Based on the same inventive concept, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer instructions for implementing the method provided in any of the above embodiments when executed by a processor.

[0167] In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0168] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A frequency shift signal check method for a track circuit, characterized in that: include: Obtaining a first count value of a first frequency-shifted square wave, and determining whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first count value; Obtaining a second count value of the second frequency-shifted square wave, and determining whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second count value; the first frequency-shifted square wave is converted into a first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave is converted into a second frequency-shifted square wave through a zero-crossing detection circuit; Obtaining a third count value of the frequency-shifted signal output by the transformer, and determining whether the frequency of the frequency-shifted signal output by the transformer meets a third requirement according to the third count value; When the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement, it is determined that the frequency-shifted signal is correct.

2. The frequency shift signal check method for track circuit according to claim 1, characterized in that: When the frequency of the first frequency-shifted square wave does not meet the first requirement, the frequency of the second frequency-shifted square wave does not meet the second requirement, or the frequency of the frequency-shifted signal output by the transformer does not meet the third requirement, it is determined that the frequency-shifted signal is wrong.

3. The frequency shift signal check method for track circuit according to claim 1, characterized in that: Obtaining a first count value of a first frequency-shifted square wave, and determining whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first count value, includes: Under the stimulation of a first fixed clock signal, using a first register to count the first frequency-shifted square wave to obtain the first count value; Determine a first upper sideband and a first lower sideband of the first frequency-shifted square wave according to the first count value and the first table; It is determined whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first upper sideband and the first lower sideband.

4. The frequency shift signal check method for track circuit according to claim 3, characterized in that: Determining whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first upper sideband and the first lower sideband includes: Determine first switching point values ​​of the upper and lower sidebands according to the first upper sideband, the first lower sideband and five first count values ​​collected continuously; Determine a cumulative counting result between two adjacent first switching point values ​​according to the two adjacent first switching point values ​​and the first counting value between the two first switching point values, and record the result as a first cumulative counting value; Determine a first carrier frequency and a first low frequency of the first frequency-shifted square wave according to five continuously collected first count values, the first switching point value, and the first cumulative count value; It is determined whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first carrier frequency and the first low frequency.

5. The frequency shift signal check method for track circuit according to claim 4, characterized in that: Determining whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first carrier frequency and the first low frequency includes: When the absolute value of the difference between the first carrier frequency and the expected carrier frequency value is less than or equal to the first carrier frequency value, and the absolute value of the difference between the first low frequency and the expected low frequency value is less than or equal to the first low frequency value, it is determined that the frequency of the first frequency-shifted square wave meets the first requirement.

6. The frequency shift signal check method for track circuit according to claim 1, characterized in that: Acquiring a second count value of the second frequency-shifted square wave, and determining whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second count value, includes: Under the stimulation of the second fixed clock signal, the second frequency-shifted square wave is counted using the second register to obtain the second count value; Determine a second upper sideband and a second lower sideband of the second frequency-shifted square wave according to the second count value and the second table; It is determined whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second upper sideband and the second lower sideband.

7. The method for checking the frequency shift signal of a track circuit according to claim 6, characterized in that: Determining whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second upper sideband and the second lower sideband includes: Determine a second switching point value of the second upper sideband and the second lower sideband according to the second upper sideband, the second lower sideband and five second count values ​​collected continuously; Determine a cumulative counting result between two adjacent second switching point values ​​according to the two adjacent second switching point values ​​and the second counting value between the two second switching point values, and record it as a second cumulative counting value; Determine a second carrier frequency and a second low frequency of the second frequency-shifted square wave according to five continuously collected second count values, the second switching point value, and the second accumulated count value; It is determined whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second carrier frequency and the second low frequency.

8. The method for checking the frequency shift signal of a track circuit according to claim 7, characterized in that: Determining whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second carrier frequency and the second low frequency includes: When the absolute value of the difference between the second carrier frequency and the expected carrier frequency value is less than or equal to the second carrier frequency value, and the absolute value of the difference between the second low frequency and the expected low frequency value is less than or equal to the second low frequency value, it is determined that the frequency of the second frequency-shifted square wave meets the second requirement.

9. The frequency shift signal check method for track circuit according to claim 1, characterized in that: Obtaining a third count value of the frequency-shifted signal output by the transformer, and determining whether the frequency of the frequency-shifted signal output by the transformer meets a third requirement according to the third count value, includes: After performing voltage attenuation on the frequency-shifted signal output by the transformer, sampling and counting the frequency-shifted signal output by the transformer at a set frequency to obtain the third count value; According to the third count values ​​of the preset number acquired most recently, it is determined whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

10. The frequency shift signal check method for track circuit according to claim 9, characterized in that: Determining whether the frequency of the frequency-shifted signal output by the transformer meets a third requirement according to the third count value of the preset number obtained most recently includes: The third count value of the preset number is divided into N 2 The third count values ​​form an N*N matrix M1; Generate an N*2 signal basis matrix B with single frequency f1; the first column element of the signal basis matrix B is 100*sin(2*π*i / 8192*f1+π / 6), and the second column element of the signal basis matrix B is 100*cos(2*π*i / 8192*f1+π / 6); wherein i is an integer between [0,7], the range of the single frequency f1 is: fc-25Hz≤f1≤fc+25Hz, the accuracy of f1 is 0.1Hz, and fc is the expected value of the carrier frequency; Determine a signal basis projection matrix T1 according to the matrix M1 and the signal basis matrix B; According to the signal-based projection matrix T1, it is determined whether the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

11. The frequency shift signal check method for track circuit according to claim 10, characterized in that: Determining a signal basis projection matrix T1 according to the matrix M1 and the signal basis matrix B includes: Performing singular value decomposition on the autocorrelation matrix M3 of the matrix M1 to obtain a U matrix; The last 5 rows of the submatrix of the transposed matrix of the U matrix are used as matrix U3; The matrix U3 is multiplied by the signal basis matrix B to obtain the signal basis projection matrix T1.

12. A frequency shift signal check device for a track circuit, characterized in that: include: A first acquisition and judgment module, used for acquiring a first count value of a first frequency-shifted square wave, and determining whether the frequency of the first frequency-shifted square wave meets a first requirement according to the first count value; A second acquisition and judgment module is used to acquire a second count value of a second frequency-shifted square wave, and determine whether the frequency of the second frequency-shifted square wave meets a second requirement according to the second count value; the first frequency-shifted square wave is converted into a first frequency-shifted sine wave through a digital-to-analog converter, and the first frequency-shifted sine wave is converted into a second frequency-shifted square wave through a zero-crossing detection circuit; A third acquisition and judgment module, used to acquire a third count value of the frequency-shifted signal output by the transformer, and determine whether the frequency of the frequency-shifted signal output by the transformer meets a third requirement according to the third count value; The determination module is used to determine that the frequency-shifted signal is correct when the frequency of the first frequency-shifted square wave meets the first requirement, the frequency of the second frequency-shifted square wave meets the second requirement, and the frequency of the frequency-shifted signal output by the transformer meets the third requirement.

13. A track circuit, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 11.

14. A computer storage medium, characterized in that: The computer storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 11 when executed.

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