Channel degradation monitoring circuit, chip degradation monitoring circuit and chip

Abstract

The invention relates to the technical field of integrated circuits and chips, and provides a channel degradation monitoring circuit, a chip degradation monitoring circuit and a chip. The channel degradation monitoring circuit comprises a degradation phase inverter, the degradation phase inverter comprises a first high-voltage transistor, a first resistor, a second resistor and a third resistor, and a grid electrode of the first high-voltage transistor is connected with an input end of the degradation phase inverter through the first resistor and is grounded through the second resistor. The drain electrode of the first high-voltage transistor is connected with the power supply end of the chip through the third resistor, and a node between the drain electrode of the first high-voltage transistor and the third resistor serves as the output end of the degeneration phase inverter. According to the invention, corresponding monitoring circuits are respectively designed for channel degradation, gate oxide degradation and substrate degradation of the high-voltage device and are integrated, so that degradation monitoring and early warning of the high-voltage device and the circuits can be supported, and the high-voltage device and the circuits can be embedded into a power supply and an isolation driving chip; the defect that an existing monitoring circuit is only suitable for monitoring a low-voltage SOC chip and cannot monitor a high-voltage circuit and a chip is overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits and chips, and in particular to a channel degradation monitoring circuit, a chip degradation monitoring circuit and a chip. Background Art

[0002] Industrial chips used in the fields of power, rail transit, and automobiles are usually mounted outdoors with terminals, and are very susceptible to strong transient electromagnetic interference generated by the operation of power devices such as IGBTs, as well as environmental factors such as high temperature and high humidity. Industrial chips need to operate stably 24 hours a day, 7 days a week, in high / low temperature, high humidity, and strong electromagnetic environments, with a lifespan of more than 15 years, which poses a huge challenge to the reliability of chip pins that are susceptible to environmental interference.

[0003] With the rapid development of ultra-large-scale integrated circuit manufacturing technology towards deep submicron, while the channel length, junction depth and gate oxide thickness of the device are proportionally reduced and the substrate concentration is increased, the power supply voltage is not proportionally reduced, resulting in a significant increase in the lateral and longitudinal electric fields in the channel region. Hot carriers obtain sufficient energy under high electric fields and cross the interface barrier (3.2eV for electron injection and 4.5eV for hole injection) to be injected into the oxide layer, generating oxide layer trap charges or interface trap charges, causing the oxide layer charge to increase or fluctuate unstably. When the energy of hot electrons is higher than the Si-SiO2 interface barrier, it is possible to cross the interface barrier and be injected into the gate oxide layer. Some carriers eventually reach the gate electrode and form part of the gate current. In the process of hot carriers passing through the gate oxide layer to reach the gate electrode, the hot carriers will use their energy to open Si-H, Si-OH bonds and other bonds at the interface, generate acceptor-type interface states at the Si-SiO2 interface, or be captured by traps in the gate oxide layer to form trapped charges. These generated interface states and trapped charges will cause changes in the local electric field of the device, thereby causing the degradation of device characteristics, causing the circuit performance to gradually degrade over time, and ultimately causing the device and the circuit to fail. Device degradation includes channel degradation, gate oxide degradation, and substrate degradation.

[0004] Power chips and isolation driver chips usually use high-voltage MOS devices and support power supplies of 12V (typically 40V) and above. Traditional degradation monitoring circuits only support low-voltage devices of 5V and are only for SOC chips. They cannot support the monitoring of high-voltage devices and circuit systems above 12V, and are not suitable for power chips and isolation driver chips containing chips. Summary of the invention

[0005] In order to solve the above technical defects, the present invention provides a channel degradation monitoring circuit and a chip degradation monitoring circuit.

[0006] The channel degradation monitoring circuit provided by the embodiment of the present invention includes: a degraded ring oscillator;

[0007] The degenerate ring oscillator comprises an odd number of degenerate inverters connected in series;

[0008] The degenerate inverter comprises: a first high-voltage transistor, a first resistor, a second resistor and a third resistor, wherein the gate of the first high-voltage transistor is connected to the input terminal of the degenerate inverter through the first resistor and is grounded through the second resistor, the source of the first high-voltage transistor is grounded, the drain of the first high-voltage transistor is connected to the power supply terminal of the chip through the third resistor, and the node between the drain of the first high-voltage transistor and the third resistor serves as the output terminal of the degenerate inverter;

[0009] The channel degradation monitoring circuit monitors the channel degradation of the first high-voltage transistor of the degraded inverter by detecting the frequency attenuation of the degraded ring oscillator over time.

[0010] In an embodiment of the present invention, the channel degradation monitoring circuit further comprises: a non-degenerate ring oscillator;

[0011] The non-degenerate ring oscillator comprises an odd number of non-degenerate inverters connected in series;

[0012] The non-degenerate inverter includes: a second high-voltage transistor, a third high-voltage transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;

[0013] The gate of the second high-voltage transistor is connected to the input terminal of the non-degenerate inverter through the eighth resistor and is grounded through the fourth resistor; the source of the second high-voltage transistor is grounded, and the drain of the second high-voltage transistor is connected to the source of the third high-voltage transistor;

[0014] The gate of the third high-voltage transistor is connected to the power supply terminal of the chip through the fifth resistor and is grounded through the sixth resistor; the drain of the third high-voltage transistor is connected to the power supply terminal of the chip through the seventh resistor, and the node between the drain of the third high-voltage transistor and the seventh resistor serves as the output terminal of the non-degenerate inverter.

[0015] In the embodiment of the present invention, the first high voltage transistor, the second high voltage transistor and the third high voltage transistor are one of LDMOS, VDMOS and BJT, and the source-drain voltage of the first high voltage transistor, the second high voltage transistor and the third high voltage transistor is 12V to 750V.

[0016] In an embodiment of the present invention, the channel degradation monitoring circuit further includes: a non-degenerate level conversion circuit, a degenerate level conversion circuit and a frequency attenuation detection circuit;

[0017] The non-degenerate ring oscillator is connected to the frequency attenuation detection circuit via a non-degenerate level conversion circuit, and the degenerate ring oscillator is connected to the frequency attenuation detection circuit via a degenerate level conversion circuit;

[0018] The non-degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the non-degenerate ring oscillator into a low-voltage oscillation signal;

[0019] The degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the degenerate ring oscillator into a low-voltage oscillation signal;

[0020] The frequency attenuation detection circuit is used to detect the frequency attenuation of the degraded ring oscillator over time, and count the number of cycles of the non-degraded ring oscillator in the corresponding cycle of the degraded ring oscillator, so as to monitor and warn the channel degradation of the first high-voltage transistor of the degraded inverter.

[0021] In the embodiment of the present invention, the degenerate level conversion circuit comprises: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube;

[0022] The gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and connected to the output end of the degenerate ring oscillator, and the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube;

[0023] The gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, and is connected to the common end where the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube, and the common end where the drain of the sixth MOS tube is connected to the drain of the seventh MOS tube serves as the output end of the degenerate level conversion circuit;

[0024] The source of the fourth MOS tube and the source of the sixth MOS tube are connected to the low voltage power supply, and the source of the fifth MOS tube and the source of the seventh MOS tube are grounded.

[0025] In the embodiment of the present invention, the non-degenerate level conversion circuit includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube and a thirteenth MOS tube;

[0026] The common end of the gate of the eighth MOS tube, the gate of the ninth MOS tube and the gate of the tenth MOS tube is connected to the output end of the non-degenerate ring oscillator, the source of the eighth MOS tube is connected to the low-voltage power supply, the drain of the eighth MOS tube is connected to the drain of the ninth MOS tube, and the source of the ninth MOS tube is connected to the drain of the tenth MOS tube;

[0027] The common end of the gate of the eleventh MOS tube connected to the gate of the thirteenth MOS tube is connected to the common end of the drain of the eighth MOS tube connected to the drain of the ninth MOS tube, the source of the eleventh MOS tube and the gate of the twelfth MOS tube are connected to the low-voltage power supply, and the common end of the drain of the eleventh MOS tube connected to the drain of the twelfth MOS tube serves as the output end of the non-degenerate level conversion circuit;

[0028] The source of the twelfth MOS tube is connected to the drain of the thirteenth MOS tube, and the source of the tenth MOS tube and the source of the thirteenth MOS tube are grounded.

[0029] In the embodiment of the present invention, the fourth MOS tube, the sixth MOS tube, the eighth MOS tube and the eleventh MOS tube are enhanced PMOS tubes; the fifth MOS tube, the seventh MOS tube, the ninth MOS tube, the tenth MOS tube, the twelfth MOS tube and the thirteenth MOS tube are enhanced NMOS tubes.

[0030] In an embodiment of the present invention, the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator and a latch;

[0031] The high-voltage oscillation signal output by the non-degenerate ring oscillator is converted into a low-voltage oscillation signal by a non-degenerate level conversion circuit and then output to the counter as a reference clock of the counter;

[0032] The high-voltage oscillation signal output by the degenerate ring oscillator is converted into a low-voltage oscillation signal by a degenerate level conversion circuit, and then output to the frequency divider for frequency division to obtain a counting signal of the counter and a latch signal of the latch;

[0033] The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator;

[0034] The discriminator determines whether the counting result is greater than a threshold value to obtain a discrimination result;

[0035] The latch latches the discrimination result according to the latch signal and then outputs a warning signal.

[0036] The chip degradation monitoring circuit provided by the embodiment of the present invention comprises: the above-mentioned channel degradation monitoring circuit, gate oxide degradation monitoring circuit and data serial output circuit;

[0037] The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit;

[0038] The data serial output circuit outputs the multi-channel monitoring signals in series.

[0039] In an embodiment of the present invention, the gate oxide degradation monitoring circuit includes a first branch and a second branch, the first branch and the second branch are connected through a current mirror; the first branch includes a MOS capacitor group, and the second branch includes an inverter; the MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor; the common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end of the source and drain of each high-voltage MOS tube is short-circuited to serve as the second end of the MOS capacitor group; the second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, and the stress voltage is greater than the working voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube;

[0040] The current mirror is used to copy the current mirror image of the first branch to the input end of the inverter of the second branch, and the level signal output by the inverter is used as a gate oxide degradation monitoring signal.

[0041] In an embodiment of the present invention, the current mirror includes: a first resistor, a second resistor, a first MOS tube and a second MOS tube; the gate of the first MOS tube is connected to the gate of the second MOS tube; the source of the first MOS tube is connected to the stress voltage through the first resistor, and the drain of the first MOS tube is connected to the first end of the MOS capacitor group; the source of the second MOS tube is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS tube is connected to the input end of the inverter.

[0042] The common end at which the gate of the first MOS tube is connected to the gate of the second MOS tube is connected to the first end of the MOS capacitor group.

[0043] In the embodiment of the present invention, the second branch further includes a third resistor, a first end of the third resistor is connected to the input end of the inverter and to the drain of the second MOS tube, and a second end of the third resistor is grounded.

[0044] The second branch further includes a Zener diode, a cathode of the Zener diode is connected to the input end of the inverter and to the drain of the second MOS tube, and an anode of the Zener diode is grounded.

[0045] In the embodiment of the present invention, the gate oxide of the high-voltage MOS tube in the MOS capacitor group is degraded under the stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, there is no mirrored current in the second branch, and the third resistor pulls down the input voltage of the inverter, and the inverter outputs a high level.

[0046] The high-voltage MOS tube in the MOS capacitor group undergoes gate oxide degradation under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, a large current is generated in the first branch, a mirrored large current is generated in the second branch, and the mirrored large current generates a voltage through the third resistor. The input end of the inverter is at a high level, and the inverter outputs a low level.

[0047] In an embodiment of the present invention, the chip degradation monitoring circuit further comprises: a substrate degradation monitoring circuit for monitoring substrate degradation of the high voltage power device;

[0048] The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit;

[0049] The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit and the substrate degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit.

[0050] In an embodiment of the invention, the substrate degradation monitoring circuit comprises a plurality of monitoring branches connected in parallel, each monitoring branch comprises: a high-voltage MOS device, a comparator and a selector, the selector comprises a first selector, a second selector and a third selector;

[0051] The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator;

[0052] The gate of the high-voltage MOS device is connected to a test voltage through a second selector, and the test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device;

[0053] The source of the high-voltage MOS device is connected to a reverse test voltage through a third selector;

[0054] A reference voltage is input to the second input terminal of the comparator of each monitoring branch, and the reference voltages input to the second input terminals of the comparators of the various monitoring branches are different.

[0055] In an embodiment of the invention, the substrate degradation monitoring circuit further comprises: a channel degradation compensation circuit, a gate oxide degradation compensation circuit and a substrate degradation compensation circuit;

[0056] The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit.

[0057] The present invention also provides a power chip, which includes the above-mentioned chip degradation monitoring circuit.

[0058] The present invention also provides an isolation driving chip, which includes the above-mentioned chip degradation monitoring circuit.

[0059] The present invention designs a corresponding channel degradation monitoring circuit for the channel degradation of high-voltage devices, and realizes the channel degradation monitoring and early warning of high-voltage devices. The present invention also designs and integrates corresponding monitoring circuits for the channel degradation, gate oxide degradation and substrate degradation of high-voltage devices in the chip, which can support the degradation monitoring and early warning of high-voltage devices and circuits in the chip, and overcomes the defects that the existing monitoring circuit is only applicable to monitoring low-voltage SOC chips and cannot monitor high-voltage circuits and chips; the degradation monitoring circuit of the present invention can be embedded in the power supply and isolation driver chip to form a power supply and isolation driver chip with high-voltage device fault monitoring function.

[0060] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0062] Figure 1 is a schematic structural diagram of a channel degradation monitoring circuit provided by an embodiment of the present invention;

[0063] Figure 2 is a circuit diagram of a degenerate inverter provided by an embodiment of the present invention;

[0064] Figure 3 is a circuit diagram of a non-degenerate inverter provided by an embodiment of the present invention;

[0065] Figure 4 is a schematic diagram of a degenerate level conversion circuit provided by an embodiment of the present invention;

[0066] Figure 5 is a schematic diagram of a non-degenerate level conversion circuit provided by an embodiment of the present invention;

[0067] Figure 6 is a schematic diagram of a frequency attenuation detection circuit provided by an embodiment of the present invention;

[0068] Figure 7 is a schematic structural diagram of a chip degradation monitoring circuit provided by an embodiment of the present invention;

[0069] Figure 8 is a schematic diagram of a gate oxide degradation monitoring circuit provided by an embodiment of the present invention;

[0070] Fig. 9 is a schematic structural diagram of a chip degradation monitoring circuit provided by another embodiment of the present invention;

[0071] Fig.10is a schematic diagram of a substrate degradation monitoring circuit provided by an embodiment of the present invention;

[0072] Fig.11 is a schematic diagram of a data serial output circuit provided by an embodiment of the present invention;

[0073] Fig.12 is a circuit diagram of a serial shift register in a data serial output circuit provided by an embodiment of the present invention;

[0074] Fig.13 is a circuit diagram of a frequency divider in a data serial output circuit provided by an embodiment of the present invention;

[0075] Fig.14 is a schematic diagram of a data serial output circuit embedded in a ring oscillator provided in an embodiment of the present invention;

[0076] Fig.15 is a schematic structural diagram of a chip degradation monitoring circuit with redundancy compensation provided by an embodiment of the present invention;

[0077] Fig.16 is a schematic diagram of a channel degradation compensation circuit provided by an embodiment of the present invention;

[0078] Fig.17 is a schematic diagram of a gate oxide degradation compensation circuit provided by an embodiment of the present invention;

[0079] Fig.18 It is a schematic diagram of a substrate degradation compensation circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0080] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0081] In the description of the present invention, the terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0082] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected" and "connection" should be understood in a broad sense, for example, it can be an electrical connection or mutual communication, it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0083] In the process of implementing the present invention, the inventors found that the traditional device degradation monitoring circuit is only for SOC chips, and is not suitable for power chips and isolation driver chips. In addition, the traditional device degradation monitoring solution is only for low-voltage process defect monitoring, and only supports 5V low-voltage devices, and cannot support the monitoring of 12V~750V high-voltage devices and circuit systems.

[0084] In view of the above problems, the embodiments of the present invention provide a high-voltage device degradation monitoring circuit suitable for power chips and isolation driver chips, which integrates a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit and a substrate degradation monitoring circuit. The channel degradation monitoring circuit is used to monitor the channel degradation of the high-voltage device in the circuit under test; the gate oxide degradation monitoring circuit is used to monitor the gate oxide degradation of the high-voltage device in the circuit under test; and the substrate degradation monitoring circuit is used to monitor the substrate degradation of the high-voltage device in the circuit under test. The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit and the substrate degradation monitoring circuit output multiple monitoring signals in parallel, and the multiple monitoring signals are output in series through the data serial output circuit. The present invention designs corresponding monitoring circuits for the channel degradation, gate oxide degradation and substrate degradation of high-voltage devices and integrates them, which can support the degradation monitoring and failure warning of high-voltage devices and circuits; the degradation monitoring circuit of the present invention can be embedded in the power supply and isolation driver chips to form a power supply and isolation driver chip with high-voltage MOS device fault monitoring function.

[0085] Figure 1 is a schematic diagram of the structure of a channel degradation monitoring circuit provided by an embodiment of the present invention. Figure 1As shown, the channel degradation monitoring circuit includes: a non-degenerate ring oscillator, a degenerate ring oscillator, a non-degenerate level conversion circuit, a degenerate level conversion circuit and a frequency attenuation detection circuit. The degenerate ring oscillator includes an odd number of degenerate inverters connected in series, and the non-degenerate ring oscillator includes an odd number of non-degenerate inverters connected in series. Both the degenerate inverter and the non-degenerate inverter have high-voltage transistors, and the high-voltage transistors in the degenerate inverter are subjected to voltage stress to cause channel degradation, so that the frequency of the degenerate ring oscillator decays over time. The frequency of the degenerate ring oscillator degenerates (decays) over time, and the frequency of the non-degenerate ring oscillator has only very slight degradation over time, and the frequency degradation of the non-degenerate ring oscillator can be ignored relative to the degenerate ring oscillator. The channel degradation monitoring and early warning circuit monitors and warns the channel degradation of the high-voltage device in the degenerate inverter by detecting the frequency attenuation of the degenerate ring oscillator over time.

[0086] The non-degenerate ring oscillator is connected to the frequency attenuation detection circuit through the non-degenerate level conversion circuit, and the degenerate ring oscillator is connected to the frequency attenuation detection circuit through the degenerate level conversion circuit; the non-degenerate level conversion circuit is used to convert the high-voltage oscillation signal CLK_REF_40V output by the non-degenerate ring oscillator into a low-voltage oscillation signal CLK_REF; the degenerate level conversion circuit is used to convert the high-voltage oscillation signal CLK_DEG_40V output by the degenerate ring oscillator into a low-voltage oscillation signal CLK_DEG; the frequency attenuation detection circuit is used to detect the frequency attenuation of the oscillation signal CLK_REF converted by the degenerate level conversion circuit relative to the oscillation signal CLK_REF converted by the non-degenerate level conversion circuit.

[0087] In this embodiment, the degenerate ring oscillator includes an odd number of degenerate inverters connected in series, and the circuit structure of the degenerate inverter is as follows: Figure 2As shown. The degenerate inverter includes: a first high-voltage transistor M1, a first resistor R1, a second resistor R2 and a third resistor R3. The gate of the first high-voltage transistor M1 is connected to the input terminal IN of the degenerate inverter (corresponding to the output terminal of the previous degenerate inverter) through the first resistor R1, and is grounded to GND through the second resistor R2. The source of the first high-voltage transistor M1 is grounded to GND. The drain of the first high-voltage transistor M1 is connected to the power supply terminal VDD of the chip through the third resistor R3. The node between the drain of the first high-voltage transistor M1 and the third resistor R3 serves as the output terminal OUT of the degenerate inverter. The first high-voltage transistor M1 is one of the high-voltage devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), BJT (Bipolar Junction Transistor), etc., and its source-drain voltage (maximum withstand voltage) ranges from 12V to 750V. The first high-voltage transistor M1 undergoes channel degradation when a stress voltage is applied, and the frequency of the degenerate ring oscillator composed of degenerate inverters decays over time. The source-drain voltage of high-voltage devices such as LDMOS in a common power chip is 40V, supporting a 40V power supply.

[0088] In a specific embodiment, an inverter capable of supporting a 40V power supply is designed as an example. Different from the existing inverter using NMOS+PMOS, this embodiment needs to support a 40V power supply input, so the gate voltage of the LDMOS capable of withstanding a 40V withstand voltage is obtained by dividing the voltage through rphripoly type resistors R1 and R2 capable of withstanding high voltage, thereby realizing the reverse function. Since when the IN signal is at a low level, the OUT signal outputs a high voltage, the 40V device M1 is an LDMOS, and its drain-source voltage VDS reaches a high voltage of 40V, forming a high-voltage channel degeneration inverter.

[0089] In this embodiment, the non-degenerate ring oscillator includes an odd number of non-degenerate inverters connected in series. The circuit structure of the non-degenerate inverter is as follows: Figure 3As shown. The non-degenerate inverter includes: a second high-voltage transistor M2, a third high-voltage transistor M3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8. The gate of the second high-voltage transistor M2 is connected to the input terminal IN of the non-degenerate inverter (corresponding to the output terminal of the previous non-degenerate inverter) through the eighth resistor R8, and is grounded to GND through the fourth resistor R4. The source of the second high-voltage transistor M2 is grounded to GND, the drain of the second high-voltage transistor M2 is connected to the source of the third high-voltage transistor M3, and the gate of the third high-voltage transistor M3 is connected to the power supply terminal VDD of the chip through the fifth resistor R5, and is grounded to GND through the sixth resistor R6. The drain of the third high-voltage transistor M3 is connected to the power supply terminal VDD of the chip through the seventh resistor R7, and the node between the drain of the third high-voltage transistor M3 and the seventh resistor R7 serves as the output terminal OUT of the non-degenerate inverter. The second high-voltage transistor M2 and the third high-voltage transistor M3 are high-voltage devices such as LDMOS, VDMOS, and BJT, and their source-drain voltage (maximum withstand voltage) ranges from 12 V to 750 V. No stress voltage is applied to the second high-voltage transistor M2 and the third high-voltage transistor M3, and their channel degradation is very slow and can be ignored, and the frequency attenuation of the degenerate ring oscillator composed of non-degenerate inverters can also be ignored.

[0090] In a specific embodiment, an inverter capable of supporting a 40V power supply is designed as an example. Different from the existing inverter using NMOS+PMOS, this embodiment needs to support a 40V power supply input, so the gate voltage of the LDMOS capable of withstanding a 40V withstand voltage is obtained by dividing the voltage through rphripoly type resistors R3, R4, R5, and R6 that can withstand high voltage, thereby realizing the reverse function. When the IN signal is at a low level, the OUT signal outputs a high voltage. Different from the degenerate inverter circuit, the non-degenerate inverter provides a biasing effect by adding a 40V LDMOS tube M3. Since the Gate voltage of M3 is a fixed value, the source terminal voltage of M3 is a fixed value, which is much less than 40V, so that the drain-source voltage (source-drain voltage) VDS of the 40V LDMOS tube M2 cannot reach the 40V high voltage, and it only withstands low voltage, so it is a high-voltage channel non-degenerate inverter.

[0091] After obtaining the above two inverters, a ring oscillator can be obtained by designing an odd number of inverters connected in series. By designing a corresponding ring oscillator and embedding it into the system under test, the purpose of testing the degradation of the system under test can be achieved by testing the frequency and degradation of the ring oscillator in real time online without affecting the operation of the circuit under test. The present invention is designed based on this principle, using a ring oscillator as a test circuit, and measuring its degradation degree by monitoring the attenuation of its frequency.

[0092] Since the internal logic circuits of the chip are relatively complex, if they are all designed in the 40V voltage range, it will waste power consumption and area, so a "high voltage 40V to low voltage 5V" conversion circuit is designed.

[0093] like Figure 4 As shown, the degenerate level conversion circuit includes: a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6 and a seventh MOS tube M7. The gate of the fourth MOS tube M4 is connected to the gate of the fifth MOS tube M5 and connected to the output end of the degenerate ring oscillator, the drain of the fourth MOS tube M4 is connected to the drain of the fifth MOS tube M5, the gate of the sixth MOS tube M6 is connected to the gate of the seventh MOS tube M7 and connected to the common end of the drain of the fourth MOS tube M4 and the drain of the fifth MOS tube M5, the common end of the drain of the sixth MOS tube M6 and the drain of the seventh MOS tube M7 is used as the output end of the degenerate level conversion circuit, the source of the fourth MOS tube M4 and the source of the sixth MOS tube M6 are connected to a 5V power supply, and the source of the fifth MOS tube M5 and the source of the seventh MOS tube M7 are grounded. Among them, the fourth MOS tube M4 and the sixth MOS tube M6 are enhanced PMOS tubes, and the fifth MOS tube M5 and the seventh MOS tube M7 are enhanced NMOS tubes.

[0094] like Figure 5 As shown, the non-degenerate level conversion circuit includes: an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12 and a thirteenth MOS tube M13. The common end of the gate of the eighth MOS tube M8 connected to the gate of the ninth MOS tube M9 and the gate of the tenth MOS tube M10 is connected to the output end of the non-degenerate ring oscillator, the source of the eighth MOS tube M8 is connected to a 5V low-voltage power supply, the drain of the eighth MOS tube M8 is connected to the drain of the ninth MOS tube M9, the source of the ninth MOS tube M9 is connected to the drain of the tenth MOS tube M10; the common end of the gate of the eleventh MOS tube M11 connected to the gate of the thirteenth MOS tube M13 is connected to the output end of the eighth MOS tube M8. The drain of the transistor M8 is connected to the common end connected to the drain of the ninth MOS transistor M9, the source of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12 are connected to a 5V low-voltage power supply, and the common end connected to the drain of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 is used as the output end of the non-degenerate level conversion circuit; the source of the twelfth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M13, and the source of the tenth MOS transistor M10 and the source of the thirteenth MOS transistor M13 are grounded. Among them, the eighth MOS transistor M8 and the eleventh MOS transistor M11 are enhanced PMOS transistors, and the ninth MOS transistor M9, the tenth MOS transistor M10, the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are enhanced NMOS transistors.

[0095] In this embodiment, the frequency attenuation detection circuit detects the frequency attenuation of the degraded ring oscillator over time, and counts the number of cycles of the non-degraded ring oscillator in the corresponding cycle of the degraded ring oscillator, thereby realizing the monitoring and early warning of the channel degradation of the first high-voltage transistor of the degraded inverter. Figure 6 The structure of the frequency attenuation detection circuit is shown, and the frequency attenuation detection circuit includes: a frequency divider, a counter, a discriminator and a latch. Figure 6 and Figure 1 The non-degenerate level conversion circuit converts the high-voltage oscillation signal CLK_REF_40V output by the non-degenerate ring oscillator into a low-voltage oscillation signal CLK_REF and outputs it to the counter as the reference clock of the counter; the degenerate level conversion circuit converts the high-voltage oscillation signal CLK_DEG_40V output by the degenerate ring oscillator into a low-voltage oscillation signal CLK_DEG and outputs it to the frequency divider for frequency division to obtain the counting signal of the counter and the latch signal of the latch. The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; the discriminator determines whether the counting result is greater than the threshold to obtain the discrimination result; the latch latches the discrimination result according to the latch signal (the rising edge of the CLK_DEG signal) and then outputs it. Among them, the frequency of CLK_DEG degenerates over time, and the frequency of CLK_REF does not degenerate over time. As the degraded ring oscillator degrades, the period of the oscillation signal CLK_DEG becomes longer and the frequency becomes smaller (frequency attenuation). After frequency division, the period is even longer. The divided signal is used as a counting signal to count the number of reference clocks (non-degraded oscillation signals). As the degraded ring oscillator degrades, the number of counts increases. If the counting result is greater than the threshold, it means that the frequency of the CLK_DEG signal is attenuated, the degraded ring oscillator reaches a certain degree of degradation, and the latch outputs a channel degradation warning signal.

[0096] Figure 7 FIG. 1 is a schematic diagram of a chip degradation monitoring circuit provided by an embodiment of the present invention. Figure 7 As shown, the chip degradation monitoring circuit provided in this embodiment includes: a channel degradation monitoring circuit and a gate oxide degradation monitoring circuit. The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel. The multiple monitoring signals are output in series through the data serial output circuit. The data serial output circuit outputs a clock signal CLK or a digital signal DOUT.

[0097] In MOS devices, hot carriers obtain enough energy under high electric field and cross the interface barrier to be injected into the oxide layer, generating oxide layer trap charge or interface trap charge, which increases or fluctuates the oxide layer charge, causing the device channel degradation, gate oxide degradation or substrate degradation. The channel degradation mechanism is: when the energy of hot electrons is higher than the Si-SiO2 interface barrier, it is possible to cross the interface barrier and be injected into the gate oxide layer. Some carriers eventually reach the gate electrode and form part of the gate current. In the process of hot carriers passing through the gate oxide layer to reach the gate electrode, the hot carriers will use their energy to open Si-H, Si-OH bonds and other bonds at the interface, generate acceptor-type interface states at the Si-SiO2 interface, or be captured by traps in the gate oxide layer to form trapped charges. These generated interface states and trapped charges will cause changes in the local electric field of the device, thereby causing the degradation of device characteristics, causing the circuit performance to gradually degrade over time, and eventually causing the device and the circuit to fail, that is, the channel degradation effect is generated.

[0098] The embodiment of the present invention designs a corresponding monitoring circuit for the gate oxide degradation of the chip, and the gate oxide of the gate oxide breakdown monitoring circuit and the host circuit (circuit under test) adopt the same gate oxide thickness and work under the same temperature environment, but the gate oxide area and voltage stress are different. A voltage stress greater than its working condition is applied to the gate dielectric of the monitoring circuit, so that the gate dielectric of the monitoring circuit fails earlier than the circuit under test. When the life of the circuit under test (chip) is away from the wear-out failure zone and there is a pre-set "prediction advance amount", the monitoring circuit subjected to a larger voltage stress enters the wear-out failure zone in advance, thereby achieving the purpose of early warning of gate oxide degradation failure.

[0099] like Figure 8As shown, the gate oxide degradation monitoring circuit provided by this embodiment includes a first branch (left branch) and a second branch (right branch), the first branch and the second branch are connected through a current mirror; the first branch includes a MOS capacitor group, and the second branch includes an inverter; the MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor; the common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end of the source and drain of each high-voltage MOS tube is short-circuited to serve as the second end of the MOS capacitor group; the second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, which is greater than the working voltage of the high-voltage MOS tube to accelerate the gate oxide degradation of the high-voltage MOS tube; the current mirror copies the current image of the first branch to the input end of the inverter of the second branch, and determines the gate oxide degradation degree of the high-voltage MOS tube according to the level signal output by the inverter. The gate oxide degradation monitoring circuit can dynamically monitor the PA (picoampere) level current in real time, the stress voltage can be adjusted, the degradation time can be controlled, and the dynamic monitoring of the reliability failure of the power supply and the isolation drive circuit over time can be realized. The high-voltage MOS tube in the MOS capacitor group can be one of the high-voltage resistant devices such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), DEMOS (Drain-Extended MOS, extended drain MOS). The withstand voltage of the high-voltage MOS tube in the embodiment of the present invention ranges from 12V to 750V.

[0100] The first branch is connected to the second branch through a current mirror, and the current image of the first branch is copied to the input end of the inverter of the second branch through the current mirror. The degree of gate oxide degradation of the high-voltage MOS tube is determined according to the level signal output by the inverter, so as to achieve the purpose of early warning.

[0101] In this embodiment, the current mirror includes a first resistor R1, a second resistor R2, a first MOS transistor PM1 and a second MOS transistor PM2, wherein the first MOS transistor PM1 and the second MOS transistor PM2 are PMOS. The gate of the first MOS transistor PM1 is connected to the gate of the second MOS transistor PM2; the source of the first MOS transistor PM1 is connected to the stress voltage through the first resistor R1, and the drain of the first MOS transistor PM1 is connected to the first end of the MOS capacitor group. The common end at which the gate of the first MOS transistor PM1 and the gate of the second MOS transistor PM2 are connected is connected to the first end of the MOS capacitor group. The source of the second MOS transistor PM2 is connected to the stress voltage through the second resistor R2 and is connected to the first resistor R1, and the drain of the second MOS transistor PM2 is connected to the input end of the inverter.

[0102] In this embodiment, the second branch further includes a third resistor R3 and a Zener diode D1, wherein a first end of the third resistor R3 is connected to the input end of the inverter and to the drain of the second MOS transistor PM2, and a second end of the third resistor R3 is grounded GND. A cathode of the Zener diode D1 is connected to the input end of the inverter and to the drain of the second MOS transistor PM2, and a positive electrode of the Zener diode D1 is grounded GND.

[0103] The chip gate oxide degradation monitoring circuit provided in this embodiment, the high-voltage MOS tube in the MOS capacitor group undergoes gate oxide degradation under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, and there is no mirrored current in the second branch. The third resistor R3 pulls down the input voltage of the inverter, and the inverter outputs a high level. The high-voltage MOS tube in the MOS capacitor group undergoes gate oxide degradation under the action of stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, the first branch generates a large current, and the second branch has a mirrored large current. The mirrored large current generates a voltage through the third resistor R3, and the input end of the inverter is a high level, and the inverter outputs a low level. Specifically, when the high-voltage MOS tube as a MOS capacitor has not degraded, the capacitor group can be equivalent to an open circuit. At this time, the branch where the first resistor R1 on the left side of the current mirror is located has no current, so the branch where the second resistor R2 on the right side is located has no current. At this time, the third resistor R3 pulls down the input voltage of the inverter, and the output inverter outputs a high level. When the high-voltage MOS tube as a MOS capacitor degrades and breaks down, it can be equivalent to a short circuit. At this time, a current appears in the branch where the first resistor R1 on the left side of the current mirror is located, and the current size is determined by the size of R1 and the PMOS tube below R1. The current size of the left branch is limited by the first resistor R1 and will not exceed the safe operating range of the circuit. At the same time, due to the characteristics of the proportional current mirror, a current also appears in the branch where the second resistor R2 on the right side of the current mirror is located. The current generates a voltage through the third resistor R3, and the Zener diode D1 limits the voltage within the safe operating range to protect the inverter from being damaged by high voltage. At this time, the inverter input is high and the output is low. The degree of degradation of the MOS capacitor is judged according to the level of the inverter output.

[0104] In a specific embodiment, the high-voltage MOS tube in the gate oxide degradation monitoring circuit adopts LDMOS with a withstand voltage of 12V to 750V, which is used to monitor the gate oxide degradation of the LDMOS in the circuit under test. The source and drain of the LDMOS are short-circuited together to form a capacitor. Since the LDMOS is designed with an even number of fingers in the actual power chip and the isolation driver chip, an even number of LDMOS is designed in the embodiment of the present invention.

[0105] In another specific embodiment, the high-voltage MOS tube in the gate oxide degradation monitoring circuit can also use a DEMOS (Drain-Extended MOS) with a withstand voltage of 40V to 750V to monitor the gate oxide degradation of the DEMOS in the circuit under test. The drain end of the DEMOS has an extended layer of a lightly doped region. The extended layer increases the withstand voltage of the drain end by maintaining charge balance, using appropriate vertical profiles, and increasing the length of the low-doped region. The lightly doped region forms a high resistance that can withstand higher voltages. Most of the high drain voltage will fall on this lightly doped region, so the lightly doped extended layer can increase the withstand voltage of the drain end. DEMOS, as a high-voltage resistant device, is used in high-voltage power supplies and isolation driver chips. The source and drain of the DEMOS are short-circuited together to form a capacitor.

[0106] It should be noted that the number of high-voltage MOS tubes in the MOS capacitor group can be an even number or an odd number. The more high-voltage MOS tubes there are in the MOS capacitor group, the more accurate the monitoring. By adjusting the magnitude of the stress voltage applied to the MOS capacitor group, the degradation time of the MOS capacitor can be controlled, and dynamic internal monitoring of PA (picoampere) level current can be performed in real time.

[0107] Fig. 9 FIG. 1 is a schematic diagram of a chip degradation monitoring circuit provided by another embodiment of the present invention. Fig. 9 As shown, the chip degradation monitoring circuit provided in this embodiment includes: a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit and a substrate degradation monitoring circuit. The channel degradation monitoring circuit is used to monitor the channel degradation of the high-voltage power device; the gate oxide degradation monitoring circuit is used to monitor the gate oxide degradation of the high-voltage power device; the substrate degradation monitoring circuit is used to monitor the substrate degradation of the high-voltage power device. The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit, and outputs multiple monitoring signals in parallel to the data serial output circuit. The multiple monitoring signals are serially output through the data serial output circuit, and the data serial output circuit outputs a clock signal CLK or a digital signal DOUT.

[0108] like Fig.10As shown, the substrate degradation monitoring circuit provided by this embodiment includes a plurality of monitoring branches connected in parallel, each monitoring branch includes a high-voltage MOS device, a comparator and a selector, and the selector includes a first selector, a second selector and a third selector; the drain of the high-voltage MOS device is connected to the stress voltage through the first selector, and is connected to the first input terminal of the comparator; the gate of the high-voltage MOS device is connected to the test voltage through the second selector, and the test voltage is used to apply a negative bias to the gate-drain terminal of the high-voltage MOS device; the source of the high-voltage MOS device is connected to the reverse test voltage through the third selector; the second input terminal of the comparator of each monitoring branch inputs a reference voltage, and the second input terminals of the comparators of different monitoring branches input different reference voltages. In a specific embodiment, the high-voltage MOS device in each monitoring branch can be one of the high-voltage MOS devices such as DEMOS (Drain-Extended MOS), LDMOS (Laterally Diffused Metal Oxide Semiconductor), VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor), BJT (Bipolar Junction Transistor), etc., and its source-drain voltage (maximum withstand voltage) ranges from 12V to 750V.

[0109] In this embodiment, the high-voltage MOS tubes in each monitoring branch are DEMOS devices, and the source-drain voltages vds of the DEMOS devices in each monitoring branch are the same. Fig.10As shown, taking a 40V pedmos device as an example, the high-voltage device substrate degradation monitoring circuit includes a plurality of monitoring branches connected in parallel, each monitoring branch includes: a pedmos 40V device, a comparator AMP and a selector sel; each monitoring branch has three selectors sel, and for the convenience of description, the selectors from top to bottom are defined as the first selector sel, the second selector sel, and the third selector sel. In each monitoring branch, the drain of the pedmos 40V device is connected to the stress voltage Stress through the first selector sel, and is connected to the first input terminal (reverse input terminal) of the comparator AMP; the gate of the pedmos 40V device is connected to the test voltage press through the second selector sel, and the test voltage press is a negative bias applied to the gate-drain terminal of the pedmos 40V device; the source of the pedmos 40V device is connected to the reversed test voltage press through the third selector sel. The gate of the pedmos 40V device is connected to the source of the pedmos 40V device through the second selector sel and the third selector sel. A different reference voltage Vref is input to the second input terminal (non-inverting input terminal) of the comparator AMP of each monitoring branch.

[0110] The power supply voltage range in the monitoring circuit is 0-5V, which is a monitoring circuit composed of ordinary low-voltage devices; in the monitored circuit, the power supply voltage is in the working range of 0-40V, which is a circuit structure composed of high-voltage pedmos 40v devices. In the fault monitoring circuit composed of 5V low-voltage devices, multiple pedmos 40v tubes for monitoring substrate degradation are included. These pedmos 40v tubes are applied with the same or different stress voltages Stress in the degradation stage. At the same time, in the stage of detecting the degree of degradation, each pedmos 40v tube output is connected to a comparator, and the reference voltage Vref of each comparator is different. Press is the negative bias stress applied to the gate-drain end of the tested pedmos 40v device. Generally, a negative bias of 0-5V is applied to the gate-drain end. The source-drain voltage vds of the pedmos 40v device is 40v, which is a high-voltage MOS tube that can meet the 40V power supply. The negative bias stress (i.e., test voltage) press applied to the gate-drain terminal of the pedmos 40v device is 0-5V, and the threshold voltage vth of the pedmos 40v device is 0.92V. By applying a constant voltage stress to the source terminal of the pedmos, when press=0V, vgs>vth, the pedmos is in the saturation region, thereby degrading it. When the stress voltage Stress is 5V, 5.5V, and 6V, it can produce a difference with the 5V voltage of the drain, thereby simulating the degradation of high-voltage devices and analyzing the impact of substrate degradation on the life of the pedmos 40v device.

[0111] Fig.10The substrate degradation monitoring circuit shown is essentially a circuit that monitors the drift of the threshold voltage. The circuit formed by connecting ABCDEF in each monitoring branch is a circuit that applies voltage stress and monitors the degree of degradation, and the output is sent to one input terminal of the comparator AMP, and the reference voltage Vref is input to the other input terminal of the comparator AMP. The power supply terminal provides a stress voltage Stress, and the stress voltage Stress of each monitoring branch can be fixed and the same, or it can be different. When the threshold voltage of the pedmos 40v device drifts under the effect of substrate degradation, the threshold voltage output at the B terminal of the monitoring circuit becomes larger. When the degraded threshold voltage is greater than a certain set value, the comparator AMP outputs a high level to issue a warning to the subsequent circuit.

[0112] In the embodiment of the present invention, the working state of the monitoring branch can be selected / switched to be a stress application state or a degradation monitoring state through three selectors Sel. When the first selector Sel selects the drain of the pedmos device to be connected to the stress voltage Stress, the second selector Sel selects the gate of the pedmos device to be connected to the test voltage Press, and the third selector Sel selects the source of the pedmos device to be connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; when the first selector Sel selects the drain of the pedmos device to be connected to the first input terminal of the comparator, and the second selector Sel and the third selector Sel select the gate and source of the pedmos device to be connected, the working state of the monitoring branch is the degradation monitoring state.

[0113] In a specific embodiment, the stress voltage Stress of the drain connection of the pedmos device in each monitoring branch is the same, and the source-drain voltage vds of the pedmos device in each monitoring branch is the same, which is 40V. The reference voltage Vref input to the comparator AMP of each monitoring branch increases in sequence, for example: 0.95V, 0.96V, 0.97V, etc. The circuit state can be switched by the selector Sel: when the circuit is in the stress state, the selector Sel selects the ACE path to apply overvoltage stress to the pedmos 40v device; when the circuit is in the monitoring circuit state, the Sel selector selects the BDF path. For example: when the substrate of a pedmos 40v device is degraded, its maximum threshold voltage vth increases to above 0.95V and below 0.96V. During the monitoring stage, the threshold voltage vth is compared with the reference voltage Vref 0.95V of the comparator. The degraded threshold voltage is higher than the reference voltage, and the output end of the comparator outputs a low level, issuing a warning for the subsequent circuit. It can be seen that the substrate of the pedmos 40v device in the monitoring branch is degraded, and the reference voltage Vref of the comparator in other monitoring branches is higher than 0.96V. The comparator does not issue a warning and can continue to work. As the circuit working time increases, the substrate of the pedmos 40v devices in other monitoring branches continues to degrade, and the maximum threshold voltage vth of the pedmos 40v devices increases to above 0.96V and below 0.97V. In the monitoring stage, the threshold voltage vth is compared with the reference voltage Vref of the comparator. The degraded threshold voltage is higher than the reference voltage Vref of the comparator by 0.95V and 0.96V. The output ends of the two comparators both output low levels, which issue warnings for subsequent circuits. It can be seen that the substrates of the pedmos 40v devices in the two monitoring branches are degraded. The remaining comparators with Vref higher than 0.97V do not issue warnings and can continue to work, and so on. The warnings issued by comparators with different reference voltages Vref show that the larger the threshold voltage after degradation, the more comparators that issue warnings, indicating a higher degree of degradation, thereby judging the degree of degradation of the threshold voltage of substrate degradation at this time, and realizing visualization of the threshold voltage vth of the monitored circuit. Since the reference voltage Vref of the comparator is an external input, a circuit structure with an adjustable monitoring degradation threshold is formed at the same time, which plays a role in fault monitoring and early warning of the high-voltage pedmos device.

[0114] In another specific embodiment, the stress voltage Stress of the drain connection of the pedmos 40V device in each monitoring branch is different. For example, the stress voltage Stress in the monitoring branch is 5V, 5.5V, 6V, etc. The difference in stress voltage Stress will lead to different degradation times of the pedmos 40V device. Increasing the stress voltage Stress will advance the degradation time, and reducing the stress voltage Stress will delay the degradation time. Assuming that the maximum threshold voltage vth of the pedmos 40v device degrades to above 0.95V, the degradation degree is 20%, and the threshold voltage vth degrades to above 0.96V, the degradation degree is 30%, and so on. Then, by increasing the stress voltage Stress, the pedmos 40V device can be degraded in advance, the degradation time can be controlled, and the waiting time for monitoring the degradation degree can be saved, so that the degree of degradation of the current pedmos 40V device can be known.

[0115] It should be noted that the reference voltage Vref of the comparator includes but is not limited to 0.95V, 0.96V, and 0.97V, and can be set according to the specific requirements. The stress voltage Stress in each monitoring branch includes but is not limited to 5V, 5.5V, and 6V, and can be set according to the specific requirements.

[0116] In the embodiment of the present invention, the channel degradation monitoring circuit, the gate oxide degradation monitoring circuit and the substrate degradation monitoring circuit output multiple monitoring signals in parallel. Since the number of pins of general analog chips, especially power supply and isolation chips, is limited, the parallel multiple monitoring signals are converted into a serial single output through a data serial output circuit.

[0117] Fig.11 Schematic diagram of a data serial output circuit provided by an embodiment of the present invention. Fig.11 As shown, the data serial output circuit includes: a serial shift register, a frequency divider and a multiplexer. The serial shift register outputs the parallel monitoring signals in series; the output signal of the frequency divider is a control signal, and its function is to refresh the monitoring signal to be output and the selection signal of the multiplexer; the function of the multiplexer is to select whether to output a clock signal or a serial data signal.

[0118] like Fig.12As shown, the core components of the serial shift register include multiple D flip-flops and multiple selectors. The output ends of the multiple selectors are respectively connected to the D input ends of the multiple D flip-flops, and the control ends of the multiple selectors are connected to the control signal sel output by the frequency divider. The control signal sel controls the update of each round of data, and outputs the parallel input data data[0], data[1], data[2], and data[3] in series under the action of the clock CLK. Among them, when the trigger edge arrives, the D flip-flop stores the value of the input end, which has nothing to do with the currently stored value. Between two valid pulse edges, the jump of D will not affect the value stored in the flip-flop, but before the pulse edge arrives, the input end D must have enough setup time to ensure signal stability.

[0119] like Fig.13 As shown, the CLK terminal of the frequency divider inputs the clock signal, and the out output terminal generates a 64-frequency clock signal. When the frequency division signal is high, the multiplexer is controlled to output the clock signal without frequency division to generate the frame header of each round of serial data; at the same time, the sel signal in the serial shift register circuit is also controlled. When the clock signal is high, the parallel data is stored in the register. When the frequency division signal is low, the multiplexer is controlled to output the serial data signal.

[0120] In order to improve the convenience of the module, a ring oscillator is embedded in the data serial output circuit. The clock signal is provided by the ring oscillator inside the data serial output circuit, and no external clock input is required. Fig.14 : is a schematic diagram of a data serial output circuit embedded in a ring oscillator provided by an embodiment of the present invention. Specifically, the structure of the ring oscillator is a series of odd-numbered inverters connected in series to form a closed loop (the last output is the initial input). If the initial trigger is "1", then the final output is "0", and then the input is also "0", and then the output becomes "1" again, thus achieving a fixed frequency alternating oscillation output of "0" and "1". In a specific embodiment, an existing push-pull inverter can be used to form a ring oscillator, and the ring oscillator can generate a stable clock signal.

[0121] The embodiment of the present invention also provides a chip degradation monitoring circuit with redundancy compensation. Fig.15As shown, the chip degradation monitoring circuit with redundant compensation of the embodiment of the present invention includes: a channel degradation monitoring circuit, a gate oxide degradation monitoring circuit, a substrate degradation monitoring circuit, a channel degradation compensation circuit, a gate oxide degradation compensation circuit and a substrate degradation compensation circuit. The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit. When the channel degradation monitoring signal output by the channel degradation monitoring circuit reaches the warning value, it can be switched to the channel degradation compensation circuit; when the gate oxide degradation monitoring signal output by the gate oxide degradation monitoring circuit reaches the warning value, it can be switched to the gate oxide degradation compensation circuit; when the substrate degradation monitoring signal output by the substrate degradation monitoring circuit reaches the warning value, it can be switched to the substrate degradation compensation circuit.

[0122] When the channel degradation monitoring circuit, gate oxide degradation monitoring circuit and substrate degradation monitoring circuit give warning signals, the chip will automatically switch to the redundant compensation circuit to compensate for chip reliability. For example, for channel degradation, the sensitive critical path is reinforced; for gate oxide degradation, it is obtained by compensating MOS capacitors; and for substrate degradation, it is switched to the Dummy tube. Since process defect monitoring and compensation include multiple outputs, and general analog chips, especially power and isolation chips, have a limited number of pins, it is necessary to convert the multi-channel parallel results into a serial single output. For the power chip, only one pin is added; for the isolation chip, only one pin is added on each side of the primary and secondary sides.

[0123] like Fig.16 As shown, the channel degradation compensation circuit includes a first MOS tube M1 and a second MOS tube M2. The gate of the first MOS tube M1 is connected to a 40V power supply, the gate of the second MOS tube M2 is connected to an input signal IN, the source of the first MOS tube M1 is connected to the drain of the second MOS tube M2, the source of the second MOS tube M2 is grounded, and the drain of the first MOS tube M1 serves as an output terminal OUT.

[0124] like Fig.17 As shown, the gate oxide degradation compensation circuit includes a third MOS tube M3, a fourth MOS tube M4 and a first switch T1, the gate of the third MOS tube M3 and the gate of the fourth MOS tube M4 are connected to the first switch T1, the drain of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, and the source of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4 and grounded. The third MOS tube M3 and the fourth MOS tube M4 are used as redundant compensation devices, one end 1 of the first switch T1 is connected to the normal working circuit of the chip, and the other end 2 of the first switch T1 is connected to the redundant compensation control signal. When the chip is working normally, the first switch T1 is connected to the normal working circuit of the chip, and when the redundant compensation control signal is "1", the redundant compensation device circuit is started.

[0125] like Fig.18 As shown, the substrate degradation compensation circuit includes a fifth MOS transistor M5, a sixth MOS transistor M6, a second switch T2 and a third switch T3, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are used as redundant compensation devices. The gate of the fifth MOS transistor M5 is connected to the common terminal 2 through the second switch T2, and the gate of the sixth MOS transistor M6 is connected to the common terminal 2 through the third switch T3, and the common terminal 2 is connected to the normal working circuit of the chip. The source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are connected to the power supply terminal VDD of the chip, and the common terminal 3 connected to the drain of the fifth MOS transistor M5 and the drain of the sixth MOS transistor M6 is connected to the normal working circuit of the chip. The common terminal 1 connected to the third switch T3 and the second switch T2 is connected to the redundant compensation control signal.

[0126] The present invention designs corresponding monitoring circuits for channel degradation, gate oxide degradation, and substrate degradation of high-voltage devices, and can support degradation monitoring and early warning of high-voltage devices and circuits. The degradation monitoring circuit for high-voltage devices of the present invention can be embedded in the power supply and isolation driver chip to form a power supply and isolation driver chip with high-voltage MOS device fault monitoring and early warning functions. The present invention fills the gap that the current process monitoring module only monitors low-voltage processes and does not monitor high-voltage processes; it overcomes the current problem of only predicting the aging reliability of the chip at the initial factory, and being unable to warn the high-voltage power supply and isolation chip of real-time dynamic aging monitoring over time as the working time increases.

[0127] The embodiment of the present invention also provides a power chip, which embeds the above-mentioned degradation monitoring circuit for high-voltage devices. The degradation monitoring circuit for high-voltage devices in the above-mentioned embodiment is embedded in the power chip, and a power chip with the function of monitoring degradation faults of 12V-750V high-voltage devices is integrated.

[0128] The embodiment of the present invention also provides an isolation driver chip, which has the above-mentioned degradation monitoring circuit for high-voltage devices embedded in it. The degradation monitoring circuit for high-voltage devices in the above-mentioned embodiment is embedded in the isolation driver chip, and an isolation driver chip with the function of monitoring degradation faults of 12V to 750V high-voltage devices is integrated.

[0129] The manufacturing process of the power chip or the isolation driver chip can adopt the ultra-high voltage bipolar CMOS-DMOS (BCD) process technology. By using the ultra-high voltage BCD process of non-epitaxial technology, a MOS device with a withstand voltage of up to 750V can be realized, and the device has higher reliability. The high-voltage device substrate degradation monitoring and early warning circuit of the above embodiment is compatible with the ultra-high voltage BCD process.

[0130] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A channel degradation monitoring circuit, characterized in that: include: Degenerate ring oscillator; The degenerate ring oscillator comprises an odd number of degenerate inverters connected in series; The degenerate inverter comprises: a first high-voltage transistor, a first resistor, a second resistor and a third resistor, wherein the gate of the first high-voltage transistor is connected to the input terminal of the degenerate inverter through the first resistor and is grounded through the second resistor, the source of the first high-voltage transistor is grounded, the drain of the first high-voltage transistor is connected to the power supply terminal of the chip through the third resistor, and the node between the drain of the first high-voltage transistor and the third resistor serves as the output terminal of the degenerate inverter; The channel degradation monitoring circuit monitors the channel degradation of the first high-voltage transistor of the degraded inverter by detecting the frequency attenuation of the degraded ring oscillator over time.

2. The channel degradation monitoring circuit according to claim 1, characterized in that: Also includes: Non-degenerate ring oscillator; The non-degenerate ring oscillator comprises an odd number of non-degenerate inverters connected in series; The non-degenerate inverter includes: a second high-voltage transistor, a third high-voltage transistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; The gate of the second high-voltage transistor is connected to the input terminal of the non-degenerate inverter through the eighth resistor and is grounded through the fourth resistor; the source of the second high-voltage transistor is grounded, and the drain of the second high-voltage transistor is connected to the source of the third high-voltage transistor; The gate of the third high-voltage transistor is connected to the power supply terminal of the chip through the fifth resistor and is grounded through the sixth resistor; the drain of the third high-voltage transistor is connected to the power supply terminal of the chip through the seventh resistor, and the node between the drain of the third high-voltage transistor and the seventh resistor serves as the output terminal of the non-degenerate inverter.

3. The channel degradation monitoring circuit according to claim 2, characterized in that: The first high-voltage transistor, the second high-voltage transistor and the third high-voltage transistor are one of LDMOS, VDMOS and BJT; The source-drain voltage of the first high-voltage transistor, the second high-voltage transistor and the third high-voltage transistor is 12V-750V.

4. The channel degradation monitoring circuit according to claim 2, characterized in that: Also includes: A non-degenerate level conversion circuit, a degenerate level conversion circuit, and a frequency attenuation detection circuit; The non-degenerate ring oscillator is connected to the frequency attenuation detection circuit via a non-degenerate level conversion circuit, and the degenerate ring oscillator is connected to the frequency attenuation detection circuit via a degenerate level conversion circuit; The non-degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the non-degenerate ring oscillator into a low-voltage oscillation signal; The degenerate level conversion circuit is used to convert the high-voltage oscillation signal output by the degenerate ring oscillator into a low-voltage oscillation signal; The frequency attenuation detection circuit is used to detect the frequency attenuation of the degraded ring oscillator over time, and count the number of cycles of the non-degraded ring oscillator in the corresponding cycle of the degraded ring oscillator, so as to monitor and warn the channel degradation of the first high-voltage transistor of the degraded inverter.

5. The channel degradation monitoring circuit according to claim 4, characterized in that: The degenerate level conversion circuit comprises: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; The gate of the fourth MOS tube is connected to the gate of the fifth MOS tube and connected to the output end of the degenerate ring oscillator, and the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube; The gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, and is connected to the common end where the drain of the fourth MOS tube is connected to the drain of the fifth MOS tube, and the common end where the drain of the sixth MOS tube is connected to the drain of the seventh MOS tube serves as the output end of the degenerate level conversion circuit; The source of the fourth MOS tube and the source of the sixth MOS tube are connected to the low voltage power supply, and the source of the fifth MOS tube and the source of the seventh MOS tube are grounded.

6. The channel degradation monitoring circuit according to claim 5, characterized in that: The non-degenerate level conversion circuit includes: an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube and a thirteenth MOS tube; The common end of the gate of the eighth MOS tube, the gate of the ninth MOS tube and the gate of the tenth MOS tube is connected to the output end of the non-degenerate ring oscillator, the source of the eighth MOS tube is connected to the low-voltage power supply, the drain of the eighth MOS tube is connected to the drain of the ninth MOS tube, and the source of the ninth MOS tube is connected to the drain of the tenth MOS tube; The common end of the gate of the eleventh MOS tube connected to the gate of the thirteenth MOS tube is connected to the common end of the drain of the eighth MOS tube connected to the drain of the ninth MOS tube, the source of the eleventh MOS tube and the gate of the twelfth MOS tube are connected to the low-voltage power supply, and the common end of the drain of the eleventh MOS tube connected to the drain of the twelfth MOS tube serves as the output end of the non-degenerate level conversion circuit; The source of the twelfth MOS tube is connected to the drain of the thirteenth MOS tube, and the source of the tenth MOS tube and the source of the thirteenth MOS tube are grounded.

7. The channel degradation monitoring circuit according to claim 6, characterized in that: The fourth MOS tube, the sixth MOS tube, the eighth MOS tube and the eleventh MOS tube are enhanced PMOS tubes; The fifth MOS tube, the seventh MOS tube, the ninth MOS tube, the tenth MOS tube, the twelfth MOS tube and the thirteenth MOS tube are enhanced NMOS tubes.

8. The channel degradation monitoring circuit according to claim 4, characterized in that: The frequency attenuation detection circuit comprises: a frequency divider, a counter, a discriminator and a latch; The high-voltage oscillation signal output by the non-degenerate ring oscillator is converted into a low-voltage oscillation signal by a non-degenerate level conversion circuit and then output to the counter as a reference clock of the counter; The high-voltage oscillation signal output by the degenerate ring oscillator is converted into a low-voltage oscillation signal by a degenerate level conversion circuit, and then output to the frequency divider for frequency division to obtain a counting signal of the counter and a latch signal of the latch; The counter counts the reference clock according to the counting signal and outputs the counting result to the discriminator; The discriminator determines whether the counting result is greater than a threshold value to obtain a discrimination result; The latch latches the discrimination result according to the latch signal and then outputs a warning signal.

9. A chip degradation monitoring circuit, characterized in that: include: The channel degradation monitoring circuit, gate oxide degradation monitoring circuit and data serial output circuit according to any one of claims 1 to 8; The channel degradation monitoring circuit and the gate oxide degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit; The data serial output circuit outputs the multi-channel monitoring signals in series.

10. The chip degradation monitoring circuit according to claim 9, characterized in that: The gate oxide degradation monitoring circuit comprises a first branch and a second branch, wherein the first branch and the second branch are connected via a current mirror; The first branch includes a MOS capacitor group, and the second branch includes an inverter; The MOS capacitor group includes a plurality of high-voltage MOS tubes connected in parallel, and the source and drain of each high-voltage MOS tube are short-circuited to be equivalent to a capacitor; The common end connected to the gate of each high-voltage MOS tube serves as the first end of the MOS capacitor group, and the common end short-circuited between the source and the drain of each high-voltage MOS tube serves as the second end of the MOS capacitor group; The second end of the MOS capacitor group is grounded, and the first end of the MOS capacitor group is connected to a stress voltage, where the stress voltage is greater than the working voltage of the high-voltage MOS tube to accelerate gate oxide degradation of the high-voltage MOS tube; The current mirror is used to copy the current mirror image of the first branch to the input end of the inverter of the second branch, and the level signal output by the inverter is used as a gate oxide degradation monitoring signal.

11. The chip degradation monitoring circuit according to claim 10, characterized in that: The current mirror comprises: a first resistor, a second resistor, a first MOS tube and a second MOS tube; The gate of the first MOS tube is connected to the gate of the second MOS tube; The source of the first MOS tube is connected to the stress voltage through the first resistor, and the drain of the first MOS tube is connected to the first end of the MOS capacitor group; The source of the second MOS tube is connected to the stress voltage through the second resistor and is connected to the first resistor, and the drain of the second MOS tube is connected to the input end of the inverter.

12. The chip degradation monitoring circuit according to claim 11, characterized in that: The common end at which the gate of the first MOS tube is connected to the gate of the second MOS tube is connected to the first end of the MOS capacitor group.

13. The chip degradation monitoring circuit according to claim 11, characterized in that: The second branch further includes a third resistor, a first end of the third resistor is connected to the input end of the inverter and to the drain of the second MOS tube, and a second end of the third resistor is grounded.

14. The chip degradation monitoring circuit according to claim 13, characterized in that: The second branch further includes a Zener diode, a cathode of the Zener diode is connected to the input end of the inverter and to the drain of the second MOS tube, and an anode of the Zener diode is grounded.

15. The chip degradation monitoring circuit according to claim 13, characterized in that: The gate oxide of the high-voltage MOS tube in the MOS capacitor group degrades under the stress voltage. When the gate oxide of the high-voltage MOS tube is not broken down, there is no current in the first branch, there is no mirrored current in the second branch, the third resistor pulls down the input voltage of the inverter, and the inverter outputs a high level; The gate oxide of the high-voltage MOS tube in the MOS capacitor group degrades under the stress voltage. When the gate oxide of the high-voltage MOS tube is broken down, the first branch generates current, the second branch has a mirrored large current, the mirrored current generates a voltage through the third resistor, the input end of the inverter is high level, and the inverter outputs a low level.

16. The chip degradation monitoring circuit according to claim 10, characterized in that: The high-voltage MOS tube in the MOS capacitor group is one of LDMOS, VDMOS and DEMOS.

17. The chip degradation monitoring circuit according to claim 9, characterized in that: Also includes: Substrate degradation monitoring circuit, used to monitor substrate degradation of high voltage power devices; The substrate degradation monitoring circuit is connected in parallel with the channel degradation monitoring circuit and the gate oxide degradation monitoring circuit; The channel degradation monitoring circuit, the gate oxide degradation monitoring circuit and the substrate degradation monitoring circuit output multiple monitoring signals in parallel to the data serial output circuit.

18. The chip degradation monitoring circuit according to claim 17, characterized in that: The substrate degradation monitoring circuit comprises a plurality of monitoring branches connected in parallel, each monitoring branch comprises: a high-voltage MOS device, a comparator and a selector, and the selector comprises a first selector, a second selector and a third selector; The drain of the high-voltage MOS device is connected to the stress voltage through the first selector and is connected to the first input terminal of the comparator; The gate of the high-voltage MOS device is connected to a test voltage through a second selector, and the test voltage is used to apply a negative bias voltage to the gate-drain terminal of the high-voltage MOS device; The source of the high-voltage MOS device is connected to a reverse test voltage through a third selector; A reference voltage is input to the second input terminal of the comparator of each monitoring branch, and the reference voltages input to the second input terminals of the comparators of the various monitoring branches are different.

19. The chip degradation monitoring circuit according to claim 18, characterized in that: The gate of the high-voltage MOS device is connected to the source of the high-voltage MOS device through the second selector and the third selector.

20. The chip degradation monitoring circuit according to claim 18, characterized in that: The substrate degradation monitoring circuit selects the working state of each monitoring branch as a stress application state or a degradation monitoring state through a first selector, a second selector and a third selector.

21. The chip degradation monitoring circuit according to claim 20, characterized in that: When the first selector selects that the drain of the high-voltage MOS device is connected to the stress voltage, the second selector selects that the gate of the high-voltage MOS device is connected to the test voltage, and the third selector selects that the source of the high-voltage MOS device is connected to the reverse test voltage, the working state of the monitoring branch is the stress application state; When the first selector selects the drain of the high-voltage MOS device to be connected to the first input terminal of the comparator, and the second selector and the third selector select the gate of the high-voltage MOS device to be connected to the source, the working state of the monitoring branch is the degradation monitoring state.

22. The chip degradation monitoring circuit according to claim 18, characterized in that: The stress voltage of the drain connection of the high-voltage MOS device in each monitoring branch is the same; The reference voltage input to the second input terminal of the comparator of each monitoring branch increases in sequence.

23. The chip degradation monitoring circuit according to claim 18, characterized in that: The stress voltage of the drain connection of the high-voltage MOS device in each monitoring branch is different; The reference voltage input to the second input terminal of the comparator of each monitoring branch increases in sequence.

24. The chip degradation monitoring circuit according to claim 22 or 23, characterized in that: The source-drain voltages of the high-voltage MOS devices in each monitoring branch are the same.

25. The chip degradation monitoring circuit according to claim 18, characterized in that: The high-voltage MOS device in each monitoring branch is one of DEMOS, LDMOS, VDMOS and BJT, and the source-drain voltage of the high-voltage MOS device is 12V-750V.

26. The chip degradation monitoring circuit according to claim 17, characterized in that: Also includes: Channel degradation compensation circuit, gate oxide degradation compensation circuit and substrate degradation compensation circuit; The channel degradation compensation circuit is connected in parallel with the channel degradation monitoring circuit, the gate oxide degradation compensation circuit is connected in parallel with the gate oxide degradation monitoring circuit, and the substrate degradation compensation circuit is connected in parallel with the substrate degradation monitoring circuit.

27. The chip degradation monitoring circuit according to claim 26, characterized in that: The gate oxide degradation compensation circuit comprises: a third MOS tube, a fourth MOS tube and a first switch, the third MOS tube and the fourth MOS tube serving as redundant compensation devices; The gate of the third MOS tube and the gate of the fourth MOS tube are connected to the first switch, the drain of the third MOS tube is connected to the source of the fourth MOS tube, and the source of the third MOS tube is connected to the drain of the fourth MOS tube and is grounded; One end of the first switch is connected to the normal working circuit of the chip, and the other end of the first switch is connected to the redundancy compensation control signal.

28. The chip degradation monitoring circuit according to claim 26, characterized in that: The substrate degradation compensation circuit comprises: a fifth MOS transistor, a sixth MOS transistor, a second switch and a third switch, wherein the fifth MOS transistor and the sixth MOS transistor serve as redundant compensation devices; The gate of the fifth MOS tube is connected to the common terminal through the second switch, and the gate of the sixth MOS tube is connected to the common terminal through the third switch, and the common terminal is connected to the normal working circuit of the chip; The source of the fifth MOS tube and the source of the sixth MOS tube are connected to the power supply end of the chip, and the common end where the drain of the fifth MOS tube and the drain of the sixth MOS tube are connected is connected to the normal working circuit of the chip; A common terminal of the third switch connected to the second switch is connected to the redundancy compensation control signal.

29. A power chip, characterized in that: A chip degradation monitoring circuit comprising any one of claims 9-28.

30. An isolation driver chip, characterized in that: A chip degradation monitoring circuit comprising any one of claims 9-28.

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