Chip reliability test interference synchronization method based on self-learning and related equipment

Abstract

The application provides a self-learning-based chip reliability test interference synchronization method and related equipment. After receiving a synchronization interference instruction output before executing a sensitive instruction, self-learning interference delay is performed, and an interference source generates an interference signal. In the self-learning process, if no running status signal of the chip is received within the waiting period, it is considered that the chip is running abnormally under the interference signal, and an abnormality confirmation signal is sent to the chip. After receiving the abnormality confirmation signal, the chip resets the wrong sensitive instruction and continues the self-learning process of the interference delay. When the number of received synchronization interference instructions reaches a preset number, and the interference delay after self-learning is not less than the execution period, the test result of the chip is generated according to the number of abnormalities under all interference delays. The application does not need to use an oscilloscope or manually modify the delay parameter, and adaptively adjusts the interference signal generation time, further improving the automation efficiency of chip reliability problem detection in the interference environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a chip reliability test interference synchronization method based on self-learning and related equipment. BACKGROUND

[0002] At present, the interference generated by inductive load, relay and the like during startup or operation will have a strong impact on the main control chip of the "brain" of household appliances. Household appliances generally need to be subjected to periodic impact experiments of interference pulse groups generated by a fast transient generator on various ports of the chip, and can enter the market after meeting the corresponding standards such as GB-T 17626.4-2008.

[0003] Although the interference pulse group impact experiment can to some extent find the chip reliability problems under the interference environment, the interference signal input time and the chip sensitive instruction execution time are asynchronous during the experiment, and the interference signal cannot affect the sensitive instruction, thereby causing many products that have passed the detection to gradually expose problems after entering the market. SUMMARY

[0004] Therefore, the present application provides a chip reliability test interference synchronization method based on self-learning and related equipment, which improves the automation efficiency of chip reliability problem detection under the interference environment, reduces the operation difficulty, and saves manpower and time cost.

[0005] The first aspect of the present application provides a chip reliability test interference synchronization method based on self-learning, comprising:

[0006] receiving a synchronization interference instruction of a chip; wherein the chip executes a sensitive instruction according to an execution period, and outputs a synchronization interference instruction before executing the sensitive instruction;

[0007] setting a first interference delay, and triggering an interference source to generate an interference signal;

[0008] If the running status signal of the chip is not received within the waiting period, the number of abnormalities under the current first interference delay is recorded, and an abnormality confirmation signal is sent to the chip; wherein the chip resets the erroneous sensitive instruction after receiving the abnormality confirmation signal, continues to execute the sensitive instruction according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instruction;

[0009] If the running status signal of the chip is received within the waiting period, and the number of received synchronization interference instructions does not reach a preset number, the waiting period is reset, and the step of receiving the synchronization interference instruction of the chip is returned to be executed;

[0010] If the number of received synchronization interference instructions reaches the preset number, the first interference delay is increased by a preset step to obtain a second interference delay;

[0011] If the second interference delay is less than the execution period, the second interference delay is taken as a new first interference delay, and the setting of the first interference delay and the triggering of the interference source to generate the interference signal are returned to be executed;

[0012] If the second interference delay is not less than the execution period, a test result of the chip is generated according to the number of exceptions under all first interference delays.

[0013] Optionally, the generating of the test result of the chip according to the number of exceptions under all first interference delays if the second interference delay is not less than the execution period comprises:

[0014] If the number of exceptions under all first interference delays is 0, a test result of a normal chip is generated;

[0015] If the number of exceptions under any first interference delay is not 0, a test result of an abnormal chip is generated.

[0016] Optionally, the generating of the test result of the chip according to the number of exceptions under all first interference delays if the second interference delay is not less than the execution period further comprises:

[0017] If the test result of the chip indicates that the chip is abnormal, a normal distribution curve is generated according to the number of exceptions of the chip under each first interference delay.

[0018] Optionally, the generating of the normal distribution curve according to the number of exceptions of the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal further comprises:

[0019] When a target chip is tested, a target interference delay in the normal distribution curve is selected as a first interference delay, and the setting of the first interference delay and the triggering of the interference source to generate the interference signal are executed.

[0020] The second aspect of the present application provides a chip reliability test interference synchronization device based on self-learning, comprising:

[0021] A receiving unit is configured to receive a synchronization interference instruction of a chip; wherein the chip executes a sensitive instruction according to an execution period and outputs the synchronization interference instruction before executing the sensitive instruction;

[0022] A triggering unit is configured to set a first interference delay and trigger an interference source to generate an interference signal.

[0023] The sending unit is configured to record the number of abnormalities under the current first interference delay if the running status signal of the chip is not received within the waiting period, and send an abnormality confirmation signal to the chip; wherein, after receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction, continues to execute the sensitive instruction according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instruction;

[0024] The first activation unit is configured to reset the waiting period and activate the receiving unit to execute the step of receiving the synchronization interference instruction of the chip if the running status signal of the chip is received within the waiting period and the number of received synchronization interference instructions does not reach the preset number.

[0025] The first generation unit is configured to increase the first interference delay by a preset step to obtain a second interference delay if the number of received synchronization interference instructions reaches the preset number.

[0026] The second activation unit is configured to take the second interference delay as a new first interference delay and activate the triggering unit to execute the step of setting the first interference delay and triggering the interference source to generate the interference signal if the second interference delay is less than the execution period.

[0027] The second generation unit is configured to generate the test result of the chip according to the number of abnormalities under all first interference delays if the second interference delay is not less than the execution period.

[0028] Optionally, the second generation unit comprises:

[0029] The second generation sub-unit is configured to generate a normal test result of the chip if the number of abnormalities under all first interference delays is 0.

[0030] The second generation sub-unit is further configured to generate an abnormal test result of the chip if the number of abnormalities under any first interference delay is not 0.

[0031] Optionally, the interference synchronization device for chip reliability test based on self-learning further comprises:

[0032] The third generation unit is configured to generate a normal distribution curve according to the number of abnormalities of the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal.

[0033] Optionally, the interference synchronization device for chip reliability test based on self-learning further comprises:

[0034] The selection unit is configured to select a target interference delay in the normal distribution curve as the first interference delay when a target chip is tested, and execute the step of setting the first interference delay and triggering the interference source to generate the interference signal.

[0035] The third aspect of the present application provides an electronic device, comprising:

[0036] one or more processors;

[0037] a storage device having one or more programs stored thereon;

[0038] The one or more programs, when executed by the one or more processors, cause the one or more processors to implement the self-learning-based chip reliability test interference synchronization method according to any one of the first aspect.

[0039] The fourth aspect of the present application provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the self-learning-based chip reliability test interference synchronization method according to any one of the first aspect.

[0040] From the above solution, the present application provides a self-learning-based chip reliability test interference synchronization method and related equipment. After outputting the synchronization interference instruction before the receiving chip executes the sensitive instruction, the self-learning interference delay is performed, and the interference source generates the interference signal. In the self-learning process, if the running status signal of the chip is not received within the waiting period, it is considered that the chip runs abnormally under the interference signal, and an abnormality confirmation signal is sent to the chip. After receiving the abnormality confirmation signal, the chip resets the erroneous sensitive instruction to continue the self-learning process of the interference delay. When the number of received synchronization interference instructions reaches the preset number, and the interference delay after self-learning is not less than the execution period, the test result of the chip is generated according to the number of abnormalities under all interference delays. The present application does not need to use an oscilloscope or manually modify the delay parameter. Through online learning of the occurrence time of the interference signal and the sensitive instruction and the chip abnormality, the interference signal generation time is adaptively adjusted to realize synchronization with the sensitive instruction, further improve the chip reliability problem detection automation efficiency in the interference environment, reduce the operation difficulty, and save the manpower and time cost. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0042] Figure 1 A specific flowchart of a self-learning-based chip reliability test interference synchronization method provided by the embodiments of the present application is provided.

[0043] Figure 2A schematic diagram of interference delay and sensitive instruction execution period is provided for another embodiment of the present application;

[0044] Figure 3 A schematic diagram of a chip reliability test interference synchronization device based on self-learning is provided for another embodiment of the present application;

[0045] Figure 4 A schematic diagram of an electronic device for implementing a chip reliability test interference synchronization method based on self-learning is provided for another embodiment of the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0047] The term "comprising" and its variants as used herein are open-ended, that is "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Related definitions of other terms will be given in the following description.

[0048] It should be noted that the information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0049] It should be noted that the "first", "second", etc. concepts mentioned in the present application are only used to distinguish different devices, modules or units, and are not used to limit the order or mutual dependence of the functions performed by these devices, modules or units.

[0050] It should be noted that the modification of "one" or "multiple" in the present application is illustrative and not limiting, and those skilled in the art should understand that unless otherwise explicitly indicated in the context, it should be understood as "one or more".

[0051] The embodiments of the present application provide a chip reliability test interference synchronization method based on self-learning, as shown in Figure 1 The specific steps include the following steps:

[0052] S101, receive a synchronization interference instruction of a chip.

[0053] The chip executes the sensitive instruction according to an execution period, and outputs the synchronization interference instruction before executing the sensitive instruction. The chip can be, but is not limited to, a microcontroller unit (MCU), which is not limited here.

[0054] It can be understood that the execution periods of different sensitive instructions can be different, and the execution period can be adjusted according to the type of the sensitive instruction, which is not limited here.

[0055] It should be noted that the sensitive instruction includes, but is not limited to, the stack and unstack operations of the periodic clock interrupt on the interrupt field, which is not limited here. The execution period is set by technicians, experts, etc. in advance, which is also not limited here.

[0056] In the specific implementation process of the present application, the key sensitive instruction, the pre-specified sensitive instruction, etc. can be selected as the target sensitive instruction, and the synchronization interference instruction is output only before the target sensitive instruction to achieve the purpose of focusing on the target sensitive instruction.

[0057] S102, set a first interference delay, and trigger the interference source to generate an interference signal.

[0058] At the beginning of the test, the first interference delay can be set to 0, or can be set to other numerical values according to actual conditions, which is not limited here.

[0059] In the specific implementation process of the present application, after triggering the interference source to generate the interference signal, the running status signal sent by the receiving chip is continuously waited for, which can be realized by, but not limited to, a general GIPO interface, which is not limited here.

[0060] It can be understood that if the chip can normally run in the interference environment (the interference signal generated by the interference source interferes with the chip), the running status signal can be sent by the chip according to the preset sending period (for example, 0.5 ms), otherwise the running status signal cannot be sent.

[0061] S103, if the running status signal of the chip is not received within the waiting period, record the number of abnormalities under the current first interference delay, and send an abnormality confirmation signal to the chip.

[0062] The chip resets the error sensitive instruction after receiving the abnormality confirmation signal, continues to execute the sensitive instruction according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instruction.

[0063] It should be noted that the waiting period is set and changed by technicians, experts, etc. in advance, which is not limited here.

[0064] Specifically, if the running status signal of the chip is not received within the waiting period, it is confirmed that the chip is abnormal in the interference environment, the number of abnormalities under the current first interference delay is recorded, for example, if the current first interference delay is t1, the number of abnormalities of t1 is +1, and an abnormality confirmation signal is sent to the chip.

[0065] S104, if the running status signal of the chip is received within the waiting period, it is judged whether the number of received synchronization interference instructions reaches a preset number.

[0066] The preset number is set or changed by technicians, experts, etc. in advance, including but not limited to 100,000 times, etc., which is not limited here.

[0067] Specifically, if it is judged that the number of received synchronization interference instructions does not reach the preset number, step S105 is executed; if it is judged that the number of received synchronization interference instructions reaches the preset number, step S106 is executed.

[0068] S105, resetting the waiting period.

[0069] S106, increasing the first interference delay by a preset step to obtain a second interference delay.

[0070] The preset step is set or changed by technicians, experts, etc. in advance, which is not limited here.

[0071] In the specific implementation process of the present application, the preset step is generally selected to be less than half of the chip single instruction period, and the single instruction period of the MCU level master control chip is generally 10-100 ns, that is, 5 ns can be selected, which is not limited here.

[0072] S107, judging whether the second interference delay is less than the execution period.

[0073] In the specific implementation process of the present application, in the self-learning process of the interference delay, it is increased by a preset step to select an optimal interference delay, but the increase of the interference delay has a fixed boundary, as shown in the following formula: Figure 2 When the interference delay is increased to the execution period T of the sensitive instruction, the increase is stopped, such as continuing to increase, which will be repeated with the next sensitive instruction, which has no actual meaning, that is, when , the preset step is stopped increasing (t0 is the initial interference delay at the beginning of the test, is the total delay after each increase step in the learning process, that is, the second interference delay).

[0074] Specifically, if the second interference delay is less than the execution period, step S108 is executed; if the second interference delay is not less than the execution period, step S109 is executed.

[0075] S108, taking the second interference delay as a new first interference delay.

[0076] S109, generating a test result of the chip according to the abnormality times under all the first interference delays.

[0077] In the specific implementation process of the present application, the test result of the chip can be generated according to the abnormality times under the first interference delay. If the abnormality times under all the first interference delays are 0, a normal test result of the chip is generated. If the abnormality times under any first interference delay are not 0, an abnormal test result of the chip is generated, or the abnormality times under all the first interference delays are lower than the abnormality times threshold, a normal test result of the chip is generated. If the abnormality times under any first interference delay are not lower than the abnormality times threshold, an abnormal test result of the chip is generated.

[0078] It should be noted that the abnormality times threshold is set or changed by technicians, experts, etc. in advance, which is not limited here.

[0079] It can be understood that the above is only an example of the embodiment of generating the test result of the chip according to the abnormality times under all the first interference delays. The abnormality frequency under all the first interference delays and the preset frequency threshold can also be used to generate the test result of the chip.

[0080] The abnormality frequency under the first interference delay can be calculated by, but not limited to, the quotient of the abnormality times under the first interference delay and the number of synchronous interference instructions under the first interference delay as the abnormality frequency under the first interference delay, which is not limited here.

[0081] It should be noted that the preset frequency threshold is set or changed by technicians, experts, etc. in advance, which is not limited here.

[0082] Specifically, if the abnormality frequency under all the first interference delays is lower than the preset frequency threshold, a normal test result of the chip is generated. If the abnormality frequency under any first interference delay is not lower than the preset frequency threshold, an abnormal test result of the chip is generated.

[0083] Optionally, in another embodiment of the present application, one embodiment of the self-learning based chip reliability test interference synchronization method further comprises:

[0084] If the test result of the chip shows that the chip is abnormal, a normal distribution curve is generated according to the abnormality times of the chip under each first interference delay.

[0085] Specifically, for each first interference delay, an abnormal frequency is generated according to the corresponding abnormal number of the chip at each first interference delay, and a result conforming to a normal distribution is fitted according to the corresponding abnormal frequency of the chip at each first interference delay, to obtain a normal distribution curve.

[0086] In the specific implementation process of the present application, the normal distribution curve can be saved to the synchronous interference device, and in the subsequent detection of other chips and abnormal chips of the same batch, the normal distribution curve can be directly used for testing, which is not limited here.

[0087] Optionally, in another embodiment of the present application, an implementation of the self-learning chip reliability test interference synchronization method further includes:

[0088] When a target chip is tested, a target interference delay in the normal distribution curve is selected as the first interference delay, and then the steps of setting the first interference delay and triggering the interference source to generate the interference signal are executed for testing.

[0089] The target chip includes but is not limited to chips of the same batch as the tested chip, chips that need to be analyzed for abnormal reasons, and the like, which are not limited here.

[0090] In the specific implementation process of the present application, the target interference delay can be but is not limited to N interference delays near the center point position of the normal distribution curve, N is a positive integer, which is pre-set by technicians, experts, and the like, which is not limited here.

[0091] By using the normal distribution curve, the reliability of the chip in the interference environment can be quickly tested, and the problem of the abnormal chip can be quickly located.

[0092] From the above scheme, the application provides a chip reliability test interference synchronization method based on self-learning. After outputting the synchronization interference instruction before the receiving chip executes the sensitive instruction, the self-learning interference delay is performed, and the interference source generates the interference signal. In the process of self-learning, if the running status signal of the chip is not received within the waiting period, it is considered that the chip runs abnormally under the interference signal, and an abnormal confirmation signal is sent to the chip. After receiving the abnormal confirmation signal, the chip resets the wrong sensitive instruction to continue the self-learning process of the interference delay. When the number of received synchronization interference instructions reaches the preset number, and the interference delay after self-learning is not less than the execution period, the test result of the chip is generated according to the number of abnormalities under all interference delays. The application does not need to use an oscilloscope or manually modify the delay parameter. Through online learning of the interference signal, the occurrence time of the sensitive instruction and the abnormal situation of the chip, the interference signal generation time is adaptively adjusted to realize synchronization with the sensitive instruction, further improve the chip reliability problem detection automation efficiency in the interference environment, reduce the operation difficulty, and save the manpower and time cost.

[0093] The embodiment of the application provides a chip reliability test interference synchronization device based on self-learning, as shown in the figure, specifically comprising: Figure 3

[0094] The receiving unit 301 is used for receiving the synchronization interference instruction of the chip.

[0095] The chip executes the sensitive instruction according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instruction.

[0096] The triggering unit 302 is used for setting the first interference delay, and triggering the interference source to generate the interference signal.

[0097] The sending unit 303 is used for recording the number of abnormalities under the current first interference delay if the running status signal of the chip is not received within the waiting period, and sending the abnormal confirmation signal to the chip.

[0098] The chip resets the wrong sensitive instruction after receiving the abnormal confirmation signal, continues to execute the sensitive instruction according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instruction.

[0099] The first activation unit 304 is used for resetting the waiting period if the running status signal of the chip is received within the waiting period, and the number of received synchronization interference instructions does not reach the preset number, and activating the receiving unit to execute the step of receiving the synchronization interference instruction of the chip.

[0100] The first generation unit 305 is used for increasing the first interference delay by a preset step length to obtain the second interference delay if the number of received synchronization interference instructions reaches the preset number.

[0101] ​The second activation unit 306 is configured to, if the second interference delay is less than the execution period, activate the trigger unit to execute the setting of the first interference delay and trigger the interference source to generate the interference signal, by taking the second interference delay as the new first interference delay.

[0102] The second generation unit 307 is configured to, if the second interference delay is not less than the execution period, generate the test result of the chip according to the abnormality times under all the first interference delays.

[0103] The specific working process of the units disclosed in the above embodiments of the present application can be referred to the corresponding method embodiment contents, for example, as shown in the above embodiments, and details are not described herein. Figure 1

[0104] Optionally, in another embodiment of the present application, one embodiment of the second generation unit 307 comprises:

[0105] The second generation sub-unit is configured to, if the abnormality times under all the first interference delays are all 0, generate the normal test result of the chip.

[0106] The second generation sub-unit is further configured to, if the abnormality times under any first interference delay are not 0, generate the abnormal test result of the chip.

[0107] The specific working process of the units disclosed in the above embodiments of the present application can be referred to the corresponding method embodiment contents, and details are not described herein.

[0108] Optionally, in another embodiment of the present application, one embodiment of the self-learning based chip reliability test interference synchronization device comprises:

[0109] The third generation unit is configured to, if the test result of the chip indicates that the chip is abnormal, generate a normal distribution curve according to the abnormality times of the chip under each first interference delay.

[0110] The specific working process of the units disclosed in the above embodiments of the present application can be referred to the corresponding method embodiment contents, and details are not described herein.

[0111] Optionally, in another embodiment of the present application, one embodiment of the self-learning based chip reliability test interference synchronization device comprises:

[0112] The selection unit is configured to, when there is a target chip to be tested, select a target interference delay in the normal distribution curve as the first interference delay, execute the setting of the first interference delay, and trigger the interference source to generate the interference signal.

[0113] The specific working process of the units disclosed in the above embodiments of the present application can be referred to the corresponding method embodiment contents, and details are not described herein.

[0114] ​From the above scheme, the application provides a chip reliability test interference synchronization device based on self-learning. After outputting the synchronization interference instruction before the receiving chip executes the sensitive instruction, the self-learning interference delay is performed, and the interference source generates the interference signal. In the process of self-learning, if the running status signal of the chip is not received within the waiting period, it is considered that the chip runs abnormally under the interference signal, and an abnormality confirmation signal is sent to the chip. After receiving the abnormality confirmation signal, the chip resets the wrong sensitive instruction to continue the self-learning process of the interference delay. When the number of received synchronization interference instructions reaches the preset number, and the interference delay after self-learning is not less than the execution period, the test result of the chip is generated according to the number of abnormalities under all interference delays. The application does not need to use an oscilloscope or manually modify the delay parameter. Through online learning of the interference signal, the occurrence time of the sensitive instruction and the abnormal situation of the chip, the interference signal generation time is adaptively adjusted to realize synchronization with the sensitive instruction, further improve the chip reliability problem detection automation efficiency in the interference environment, reduce the operation difficulty, and save the manpower and time cost.

[0115] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc.

[0116] Another embodiment of the application provides an electronic device, such as Figure 4 as shown, comprising:

[0117] one or more processors 401.

[0118] a storage 402 having stored thereon one or more programs.

[0119] When the one or more programs are executed by the one or more processors 401, the one or more processors 401 implement the self-learning-based chip reliability test interference synchronization method as described in any of the above embodiments.

[0120] Another embodiment of the application provides a computer storage medium having stored thereon a computer program, wherein the computer program is executed by a processor to implement the self-learning-based chip reliability test interference synchronization method as described in any of the above embodiments.

[0121] In the context of this application, a machine-readable medium can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical wire, portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing.

[0122] Note that the computer-readable medium described above in the present application can be either a computer-readable signal medium or a computer-readable storage medium or any combination thereof. The computer-readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the computer-readable storage medium can include, but are not limited to, one or more lines of electrical wire, portable computer diskette, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing. In the present application, the computer-readable storage medium can be any tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, the computer-readable signal medium can include a computer-readable storage medium in baseband or propagated as a carrier wave in a propagated data signal, which bears computer-readable program code. Such propagated data signal can take a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium that is not a computer-readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including, but not limited to, wire, cable, RF, etc., or any suitable combination of the foregoing.

[0123] The computer-readable medium described above can be included in the electronic device described above; or can exist separately from the electronic device and be not assembled into the electronic device.

[0124] Another embodiment of the present application provides a computer program product for performing the self-learning based chip reliability test interference synchronization method described above when the computer program product is executed.

[0125] In particular, the processes described above with reference to the flowcharts can be implemented as a computer software program according to embodiments of the present application. For example, embodiments of the present application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods illustrated by the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processing device, the above-described functions defined in the methods of embodiments of the present application are performed.

[0126] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0127] While several inventive embodiments have been discussed above, it should be appreciated that many modifications can be made by those skilled in the art. For example, some of the steps described above can be order independent, and thus can be performed in an order different than described. Yet further, some steps can be combined or omitted, and other steps can be added while still falling within the scope of the present application. Therefore, the described embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

[0128] The above description is only preferred embodiments of the present application and the explanation of the technical principles of the application. Those skilled in the art should understand that the scope of the application involved in the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and should also cover other technical solutions formed by any combinations of the above technical features or their equivalent features without departing from the above application concept. For example, the technical solutions formed by replacing the above features with technical features having similar functions and applied in the present application (but not limited to) with each other.

Claims

1. A self-learning based chip reliability test interference synchronization method, characterized in that, The method comprises the following steps: receiving a synchronization interference instruction of a chip; wherein the chip executes sensitive instructions according to an execution period, and outputs a synchronization interference instruction before executing the sensitive instructions; setting a first interference delay, and triggering an interference source to generate an interference signal; if a running status signal of the chip is not received within a waiting period, recording an abnormal number under the current first interference delay, and sending an abnormality confirmation signal to the chip; wherein after receiving the abnormality confirmation signal, the chip resets the error sensitive instructions, continues to execute the sensitive instructions according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instructions; if the running status signal of the chip is received within the waiting period, and the number of received synchronization interference instructions does not reach a preset number, resetting the waiting period, and returning to the step of receiving the synchronization interference instruction of the chip; if the number of received synchronization interference instructions reaches the preset number, increasing the first interference delay by a preset step to obtain a second interference delay; if the second interference delay is less than the execution period, taking the second interference delay as a new first interference delay, and returning to the step of setting the first interference delay and triggering the interference source to generate the interference signal; if the second interference delay is not less than the execution period, generating a test result of the chip according to the abnormal numbers under all first interference delays.

2. The self-learning based chip reliability test interference synchronization method of claim 1, wherein, The step of generating the test result of the chip according to the abnormal numbers under all first interference delays if the second interference delay is not less than the execution period comprises: if the abnormal numbers under all first interference delays are all 0, generating a normal test result of the chip; if the abnormal number under any first interference delay is not 0, generating an abnormal test result of the chip.

3. The self-learning based chip reliability test interference synchronization method of claim 1, wherein, After the step of generating the test result of the chip according to the abnormal numbers under all first interference delays if the second interference delay is not less than the execution period, the method further comprises: if the test result of the chip indicates that the chip is abnormal, generating a normal distribution curve according to the corresponding abnormal numbers of the chip under each first interference delay.

4. The self-learning based chip reliability test interference synchronization method of claim 3, wherein, After the step of generating the normal distribution curve according to the corresponding abnormal numbers of the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal, the method further comprises: when a target chip is tested, selecting a target interference delay in the normal distribution curve as the first interference delay, and executing the step of setting the first interference delay and triggering the interference source to generate the interference signal.

5. A self-learning based chip reliability test interference synchronization device, characterized in that, The method comprises the following steps: a receiving unit is configured to receive a synchronization interference instruction of a chip; wherein the chip executes sensitive instructions according to an execution period, and outputs a synchronization interference instruction before executing the sensitive instructions; a triggering unit is configured to set a first interference delay, and trigger an interference source to generate an interference signal; a sending unit is configured to, if a running status signal of the chip is not received within a waiting period, record an abnormal number under the current first interference delay, and send an abnormality confirmation signal to the chip; wherein after receiving the abnormality confirmation signal, the chip resets the error sensitive instructions, continues to execute the sensitive instructions according to the execution period, and outputs the synchronization interference instruction before executing the sensitive instructions; The first activation unit is configured to reset the waiting period and activate the receiving unit to execute the step of receiving the synchronization interference instruction of the chip if the running status signal of the chip is received in the waiting period and the number of received synchronization interference instructions does not reach the preset number; The first generation unit is configured to increase the first interference delay by a preset step to obtain a second interference delay if the number of received synchronization interference instructions reaches the preset number; The second activation unit is configured to take the second interference delay as a new first interference delay and activate the triggering unit to execute the step of setting the first interference delay and triggering the interference source to generate the interference signal if the second interference delay is smaller than the execution period; The second generation unit is configured to generate the test result of the chip according to the number of abnormalities under all the first interference delays if the second interference delay is not smaller than the execution period.

6. The self-learning based chip reliability test interference synchronization device according to claim 5, characterized in that, The second generation unit comprises: The second generation sub-unit is configured to generate a test result of a normal chip if the number of abnormalities under all the first interference delays is 0; The second generation sub-unit is further configured to generate a test result of an abnormal chip if the number of abnormalities under any first interference delay is not 0.

7. The self-learning based chip reliability test interference synchronization device according to claim 5, characterized in that, Further comprising: The third generation unit is configured to generate a normal distribution curve according to the number of abnormalities of the chip under each first interference delay if the test result of the chip indicates that the chip is abnormal.

8. The self-learning based chip reliability test interference synchronization device according to claim 7, characterized in that, Further comprising: The selection unit is configured to select a target interference delay in the normal distribution curve as the first interference delay when a target chip is tested, and execute the step of setting the first interference delay and triggering the interference source to generate the interference signal.

9. An electronic device, comprising: One or more processors; A storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the self-learning-based chip reliability test interference synchronization method according to any one of claims 1 to 4. A computer program is stored thereon, and the computer program is executed by a processor to implement the self-learning-based chip reliability test interference synchronization method according to any one of claims 1 to 4.

10. A computer storage medium, characterized in that, ​

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