Real-time shutdown system for abnormal test

Abstract

The invention relates to the technical field of integrated circuit testing, and discloses a real-time shutdown system for abnormal testing, which comprises a testing machine, the output end of the testing machine is electrically connected with the input end of a testing data unit, and the output end of the testing data unit is electrically connected with an analysis unit. The test machine comprises a voltage circuit test and a visual sensor, the test machine is provided with a physical interface and a multi-angle adjusting platform, and the test machine further comprises a voltage blocker. Detailed data numbered by the test data unit is compared with a card control rule and visual data imported into a temporary memory through the data analysis unit, a chip is pushed out and recorded when an error value exceeds a threshold value, and a shutdown unit and an alarm unit are triggered when the error value still exceeds the threshold value after the number of times of secondary review is exceeded; according to the invention, the system can stop in real time when finding the abnormality, the abnormality is stopped at the present, the diffusion of the abnormality is reduced, the energy invested for subsequent troubleshooting is reduced, and the loss is reduced to the minimum.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and specifically to a real-time shutdown system for testing abnormalities. Background Art

[0002] With the development of science and technology, the demand for chip testing in the computer industry is gradually increasing. There are more and more types of chips, and different types of chips have different testing requirements for chip testing.

[0003] In production, traditional testing equipment only compares parameters after a batch of tests is completed. If an abnormality occurs, the entire batch may be affected. Some irreversible tests may cause the chip to be scrapped, and eventually lead to compensation. It is impossible to achieve real-time monitoring data comparison to make the system shut down in real time when an abnormality is discovered, thereby reducing the spread of abnormalities and minimizing losses. In traditional equipment, only voltage and circuit are tested. If there is a cold solder joint or the chip line path is too narrow, it will not be effectively detected. In addition, when the testing organization conducts inspections, data delays often occur. When the equipment is shut down, the good chips will be stuck, and the defective chips will enter the finished product collection channel, resulting in an increase in the defective rate. Therefore, we propose an abnormal real-time shutdown system to solve the above problems. Summary of the invention

[0004] 1. Technical issues to be resolved In view of the deficiencies in the prior art, the present invention provides a real-time shutdown system for test abnormalities, which has the advantages of control rules for visually setting voltage, and performing multiple comparisons and data recording, etc., which solves the problem that traditional equipment only tests voltage and circuit, such as poor soldering or narrow chip line paths, cannot be effectively detected, and data delays often occur when the test organization conducts detection. When the equipment is shut down, good chips will be stuck, and defective chips will enter the finished product collection channel, resulting in an increase in the defective rate.

[0005] (II) Technical solution To achieve the above-mentioned object, the present invention provides the following technical solutions: a test abnormal real-time shutdown system, comprising a test machine, wherein the output end of the test machine is electrically connected to the input end of a test data unit, the output end of the test data unit is electrically connected to a parsing unit, the test machine comprises a voltage circuit test and a visual sensor, and the test machine is provided with a physical interface and a multi-angle adjustment platform; The output end of the card control setting unit is electrically connected to the input end of the analysis unit, the output end of the analysis unit is electrically connected to the input end of the data analysis unit, and the output end of the visual sensor is electrically connected to the input end of the data analysis unit; The output ends of the card control setting unit and the data analysis unit are electrically connected to the input end of the shutdown unit, and the output ends of the card control setting unit, the data analysis unit and the shutdown unit are electrically connected to the input end of the alarm unit.

[0006] Preferably, the test machine further comprises a voltage blocker, the output end of the test machine is electrically connected to the input end of the temporary memory, and a shutdown resistor can be provided in the temporary memory to temporarily power the temporary memory.

[0007] Preferably, the output end of the temporary memory is electrically connected to the input end of the parsing unit and the card control setting unit, and the test data exported by the visual sensor and the voltage circuit test platform in the test machine are recorded and numbered through the test data unit. The test data are entered into the temporary memory for temporary archiving, and basic feedback is provided to the card control setting unit, and the basic feedback includes brief information about the image recorded by the visual sensor and the voltage circuit test data.

[0008] Preferably, the card control setting unit can set the card control rules of the product in advance, and the test data unit can enter the numbered detailed data into the parsing unit, and the parsing unit can parse the acquired data and store it in a database.

[0009] Preferably, the data analysis unit compares the detailed data with the data in the product database corresponding to the card control rule analysis, and performs appearance verification on the data recorded by the visual sensor in the card control setting unit.

[0010] Preferably, after the card control rules are compared in the data analysis unit and the defective product information is triggered, the chip is introduced into the return unit and enters the test machine for secondary review.

[0011] Preferably, when the chip that triggers the card control rule still appears after the second review, the alarm unit sends an email to notify the relevant department, and the email displays information such as the machine, product, time, triggered rule, etc.

[0012] Preferably, a voltage blocker is provided in the test machine. After the shutdown unit takes effect, the voltage blocker will discharge the chip being tested in the device to avoid breakdown after power is stored. The shutdown resistor in the temporary memory will play a role and store the data in the temporary memory into the database of the analysis unit.

[0013] Preferably, if data anomalies, data interruptions or shutdowns occur during storage in the test data unit, the return unit will be triggered, and the chip being tested in the test machine will be ejected and retested.

[0014] Preferably, when the card control setting unit specifies the card control rules to the analysis unit, the chip being tested in the test machine can also be pushed out through the return unit and retested, and the data analysis unit compares the detailed data after the test data unit number with the card control rules and the visual data imported into the temporary memory. When the error value exceeds the threshold, the chip will be pushed out and recorded. If the error value still exceeds the threshold after more than two rechecks, the shutdown unit and the alarm unit will be triggered.

[0015] (III) Beneficial effects Compared with the prior art, the present invention provides a test abnormality real-time shutdown system, which has the following beneficial effects: 1. The test abnormality real-time shutdown system compares the detailed data after the test data unit number with the card control rules and the visual data imported into the temporary memory through the data analysis unit. When the error value exceeds the threshold, the chip will be pushed out and recorded. If the error value still exceeds the threshold after more than two rechecks, the shutdown unit and the alarm unit will be triggered. The system can realize the real-time shutdown function when an abnormality is found, stop the abnormality at the current state, reduce the spread of the abnormality, reduce the energy invested in subsequent investigations, and minimize the loss.

[0016] 2. The test abnormality real-time shutdown system is equipped with a voltage blocker in the test machine. After the shutdown unit takes effect, the voltage blocker will discharge the chip being tested in the device to avoid breakdown after power is stored. The shutdown resistor in the temporary memory will play a role and store the data in the temporary memory into the database of the analysis unit to avoid data loss and data without matching values ​​during shutdown or power outage, which will lead to retesting of the entire batch of chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of a test abnormality real-time shutdown system proposed by the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] See also Figure 1A test abnormality real-time shutdown system shown includes a test machine, an output end of the test machine is electrically connected to an input end of a test data unit, an output end of the test data unit is electrically connected to a parsing unit, the test machine includes a voltage circuit test and a visual sensor, the test machine is provided with a physical interface and a multi-angle adjustment platform, the multi-angle adjustment platform can rotate the chip, so as to facilitate the visual sensor to record the chip at multiple angles; The voltage circuit test platform installed in the tester samples the current of the chip according to the power consumption test instruction during the chip test, calculates the current value and converts it into a power value, and then sends it to the test data unit. The test data unit determines whether the power value is within the predetermined power range; when it is determined to be within the predetermined power range, a power consumption test pass result is generated; when it is determined not to be within the predetermined power range, a defective product test result is generated, and the test data unit records it for comparison with the card control rules. It is worth noting that the good product test result includes the input pin test pass result; the tester generates an input pin test instruction and sets the high and low levels of the chip. The tester detects whether the chip input pin has high and low levels according to the input pin test instruction; if high and low levels are detected, an input pin test pass result is generated; if high and low levels are not detected, a defective product test result is generated. Due to the differences in the test procedures of different testers, the testers are not described excessively.

[0020] The tester also includes a voltage blocker, the output end of the tester is electrically connected to the input end of the temporary memory, a shutdown resistor can be provided in the temporary memory, and the temporary memory can be temporarily powered. The shutdown resistor is in a DC circuit, and the shutdown resistor is connected in parallel with a capacitor. The capacitor can store electrical energy, and the electrical energy consumed by the resistor when the capacitor is charged will also be stored. When the circuit is shut down or disconnected, the capacitor will release the stored electrical energy, and the capacitor will discharge slowly through the resistor, thereby realizing the storage and release of electrical energy, and the data in the temporary memory will not be disordered due to the resistor discharging too quickly.

[0021] The output end of the card control setting unit is electrically connected to the input end of the analysis unit, the output end of the analysis unit is electrically connected to the input end of the data analysis unit, and the output end of the visual sensor is electrically connected to the input end of the data analysis unit; The output end of the temporary memory is electrically connected to the input end of the parsing unit and the card control setting unit. The test data exported by the visual sensor and the voltage circuit test platform in the test machine are recorded and numbered through the test data unit. The test data are entered into the temporary memory for temporary archiving, and basic feedback is given to the card control setting unit. The basic feedback includes brief information about the image recorded by the visual sensor and the voltage circuit test data.

[0022] The output ends of the card control setting unit and the data analysis unit are electrically connected to the input end of the shutdown unit, and the output ends of the card control setting unit, the data analysis unit and the shutdown unit are electrically connected to the input end of the alarm unit; The card control setting unit can set the card control rules of the product in advance. The test data unit enters the numbered detailed data into the parsing unit. The parsing unit can parse the acquired data and store it in the database. The data analysis unit compares the detailed data with the data in the product database corresponding to the card control rule analysis, and performs appearance verification on the data recorded by the visual sensor in the card control setting unit. After comparing the card control rules in the data analysis unit and triggering the defective product information, the chip is imported into the return unit and enters the test machine for a second review. If the chip that triggers the card control rule still appears after the second review, the alarm unit sends an email to notify the relevant department, and the email shows Display information: machine, product, time, triggering rules and other information. When the test data unit is stored, if there is data abnormality, data interruption or shutdown, the return unit will be triggered, and the chip being tested in the test machine will be ejected and retested. Through this system, multiple comparisons and data recording will be performed, which will trigger the shutdown unit and the alarm unit. The system can realize the real-time shutdown function when it finds an abnormality, and stop the abnormality at the current time, reducing the possibility of data delay. When the equipment is shut down, the good chips will be stuck, and the defective chips will enter the finished product collection channel, resulting in an increase in the defective rate, reducing the spread of abnormalities, and reducing the energy invested in subsequent investigations, and minimizing losses.

[0023] A voltage blocker is provided in the test machine. After the shutdown unit takes effect, the voltage blocker will discharge the chip being tested in the equipment to avoid breakdown after power is stored. The shutdown resistor in the temporary memory will play a role and store the data in the temporary memory into the database of the analysis unit. When the card control setting unit specifies the card control rules for the analysis unit, the chip being tested in the test machine can also be pushed out through the return unit for retesting. The data analysis unit compares the detailed data after the test data unit number with the card control rules and the visual data imported into the temporary memory. When the error value exceeds the threshold, the chip will be pushed out and recorded. If the error value still exceeds the threshold after more than two rechecks, the shutdown unit and the alarm unit will be triggered, reducing the possible errors caused by multi-angle entry of the chip, and performing multiple comparisons on multiple angles to avoid the waste of finished chips caused by misdetection due to abnormal installation angles during testing, and the increase of defective rate due to misdetection of defective chips.

[0024] The electrical components mentioned in this article are all connected to an external main controller and 220V mains electricity, and the main controller can be a conventional known device for controlling a computer or the like.

[0025] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0026] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A test abnormality real-time shutdown system, comprising a test machine, characterized in that: The output end of the test machine is electrically connected to the input end of the test data unit, the output end of the test data unit is electrically connected to the analysis unit, the test machine includes a voltage circuit test and a visual sensor, and the test machine is provided with a physical interface and a multi-angle adjustment platform; The output end of the card control setting unit is electrically connected to the input end of the analysis unit, the output end of the analysis unit is electrically connected to the input end of the data analysis unit, and the output end of the visual sensor is electrically connected to the input end of the data analysis unit; The output ends of the card control setting unit and the data analysis unit are electrically connected to the input end of the shutdown unit, and the output ends of the card control setting unit, the data analysis unit and the shutdown unit are electrically connected to the input end of the alarm unit.

2. A test abnormality real-time shutdown system according to claim 1, characterized in that: The test machine further comprises a voltage blocker, the output end of the test machine is electrically connected to the input end of the temporary memory, and a shutdown resistor can be provided in the temporary memory to temporarily supply power to the temporary memory.

3. A test abnormality real-time shutdown system according to claim 1, characterized in that: The output end of the temporary memory is electrically connected to the input end of the parsing unit and the card control setting unit. The test data exported by the visual sensor and the voltage circuit test platform in the test machine are recorded and numbered through the test data unit. The test data are entered into the temporary memory for temporary archiving, and basic feedback is provided to the card control setting unit. The basic feedback includes brief information about the image recorded by the visual sensor and the voltage circuit test data.

4. The test abnormality real-time shutdown system according to claim 1, characterized in that: The card control setting unit can set the card control rules of the product in advance, and the test data unit can enter the numbered detailed data into the parsing unit, and the parsing unit can parse the acquired data and store it in a database.

5. The test abnormality real-time shutdown system according to claim 1, characterized in that: The data analysis unit compares the detailed data with the data in the product database corresponding to the card control rule analysis, and performs appearance verification on the data recorded by the visual sensor in the card control setting unit.

6. The test abnormality real-time shutdown system according to claim 1, characterized in that: After the card control rules are compared in the data analysis unit and the defective product information is triggered, the chip is introduced into the return unit and enters the test machine for secondary review.

7. The test abnormality real-time shutdown system according to claim 1, characterized in that: When the chip that triggers the card control rule still appears after the second review, the alarm unit sends an email to notify the relevant department, and the email displays information such as the machine, product, time, and triggered rules.

8. The test abnormality real-time shutdown system according to claim 1, characterized in that: The test machine is provided with a voltage blocker. After the shutdown unit takes effect, the voltage blocker will discharge the chip being tested in the device to avoid breakdown after power is stored. The shutdown resistor in the temporary memory plays a role and stores the data in the temporary memory into the database of the analysis unit.

9. The test abnormality real-time shutdown system according to claim 1, characterized in that: If data anomalies, data interruptions or shutdowns occur during storage in the test data unit, the return unit will be triggered, and the chip being tested in the test machine will be ejected and retested.

10. The test abnormality real-time shutdown system according to claim 1, characterized in that: When the card control setting unit specifies the card control rules to the analysis unit, the chip being tested in the test machine can also be pushed out through the return unit and retested, and the data analysis unit compares the detailed data after the test data unit number with the card control rules and the visual data imported into the temporary memory. When the error value exceeds the threshold, the chip will be pushed out and recorded. If the error value still exceeds the threshold after more than two rechecks, the shutdown unit and the alarm unit will be triggered.

Images