Exposure method of semiconductor pattern
By using the double exposure method to form the splicing pattern on super-large grains, the problem of the super-large grain area exceeding the photomask range is solved, and the ability to form various sized component patterns on super-large grains is realized.
Patent Information
- Application Number
- CN202311243129.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-25
- Publication Date
- 2025-03-25
AI Technical Summary
While increasing the grain area, if the grain area exceeds the limit value of the photomask range in the exposure step, it is impossible to form a pattern outside the exposure range, which limits the formation of components and the development of large-scale grain technology.
Using a double exposure method, a splicing pattern is formed on the super-large grains, a pattern is formed in different regions of the substrate through the first and second photomasks, and the patterns are connected at the junction to achieve splicing.
Without changing the existing production process environment, component patterns of various sizes can be simply formed on super-large grains to meet the component size requirements of super-large grains.
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Figure CN119689786A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a pattern on an ultra-large die. Background Art
[0002] With the advancement of semiconductor manufacturing technology, the size of components that can be accommodated in a unit area of semiconductor components is getting smaller and smaller, and the component density is getting higher and higher. At the same time, the size of the die is gradually increasing to accommodate more components. However, while increasing the die area, if the die area exceeds the limit of the photomask range in the exposure step, it will not be possible to form a pattern outside the exposure range, which will also limit the formation of components and hinder the development of large die technology.
[0003] Therefore, a method for exposing a semiconductor pattern is needed to solve the above problems. Summary of the invention
[0004] The present invention provides an exposure method for a semiconductor pattern, comprising providing a substrate, performing a first exposure step with a first photomask to form a first pattern in a first area on the substrate, and performing a second exposure step with a second photomask to form a second pattern in a second area on the substrate, wherein the first pattern and the second pattern are in contact with each other, and at a junction, the first pattern and the second pattern are aligned with each other.
[0005] The present invention is characterized in that a splicing pattern is formed on a super-large grain by a double exposure method to meet the component size requirements of the super-large grain. The difference between the present invention and the double exposure in the existing steps is that the formed patterns will be connected to each other and can be spliced to form a larger or longer pattern. Therefore, component patterns of various sizes can be simply formed on the super-large grain without changing the existing manufacturing process environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 3 is a schematic diagram of the process structure of the first preferred embodiment of the present invention, wherein a top view of forming a pattern on a die is drawn;
[0007] Figures 4 to 5 FIG. 1 is a schematic diagram of a process structure of a second preferred embodiment of the present invention, wherein a top view of forming a pattern on a die is depicted.
[0008] Main component symbols
[0009] 10: Base (grain)
[0010] 12: Component pattern
[0011] 14: Wire pattern
[0012] 14A: Wire pattern
[0013] 14B: Conductor pattern
[0014] A: First area
[0015] B: Second Area
[0016] C: Repeated exposure area (area)
[0017] E1: First side
[0018] E2: Second side
[0019] E3: The Third Side
[0020] E4: The fourth side
[0021] I: Boundary Line DETAILED DESCRIPTION
[0022] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.
[0023] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.
[0024] Please refer to Figures 1 to 3 , Figures 1 to 3 A schematic diagram of the process structure of the first preferred embodiment of the present invention is shown, wherein a top view of forming a pattern on a die is shown. Figure 1 As shown, a die 10 is provided, and the die 10 includes a first region A and a second region B arranged adjacent to each other, but the first region A and the second region B do not overlap each other. The die may be formed by a wafer through a cutting process. Generally speaking, the entire wafer is first placed in a semiconductor manufacturing process machine (such as an exposure and development machine or a deposition machine), and after various required material layers are formed on the surface of the wafer, the wafer is cut into multiple die. The present invention focuses on describing the pattern on a single die. In order to clearly show the characteristics of the present invention, Figure 1 Only a single grain 10 is shown in FIG. 1 , but it is understandable that Figure 1 The die in the wafer may not have gone through the sawing step and are therefore still part of the wafer rather than individual die.
[0025] Please continue to refer to Figure 1 As the manufacturing process advances, more components may be placed in the same die. For example, for display die, it is necessary to form a drive circuit and a light-emitting element array on the die, so larger and larger die will be used. However, the size of the die may exceed the maximum area that the exposure machine can expose in a single area, so the size of the pattern formed on the die is also limited. In more detail, the wafer contains multiple areas preferably arranged in an array, and each area is cut into pieces in the subsequent steps. Figure 1 The die shown. When the exposure machine exposes the entire wafer, it also performs the same exposure steps in each area. At this time, the area that the exposure machine can expose in a single area is usually called a shot. When the size of the die is larger than the shot of the exposure machine, it will be impossible to form the required pattern on the die in a single exposure step.
[0026] Referring to the current production technology, Figure 1 For example, Figure 1 The shot area of the exposure machine used in the experiment is about 26 mm × 33 mm, which is equal to Figure 1 The sizes of the first area A and the second area B are indicated in . That is to say, the areas of the first area A and the second area B are the same and are adjacent to each other. In addition, the area of the grain 10 is preferably more than twice that of the first area A or the second area B. However, it is worth noting that the grain 10 described in the present invention is different from, for example, a splicing substrate used for a display panel. Specifically, the area of the grain 10 described in the present invention is only several times the area of the shot, while the area of the substrate used for splicing in the display panel is hundreds or thousands of times the area of the shot. Therefore, the ratio of the area of the grain 10 to the shot area in the present invention is approximately less than 5, and the ratio is preferably between 2 and 3.
[0027] Therefore, Figure 1 Taking the die 10 as an example, a single exposure can only form the desired pattern within the size range of the first area A or the second area B, but it is impossible to form the desired pattern on the entire die 10 by a single exposure. Therefore, the present invention provides a method for forming a pattern, which forms a pattern across regions in a splicing manner to meet the needs of a die with a larger area, as shown in the following paragraphs.
[0028] Please continue to refer to Figure 2 and Figure 3 ,exist Figure 2 In the embodiment, the required element patterns 12 are formed in the first region A and the second region B respectively. The element patterns 12 described here are structures such as transistors, resistors, capacitors, etc., but are not limited thereto. It is worth noting that Figure 2The device patterns 12 required for the first region A and the second region B may be formed by separate processes such as exposure, development, etching, and deposition. The above-mentioned steps such as exposure, development, and deposition may include multiple steps and may be repeated. As mentioned above, since the size of the grain 10 is larger than the maximum exposure range (shot) of the exposure machine, it takes at least two exposures in total to form the device patterns included in the first region A and the second region B.
[0029] like Figure 3 As shown, a conductor structure is formed to connect some of the device patterns 12 to each other. A portion of the conductor pattern 14 connects the device patterns 12 in the first area A or the second area B to each other, while another portion of the conductor pattern 14 connects across the area, for example Figure 3 The conductor pattern 14A and the conductor pattern 14B marked in the first area A and the second area B extend to the boundary line I between the two areas and contact and connect with each other. In this way, even if there is a component that exceeds the size of the exposure range to be formed (such as an extra-long conductor pattern), it can be completed by the method provided by the present invention of performing two exposures and then splicing the patterns together.
[0030] In this embodiment, the conductor pattern 14A and the conductor pattern 14B connected to the adjacent regions are also aligned with each other. More specifically, the conductor pattern 14A has a first side E1 and a second side E2, and the conductor pattern 14B has a third side E3 and a fourth side E4, and the first side E1 and the third side E3 are aligned with each other in a first direction (such as a horizontal direction, but not limited thereto), and the second side E2 and the fourth side E4 are also aligned with each other in the first direction (such as a horizontal direction, but not limited thereto).
[0031] Please refer to Figures 4 to 5 , Figures 4 to 5 A schematic diagram of the process structure of the second preferred embodiment of the present invention is shown, wherein a top view of forming a pattern on a die is shown. This embodiment also provides a die 10, and the die 10 also includes a first region A and a second region B. The definitions of the die 10, the first region A, and the second region B are the same as those in the above embodiment, and are not repeated here. The difference between this embodiment and the above embodiment is that the first region A and the second region B partially overlap each other, and are defined as Figure 4 The area of the region C accounts for less than 20% of the area of the first region A or the second region B, preferably less than 10%, that is, the first region A and the second region B only overlap with each other in a small part, and most of the rest do not overlap.
[0032] Then as Figure 5As shown, after the required element pattern 12 is formed in the first area A and the second area B, the conductor pattern (including the conductor pattern 14, the conductor pattern 14A and the conductor pattern 14B) is formed. The conductor pattern 14A and the conductor pattern 14B are formed in the first area A and the second area B respectively, and the two overlap each other in the area C. In other words, the conductor pattern 14A and the conductor pattern 14B are connected to each other.
[0033] In this embodiment, since the first area A and the second area B partially overlap, the conductor pattern 14A and the conductor pattern 14B can be truly connected. Compared with the above-mentioned first embodiment, this embodiment can avoid the situation where the conductor pattern 14A and the conductor pattern 14B are not connected due to incomplete exposure near the boundary line I.
[0034] It is also worth noting that the applicant has found that the line width of the conductive pattern in area C may be slightly different from the line width of other conductive patterns not located in area C due to the two repeated exposures, affected by the manufacturing process. Generally, the line width of the pattern in area C may be smaller than the line width of the pattern in other areas. Therefore, preferably, before performing the two exposure steps, the present embodiment first performs an optical proximity correction (OPC) step to adjust the line width of the conductive pattern in different areas to improve the quality of the manufacturing process.
[0035] It is also worth noting that although the conductor patterns 14A and 14B are used as components that span across regions in the above-mentioned embodiment, the present invention can also use other types of component patterns other than conductors to span across two regions. For example, the size of components such as gate structures or fin structures is longer and may exceed the range of a single exposure (shot). It is also possible to form a component pattern that exceeds the range of a single exposure (shot) through the double exposure and splicing method provided by the present invention.
[0036] The present invention forms patterns in the first area A and the second area B on the same die 10 by a double exposure method, and then uses a splicing method to splice the patterns that need to cross the two areas. The difference from the double exposure (double patterning) used in the prior art is that the double exposure technology of the prior art usually aims to reduce the density of component patterns in a single exposure, so a pattern is formed at different positions in the same area by two exposure steps. Please note that the area of the same area mentioned here is usually smaller than the single exposure range of the exposure machine (i.e., the above-mentioned shot). In other words, in the existing double exposure technology, the range of the two exposure production processes is basically completely or mostly overlapped (approximately more than 90% of the range overlaps). The range of the two exposures in the present invention (the first area A and the second area B) may be only adjacent but not completely overlapping (such as Figure 3), or only a small overlap (such as Figure 5 embodiment shown).
[0037] In addition, another difference between the present invention and the existing double exposure technology is that the purpose of the existing double exposure technology is to reduce the density of components, so the component patterns formed usually do not contact each other to avoid mutual interference or short circuit. For example, multiple closely adjacent patterns (such as parallel conductive lines or contact pillars, but not limited to these) are formed in the same area. These patterns are preferably independent of each other and do not contact each other. The purpose of the present invention is to splice patterns in different areas, so a part of the pattern finally formed will cross two areas and contact each other.
[0038] In summary, the present invention provides an exposure method for a semiconductor pattern, comprising providing a substrate (e.g., a wafer), performing a first exposure step using a first photomask to form a first pattern (including a component pattern 12, a conductor pattern 14, and a conductor pattern 14A formed in the first region A, specifically the conductor pattern 14A) in a first region (first region A) on the substrate, and performing a second exposure step using a second photomask to form a second pattern (including a component pattern 12, a conductor pattern 14, and a conductor pattern 14B formed in the second region B, specifically the conductor pattern 14B) in a second region (second region B) on the substrate, wherein the first pattern 14A and the second pattern 14B are in contact with each other, and at a boundary line I, the first pattern 14A and the second pattern 14B are aligned with each other.
[0039] In some embodiments of the present invention, there is also a cutting step for cutting the substrate into a plurality of dies 10, wherein the size of each of the dies 10 is larger than an area of a first region A, and the first region A is equal to a single maximum exposure range (i.e., shot) of the first photomask.
[0040] In some embodiments of the present invention, the first region A and the second region B have the same area, and the second region B is equal to a single maximum exposure range (ie, shot) of the second photomask.
[0041] In some embodiments of the present invention, the area of the first region A is 26 mm×33 mm.
[0042] In some embodiments of the present invention, the size of each of the grains 10 is larger than the area of the first region A.
[0043] In some embodiments of the present invention, the first pattern 14A includes a first edge E1 and a second edge E2 , and the second pattern 14B includes a third edge E3 and a fourth edge E4 .
[0044] In some embodiments of the present invention, the first side E1 and the third side E3 are in contact with each other and are arranged along the same direction, and the second side E2 and the fourth side E4 are in contact with each other and are arranged along the same direction.
[0045] In some embodiments of the present invention, the first pattern 14A and the second pattern 14B partially overlap, and the overlapping portion is defined as a pattern overlapping portion (ie, the overlapping portion of the conductive line pattern 14A and the conductive line pattern 14B in region C).
[0046] In some embodiments of the present invention, an optical proximity correction (OPC) step is further included to adjust an exposure critical dimension of the first pattern 14A and the second pattern 14B in the pattern overlap portion.
[0047] In some embodiments of the present invention, the first region A and the second region B partially overlap, and the overlapping range is defined as a repeated exposure area (ie, region C).
[0048] In some embodiments of the present invention, a ratio of an area of the repeated exposure zone C to an area of the first region A is less than 0.1.
[0049] In some embodiments of the present invention, the first pattern 14A and the second pattern 14B are in contact with each other, but the first pattern 14A and the second pattern 14B do not overlap each other (eg, Figure 3 shown).
[0050] In some embodiments of the present invention, the first region A does not overlap with the second region B, and the first region A is aligned with the second region B (e.g. Figure 1 (shown)
[0051] In some embodiments of the present invention, both the first pattern 14A and the second pattern 14B include conductive line patterns.
[0052] In some embodiments of the present invention, after a first exposure step is performed using a first photomask, a plurality of first element patterns (element patterns 12 formed in the first area A) are formed on the substrate in the first area A, and after a second exposure step is performed using a second photomask, a plurality of second element patterns (element patterns 12 formed in the second area B) are formed on the substrate in the second area.
[0053] In some embodiments of the present invention, the device patterns 12 are formed in the first region A, wherein each first device pattern and each second device pattern are not in contact with each other.
[0054] In some embodiments of the present invention, a ratio of the area of the die 10 to the area of the first region A is less than 5.
[0055] The present invention is characterized in that a splicing pattern is formed on a super-large grain by a double exposure method to meet the component size requirements of the super-large grain. The difference between the present invention and the double exposure in the existing steps is that the formed patterns will be connected to each other and can be spliced to form a larger or longer pattern. Therefore, component patterns of various sizes can be simply formed on the super-large grain without changing the existing manufacturing process environment.
[0056] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for exposing a semiconductor pattern, comprising: providing a substrate; Performing a first exposure step with a first photomask to form a first pattern in a first area on the substrate; as well as A second exposure step is performed using a second photomask to form a second pattern in a second area on the substrate, wherein the first pattern and the second pattern are in contact with each other and aligned with each other at the interface.
2. The exposure method of a semiconductor pattern as described in claim 1 further comprises a cutting step, wherein the substrate is cut into a plurality of dies, wherein the size of each die is larger than the area of the first region, and the first region is equal to the maximum single exposure range of the first photomask. 3 . The exposure method of a semiconductor pattern as claimed in claim 2 , wherein the first region and the second region have the same area, and the second region is equal to a single maximum exposure range of the second photomask. 4 . The exposure method of a semiconductor pattern as claimed in claim 3 , wherein an area of the first region is 26 mm×33 mm. 5 . The exposure method of a semiconductor pattern as claimed in claim 3 , wherein a size of each grain is larger than an area of the first region. 6 . The exposure method of a semiconductor pattern as claimed in claim 1 , wherein the first pattern includes a first side and a second side, and the second pattern includes a third side and a fourth side. 7 . The exposure method of a semiconductor pattern as claimed in claim 1 , wherein the first side and the third side are in contact with each other and arranged along the same direction, and the second side and the fourth side are in contact with each other and arranged along the same direction. 8 . The exposure method of a semiconductor pattern as claimed in claim 1 , wherein the first pattern and the second pattern partially overlap, and the overlapping portion is defined as a pattern overlapping portion.
9. The semiconductor pattern exposure method according to claim 8, further comprising an optical correction step of adjusting an exposure critical dimension of the first pattern and the second pattern in the pattern overlap portion. 10 . The exposure method of a semiconductor pattern as claimed in claim 8 , wherein the first region and the second region partially overlap, and the overlapping range is defined as a repeated exposure area. 11 . The exposure method of a semiconductor pattern as claimed in claim 10 , wherein a ratio of an area of the repeated exposure region to an area of the first region is less than 0.
1. 12 . The exposure method of a semiconductor pattern as claimed in claim 1 , wherein the first pattern and the second pattern are in contact with each other, but the first pattern and the second pattern do not overlap each other. 13 . The exposure method of a semiconductor pattern as claimed in claim 12 , wherein the first region does not overlap with the second region, and the first region is aligned with the second region. 14 . The exposure method of a semiconductor pattern as claimed in claim 1 , wherein both the first pattern and the second pattern include a conductive line pattern.
15. The exposure method of a semiconductor pattern as described in claim 1, wherein after the first exposure step is performed using the first photomask, a plurality of first device patterns are formed on the substrate in the first region, and after the second exposure step is performed using the second photomask, a plurality of second device patterns are formed on the substrate in the second region. 16 . The exposure method of a semiconductor pattern as claimed in claim 15 , wherein each of the first device patterns and each of the second device patterns are not in contact with each other. 17 . The exposure method of a semiconductor pattern as claimed in claim 2 , wherein a ratio of an area of the grain to an area of the first region is less than 5.