Low dropout regulator without off-chip capacitor, power supply circuit and electronic system

Abstract

The invention provides a low dropout linear regulator without an off-chip capacitor, which comprises a power tube, a feedback resistance network, an error amplifier, a load switching module, a switching frequency detection module and a power consumption / response control module, and is characterized in that the load switching module is connected with a second end of the power tube and is used for performing switching control of an access load according to a switching control signal; the switching frequency detection module is used for detecting the switching frequency of the access load according to the switching control signal and generating a first power control signal according to the speed of the switching frequency; and the power consumption / response control module is connected with the error amplifier and the output end of the switching frequency detection module, and is used for adjusting the working current of the power consumption / response control module according to the first power control signal, and performing output adjustment by controlling a power tube under different working currents. By means of the low-dropout linear voltage regulator without the off-chip capacitor, the problems that an existing low-dropout linear voltage regulator without the off-chip capacitor is disturbed in output and large in power consumption are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a low voltage difference linear regulator without an off-chip capacitor, a power supply circuit and an electronic system. Background Art

[0002] The integration of the system on chip (SOC) inside portable communication devices, including multiple circuit modules such as analog, digital and RF, is getting higher and higher. However, SOC is susceptible to interference from noise from high-frequency digital switches, RF modules, etc. The application of low dropout linear regulator (Low Dropout Regulator, LDO) can reduce the impact of environmental noise on the performance of sensitive circuits in SOC.

[0003] The main pole of a traditional LDO is generally set at the output end, which requires connecting an off-chip capacitor of the microfarad level at the output end and compensating the gate pole of the power tube with the equivalent series resistance to improve the transient response speed of the LDO and improve the circuit stability. If there is no off-chip capacitor at the output end or the ESR parameters of the off-chip capacitor do not meet the requirements, the LDO will not respond normally or even lock incorrectly; moreover, the use of off-chip capacitors not only occupies a circuit pin, but also increases the component cost of the application solution.

[0004] Some LDO solutions without external capacitors cannot respond to the instantaneous change of output voltage in time and cause output disturbance due to the limited loop bandwidth of adjusting the output voltage. This problem is more prominent in multi-carrier modulation systems when the multi-carrier modulation signal to be transmitted has a high peak average power ratio (PAPR). In order to achieve fast response and improve load regulation, LDO solutions without external capacitors use higher operating currents in the error amplifier and driver stage, but this will generate greater power consumption, which is not conducive to reducing the energy consumption of portable products during operation.

[0005] In view of this, designing an LDO without external capacitors that has both high energy efficiency and low disturbance is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a low voltage dropout linear regulator, a power supply circuit and an electronic system without external capacitors, so as to solve the problems of output disturbance and high power consumption in the existing LDO solutions without external capacitors.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a low voltage drop linear regulator without an off-chip capacitor, the low voltage drop linear regulator comprising:

[0008] Power tube, feedback resistor network, error amplifier, load switching module, switching frequency detection module and power consumption / response control module, wherein:

[0009] The control end of the power tube is connected to the output end of the power consumption / response control module, the first end is connected to the input power supply, and the second end is grounded through the feedback resistor network to generate an output voltage, wherein the feedback resistor network divides the output voltage to generate a feedback voltage;

[0010] The first input terminal of the error amplifier is connected to the reference voltage, and the second input terminal is connected to the feedback voltage;

[0011] The load switching module is connected to the second end of the power tube and is used to perform switching control of the access load according to the switching control signal;

[0012] The switching frequency detection module receives the switching control signal, is used to detect the switching frequency of the connected load according to the switching control signal, and generate a first power control signal according to the speed of the switching frequency;

[0013] The power consumption / response control module is connected to the output ends of the error amplifier and the switching frequency detection module, and is used to adjust the operating current of the power consumption / response control module according to the first power control signal, and to perform output regulation by controlling the power tube under different operating currents.

[0014] Optionally, the load switching module includes: a multi-way selection switch and at least two load units; the control end of the multi-way selection switch is connected to the switching control signal, the common end is connected to the second end of the power tube, and each selection end is correspondingly connected to the first end of each load unit; the second end of each load unit is grounded.

[0015] Optionally, the switching frequency detection module includes a first pulse shaping unit and a signal generating unit, wherein:

[0016] The first pulse shaping unit is used for performing pulse stretching processing on the pulse in the switching control signal to obtain a first rectangular pulse;

[0017] The signal generating unit is connected to the output end of the first pulse shaping unit, and is used for converting the first rectangular pulse into a first analog voltage as the first power control signal by capacitor charging.

[0018] Optionally, the first pulse shaping unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a discharge tube, a first comparator, a second comparator, an RS trigger, a NAND gate and an inverter; the first resistor and the first capacitor are connected in series between the working voltage and the ground; the second resistor, the third resistor and the fourth resistor are connected in series between the working voltage and the ground; the in-phase input terminal of the first comparator is grounded through the second capacitor and connected to the connection node of the second resistor and the third resistor, the inverting input terminal is connected to the connection node of the first resistor and the first capacitor, and the output terminal is connected to the reset terminal of the RS trigger ; The non-inverting input terminal of the second comparator is connected to the switching control signal, the inverting input terminal is connected to the connection node of the third resistor and the fourth resistor, and the output terminal is connected to the set terminal of the RS trigger; the reset terminal of the RS trigger is connected to the inverted signal of the reset signal, and the output terminal is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the inverted signal of the reset signal, and the output terminal is connected to the input terminal of the inverter and connected to the gate of the discharge tube through the fifth resistor; the output terminal of the inverter serves as the output terminal of the first pulse shaping unit; the drain of the discharge tube is connected to the connection node of the first resistor and the first capacitor, and the source is grounded;

[0019] And / or, the signal generating unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third capacitor; the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the second NMOS tube are connected in series between the working voltage and the ground, the gate ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the second NMOS tube are connected to their respective drain ends, the gate end of the first NMOS tube is connected to the output end of the first pulse shaping unit, and the source end of the first NMOS tube is grounded via the third capacitor and serves as the output end of the signal generating unit.

[0020] Optionally, the power consumption / response control module includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first operational amplifier and a sixth resistor; the gate end of the fourth PMOS tube is connected to the output end of the error amplifier, the source end is connected to the output voltage, and the drain end is connected to the drain end of the third NMOS tube and the source end of the sixth NMOS tube; the gate ends of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected to each other and connected to the inverting input end of the first operational amplifier, and the third NMOS tube, the fourth NMOS tube and The source end of the fifth NMOS tube is grounded, the drain end of the fourth NMOS tube is connected to its gate end, and the drain end of the fifth NMOS tube is connected to the drain end of the fifth PMOS tube; the gate end of the sixth NMOS tube is connected to the bias voltage, and the drain end is connected to the drain end of the sixth PMOS tube and serves as the output end of the power consumption / response control module; the gate end of the fifth PMOS tube is connected to its drain end and connected to the gate end of the sixth PMOS tube, and the source ends of the fifth PMOS tube and the sixth PMOS tube are connected to the input power supply; the non-inverting input end of the first operational amplifier is connected to the output end of the load switching module, and the output end is connected to its inverting input end through the sixth resistor.

[0021] Optionally, the power consumption / response control module further includes: a fourth capacitor and a seventh resistor; the fourth capacitor and the seventh resistor are connected in series between the gate terminal and the drain terminal of the fourth PMOS tube.

[0022] Optionally, the low voltage dropout linear regulator further includes: a peak-to-average ratio detection module and a comprehensive control module, wherein:

[0023] The peak-to-average ratio detection module is used to detect the peak-to-average ratio of the multi-carrier modulation signal, and generate a second power control signal according to the number of times the peak-to-average ratio exceeds a set value;

[0024] The integrated control module is connected to the output ends of the switching frequency detection module and the peak-to-average ratio detection module, and is used to generate a total power control signal according to the first power control signal and the second power control signal;

[0025] The power consumption / response control module adjusts the operating current according to the total power control signal, and performs output regulation by controlling the power tube under different operating currents.

[0026] Optionally, the peak-to-average ratio detection module includes: a comparison unit, a second pulse shaping unit and a low-pass filtering unit, wherein:

[0027] The comparison unit is used to compare the peak voltage of the multi-carrier modulation signal with a set voltage, and generate a comparison pulse when the peak voltage is greater than the set voltage;

[0028] The second pulse shaping unit is connected to the output end of the comparison unit, and is used for performing pulse stretching processing on the comparison pulse to generate a second rectangular pulse;

[0029] The low-pass filtering unit is connected to the output end of the second pulse shaping unit, and is used for converting the second rectangular pulse into a second analog voltage as the second power control signal through low-pass filtering.

[0030] Optionally, when the switching frequency detection module includes the first pulse shaping unit, the first pulse shaping unit and the second pulse shaping unit have the same structure.

[0031] Optionally, the integrated control module includes: a second operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; the non-inverting input terminal of the second operational amplifier is grounded via the eighth resistor, the inverting input terminal is connected to the output terminal of the switching frequency detection module via the ninth resistor, and is connected to the output terminal of the peak-to-average ratio detection module via the tenth resistor, and the output terminal is connected to its inverting input terminal via the eleventh resistor and serves as the output terminal of the integrated control module.

[0032] The present invention further provides a power supply circuit, which includes the low voltage dropout linear regulator as described in any one of the above items.

[0033] The present invention also provides an electronic system, which includes the power supply circuit as described above.

[0034] As described above, the low voltage difference linear regulator, power supply circuit and electronic system without external capacitors of the present invention adjusts the working current of the power consumption / response control module by the switching frequency of the connected load, or even the number of times the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value; and the working current of the power consumption / response control module is related to the response speed of the LDO, and the static power consumption of the LDO is adjusted by adjusting the working current of the power consumption / response control module, so that the LDO has a lower average working energy consumption. In the present invention, when the switching frequency of the connected load is fast or the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value many times, the working current of the power consumption / response control module is large, and the response speed is improved by increasing the loop bandwidth; when the switching frequency of the connected load is slow and the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value few times, the working current of the power consumption / response control module is small, and the overall energy efficiency is improved by reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of a low voltage dropout linear regulator in the first embodiment.

[0036] Figure 2It is a schematic diagram of the structure of the switching frequency detection module in the first embodiment.

[0037] Figure 3 Shown is a relevant signal waveform diagram of the first pulse shaping unit in Example 1.

[0038] Figure 4 Shown is a schematic diagram of the structure of the power consumption / response control module in the first embodiment.

[0039] Figure 5 It is a schematic diagram of the structure of a low voltage dropout linear regulator in the second embodiment.

[0040] Figure 6 It is a schematic diagram of the structure of the peak-to-average ratio detection module in the second embodiment.

[0041] Figure 7 Shown is a relevant signal waveform diagram of the peak-to-average ratio detection module in Example 2.

[0042] Figure 8 It shows a structural diagram of the integrated control module in the second embodiment.

[0043] Component number description

[0044] 100 Feedback resistor network

[0045] 200 Error Amplifier

[0046] 300 Load Switching Module

[0047] 400 Switching frequency detection module

[0048] 410 First pulse shaping unit

[0049] 411 First Comparator

[0050] 412 Second comparator

[0051] 413 RS Flip Flop

[0052] 414 NAND Gate

[0053] 415 Inverter

[0054] 420 signal generation unit

[0055] 500 Power consumption / response control module

[0056] 600 Bandgap Reference Module

[0057] 700 Peak-to-Average Ratio Detection Module

[0058] 710 Comparison unit

[0059] 720 Second pulse shaping unit

[0060] 730 Low-pass filter unit

[0061] 800 Integrated Control Module DETAILED DESCRIPTION

[0062] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0063] See also Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0064] Embodiment 1

[0065] like Figure 1 As shown, this embodiment provides a low-dropout linear regulator (LDO) without off-chip capacitors, including a power tube M0, a feedback resistor network 100, an error amplifier 200, a load switching module 300, a switching frequency detection module 400 and a power consumption / response control module 500; further, it also includes a bandgap reference module 600 and a driving module (not shown in the figure). Among them:

[0066] The control end of the power tube M0 is connected to the output end of the power consumption / response control module 500, the first end is connected to the input power supply VIN, and the second end is grounded through the feedback resistor network 100 to generate an output voltage VOUT, wherein the feedback resistor network 100 divides the output voltage VOUT to generate a feedback voltage VFB.

[0067] Specifically, the power tube M0 is an output adjustment tube, and the output voltage VOUT is adjusted by controlling its conduction degree through the output of the power consumption / response control module 500, so that the output voltage VOUT is stable; wherein, the power tube M0 includes at least one of a PMOS tube, an NMOS tube, a PNP transistor, and an NPN transistor. When designing the circuit, the selection should be made in combination with actual needs; for different types of devices, the circuit should be appropriately adjusted for easy driving.

[0068] The figure shows that the power tube M0 is an enhanced PMOS tube, the gate end of the PMOS tube is connected to the output end of the power consumption / response control module 500, the source end is connected to the input power supply VIN, the drain end is grounded through the feedback resistor network 100 and generates an output voltage VOUT; correspondingly, the non-inverting input end of the error amplifier 200 is connected to the reference voltage VREF, and the inverting input end is connected to the feedback voltage VFB;

[0069] For the solution without a driving module, if the power tube M0 is replaced by an NMOS tube from a PMOS tube, in order to drive the power tube, the two input terminals of the error amplifier 200 should be adjusted, that is, the positive input terminal of the error amplifier 200 is connected to the feedback voltage VFB, and the negative input terminal is connected to the reference voltage VREF;

[0070] For the scheme of setting a driving module, if the power tube M0 is replaced by an NMOS tube from a PMOS tube, in addition to the above adjustment method, it can also be achieved by inverting the phase of the output of the driving module without adjusting the input end of the error amplifier 200.

[0071] Of course, PNP transistors can refer to PMOS tubes, and NPN transistors can refer to NMOS tubes. However, when using transistors as power tubes, the input voltage VIN is lower than that of MOS tubes. In practical applications, transistors are current-controlled devices, and MOS tubes are voltage-controlled devices. Compared with the two, the static current of MOS tubes is lower; and NMOS tubes require a driving signal higher than the output voltage when working, while PMOS tubes do not have this requirement; therefore, PMOS tubes are generally preferred as power tubes in applications.

[0072] Specifically, the feedback resistor network 100 includes a first feedback resistor RF1 and a second feedback resistor RF2; the first feedback resistor RF1 and the second feedback resistor RF2 are connected in series between the second end of the power tube M0 and the ground, and the connection node of the first feedback resistor RF1 and the second feedback resistor RF2 generates a feedback voltage VFB. It should be noted that the above example only gives a case where two resistors are connected in series for voltage division. In fact, more resistors are connected in series for voltage division.

[0073] The first input terminal of the error amplifier 200 is connected to the reference voltage VREF, and the second input terminal is connected to the feedback voltage VFB, so as to amplify the error between the reference voltage VREF and the feedback voltage VFB and output the error.

[0074] As described above, for different types of power tubes M0, driving can be achieved by adjusting the input end of the error amplifier 200; in this embodiment, taking the power tube M0 as an enhanced PMOS tube as an example, the non-inverting input end of the error amplifier 200 is connected to the reference voltage VREF, and the inverting input end is connected to the feedback voltage VFB.

[0075] Specifically, the error amplifier 200 is implemented by a single-stage amplification structure or a two-stage amplification structure, wherein both the single-stage amplification structure and the two-stage amplification structure can be implemented by an existing known circuit structure, and this embodiment does not limit this. As an optional solution, the error amplifier 200 is implemented by a two-stage amplification structure, so that the error amplifier 200 has a higher signal gain, which is conducive to improving the power supply rejection ratio (PSRR).

[0076] The load switching module 300 is connected to the second end of the power tube M0 and is used for switching control of the access load according to the switching control signal SW.

[0077] Specifically, the load switching module 300 includes a multi-way selection switch K1 and at least two load units 310; the control end of the multi-way selection switch K1 is connected to the switching control signal SW, the common end is connected to the second end of the power tube M0, and each selection end is correspondingly connected to the first end of each load unit 310; the second end of each load unit 310 is grounded. The common end of the multi-way selection switch K1 is controlled to be connected to the corresponding selection end by the switching control signal SW, and the corresponding load unit 310 is connected to the second end of the power tube M0, so as to realize the switching control of the connected load.

[0078] In a possible implementation, the switching control signal SW is a set of binary code values, and the multi-way selection switch K1 is composed of at least two switch devices, wherein the first ends of the switch devices are connected to each other as the common end of the multi-way selection switch K1, and the second ends of the switch devices serve as the selection ends of the multi-way selection switch K1, and the control ends of the switch devices correspond to different bits in the binary code value; when the corresponding bit in the binary code value is a high level, the corresponding switch device is closed, otherwise, the corresponding switch device is opened.

[0079] The switching frequency detection module 400 receives the switching control signal SW, and is used to detect the switching frequency of the connected load according to the switching control signal SW, and generate a first power control signal according to the speed of the switching frequency.

[0080] Specifically, Figure 2 As shown, the switching frequency detection module 400 includes a first pulse shaping unit 410 and a signal generating unit 420. Among them:

[0081] The first pulse shaping unit 410 is used to perform pulse stretching processing on the pulse in the switching control signal SW to obtain a first rectangular pulse, so as to characterize the switching frequency of the connected load according to the density arrangement of the first rectangular pulse; for example, if the first rectangular pulses are arranged more densely, it means that the switching frequency of the connected load is faster, and if the first rectangular pulses are arranged more sparsely, it means that the switching frequency of the connected load is slower.

[0082] As an example, the first pulse shaping unit 410 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a discharge tube VT, a first comparator 411, a second comparator 412, an RS trigger 413, a NAND gate 414 and an inverter 415; the first resistor R1 and the first capacitor C1 are connected in series between the working voltage VCC and the ground; the second resistor R2, the third resistor R3 and the fourth resistor R4 are connected in series between the working voltage VCC and the ground; the in-phase input terminal of the first comparator 411 is grounded through the second capacitor C2 and connected to the connection node of the second resistor R2 and the third resistor R3, the inverting input terminal is connected to the connection node of the first resistor R1 and the first capacitor C1, and the output The output end is connected to the reset end of the RS trigger 413; the non-inverting input end of the second comparator 412 is connected to the switching control signal SW, the inverting input end is connected to the connection node of the third resistor R3 and the fourth resistor R4, and the output end is connected to the set end of the RS trigger 413; the reset end of the RS trigger 413 is connected to the inverted signal R of the reset signal, and the output end is connected to the first input end of the NAND gate 414; the second input end of the NAND gate 414 is connected to the inverted signal R of the reset signal, and the output end is connected to the input end of the inverter 415 and connected to the gate of the discharge tube VT through the fifth resistor R5; the output end of the inverter 415 serves as the output end of the first pulse shaping unit 410; the drain of the discharge tube VT is connected to the connection node of the first resistor R1 and the first capacitor C1, and the source is grounded.

[0083] When the inverted signal R of the clear signal is at a high level: the working voltage VCC charges the first capacitor C1 through the first resistor R1, and when the capacitor voltage rises to the first set threshold value Vth1, the first comparator 411 outputs "0", the output of the RS trigger 413 is set to 0, the NAND gate 414 outputs "1", and the inverter 415 outputs "0"; at the same time, the discharge tube VT is turned on, the first capacitor C1 is discharged through the discharge tube VT, and the circuit enters a steady state. When the pulse in the switching control signal SW arrives, since the potential of the pulse is less than the second set threshold value Vth2 and the second set threshold value Vth2 is less than the first set threshold value Vth1, the second comparator 412 outputs "0", the output of the RS trigger 413 is set to 1, the NAND gate 414 outputs "0", the inverter 415 outputs "1", and the circuit enters a temporary steady state; at the same time, the discharge tube VT is cut off, and the working voltage VCC charges the first capacitor C1 through the first resistor R1. Even if the pulse in the switching control signal SW disappears, the second comparator 412 outputs "1", but the charging continues until the capacitor voltage reaches the first set threshold value Vth1, the first comparator 411 outputs "0", and the circuit enters a steady state again. The relevant signal waveforms are shown as follows: Figure 3 shown.

[0084] The signal generating unit 420 is connected to the output end of the first pulse shaping unit 410 and is used for converting the first rectangular pulse into a first analog voltage V1 as a first power control signal by capacitor charging.

[0085] As an example, the signal generating unit 420 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, a second NMOS transistor NM2 and a third capacitor C3; the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected in series between the operating voltage VCC and the ground, the gate ends of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the second NMOS transistor NM2 are connected to their respective drain ends, the gate end of the first NMOS transistor NM1 is connected to the output end of the first pulse shaping unit 410, and the source end of the first NMOS transistor NM1 is grounded via the third capacitor C3 and serves as the output end of the signal generating unit 420.

[0086] The first rectangular pulse CTL output by the first pulse shaping unit 410 controls the on-time of the first NMOS tube NM1 to control the charging time of the third capacitor C3 by the working voltage VCC, thereby controlling the magnitude of the first analog voltage V1; when the pulses in the switching control signal SW are arranged more densely, the arrangement of the first rectangular pulses obtained after the pulse widening process is also more dense, so that the total charging time of the third capacitor C3 in this time period is increased, and the first analog voltage V1 is increased.

[0087] The power consumption / response control module 500 is connected to the output end of the error amplifier 200 and the switching frequency detection module 400, and is used to adjust the operating current of the power consumption / response control module 500 according to the first power control signal, and to adjust the output by controlling the power tube M0 under different operating currents.

[0088] Specifically, Figure 4As shown, the power consumption / response control module 500 includes: a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a first operational amplifier OP1 and a sixth resistor R6; the gate end of the fourth PMOS transistor PM4 is connected to the output end of the error amplifier 200, the source end is connected to the output voltage VOUT, and the drain end is connected to the drain end of the third NMOS transistor NM3 and the source end of the sixth NMOS transistor NM6; the gate ends of the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are connected to each other and to the inverting input end of the first operational amplifier OP1, the source ends of the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 are grounded, the drain end of the fourth NMOS transistor NM4 is connected to its gate end, and the drain end of the fifth NMOS transistor NM5 is connected to the gate end. The drain end of the NMOS tube NM5 is connected to the drain end of the fifth PMOS tube PM5; the gate end of the sixth NMOS tube NM6 is connected to the bias voltage VB2, and the drain end is connected to the drain end of the sixth PMOS tube PM6 and serves as the output end of the power consumption / response control module 500; the gate end of the fifth PMOS tube PM5 is connected to its drain end and connected to the gate end of the sixth PMOS tube PM6, and the source ends of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are connected to the input power supply VIN; the non-inverting input end of the first operational amplifier OP1 is connected to the output end of the load switching module 400, and the output end is connected to its inverting input end via the sixth resistor R6; wherein, the substrate ends of the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth PMOS tube PM6, the third NMOS tube NM3, the fourth NMOS tube NM4 and the fifth NMOS tube NM5 are connected to their respective source ends, and the substrate end of the sixth NMOS tube NM6 is grounded.

[0089] The third NMOS transistor NM3, the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 form a current mirror structure, and the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 form a current mirror structure, wherein the ratio of the current flowing through the third NMOS transistor NM3 to the current flowing through the fifth NMOS transistor NM5 is P:1, and the ratio of the current flowing through the fifth PMOS transistor PM5 to the current flowing through the sixth PMOS transistor PM6 is 1:Q, and P and Q are both arbitrary values ​​greater than 1;

[0090] Through the virtual short and virtual open principle of the first operational amplifier OP1, the voltages of its two input terminals are made the same; through the first analog voltage V1, the conduction degree of the third NMOS tube NM3 is controlled to control the magnitude of the current flowing through it, thereby controlling the magnitude of the working current of the power consumption / response control module 500, so that the working current of the power consumption / response control module 500 is positively correlated with the switching frequency of the connected load, so that when the switching frequency of the connected load is fast, the power consumption / response control module 500 performs output regulation at a larger working current to achieve the purpose of fast response, and when the switching frequency of the connected load is slow, the power consumption / response control module 500 performs output regulation at a smaller working current to achieve the purpose of reducing power consumption.

[0091] When output regulation is performed, the error amplifier 200, the fourth PMOS transistor PM4, the sixth NMOS transistor NM6 and the power transistor M0 form a main control loop, and the fourth PMOS transistor PM4, the sixth NMOS transistor NM6 and the power transistor M0 form a fast response loop. For the above two loops:

[0092] The loop bandwidth of the main control loop is narrow, resulting in poor transient response, but this defect can be compensated by the fast response loop; in the fast response loop, the fourth PMOS tube PM4 forms a common gate structure, so that the input impedance is low, thereby having a high response speed; the fast response loop monitors the output voltage VOUT, and can quickly respond to the output voltage VOUT when the load current suddenly changes, and reduce the overshoot and undershoot of the output voltage VOUT through the fast response loop control;

[0093] When the load switches from light load to heavy load, the output voltage VOUT generates an undershoot, because the source of the fourth PMOS tube PM4 is connected to the output voltage VOUT, so that the drain voltage of the fourth PMOS tube PM4 decreases, and the drain voltage of the sixth NMOS tube NM6 decreases, that is, the control terminal voltage of the power tube M0 decreases, thus increasing the voltage of the control terminal of the power tube M0. GS |, making its conduction degree larger, pulling up the output voltage VOUT to keep the output stable;

[0094] Similarly, when the load switches from heavy load to light load, the output voltage VOUT generates an overshoot, because the source of the fourth PMOS tube PM4 is connected to the output voltage VOUT, so that the drain voltage of the fourth PMOS tube PM4 rises, and the drain voltage of the sixth NMOS tube NM6 rises, that is, the control terminal voltage of the power tube M0 rises, thus reducing the |V GS |, reducing its conduction degree and pulling down the output voltage VOUT to keep the output stable.

[0095] Furthermore, the power consumption / response control module 500 further includes: a fourth capacitor C4 and a seventh resistor R7; the fourth capacitor C4 and the seventh resistor R7 are connected in series between the gate terminal and the drain terminal of the fourth PMOS transistor PM4. Due to the existence of the parasitic capacitance of the gate of the power transistor M0, a bypass is formed for the high-frequency signal. In order to avoid oscillation of the high-frequency signal, the fourth capacitor C4 and the seventh resistor R7 are used to compensate for the phase shift of the high-frequency signal in the amplification stage where the fourth PMOS transistor PM4 is located, so that the loop phase of the high-frequency signal is far away from the oscillation condition.

[0096] The bandgap reference module 600 is used to provide a reference voltage VREF. The reference voltage VREF is a voltage that does not change with temperature, and is formed by adding a negative temperature coefficient voltage VBE and a positive temperature coefficient voltage ΔVBE to offset the temperature effect. It can be implemented by any known bandgap reference circuit that can generate a zero temperature coefficient voltage, which has no substantial impact on this embodiment.

[0097] The driving module is connected between the output end of the power consumption / response control module 500 and the control end of the power tube M0 to enhance the driving. Of course, for different types of power tubes M0, the driving can also be achieved by inverting the phase of the output of the driving module. In the application, it can be achieved by adding an inverter to the output end of the driving module. Among them, the driving module can be implemented by a dedicated driving stage circuit or an inverter chain, which has no substantial impact on this embodiment.

[0098] Embodiment 2

[0099] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that the low voltage difference linear regulator of this embodiment further includes a peak-to-average ratio detection module 700 and an integrated control module 800. At this time, the power consumption / response control module 500 is no longer connected to the output end of the switching frequency detection module 400, but is connected to the output end of the integrated control module 800, and is used to adjust its working current according to the total power control signal, and to adjust the output by controlling the power tube M0 under different working currents. Wherein:

[0100] The peak-to-average ratio detection module 700 is used to detect the peak-to-average ratio (ie, peak-to-average power ratio, PAPR) of the multi-carrier modulation signal, and generate a second power control signal according to the number of times the peak-to-average ratio exceeds a set value.

[0101] Specifically, Figure 6 As shown, the peak-to-average ratio detection module 700 includes a comparison unit 710, a second pulse shaping unit 720 and a low-pass filtering unit 730. Among them:

[0102] The comparison unit 710 is used to compare the peak voltage VP_S(t) of the multi-carrier modulation signal with the set voltage VS, and to generate a comparison pulse when the peak voltage VP_S(t) is greater than the set voltage VS. The comparison unit 710 is implemented by a comparator, the non-inverting input terminal of the comparator is connected to the peak voltage VP_S(t), the inverting input terminal is connected to the set voltage VS, and the output terminal generates a comparison pulse.

[0103] The second pulse shaping unit 720 is connected to the output end of the comparison unit 710, and is used to perform pulse stretching processing on the comparison pulse to generate a second rectangular pulse. The second pulse shaping unit 720 has the same structure as the first pulse shaping unit 410, and the details can be found in the relevant content of the first embodiment, which will not be repeated here.

[0104] The low-pass filter unit 730 is connected to the output end of the second pulse shaping unit 720 and is used to convert the second rectangular pulse into a second analog voltage V2 as the second power control signal through low-pass filtering. The low-pass filter unit 730 is implemented by a low-pass filter.

[0105] The relevant signal waveforms involved in the comparison unit 710, the second pulse shaping unit 720 and the low-pass filtering unit 730 are as follows: Figure 7 As shown. In this embodiment, the peak-to-average ratio of the multi-carrier modulation signal is measured by the magnitude of the peak voltage VP_S(t), and the peak-to-average ratio of the multi-carrier modulation signal is judged by comparing the peak voltage VP_S(t) with the set voltage VS to determine whether the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting, and a comparison pulse is generated when the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting. In fact, within a certain period of time, if the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting only once in a while, the impact on the low-dropout linear regulator is very small and can be ignored; in order to effectively regulate the low-dropout linear regulator, the second analog voltage quantity V2 should be generated according to the number of times the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting, so that the working current of the power consumption / response control module 500 is positively correlated with the number of times the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting, so that when the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting number of times, the power consumption / response control module 500 performs output regulation at a larger working current to achieve the purpose of rapid response, and when the peak-to-average ratio of the multi-carrier modulation signal exceeds the setting number of times, the power consumption / response control module 500 performs output regulation at a smaller working current to achieve the purpose of reducing power consumption.

[0106] The integrated control module 800 is connected to the output ends of the switching frequency detection module 400 and the peak-to-average ratio detection module 700, and is used to generate a total power control signal according to the first power control signal and the second power control signal.

[0107] Specifically, Figure 8As shown, the integrated control module 800 includes: a second operational amplifier OP2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11; the in-phase input terminal of the second operational amplifier OP2 is grounded via the eighth resistor R8, the inverting input terminal is connected to the output terminal of the switching frequency detection module 400 via the ninth resistor R9, and is connected to the output terminal of the peak-to-average ratio detection module 700 via the tenth resistor R10, and the output terminal is connected to the inverting input terminal thereof via the eleventh resistor R11 and serves as the output terminal of the integrated control module 800.

[0108] The second operational amplifier OP2, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11 constitute a circuit structure for adding analog voltage quantities, and the relationship between its output voltage and the two input voltages satisfies the following formula: (V1 / R9+V2 / R10)+VB1 / R11=0, wherein V1 is the first analog voltage quantity output by the switching frequency detection module 400, V2 is the second analog voltage quantity output by the peak-to-average ratio detection module 700, VB1 is the analog voltage quantity corresponding to the total power control signal, R9 is the resistance value of the ninth resistor, R10 is the resistance value of the tenth resistor, and R11 is the resistance value of the eleventh resistor.

[0109] Embodiment 3

[0110] This embodiment provides a power supply circuit, including a low voltage dropout linear regulator as described in Embodiment 1 or Embodiment 2; of course, in addition to the low voltage dropout linear regulator, the power supply circuit may also include other functional circuits, such as a startup circuit, an overcurrent protection circuit, an overvoltage protection circuit, etc., and this embodiment does not limit this.

[0111] Embodiment 4

[0112] This embodiment provides an electronic system, including a power supply circuit as described in Example 3; of course, in addition to the power supply circuit, the electronic system may also include other functional circuits, such as analog-to-digital conversion circuits, audio processing circuits, radio frequency circuits, etc., which are not limited in this embodiment. As an optional solution, the electronic system is a system on chip SOC. In fact, the system on chip SOC is suitable for a variety of application scenarios, especially multi-carrier modulation application scenarios.

[0113] In summary, the present invention is a low-voltage difference linear regulator, power supply circuit and electronic system without external capacitors. The working current of the power consumption / response control module is adjusted by the switching frequency of the access load, or even the number of times the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value. The working current of the power consumption / response control module is related to the response speed of the LDO. By adjusting the working current of the power consumption / response control module, the static power consumption of the LDO is adjusted, so that the LDO has a lower average working energy consumption. In the present invention, when the switching frequency of the access load is fast or the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value many times, the working current of the power consumption / response control module is large, and the response speed is improved by increasing the loop bandwidth; when the switching frequency of the access load is slow and the peak-to-average ratio of the multi-carrier modulation signal exceeds the set value few times, the working current of the power consumption / response control module is small, and the overall energy efficiency is improved by reducing power consumption. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A low voltage dropout linear regulator without external capacitor, characterized in that: The low dropout linear regulator comprises: Power tube, feedback resistor network, error amplifier, load switching module, switching frequency detection module and power consumption / response control module, wherein: The control end of the power tube is connected to the output end of the power consumption / response control module, the first end is connected to the input power supply, and the second end is grounded through the feedback resistor network to generate an output voltage, wherein the feedback resistor network divides the output voltage to generate a feedback voltage; The first input terminal of the error amplifier is connected to the reference voltage, and the second input terminal is connected to the feedback voltage; The load switching module is connected to the second end of the power tube and is used to perform switching control of the access load according to the switching control signal; The switching frequency detection module receives the switching control signal, is used to detect the switching frequency of the connected load according to the switching control signal, and generate a first power control signal according to the speed of the switching frequency; The power consumption / response control module is connected to the output ends of the error amplifier and the switching frequency detection module, and is used to adjust the operating current of the power consumption / response control module according to the first power control signal, and to perform output regulation by controlling the power tube under different operating currents.

2. The low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The load switching module includes: a multi-way selection switch and at least two load units; the control end of the multi-way selection switch is connected to the switching control signal, the common end is connected to the second end of the power tube, and each selection end is correspondingly connected to the first end of each load unit; the second end of each load unit is grounded.

3. The low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The switching frequency detection module includes a first pulse shaping unit and a signal generating unit, wherein: The first pulse shaping unit is used to perform pulse stretching processing on the pulse in the switching control signal to obtain a first rectangular pulse; The signal generating unit is connected to the output end of the first pulse shaping unit, and is used for converting the first rectangular pulse into a first analog voltage as the first power control signal by capacitor charging.

4. The low voltage dropout linear regulator without external capacitor according to claim 3, characterized in that: The first pulse shaping unit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a discharge tube, a first comparator, a second comparator, an RS trigger, a NAND gate and an inverter; the first resistor and the first capacitor are connected in series between the working voltage and the ground; the second resistor, the third resistor and the fourth resistor are connected in series between the working voltage and the ground; the in-phase input terminal of the first comparator is grounded through the second capacitor and connected to the connection node of the second resistor and the third resistor, the inverting input terminal is connected to the connection node of the first resistor and the first capacitor, and the output terminal is connected to the reset terminal of the RS trigger; The non-inverting input terminal of the second comparator is connected to the switching control signal, the inverting input terminal is connected to the connection node of the third resistor and the fourth resistor, and the output terminal is connected to the set terminal of the RS trigger; the reset terminal of the RS trigger is connected to the inverted signal of the reset signal, and the output terminal is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the inverted signal of the reset signal, and the output terminal is connected to the input terminal of the inverter and connected to the gate of the discharge tube through the fifth resistor; the output terminal of the inverter serves as the output terminal of the first pulse shaping unit; the drain of the discharge tube is connected to the connection node of the first resistor and the first capacitor, and the source is grounded; And / or, the signal generating unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third capacitor; the first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the second NMOS tube are connected in series between the working voltage and the ground, the gate ends of the first PMOS tube, the second PMOS tube, the third PMOS tube and the second NMOS tube are connected to their respective drain ends, the gate end of the first NMOS tube is connected to the output end of the first pulse shaping unit, and the source end of the first NMOS tube is grounded via the third capacitor and serves as the output end of the signal generating unit.

5. The low voltage dropout linear regulator without external capacitor according to claim 1, characterized in that: The power consumption / response control module includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first operational amplifier and a sixth resistor; the gate end of the fourth PMOS tube is connected to the output end of the error amplifier, the source end is connected to the output voltage, and the drain end is connected to the drain end of the third NMOS tube and the source end of the sixth NMOS tube; the gate ends of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected to each other and connected to the inverting input end of the first operational amplifier, and the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected to the inverting input end of the first operational amplifier. The source end of the fifth NMOS tube is grounded, the drain end of the fourth NMOS tube is connected to the gate end thereof, and the drain end of the fifth NMOS tube is connected to the drain end of the fifth PMOS tube; the gate end of the sixth NMOS tube is connected to the bias voltage, and the drain end is connected to the drain end of the sixth PMOS tube and serves as the output end of the power consumption / response control module; the gate end of the fifth PMOS tube is connected to the drain end thereof and connected to the gate end of the sixth PMOS tube, and the source ends of the fifth PMOS tube and the sixth PMOS tube are connected to the input power supply; the non-inverting input end of the first operational amplifier is connected to the output end of the load switching module, and the output end is connected to the inverting input end thereof via the sixth resistor.

6. The low voltage drop linear regulator without external capacitor according to claim 5, characterized in that: The power consumption / response control module further includes: a fourth capacitor and a seventh resistor; the fourth capacitor and the seventh resistor are connected in series between the gate terminal and the drain terminal of the fourth PMOS tube.

7. The low voltage dropout linear regulator without external capacitor according to any one of claims 1 to 6, characterized in that: The low voltage drop linear regulator further includes: a peak-to-average ratio detection module and a comprehensive control module, wherein: The peak-to-average ratio detection module is used to detect the peak-to-average ratio of the multi-carrier modulation signal, and generate a second power control signal according to the number of times the peak-to-average ratio exceeds a set value; The integrated control module is connected to the output ends of the switching frequency detection module and the peak-to-average ratio detection module, and is used to generate a total power control signal according to the first power control signal and the second power control signal; The power consumption / response control module adjusts the operating current according to the total power control signal, and performs output regulation by controlling the power tube under different operating currents.

8. The low voltage dropout linear regulator without external capacitor according to claim 7, characterized in that: The peak-to-average ratio detection module includes: a comparison unit, a second pulse shaping unit and a low-pass filtering unit, wherein: The comparison unit is used to compare the peak voltage of the multi-carrier modulation signal with a set voltage, and generate a comparison pulse when the peak voltage is greater than the set voltage; The second pulse shaping unit is connected to the output end of the comparison unit, and is used for performing pulse stretching processing on the comparison pulse to generate a second rectangular pulse; The low-pass filtering unit is connected to the output end of the second pulse shaping unit, and is used for converting the second rectangular pulse into a second analog voltage as the second power control signal through low-pass filtering.

9. The low voltage dropout linear regulator without external capacitor according to claim 8, characterized in that: When the switching frequency detection module includes the first pulse shaping unit, the first pulse shaping unit and the second pulse shaping unit have the same structure.

10. The low voltage dropout linear regulator without external capacitor according to claim 7, characterized in that: The integrated control module includes: a second operational amplifier, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; the in-phase input terminal of the second operational amplifier is grounded via the eighth resistor, the inverting input terminal is connected to the output terminal of the switching frequency detection module via the ninth resistor, and is connected to the output terminal of the peak-to-average ratio detection module via the tenth resistor, and the output terminal is connected to the inverting input terminal via the eleventh resistor and serves as the output terminal of the integrated control module.

11. A power supply circuit, characterized in that: The power supply circuit comprises a low voltage dropout linear regulator as claimed in any one of claims 1 to 10.

12. An electronic system, characterized in that: The electronic system comprises the power supply circuit as claimed in claim 11.

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