Overvoltage control circuit, control device, storage device and control method

Abstract

This application provides an overvoltage control circuit, control device, storage device, and control method, relating to the field of circuit control technology. The circuit includes: an operational amplifier circuit, a first detection circuit, a second detection circuit, and a mode control circuit. The bias terminal of the operational amplifier circuit receives a preset bias current. The positive input terminal of the operational amplifier circuit is connected to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit. The negative input terminal of the operational amplifier circuit is grounded. The output terminal of the operational amplifier circuit is connected to the mode control circuit. The detection terminal of the operational amplifier circuit is connected to the first detection circuit. The detection terminal of the operational amplifier circuit is connected to the second detection circuit. The first and second detection circuits are respectively connected to the first and second control terminals of the mode control circuit. The output terminal of the mode control circuit is used to connect to the output terminal of the negative charge pump circuit through a Miller capacitor. This application optimizes the output of the charge pump circuit and reduces the manufacturing cost of the circuit board.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and more specifically, to an overvoltage control circuit, control device, storage device, and control method. Background Technology

[0002] In existing FLASH programming and erasing technologies, the negative (positive) charge pump may generate overshoot during voltage build-up. This overshoot manifests as a voltage pulse exceeding the target voltage value, sometimes even exceeding 400 millivolts. This excessive overshoot voltage can not only cause instantaneous damage to the FLASH memory cells but may also lead to gradual degradation of device performance, thereby affecting the overall reliability of the product.

[0003] Currently, the output voltage of the negative (positive) charge pump is controlled by setting a fixed bias current and a fixed Miller capacitance, thereby controlling the output of the clock circuit connected to the negative (positive) charge pump circuit. Specifically, the voltage settling time of the negative (positive) charge pump can be extended by reducing the bias current or by increasing the Miller capacitance, thus optimizing the output voltage of the negative (positive) charge pump.

[0004] However, existing technologies have limited ability to change the bias current. Even when the bias current is at its minimum, they cannot extend the voltage settling time of the negative (positive) charge pump, making it impossible to optimize the output voltage of the negative (positive) charge pump. Adding Miller capacitance increases its area, leading to a larger circuit board size and increased manufacturing costs. Therefore, it is currently impossible to optimize the output voltage of the negative (positive) charge pump without increasing the manufacturing cost of the circuit board. Summary of the Invention

[0005] The purpose of this application is to address the shortcomings of the prior art by providing an overvoltage control circuit, control device, storage device, and control method. This application optimizes the output of the charge pump circuit and reduces the manufacturing cost of the circuit board without changing the input bias circuit and Miller capacitor.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, one embodiment of this application provides an overvoltage control circuit, the overvoltage control circuit comprising: an operational amplifier circuit, a first detection circuit, a second detection circuit, and a mode control circuit;

[0008] The bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit.

[0009] The first detection terminal of the operational amplifier circuit is connected to the first detection circuit, and the second detection terminal of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection terminal of the operational amplifier circuit is connected to the second detection circuit, and the second detection terminal of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal.

[0010] The first detection circuit and the second detection circuit are respectively connected to the first control terminal and the second control terminal of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal.

[0011] The output of the mode control circuit is connected to the output of the negative charge pump circuit via a Miller capacitor, so that the negative charge pump circuit outputs the output voltage of the first mode based on the first clamping voltage, or outputs the output voltage of the second mode based on the second clamping voltage.

[0012] Optionally, the mode control circuit includes: a timing control circuit and a mode switching circuit;

[0013] The first input terminal and the second input terminal of the timing control circuit are respectively the first control terminal and the second control terminal of the mode control circuit, which are used to connect to the first detection circuit and the second detection circuit respectively. The first mode output terminal of the timing control circuit is connected to the first control terminal of the mode switching circuit to output a first control signal based on the first logic trigger signal. The second mode output terminal of the timing control circuit is connected to the second control terminal of the mode switching circuit to output a second control signal based on the second logic trigger signal.

[0014] The input terminal of the mode switching circuit is the input terminal of the mode control circuit, and is used to connect to the output terminal of the operational amplifier circuit, so that the mode switching circuit outputs the first clamping voltage or the second clamping voltage based on the first control signal and the second control signal.

[0015] Optionally, the operational amplifier circuit includes: a first current mirror, an operational amplifier unit, a second current mirror, a third current mirror, and a fourth current mirror;

[0016] The input terminal of the first current mirror is the bias terminal of the operational amplifier circuit, used to receive the preset bias current. The output terminal of the first current mirror is connected to the bias terminal of the operational amplifier unit. The positive input terminal and the negative input terminal of the operational amplifier unit are the positive input terminal and the negative input terminal of the operational amplifier circuit, respectively.

[0017] The first output terminal of the operational amplifier unit is connected to the input terminal of the second current mirror, and the output terminal of the second current mirror is connected to the input terminal of the third current mirror.

[0018] The second output terminal of the operational amplifier unit is connected to the input terminal of the fourth current mirror, and the series connection point of the output terminals of the third current mirror and the fourth current mirror is the output terminal of the operational amplifier circuit.

[0019] The midpoint of the third current mirror and the second output terminal of the operational amplifier unit are respectively the first detection terminal and the second detection terminal of the operational amplifier circuit.

[0020] Optionally, the overvoltage control circuit further includes an output circuit, wherein the input terminal of the output circuit is connected to the output terminal of the operational amplifier circuit, and the output terminal of the output circuit is connected to the control terminal of the clock circuit of the negative charge pump circuit to output a drive signal to the clock circuit.

[0021] Optionally, the first detection circuit includes: a first PMOS and a first NMOS with their drains connected in series; the gates of the first PMOS and the first NMOS are respectively the first input terminal and the second input terminal of the first detection circuit, and the drains of the first PMOS and the first NMOS are the output terminals of the first detection circuit to output the first logic trigger signal.

[0022] The second detection circuit includes: a second PMOS and a second NMOS with their drains connected in series; the gates of the second PMOS and the second NMOS are respectively the first input terminal and the second input terminal of the second detection circuit, and the drains of the second PMOS and the second NMOS are the output terminals of the second detection circuit to output the second logic trigger signal.

[0023] Optionally, the mode switching circuit includes: a first mode circuit and a second mode circuit;

[0024] The control terminal of the first mode circuit is the first control terminal of the mode switching circuit, connected to the first mode output terminal of the timing control circuit, and used to receive the first control signal. The input terminal of the first mode circuit is the input terminal of the mode switching circuit, and used to connect to the output terminal of the operational amplifier circuit. The output terminal of the first mode circuit is grounded.

[0025] The control terminal of the second mode circuit is the second control terminal of the mode switching circuit, connected to the second mode output terminal of the timing control circuit, and used to receive the second control signal. The input terminal of the second mode circuit is the input terminal of the mode switching circuit, and used to connect to the output terminal of the operational amplifier circuit. The output terminal of the second mode circuit is the output terminal of the mode switching circuit.

[0026] Optionally, the first mode circuit includes: a third NMOS and a third PMOS, wherein the drain of the third NMOS and the source of the third PMOS are the input terminals of the first mode circuit, the gate of the third NMOS and the gate of the third PMOS are the control terminals of the first mode circuit, and the source of the third NMOS and the drain of the third PMOS are the output terminals of the first mode circuit.

[0027] The second mode circuit includes a fourth NMOS and a fourth PMOS. The drain of the fourth NMOS and the source of the fourth PMOS are the input terminals of the second mode circuit. The gate of the fourth NMOS and the gate of the fourth PMOS are the control terminals of the second mode circuit. The source of the fourth NMOS and the drain of the fourth PMOS are the output terminals of the second mode circuit.

[0028] Secondly, another embodiment of this application provides a control device, the control device comprising: the overvoltage control circuit, negative charge pump circuit, clock circuit, and voltage detection circuit described in the first aspect of the claims;

[0029] The output terminal of the clock circuit is connected to the clock control terminal of the negative charge pump circuit, so that the negative charge pump circuit generates an output voltage under the action of the clock signal; the voltage detection circuit is connected to the output terminal of the negative charge pump circuit to obtain the detection voltage corresponding to the output voltage.

[0030] The overvoltage control circuit is connected to the output terminal of the voltage detection circuit, and the overvoltage control circuit is also connected to the output terminal of the negative charge pump circuit, so that the negative charge pump circuit outputs a first mode output voltage based on a first clamping voltage, or outputs a second mode output voltage based on a second clamping voltage.

[0031] Thirdly, another embodiment of this application provides a storage device, which includes at least the control device and storage unit described in the second aspect above;

[0032] The output of the control device is connected to the drive terminal of the storage unit.

[0033] Fourthly, another embodiment of this application provides an overvoltage control method for a negative charge pump circuit, applied to the overvoltage control circuit described in the first aspect above, the method comprising:

[0034] When the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the overvoltage control circuit generates a high-level first logic trigger signal and a low-level second logic trigger signal, and outputs a first clamping voltage based on the high-level first logic trigger signal and the low-level second logic trigger signal, so that the negative charge pump circuit outputs a first mode output voltage based on the first clamping voltage;

[0035] When the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to the preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a second clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the second clamping voltage.

[0036] The beneficial effects of this application are:

[0037] This application provides an overvoltage control circuit, control device, storage device, and control method, including: an operational amplifier circuit, a first detection circuit, a second detection circuit, and a mode control circuit; the bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit; the first detection terminal of the operational amplifier circuit is connected to the first detection circuit, and the second detection terminal of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the operational amplifier... The first detection terminal of the circuit is connected to the second detection circuit, and the second detection terminal of the operational amplifier circuit is also connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal. The first and second detection circuits are respectively connected to the first and second control terminals of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first and second logic trigger signals. The output terminal of the mode control circuit is used to connect to the output terminal of the negative charge pump circuit through a Miller capacitor, so that the negative charge pump circuit outputs the output voltage of the first mode based on the first clamping voltage, or outputs the output voltage of the second mode based on the second clamping voltage. This application determines the operating state of the charge pump circuit by setting the first and second detection circuits, and thus by using the first and second logic trigger signals of the first and second detection circuits. By setting a mode control circuit, the corresponding control mode is determined according to the first logic trigger signal and the second logic trigger signal, thereby outputting a clamping voltage. Under the action of the clamping voltage and the Miller capacitor, the negative charge pump circuit outputs the corresponding output voltage. This application can optimize the output of the charge pump circuit without changing the input bias circuit and the Miller capacitor, reducing the manufacturing cost of the circuit board. At the same time, it avoids the output voltage of the charge pump circuit from exceeding the overshoot voltage, protects the normal operation of the charge pump circuit, and improves the life of the charge pump circuit. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of an overvoltage control circuit provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the mode control circuit in an overvoltage control circuit provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of the operation method circuit in an overvoltage control circuit provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of the output circuit in an overvoltage control circuit provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the detection circuit in an overvoltage control circuit provided in an embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the mode switching circuit in an overvoltage control circuit provided in an embodiment of this application;

[0045] Figure 7a This is a schematic diagram of the mode circuit in the first type of overvoltage control circuit provided in the embodiments of this application;

[0046] Figure 7b This is a schematic diagram of the mode circuit in the second type of overvoltage control circuit provided in the embodiments of this application;

[0047] Figure 7c This is a schematic diagram of the mode circuit in the third type of overvoltage control circuit provided in the embodiments of this application;

[0048] Figure 8 A voltage control schematic diagram of an overvoltage control circuit provided in an embodiment of this application;

[0049] Figure 9 A voltage control schematic diagram of another overvoltage control circuit provided in an embodiment of this application;

[0050] Figure 10 This is a schematic diagram of the structure of a control device provided in an embodiment of this application;

[0051] Figure 11 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0052] Figure 12 This is a schematic flowchart of an overvoltage control method for a negative charge pump circuit provided in an embodiment of this application.

[0053] Figure reference numerals: Operational amplifier circuit - 100; First current mirror - 101; Operational amplifier unit - 102; Second current mirror - 103; Third current mirror - 104; Fourth current mirror - 105; First detection circuit - 200; Second detection circuit - 300; Mode control circuit - 400; Timing control circuit - 404; Mode switching circuit - 402; First mode circuit - 4021; Second mode circuit - 4022; Negative charge pump circuit - 500; Output circuit - 600; Clock circuit - 700; Preset bias current - Ibias; Control voltage - Vgate; Drive signal - Vsin; Detection voltage - Vbias; First clamping voltage - CV1; The... Two clamping voltages - CV2; Output voltage of the first mode - V1; Output voltage of the second mode - V2; First logic trigger signal - strg1; Second logic trigger signal - strg2; First control signal - Mode1; Inverted signal of the first control signal - Mode1_b; Second control signal - Mode2; Inverted signal of the second control signal - Mode2_b; First PMOS transistor - PM1; First NMOS transistor - NM1; Second PMOS transistor - PM2; Second NMOS transistor - NM2; Third NMOS transistor - NM3; Third PMOS transistor - PM3; Fourth NMOS transistor - NM4; Fourth PMOS transistor - PM4; Fifth PMOS transistor - PM5; Sixth PMOS transistor - PM6; Fifth NMOS transistor - NM5; Sixth NMOS transistor - NM6; Seventh PMOS transistor - PM7; Eighth PMOS transistor - PM8; Seventh NMOS transistor - NM7; Eighth NMOS transistor - NM8; Ninth PMOS transistor - PM9; Tenth PMOS transistor - PM10; Eleventh NMOS transistor - NM11; Overvoltage control circuit - 1000; Negative charge pump circuit - 2000; Clock circuit - 3000; Voltage detection circuit - 4000; Control device - 10000; Storage unit - 20000. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0056] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0057] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0058] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0059] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0060] In existing FLASH programming and erasing technologies, overshoot may occur during the voltage build-up process of the negative (positive) charge pump. This is mainly addressed by setting a fixed bias current and a fixed Miller capacitance to output a drive signal during the voltage build-up process of the negative (positive) charge pump, controlling the output of the clock circuit connected to the negative (positive) charge pump circuit, thereby controlling the output voltage of the negative (positive) charge pump. Specifically, the voltage build-up time of the negative (positive) charge pump can be extended by reducing the bias current or by increasing the Miller capacitance, thus optimizing the output voltage of the negative (positive) charge pump. However, the existing methods have limited flexibility in changing the bias current; even at its minimum, the voltage build-up time of the negative (positive) charge pump cannot be extended, making it impossible to optimize the output voltage. Increasing the Miller capacitance increases its area, leading to a larger circuit board size and increased manufacturing costs. Therefore, it is currently impossible to optimize the output voltage of the negative (positive) charge pump without increasing the circuit board manufacturing cost. To address this, this application provides an overvoltage control circuit that optimizes the output voltage of the negative charge pump without increasing or decreasing the circuit board manufacturing cost. It is worth noting that this application takes a negative charge pump as an example. The principle of optimizing the output voltage circuit of a positive charge pump is the same as that of this application, and it can be achieved by referring to the overvoltage control circuit in this application.

[0061] Figure 1 This is a schematic diagram of an overvoltage control circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, the overvoltage control circuit includes: an operational amplifier circuit 100, a first detection circuit 200, a second detection circuit 300, a mode control circuit 400, and an output circuit 600.

[0062] The bias terminal BIAS of the operational amplifier circuit 100 is used to receive the preset bias current Ibias. The positive input terminal IP of the operational amplifier circuit 100 is used to connect to the voltage detection terminal corresponding to the output terminal OUT of the negative charge pump circuit 500. The negative input terminal IN of the operational amplifier circuit 100 is grounded. The output terminal OUT of the operational amplifier circuit 100 is connected to the input terminal IN of the mode control circuit 500.

[0063] The first detection terminal Signal1 of the operational amplifier circuit 100 is connected to the first input terminal IN1 of the first detection circuit 200, and the second detection terminal Signal2 of the operational amplifier circuit 100 is connected to the second input terminal IN2 of the first detection circuit 200, so that the first detection circuit 200 generates a first logic trigger signal strg1 based on the detection voltage Vbias of the first detection terminal Signal1 of the operational amplifier circuit 100; the first detection terminal Signal1 of the operational amplifier circuit 100 is connected to the first input terminal IN1 of the second detection circuit 300, and the second detection terminal Signal2 of the operational amplifier circuit 100 is connected to the second input terminal IN2 of the second detection circuit 300, so that the second detection circuit 300 generates a second logic trigger signal strg2 based on the detection voltage Vbias;

[0064] The output terminal OUT of the first detection circuit 200 and the output terminal OUT of the second detection circuit 300 are respectively connected to the first control terminal Control1 and the second control terminal Control2 of the mode control circuit 400. The input terminal IN of the mode control circuit 400 is connected to the output terminal OUT of the operational amplifier circuit 100, so that the mode control circuit 400 outputs the first clamping voltage CV1 or the second clamping voltage CV2 under the action of the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0065] The output terminal OUT of the mode control circuit 400 is connected to the output terminal OUT of the negative charge pump circuit 500 through the Miller capacitor CM, so that the negative charge pump circuit 500 outputs the output voltage V1 of the first mode based on the first clamping voltage CV1, or outputs the output voltage V2 of the second mode based on the second clamping voltage CV2.

[0066] The bias current Ibias can be 2~4uA, and the specific value is determined according to the requirements of the operational amplifier circuit 100. This application embodiment does not limit this.

[0067] The output terminal OUT of the charge pump circuit 500 is connected to a detection circuit, which is a voltage divider circuit. The detection circuit divides the output voltage of the charge pump circuit 500's output terminal OUT to obtain a corresponding detection voltage, which is then input to the positive input terminal IP of the operational amplifier circuit 100 through the voltage detection terminal. The detection circuit includes a voltage divider resistor and a preset reference voltage, which can be 0.6V, 0.85V, 1V, or 1.2V; this embodiment does not limit this. The negative input terminal IN of the operational amplifier circuit 100 is grounded. When the positive input terminal IP of the operational amplifier circuit 100 changes, the corresponding output terminal OUT of the operational amplifier circuit 100 generates a positive voltage change, making the voltage difference between the negative input terminal IN and the positive input terminal IP of the operational amplifier circuit 100 approach zero.

[0068] The first detection circuit 200 and the second detection circuit 300 respectively output a first logic trigger signal strg1 and a second logic trigger signal strg2. The operation of the overvoltage control circuit is determined by the different judgments made by the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0069] The first control terminal Control1 and the second control terminal Control2 of the mode control circuit 400 receive the first logic trigger signal strg1 and the second logic trigger signal strg2 respectively, and are used to perform mode control according to the first logic trigger signal strg1 and the second logic trigger signal strg2, so that the mode control circuit 400 outputs the first clamping voltage CV1 or the second clamping voltage CV2 according to the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0070] The Miller capacitor CM can be 4~5pF, and this embodiment does not limit this; the specific value is determined according to the application. The first clamping voltage CV1 or the second clamping voltage CV2, through the Miller capacitor CM, ensures that the output voltage V1 of the first mode or the output voltage V2 of the second mode is less than the overshoot voltage of the charge pump circuit 500. Specifically, both the output voltage V1 of the first mode and the output voltage V2 of the second mode are less than the overshoot voltage of the charge pump circuit 600. The overshoot voltage of the charge pump circuit 600 can be determined based on the specific circuit of the charge pump circuit 600, and this embodiment does not limit this.

[0071] This application provides an overvoltage control circuit, including: an operational amplifier circuit, a first detection circuit, a second detection circuit, and a mode control circuit; the bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit; the first detection terminal of the operational amplifier circuit is connected to the first detection circuit, and the second detection terminal of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection terminal of the operational amplifier circuit is connected to the second detection circuit, and the second detection terminal of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal; the first detection circuit and the second detection circuit are respectively connected to the first control terminal and the second control terminal of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal; the output terminal of the mode control circuit is used to connect to the output terminal of the negative charge pump circuit through a Miller capacitor, so that the negative charge pump circuit outputs the output voltage of a first mode based on the first clamping voltage, or outputs the output voltage of a second mode based on the second clamping voltage. This application establishes a first detection circuit and a second detection circuit, thereby determining the operating state of the charge pump circuit through the first and second logic trigger signals of the first and second detection circuits. By setting up a mode control circuit, a corresponding control mode is determined based on the first and second logic trigger signals, thereby outputting a clamping voltage. This causes the negative charge pump circuit to output a corresponding output voltage under the action of the clamping voltage and the Miller capacitance. This application can optimize the output of the charge pump circuit without changing the input bias circuit and the Miller capacitance, reducing the manufacturing cost of the circuit board. Simultaneously, it prevents the output voltage of the charge pump circuit from exceeding the overshoot voltage, protecting the normal operation of the charge pump circuit and improving its lifespan.

[0072] Based on the above embodiments, this application also provides a mode control circuit in an overvoltage control circuit. Figure 2 This is a schematic diagram of the mode control circuit in an overvoltage control circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the mode control circuit 500 includes: a timing control circuit 401 and a mode switching circuit 402;

[0073] The first input terminal IN1 and the second input terminal IN2 of the timing control circuit 401 are respectively the first control terminal Control1 and the second control terminal Control2 of the mode control circuit 500, and are used to connect to... Figure 1The output terminal OUT of the first detection circuit 200 and the output terminal OUT of the second detection circuit 300 are connected to the first mode output terminal OUT1 of the timing control circuit 401, which is connected to the first control terminal Control1 of the mode switching circuit 402 to output the first control signal Mode1 to the first control terminal. The second mode output terminal OUT2 of the timing control circuit 401 is connected to the second control terminal Control1 of the mode switching circuit 402 to output the second control signal Mode2 to the second control terminal.

[0074] The input terminal IN of the mode switching circuit 402 is the same as the input terminal IN of the mode control circuit 500. It is used to connect to the output terminal OUT of the operational amplifier circuit 100, so that the mode switching circuit 402 outputs the first clamping voltage CV1 or the second clamping voltage CV2 respectively under the action of the first control signal Mode1 and the second control signal Mode2.

[0075] The timing control circuit 401 includes a clock source, a frequency divider, a counter, a flip-flop, a register, logic gates, and delay elements. The timing control circuit 401 receives a first logic trigger signal strg1 and a second logic trigger signal strg2, and generates a first control signal Mode1 and a second control signal Mode2 based on the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0076] The mode switching circuit 402 is used to control the mode according to the first control signal Mode1 and the second control signal Mode2, and output the first clamping voltage CV1 or the second clamping voltage CV2 according to the corresponding control mode.

[0077] In this embodiment, the mode control circuit includes a timing control circuit and a mode switching circuit. The timing control circuit generates a corresponding control signal based on the logic trigger signal, and the mode switching circuit determines the control mode based on the corresponding control signal, thereby outputting a clamping voltage. This application can ensure that the operation is executed in a precise time sequence through the timing control circuit, and the mode switching circuit can easily switch between different working modes according to different control signals, thereby improving the stability and reliability of the overvoltage control circuit.

[0078] Based on the above embodiments, this application also provides a bias circuit in an overvoltage control circuit. Figure 3 This is a schematic diagram of the operational amplifier circuit in an overvoltage control circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, the operational amplifier circuit 100 includes: an operational amplifier unit 102, a second current mirror 103, a third current mirror 104, and a fourth current mirror 105.

[0079] The first current mirror 101 has an input terminal IN that is the bias terminal BIAS of the operational amplifier circuit 100, used to receive the preset bias current Ibias. The output terminal OUT of the first current mirror 101 is connected to the bias terminal BIAS of the operational amplifier unit 102. The positive input terminal IP and the negative input terminal IN of the operational amplifier unit 102 are the positive input terminal IP and the negative input terminal IN of the operational amplifier circuit 100, respectively.

[0080] The first output terminal OUT1 of the operational amplifier unit 102 is connected to the input terminal IN of the second current mirror 103, and the output terminal OUT of the second current mirror 103 is connected to the input terminal IN of the third current mirror 104.

[0081] The second output terminal OUT of the operational amplifier unit 102 is connected to the input terminal IN of the fourth current mirror 104, and the series connection point of the output terminal OUT of the third current mirror 104 and the output terminal OUT of the fourth current mirror 105 is the output terminal OUT of the operational amplifier circuit 100.

[0082] The midpoint of the third current mirror 104 and the second output terminal OUT2 of the operational amplifier unit 102 are respectively the first detection terminal Signal1 and the second detection terminal Signal2 of the operational amplifier circuit 100.

[0083] The first current mirror 101 is a bias circuit. The first current mirror 101 includes a fifth PMOS (positive-channel metal-oxide-semiconductor, PMOS transistor) PM5 and a sixth PMOS transistor PM6. The drain and gate of the fifth PMOS transistor PM5 and the gate of the sixth PMOS transistor PM6 form the input terminal IN of the first current mirror 101, used to receive a preset bias current Ibisa. The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected. The drain of the sixth PMOS transistor PM6 forms the output terminal OUT of the first current mirror 101, used to connect to the bias terminal BIAS of the operational amplifier circuit 100. The width ratio of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 is any ratio from 1:0.2 to 4, and this embodiment does not impose a limitation on this ratio. The sixth PMOS transistor PM6 can amplify the current flowing through the fifth PMOS transistor PM5 by 0.2 to 4 times, and the specific amplification ratio is determined based on the width ratio of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6.

[0084] Specifically, the preset bias current Ibisa is input to the first current mirror 101 through the drain of the fifth PMOS transistor PM5. After the sixth PMOS transistor PM6 amplifies the preset bias current Ibisa, it enters the bias terminal BIAS of the operational amplifier unit 102 through the drain of the sixth PMOS transistor PM6.

[0085] The second current mirror 103 includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6. The gate and drain of the fifth NMOS transistor NM5 and the gate of the sixth NMOS transistor NM6 are the input terminals of the second current mirror 103, which are used to connect to the first output terminal of the operational amplifier unit 102. The source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6 are grounded. The drain of the sixth NMOS transistor NM6 is the output terminal of the second current mirror 103, which is used to connect to the third current mirror 104. The width ratio of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 is 1:1, and the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are identical.

[0086] The third current mirror 104 includes a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8. The gate and drain of the seventh PMOS transistor PM7 and the gate of the eighth PMOS transistor PM8 form the input terminals of the third current mirror 104, which are used to connect to the output terminal of the second current mirror 103. The source of the seventh PMOS transistor PM7 and the source of the eighth PMOS transistor PM8 are connected, and the drain of the eighth PMOS transistor PM8 forms the output terminal of the third current mirror 104. The width ratio of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 is 1:1, and the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are identical.

[0087] The fourth current mirror 105 includes a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8. The gate and drain of the seventh NMOS transistor NM7 and the gate of the eighth NMOS transistor NM8 are the input terminals of the fourth current mirror 105, used to connect to the second output terminal of the operational amplifier unit 1021. The source of the seventh NMOS transistor NM7 and the source of the eighth NMOS transistor NM8 are grounded, and the drain of the eighth NMOS transistor NM8 is the output terminal of the fourth current mirror 105. The width ratio of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 is 1:1, and the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are identical.

[0088] Operational amplifier unit 102 includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10. The gate of the ninth PMOS transistor PM9 is the positive input terminal IP of operational amplifier unit 102, and the gate of the tenth PMOS transistor PM10 is the negative input terminal IN of operational amplifier unit 102. The sources of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are the bias terminals BIAS of operational amplifier unit 102. The drain of the ninth PMOS transistor PM9 is the second output terminal of operational amplifier unit 102, and the drain of the tenth PMOS transistor PM10 is the first output terminal of operational amplifier unit 102. The width ratio of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 is 1:1, that is, the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are identical.

[0089] Specifically, when the gate of the ninth PMOS transistor PM9 is the positive input terminal IP of the operational amplifier unit 102, and the gate of the tenth PMOS transistor PM10 is the negative input terminal IN of the operational amplifier unit 102, and the negative input terminal IN of the operational amplifier unit 102 is grounded, that is, when the gate voltage of the tenth PMOS transistor PM10 is 0, the gate voltage of the ninth PMOS transistor PM9 is the detection voltage input to the detection circuit. At this time, the gate voltage of the ninth PMOS transistor PM9 is greater than the gate voltage of the tenth PMOS transistor PM10, and the current flowing through the tenth PMOS transistor PM10 is greater than the current flowing through the ninth PMOS transistor PM9. The currents flowing through the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are all the same as the current flowing through the tenth PMOS transistor PM10. The currents flowing through the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are also the same as the current flowing through the ninth PMOS transistor PM9. When the current flowing through the eighth PMOS transistor PM8 across the two ends of the output circuit 600 is greater than the current flowing through the eighth NMOS transistor NM8, the output control voltage Vgate is pulled high, the drive signal Vsin is grounded, and the clock signal clk and the reverse clock signal clkb swing at full amplitude, and the charge pump starts to work.

[0090] In this embodiment, the operational amplifier circuit includes an operational amplifier unit, a second current mirror, a third current mirror, and a fourth current mirror. By comparing the currents at the positive and negative input terminals of the operational amplifier unit through multiple current mirrors, a control voltage is generated, which can improve the linearity and accuracy of the operational amplifier unit. The current mirrors can maintain a stable input to the operational amplifier circuit and optimize the gain and anti-interference capability of the operational amplifier unit.

[0091] Based on the above embodiments, this application also provides an output circuit in an overvoltage control circuit. Figure 4This is a schematic diagram of the output circuit in an overvoltage control circuit provided in an embodiment of this application, as shown below. Figure 4 As shown, the overvoltage control circuit also includes an output circuit 600. The input terminal IN of the output circuit 600 is connected to the output terminal OUT of the operational amplifier circuit 100. The output terminal OUT of the output circuit 600 is connected to the control terminal Control of the clock circuit 700 of the negative charge pump circuit 500 to output a drive signal Vsin to the clock circuit 700.

[0092] Output circuit 600 includes an NMOS transistor. Its input terminal IN is connected to the output terminal OUT of operational amplifier circuit 100. The control voltage Vgate output from the output terminal OUT of operational amplifier circuit 100 drives the NMOS transistor in output circuit 600, causing output circuit 600 to output a drive signal Vsin to clock circuit 700. Clock circuit 700 outputs clock signal clk and an inverted clock signal clkb. Clock circuit 700 includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter receives the master clock signal clock, and its output terminal outputs the clock signal clk. The power supply terminal of the first inverter is connected to a voltage regulator, and its control terminal receives the drive signal Vsin. The input terminal of the second inverter receives the master clock signal clock, and its output terminal is connected to the input terminal of the third inverter. The output terminal of the third inverter outputs the inverted clock signal clkb, and its power supply terminal is connected to a voltage regulator. Its control terminal receives the drive signal Vsin.

[0093] In this embodiment, the overvoltage control circuit also includes a clock circuit, which adjusts the output signal in a timely manner according to the driving voltage of the operational amplifier circuit, thereby protecting the circuit from overvoltage damage. By outputting a driving signal to the clock circuit through the output circuit, the working state of the negative charge pump circuit can be effectively managed.

[0094] Based on the above embodiments, this application also provides a detection circuit in an overvoltage control circuit. Figure 5 This is a schematic diagram of the detection circuit in an overvoltage control circuit provided in an embodiment of this application, as shown below. Figure 5 As shown, the first detection circuit 200 includes: a first PMOS transistor PM1 and a first NMOS transistor NM1 connected in series with their drains connected in series; the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 are respectively the first input terminal IN1 and the second input terminal IN2 of the first detection circuit 200; the drains of the first PMOS transistor PM1 and the first NMOS transistor NM2 are the output terminals of the first detection circuit 200 to output a first logic trigger signal strg1;

[0095] The second detection circuit 300 includes: a second PMOS transistor PM2 and a second NMOS transistor NM2 connected in series with their drains; the gates of the second PMOS transistor PM2 and the second NMOS transistor NM2 are respectively the first input terminal IN1 and the second input terminal IN2 of the second detection circuit 300; the drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 are the output terminals of the second detection circuit 300 to output a second logic trigger signal strg2.

[0096] The width ratio of the first PMOS transistor PM1 to the eighth PMOS transistor PM8 is any ratio from 0.2 to 4:1, specifically determined based on the first inflection point voltage of the driving voltage Vgate; this embodiment does not impose any limitation on this ratio. Similarly, the width ratio of the first NMOS transistor NM1 to the eighth NMOS transistor NM8 is any ratio from 0.2 to 4:1, specifically determined based on the first inflection point voltage of the driving voltage Vgate; this embodiment does not impose any limitation on this ratio. The width ratios of the first PMOS transistor PM1 to the eighth PMOS transistor PM8 and the first NMOS transistor NM1 to the eighth NMOS transistor NM8 are the same.

[0097] The width ratio of the second PMOS transistor PM2 to the eighth PMOS transistor PM8 is any ratio from 0.2 to 4:1, specifically determined based on the second inflection point voltage of the driving voltage Vgate; this embodiment does not impose such a limitation. Similarly, the width ratio of the second NMOS transistor NM2 to the eighth NMOS transistor NM8 is any ratio from 0.2 to 4:1, specifically determined based on the second inflection point voltage of the driving voltage Vgate; this embodiment does not impose such a limitation. The width ratios of the second PMOS transistor PM2 to the eighth PMOS transistor PM8 and the second NMOS transistor NM2 to the eighth NMOS transistor NM8 are the same.

[0098] Specifically, when the first inflection point voltage is greater than the second inflection point voltage, if the dimensions of the first PMOS transistor PM1 and the second PMOS transistor PM2 are the same, the dimension of the first NMOS transistor NM1 is greater than that of the second NMOS transistor NM2; if the dimension of the first NMOS transistor NM1 is equal to that of the second NMOS transistor NM2, the dimension of the first PMOS transistor PM1 is smaller than that of the second PMOS transistor PM2.

[0099] Specifically, when the driving voltage Vgate reaches the first inflection point voltage, the first logic trigger signal strg1 outputs a high level, and the second logic trigger signal strg1 outputs a low level; when the driving voltage Vgate reaches the second inflection point voltage, the first logic trigger signal strg1 outputs a low level, and the second logic trigger signal strg1 outputs a high level. The first and second inflection point voltages are determined based on the actual situation of the charge pump circuit 600, with the second inflection point voltage being lower than the first inflection point voltage.

[0100] In this embodiment, a first detection circuit and a second detection circuit are set to detect the first inflection point voltage and the second inflection point voltage respectively, and output the corresponding logic trigger signal according to the first inflection point voltage or the second inflection point voltage. The first detection circuit and the second detection circuit respond quickly to the change of the inflection point voltage, so as to ensure the accuracy and reliability of the generated logic trigger signal.

[0101] Based on the above embodiments, this application also provides a mode switching circuit in an overvoltage control circuit. Figure 6 This is a schematic diagram of the structure of a mode switching circuit in an overvoltage control circuit provided in an embodiment of the present application. The mode switching circuit 402 includes: a first mode circuit 4021 and a second mode circuit 4022.

[0102] The control terminal Control of the first mode circuit 4021 is the first control terminal Control1 of the mode switching circuit 402, connected to the first mode output terminal OUT1 of the timing control circuit 502, used to receive the first control signal Mode1. The input terminal IN of the first mode circuit 4021 is the input terminal IN of the mode switching circuit, used to connect to... Figure 1 The output terminal ONT of the operational amplifier circuit 100 and the output terminal OUT of the first mode circuit 4021 are grounded.

[0103] The control terminal Control of the second mode circuit 4022 is the second control terminal Control2 of the mode switching circuit 402, connected to the second mode output terminal OUT2 of the timing control circuit 502, used to receive the second control signal Mode2. The input terminal IN of the second mode circuit 5022 is the input terminal IN of the mode switching circuit, used to connect to... Figure 1 The input terminal OUT of the operational amplifier circuit 100 and the output terminal OUT of the second mode circuit 4022 are the output terminals OUT of the mode switching circuit 402.

[0104] Specifically, the operation of the first mode circuit 4021 and the second mode circuit 4022 is determined according to the first control signal Mode1 or the second control signal Mode2. When the first control signal Mode1 is high and the second control signal Mode2 is low, the first mode circuit 4021 is working and the second mode circuit 4022 is not working. At this time, the first mode circuit 4021 pulls down the driving voltage Vgate, thereby limiting the control signal Vsin and optimizing the output of the negative charge pump circuit. When the first control signal Mode1 is low and the second control signal Mode2 is high, the first mode circuit 4021 is not working and the second mode circuit 4022 is working. Through the Miller capacitor CM, the output voltage of the negative charge pump circuit 500 is controlled to approach the target voltage.

[0105] In this embodiment, the mode switching circuit includes a first mode circuit and a second mode circuit. The operating mode circuit is determined based on the input control signal. It can adjust the output voltage of the charge pump circuit according to different operating conditions, thereby improving the accuracy and stability of the output voltage. This reduces the power consumption of the charge pump circuit and improves overall energy efficiency.

[0106] Based on the above embodiments, this application also provides various mode circuits in overvoltage control circuits. Figure 7a This is a schematic diagram of the mode circuit in the first type of overvoltage control circuit provided in the embodiments of this application, as shown below. Figure 7a As shown, the first mode circuit 4021 includes: a third NMOS transistor NM3 and a third PMOS transistor PM3. The drain of the third NMOS transistor NM3 and the source of the third PMOS transistor PM3 are the input terminals IN of the first mode circuit 4021. The gates of the third NMOS transistor NM3 and the third PMOS transistor PM3 are the control terminals Control of the first mode circuit 4021. The source of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3 are the output terminals OUT of the first mode circuit 4021. The first mode circuit 4021 also includes: an eleventh NMOS transistor NM11. The gate and drain of the eleventh NMOS transistor NM11 are connected to the source of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3. The source of the eleventh NMOS transistor NM11 is the output terminal OUT of the first mode circuit 4021, and the source of the eleventh NMOS transistor NM11 is grounded. Correspondingly, the first control signal Mode1 also includes the inverse signal Mode1_b of the first control signal. The gate of the third NMOS transistor NM3 is used to receive the first control signal Mode1, and the gate of the third PMOS transistor PM3 is used to receive the inverse signal Mode1_b of the first control signal. When the first control signal Mode1 is high, the inverse signal Mode1_b of the first control signal is low. At this time, the third NMOS transistor NM3 and the third PMOS transistor PM3 are turned on, and the eleventh NMOS transistor NM11 is turned on. At this time, the control voltage Vgate is pulled down, thereby limiting the drive voltage Vsin.

[0107] The second mode circuit 4022 includes a fourth NMOS transistor NM4 and a fourth PMOS transistor PM4. The drain of the fourth NMOS transistor NM4 and the source of the fourth PMOS transistor PM4 are the input terminals IN of the second mode circuit 4022. The gates of the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are the control terminals Control of the second mode circuit 4022. The source and drain of the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are the output terminals of the second mode circuit. Correspondingly, the second control signal Mode2 also includes the inverted signal Mode2_b. The gate of the fourth NMOS transistor NM4 is used to receive the second control signal Mode2, and the gate of the fourth PMOS transistor PM4 is used to receive the inverted signal Mode2_b. When the second control signal Mode2 is high, the inverted signal Mode2_b is low. At this time, the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on, and the output voltage of the charge pump circuit 600 is controlled to approach the target voltage through the Miller capacitor CM.

[0108] Among them, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 have the same size, and the third PMOS transistor PM3 and the fourth PMOS transistor PM4 have the same size.

[0109] Optionally, Figure 7b This is a schematic diagram of the mode circuit in the second type of overvoltage control circuit provided in the embodiments of this application, as shown below. Figure 7b As shown, in Figure 7a Based on this, the first mode circuit 4021 further includes: a twelfth NMOS transistor NM12, the gate and drain of the twelfth NMOS transistor NM12 are connected to the source of the eleventh NMOS transistor NM11, the source of the twelfth NMOS transistor NM12 is the output terminal OUT of the first mode circuit 4021, and the source of the twelfth NMOS transistor NM12 is grounded.

[0110] Optionally, Figure 7c This is a schematic diagram of the mode circuit in the third type of overvoltage control circuit provided in the embodiments of this application, as shown below. Figure 7c As shown, in Figure 7b Based on this, the gate of the twelfth NMOS transistor NM12 is used to receive the above... Figure 1 The first detection terminal Signal1 of the operational amplifier circuit 100 has a detection voltage Vbias. The drain of the twelfth NMOS transistor NM12 is connected to the source of the eleventh NMOS transistor NM11. The source of the twelfth NMOS transistor NM12 is the output terminal OUT of the first mode circuit 4021. The source of the twelfth NMOS transistor NM12 is grounded.

[0111] It is worth noting that the above-mentioned mode circuit is only a possible implementation of the mode circuit. In actual use, there are many other structures of the mode circuit. The specific mode circuit can be determined according to the actual use scenario. This application embodiment does not limit this.

[0112] In this embodiment, by switching the corresponding modes using multiple NMOS and PMOS transistors in the first mode control circuit and the second mode circuit, the output voltage of the charge pump circuit can be precisely controlled, optimizing the efficiency of the charge pump circuit and reducing power consumption. Simultaneously, this application utilizes various mode circuit structures to reduce parasitic effects and improve signal integrity, allowing for finer adjustments to circuit behavior and enhancing the flexibility of the mode control circuit.

[0113] The overvoltage control circuit provided in the embodiments of this application will be described below with reference to the accompanying drawings. Figure 8 A voltage control schematic diagram of an overvoltage control circuit provided in this application embodiment is shown below. Figure 8 As shown, the first inflection point voltage of the charge pump circuit is Vtg0, the second inflection point voltage is Vtg1, and the target voltage is Vtg.

[0114] The gate of the ninth PMOS transistor PM9 is the positive input terminal IP of the operational amplifier unit 102, and the gate of the tenth PMOS transistor PM10 is the negative input terminal IN of the operational amplifier unit 102. When the negative input terminal IN of the operational amplifier unit 102 is grounded, that is, the gate voltage of the tenth PMOS transistor PM10 is 0. At this time, the gate voltage of the ninth PMOS transistor PM9 is the detection voltage input to the detection circuit. At this time, the gate voltage of the ninth PMOS transistor PM9 is greater than the gate voltage of the tenth PMOS transistor PM10, and the current flowing through the tenth PMOS transistor PM10 is greater than the current flowing through the ninth PMOS transistor PM9. The currents flowing through the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are all the same as the current flowing through the tenth PMOS transistor PM10. The currents flowing through the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are also the same as the current flowing through the ninth PMOS transistor PM9. The current flowing through the eighth PMOS transistor PM8 across the two ends of the output circuit 600 is greater than the current flowing through the eighth NMOS transistor NM8. At this time, the output control voltage Vgate is pulled high, the drive signal Vsin is grounded, the clock signal clk and the reverse clock signal clkb swing at full amplitude, the charge pump starts to work, and the output voltage starts to drop from Vini.

[0115] When the output voltage drops from Vini to the first inflection point voltage Vtg0, the first logic trigger signal strg1 outputs a high level, and the second logic trigger signal strg1 outputs a low level. The first control signal Mode1 is high, and its inverse Mode1_b is low. The second control signal Mode2 is low, and its inverse Mode2_b is high. At this time, the third NMOS transistor NM3 and the third PMOS transistor PM3 are turned on, and the eleventh NMOS transistor NM11 is turned on. This pulls down the control voltage Vgate, thereby limiting the drive voltage Vsin.

[0116] When the output voltage drops from the first inflection point voltage Vtg0 to the second inflection point voltage Vtg1, the first logic trigger signal strg1 outputs a low level, and the second logic trigger signal strg1 outputs a high level. The first control signal Mode1 is low, and its inverse Mode1_b is high. The second control signal Mode2 is high, and its inverse Mode2_b is low. The fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on, and through the Miller capacitor CM, the output voltage of the charge pump circuit 600 is controlled to approach the target voltage Vtg.

[0117] Based on the above embodiments, this application also provides a voltage control schematic diagram of another overvoltage control circuit. Figure 9 A voltage control schematic diagram of another overvoltage control circuit provided in this application embodiment is shown below. Figure 9 As shown, the first inflection point voltage of the charge pump circuit's output voltage is Vtg0, the second inflection point voltage is Vtg1, the third inflection point voltage is Vtg2, the fourth inflection point voltage is Vtg3, and the target voltage is Vtg. When there are four inflection point voltages, four detection circuits are set. The output voltage of the charge pump circuit can be controlled based on the logic signals output by these four detection circuits. When the corresponding step voltage is reached, a timer is set to maintain the inflection point voltage for a certain period, thereby precisely controlling the output voltage of the charge pump circuit and gradually reaching the final target voltage Vtg. This effectively controls the output of the charge pump circuit and avoids overshoot.

[0118] Another embodiment of this application also provides a control device. Figure 10 This is a schematic diagram of the structure of a control device provided in an embodiment of this application, such as... Figure 10 As shown, the control device includes: an overvoltage control circuit 1000, a negative charge pump circuit 2000, a clock circuit 3000, and a voltage detection circuit 4000.

[0119] The voltage detection circuit 4000 is connected to the output terminal OUT of the negative charge pump circuit 2000 to obtain the detection voltage corresponding to the output voltage.

[0120] The overvoltage control circuit 1000 is connected to the output terminal OUT of the voltage detection circuit 4000. The overvoltage control circuit 1000 is also connected to the output terminal OUT of the negative charge pump circuit 2000, so that the negative charge pump circuit 2000 outputs the first mode output voltage V1 based on the first clamping voltage CV1, or outputs the second mode output voltage V2 based on the second clamping voltage CV2.

[0121] The voltage detection circuit 4000 includes two voltage divider resistors. The first voltage divider resistor is connected to the input terminal of the negative charge pump circuit 2000, and the second voltage divider resistor is used to connect to a preset reference voltage. The connection terminal of the two voltage divider resistors is used to connect to the input terminal IN of the overvoltage control circuit 1000.

[0122] Another embodiment of this application also provides a storage device. Figure 11 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application, such as... Figure 11 As shown, the storage device includes a control device 10000 and a storage unit 20000; the output terminal OUT of the control device 10000 is connected to the drive terminal D of the storage unit 20000.

[0123] Another embodiment of this application provides an overvoltage control method for a negative charge pump circuit, applied to an overvoltage control circuit. Figure 12 A flowchart illustrating an overvoltage control method for a negative charge pump circuit provided in this application embodiment is shown below. Figure 12 As shown, the method includes:

[0124] Step 1201: When the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the first detection circuit and the second detection circuit in the overvoltage control circuit generate and output a high-level first logic trigger signal and a low-level second logic trigger signal, and output a first clamping voltage based on the high-level first logic trigger signal and the low-level second logic trigger signal, so that the negative charge pump circuit outputs the first mode output voltage based on the first clamping voltage.

[0125] Step 1202: When the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to the preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a second clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the second clamping voltage.

[0126] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An overvoltage control circuit, characterized in that, The overvoltage control circuit includes: an operational amplifier circuit, a first detection circuit, a second detection circuit, and a mode control circuit; The bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit. The first detection terminal of the operational amplifier circuit is connected to the first detection circuit, and the second detection terminal of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection terminal of the operational amplifier circuit is connected to the second detection circuit, and the second detection terminal of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal. The first detection circuit and the second detection circuit are respectively connected to the first control terminal and the second control terminal of the mode control circuit, so that the mode control circuit outputs a clamping voltage or a pull-down control voltage based on the first logic trigger signal and the second logic trigger signal. The output terminal of the mode control circuit is used to connect to the output terminal of the negative charge pump circuit through a Miller capacitor, pull down the control voltage, and cause the output voltage to decrease through the control voltage, so that the negative charge pump circuit outputs the output voltage of the first mode; or causes the negative charge pump circuit to output the output voltage of the second mode based on the clamping voltage.

2. The overvoltage control circuit according to claim 1, characterized in that, The mode control circuit includes: a timing control circuit and a mode switching circuit; The first input terminal and the second input terminal of the timing control circuit are respectively the first control terminal and the second control terminal of the mode control circuit, which are used to connect to the first detection circuit and the second detection circuit respectively. The first mode output terminal of the timing control circuit is connected to the first control terminal of the mode switching circuit to output a first control signal based on the first logic trigger signal. The second mode output terminal of the timing control circuit is connected to the second control terminal of the mode switching circuit to output a second control signal based on the second logic trigger signal. The input terminal of the mode switching circuit is the input terminal of the mode control circuit, and is used to connect to the output terminal of the operational amplifier circuit, so that the mode switching circuit outputs the clamping voltage or pulls down the control voltage based on the first control signal and the second control signal.

3. The overvoltage control circuit according to claim 1, characterized in that, The operational amplifier circuit includes: a first current mirror, an operational amplifier unit, a second current mirror, a third current mirror, and a fourth current mirror; The input terminal of the first current mirror is the bias terminal of the operational amplifier circuit, used to receive the preset bias current. The output terminal of the first current mirror is connected to the bias terminal of the operational amplifier unit. The positive input terminal and the negative input terminal of the operational amplifier unit are the positive input terminal and the negative input terminal of the operational amplifier circuit, respectively. The first output terminal of the operational amplifier unit is connected to the input terminal of the second current mirror, and the output terminal of the second current mirror is connected to the input terminal of the third current mirror. The second output terminal of the operational amplifier unit is connected to the input terminal of the fourth current mirror, and the series connection point of the output terminals of the third current mirror and the fourth current mirror is the output terminal of the operational amplifier circuit. The midpoint of the third current mirror and the second output terminal of the operational amplifier unit are respectively the first detection terminal and the second detection terminal of the operational amplifier circuit.

4. The overvoltage control circuit according to claim 1, characterized in that, The overvoltage control circuit further includes an output circuit, the input terminal of which is connected to the output terminal of the operational amplifier circuit, and the output terminal of which is connected to the control terminal of the clock circuit of the negative charge pump circuit, so as to output a drive signal to the clock circuit.

5. The overvoltage control circuit according to claim 1, characterized in that, The first detection circuit includes: a first PMOS and a first NMOS connected in series with their drains connected in series; the gates of the first PMOS and the first NMOS are respectively the first input terminal and the second input terminal of the first detection circuit, and the drains of the first PMOS and the first NMOS are the output terminals of the first detection circuit to output the first logic trigger signal. The second detection circuit includes: a second PMOS and a second NMOS with their drains connected in series; the gates of the second PMOS and the second NMOS are respectively the first input terminal and the second input terminal of the second detection circuit, and the drains of the second PMOS and the second NMOS are the output terminals of the second detection circuit to output the second logic trigger signal.

6. The overvoltage control circuit according to claim 2, characterized in that, The mode switching circuit includes: a first mode circuit and a second mode circuit; The control terminal of the first mode circuit is the first control terminal of the mode switching circuit, connected to the first mode output terminal of the timing control circuit, and used to receive the first control signal. The input terminal of the first mode circuit is the input terminal of the mode switching circuit, and used to connect to the output terminal of the operational amplifier circuit. The output terminal of the first mode circuit is grounded. The control terminal of the second mode circuit is the second control terminal of the mode switching circuit, connected to the second mode output terminal of the timing control circuit, and used to receive the second control signal. The input terminal of the second mode circuit is the input terminal of the mode switching circuit, and used to connect to the output terminal of the operational amplifier circuit. The output terminal of the second mode circuit is the output terminal of the mode switching circuit.

7. The overvoltage control circuit according to claim 6, characterized in that, The first mode circuit includes a third NMOS and a third PMOS, wherein the drain of the third NMOS and the source of the third PMOS are the input terminals of the first mode circuit, the gate of the third NMOS and the gate of the third PMOS are the control terminals of the first mode circuit, and the source of the third NMOS and the drain of the third PMOS are the output terminals of the first mode circuit. The second mode circuit includes a fourth NMOS and a fourth PMOS. The drain of the fourth NMOS and the source of the fourth PMOS are the input terminals of the second mode circuit. The gate of the fourth NMOS and the gate of the fourth PMOS are the control terminals of the second mode circuit. The source of the fourth NMOS and the drain of the fourth PMOS are the output terminals of the second mode circuit.

8. A control device, characterized in that, The control device includes: the overvoltage control circuit, the negative charge pump circuit, and the voltage detection circuit as described in any one of claims 1-7; The voltage detection circuit is connected to the output terminal of the negative charge pump circuit to obtain the detection voltage corresponding to the output voltage. The overvoltage control circuit is connected to the output terminal of the voltage detection circuit and is also connected to the output terminal of the negative charge pump circuit. It pulls down the control voltage, causing the output voltage to drop, so that the negative charge pump circuit outputs a first mode output voltage, or the negative charge pump circuit outputs a second mode output voltage based on the clamping voltage.

9. A storage device, characterized in that, The storage device includes at least the control device and storage unit as described in claim 8; The output of the control device is connected to the drive terminal of the storage unit.

10. An overvoltage control method for a negative charge pump circuit, characterized in that, The method, applied to the overvoltage control circuit according to any one of claims 1-7, comprises: When the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the overvoltage control circuit generates a high-level first logic trigger signal and a low-level second logic trigger signal, and pulls down the control voltage based on the high-level first logic trigger signal and the low-level second logic trigger signal, thereby causing the output voltage to drop and the negative charge pump circuit to output the first mode output voltage. When the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to the preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the clamping voltage.

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