Circuit structure for improving hot carrier effect

Abstract

The invention provides a circuit structure improving a hot carrier effect, the circuit structure comprises a first current mirror module, a second current mirror module, a load module, a first voltage degradation MOS tube and a second voltage degradation MOS tube, the first current mirror module comprises a first branch and a second branch, the input end of the first branch is connected with a first voltage, and the output end of the second branch is connected with a second voltage. The output end of the second branch is connected with second voltage through the current source, the input end of the second branch is connected with the first voltage, and the output end of the second branch is connected with the first end of the first voltage degradation MOS tube; the second current mirror module comprises a third branch and a fourth branch, the input end of the third branch is connected with the second end of the first voltage degradation MOS tube, the output end of the third branch is connected with the second voltage, the input end of the fourth branch is connected with the first end of the second voltage degradation MOS tube, and the output end of the fourth branch is connected with the second voltage. The current mirror circuit structure solves the problem that an existing current mirror circuit structure is large in hot carrier effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit structure for improving hot carrier effects. Background Art

[0002] In the design of integrated circuits, the current mirror circuit is a very important basic unit, which usually exists in the entire chip as a bias or signal processing sub-module.

[0003] The operating voltage of MCU home appliances is usually 5 V, and the maximum operating voltage is 5.5 V. In nanotechnology, when the source-drain voltage exceeds a certain value, it can be seen that the drain current is significantly greater than the source-drain current at high temperature and high pressure, and the excess current scatters to the substrate, resulting in inconsistent copy current in the current mirror circuit.

[0004] Figure 1 An existing current mirror circuit structure is shown. In the figure, the drain current of the device MN22C is greater than the source leakage current, resulting in inconsistency between the upper and lower currents. The resulting impact is that the current that is originally insensitive to voltage is affected by this, and the rate of change becomes larger under high voltage, increasing by about 1.37% at high temperature and high pressure, thus bringing challenges to high-precision analog design. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a circuit structure with improved hot carrier effect, so as to solve the problem of large hot carrier effect in the existing current mirror circuit structure.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a circuit structure with improved hot carrier effect, which includes: a first current mirror module, a second current mirror module, a load module and at least two voltage-degraded MOS transistors working in a linear region, and the two voltage-degraded MOS transistors are respectively a first voltage-degraded MOS transistor and a second voltage-degraded MOS transistor.

[0007] The first current mirror module includes a first branch and a second branch, each branch has at least two transistors, and the input end of the first branch is connected to the first voltage, and the output end thereof is connected to the second voltage through a current source, and the input end of the second branch is connected to the first voltage, and the output end thereof is connected to the first end of the first voltage-degenerating MOS tube;

[0008] The second current mirror module includes a third branch and a fourth branch, each branch has at least two transistors, and the input end of the third branch is connected to the second end of the first voltage-degenerated MOS tube, and the output end thereof is connected to the second voltage, the input end of the fourth branch is connected to the first end of the second voltage-degenerated MOS tube, and the output end of the fourth branch is connected to the second voltage;

[0009] The input end of the load module is connected to the first voltage, and the output end thereof is connected to the second end of the second voltage degradation MOS tube;

[0010] The third ends of the first voltage-degradation MOS tube and the second voltage-degradation MOS tube both receive a third voltage, and the base of the first voltage-degradation MOS tube receives the first voltage, and the base of the second voltage-degradation MOS tube receives the second voltage;

[0011] The type of the first voltage-degeneration MOS tube is the same as the type of the transistor used in the first current mirror module, and the type of the second voltage-degeneration MOS tube is the same as the type of the transistor used in the second current mirror module.

[0012] Optionally, the first current mirror module includes the first branch formed by a first PMOS tube, a second PMOS tube and a first resistor, and the second branch formed by a third PMOS tube and a fourth PMOS tube. In this case, the first voltage-degraded MOS tube is a PMOS tube, a first end of which is a source, a second end of which is a drain, and a third end of which is a gate, wherein:

[0013] The source of the first PMOS tube is connected to the first voltage as the input end of the first branch, the gate thereof is connected to the drain of the second PMOS tube and the gate of the third PMOS tube, the base thereof is connected to the first voltage, the drain thereof is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the first end of the first resistor, the gate thereof is connected to the second end of the first resistor and the gate of the fourth PMOS tube, the base thereof is connected to the first voltage, and the second end of the first resistor is connected to the second voltage through the current source;

[0014] The source and base of the third PMOS tube are connected to the first voltage, and the drain thereof is connected to the source of the fourth PMOS tube. The base of the fourth PMOS tube is connected to the first voltage, and the drain thereof is connected to the source of the first voltage-degraded MOS tube.

[0015] Optionally, the second current mirror module includes the third branch formed by the second resistor, the first NMOS tube and the second NMOS tube, and the fourth branch formed by the third NMOS tube and the fourth NMOS tube. In this case, the second voltage-degenerated MOS tube is an NMOS tube, a first end of which is a source, a second end of which is a drain, and a third end of which is a gate, wherein:

[0016] The first end of the second resistor serves as the input end of the third branch, and is connected to the drain of the first voltage-degenerated MOS transistor, and the second end of the second resistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the first end of the second resistor and the gate of the third NMOS transistor, the base of the first NMOS transistor is connected to the second voltage, the source of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the source of the first NMOS transistor and the gate of the fourth NMOS transistor, and the source and base of the second NMOS transistor are connected to the second voltage.

[0017] The drain of the third NMOS tube serves as the input end of the fourth branch, is connected to the source of the second voltage-degenerated MOS tube, has a base connected to the second voltage, and has a source connected to the drain of the fourth NMOS tube. The base and source of the fourth NMOS tube are connected to the second voltage.

[0018] Optionally, the load module includes a fifth PMOS tube, a sixth PMOS tube and a third resistor, the source and base of the fifth PMOS tube are connected to the first voltage, the gate thereof is connected to the drain of the sixth PMOS tube, the drain thereof is connected to the source of the sixth PMOS tube, the base of the sixth PMOS tube is connected to the first voltage, the drain thereof is connected to the first end of the third resistor, and the gate thereof is connected to the second end of the third resistor.

[0019] Optionally, a threshold voltage Vth of the first voltage-degraded MOS transistor and the second voltage-degraded MOS transistor is:

[0020]

[0021] Where Vth0 represents the threshold voltage without liner bias effect, γ represents the body effect coefficient, represents the Fermi potential, and VSB represents the source-substrate voltage.

[0022] Optionally, the current formula of the first voltage-degraded MOS transistor and the second voltage-degraded MOS transistor in the linear region is expressed as:

[0023]

[0024] Wherein, Id represents drain current, μ represents carrier mobility, Cox represents gate oxide capacitance density, W represents channel width, L represents channel length, Vgs represents gate-source voltage, Vth represents threshold voltage, and Vds represents drain-source voltage.

[0025] Optionally, a width-to-length ratio of the first voltage-degradation MOS transistor to the second voltage-degradation MOS transistor is greater than or equal to 2.

[0026] Optionally, the first voltage has a value range of 2V to 5.5V, and the second voltage has a value range of 2V to 5.5V.

[0027] As described above, the present invention improves the circuit structure of the hot carrier effect. By adding a voltage-degraded MOS tube at the drain end of the MOS tube with an excessively large source-drain voltage, the hot carrier effect caused by the excessively large source-drain voltage of the MOS tube can be reduced, and it can also be used as a switch to disable leakage protection for the path (disalbe indicates that the entire circuit is in a closed state). BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of an existing current mirror circuit with severe hot carrier effect.

[0029] Figure 2 It is a schematic diagram showing the circuit structure in which the hot carrier effect of the present invention is improved. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0032] like Figure 2 As shown, this embodiment provides a circuit structure that improves the hot carrier effect, which includes: a first current mirror module, a second current mirror module, a load module, and at least two voltage-degraded MOS transistors working in a linear region, and the two voltage-degraded MOS transistors are respectively a first voltage-degraded MOS transistor and a second voltage-degraded MOS transistor.

[0033] The first current mirror module includes a first branch and a second branch, each branch has at least two transistors, and the input end of the first branch is connected to the first voltage, and the output end thereof is connected to the second voltage through a current source, and the input end of the second branch is connected to the first voltage, and the output end thereof is connected to the first end of the first voltage-degenerating MOS tube;

[0034] The second current mirror module includes a third branch and a fourth branch, each branch has at least two transistors, and the input end of the third branch is connected to the second end of the first voltage-degenerated MOS tube, and the output end thereof is connected to the second voltage, the input end of the fourth branch is connected to the first end of the second voltage-degenerated MOS tube, and the output end of the fourth branch is connected to the second voltage;

[0035] The input end of the load module is connected to the first voltage, and the output end thereof is connected to the second end of the second voltage degradation MOS tube;

[0036] The third ends of the first voltage-degradation MOS tube and the second voltage-degradation MOS tube both receive a third voltage, and the base of the first voltage-degradation MOS tube receives the first voltage, and the base of the second voltage-degradation MOS tube receives the second voltage;

[0037] The type of the first voltage-degeneration MOS tube is the same as the type of the transistor used in the first current mirror module, and the type of the second voltage-degeneration MOS tube is the same as the type of the transistor used in the second current mirror module.

[0038] In this embodiment, by utilizing the substrate bias effect of the MOS tube, when the drain voltage of the transistors used in the first current mirror module and the second current mirror module is large, the threshold voltage of the first voltage-degradation MOS tube or the second voltage-degradation MOS tube added at the drain end of the transistor becomes larger, and by slightly adjusting the width-to-length ratio of the first voltage-degradation MOS tube and the second voltage-degradation MOS tube, the source-drain voltage can be reasonably distributed to the transistor, thereby greatly reducing the influence of the hot carrier effect.

[0039] Specifically, the first current mirror module includes the first branch formed by the first PMOS tube MP1, the second PMOS tube MP2 and the first resistor R1, and the second branch formed by the third PMOS tube MP3 and the fourth PMOS tube MP4. At this time, the first voltage-degenerated MOS tube is a PMOS tube MP0, whose first end is a source, whose second end is a drain, and whose third end is a gate, wherein:

[0040] The source of the first PMOS transistor MP1 is connected to the first voltage VCC as the input end of the first branch, the gate thereof is connected to the drain of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3, the base thereof is connected to the first voltage VCC, the drain thereof is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the first end of the first resistor R1, the gate thereof is connected to the second end of the first resistor R1 and the gate of the fourth PMOS transistor MP4, the base thereof is connected to the first voltage VCC, and the second end of the first resistor R1 is connected to the second voltage VSS through the current source I;

[0041] The source and base of the third PMOS transistor MP3 are connected to the first voltage VCC, and the drain is connected to the source of the fourth PMOS transistor MP4. The base of the fourth PMOS transistor MP4 is connected to the first voltage VCC, and the drain is connected to the source of the first voltage-degradation MOS transistor MP0.

[0042] Specifically, the second current mirror module includes the third branch formed by the second resistor R2, the first NMOS transistor MN1 and the second NMOS transistor MN2, and the fourth branch formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4. At this time, the second voltage-degenerated MOS transistor is an NMOS transistor MN0, whose first end is a source, whose second end is a drain, and whose third end is a gate, wherein:

[0043] The first end of the second resistor R2 serves as the input end of the third branch, and is connected to the drain of the first voltage-degenerated MOS transistor MP0. The second end of the second resistor R2 is connected to the drain of the first NMOS transistor MN1. The gate of the first NMOS transistor MN1 is connected to the first end of the second resistor R2 and the gate of the third NMOS transistor MN3. The base of the first NMOS transistor MN1 is connected to the second voltage VSS. The source of the second NMOS transistor MN2 is connected to the drain of the second NMOS transistor MN2. The gate of the second NMOS transistor MN2 is connected to the source of the first NMOS transistor MN1 and the gate of the fourth NMOS transistor MN4. The source and base of the second NMOS transistor MN2 are connected to the second voltage VSS.

[0044] The drain of the third NMOS transistor MN3 serves as the input end of the fourth branch, is connected to the source of the second voltage-degenerated MOS transistor MN0, has a base connected to the second voltage VSS, and has a source connected to the drain of the fourth NMOS transistor MN4. The base and source of the fourth NMOS transistor MN4 are connected to the second voltage VSS.

[0045] Specifically, the load module includes a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a third resistor R3, the source and base of the fifth PMOS tube MP5 are connected to the first voltage VCC, the gate thereof is connected to the drain of the sixth PMOS tube MP6, the drain thereof is connected to the source of the sixth PMOS tube MP6, the base of the sixth PMOS tube MP6 is connected to the first voltage VCC, the drain thereof is connected to the first end of the third resistor R3, and the gate thereof is connected to the second end of the third resistor R3.

[0046] In this embodiment, the source of the fifth PMOS transistor MP5 serves as the input end of the load module, and the second end of the third resistor R3 serves as the output end of the load module.

[0047] Specifically, the threshold voltage Vth of the first voltage-degraded MOS transistor and the second voltage-degraded MOS transistor is:

[0048]

[0049] Where Vth0 represents the threshold voltage without liner bias effect, γ represents the body effect coefficient, represents the Fermi potential, and VSB represents the source-substrate voltage.

[0050] Specifically, the current formula of the first voltage-degraded MOS tube and the second voltage-degraded MOS tube in the linear region is expressed as:

[0051]

[0052] Wherein, Id represents drain current, μ represents carrier mobility, Cox represents gate oxide capacitance density, W represents channel width, L represents channel length, Vgs represents gate-source voltage, Vth represents threshold voltage, and Vds represents drain-source voltage.

[0053] More specifically, a width-to-length ratio of the first voltage-degradation MOS transistor and the second voltage-degradation MOS transistor is greater than or equal to 2.

[0054] Specifically, the value range of the first voltage includes 2V~5.5V, and the value range of the second voltage is 2V~5.5V.

[0055] In summary, the circuit structure of the present invention improves the hot carrier effect. By adding a voltage-degraded MOS tube at the drain end of the MOS tube with excessive source-drain voltage, the hot carrier effect caused by the excessive source-drain voltage of the MOS tube can be reduced, and it can also be used as a switch to disable leakage protection for the path (disalbe means the overall circuit is closed). Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0056] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A circuit structure with improved hot carrier effect, characterized in that: It includes: A first current mirror module, a second current mirror module, a load module and at least two voltage-degraded MOS transistors working in a linear region, wherein the two voltage-degraded MOS transistors are respectively a first voltage-degraded MOS transistor and a second voltage-degraded MOS transistor. The first current mirror module includes a first branch and a second branch, each branch has at least two transistors, and the input end of the first branch is connected to the first voltage, and the output end thereof is connected to the second voltage through a current source, and the input end of the second branch is connected to the first voltage, and the output end thereof is connected to the first end of the first voltage-degenerating MOS tube; The second current mirror module includes a third branch and a fourth branch, each branch has at least two transistors, and the input end of the third branch is connected to the second end of the first voltage-degenerated MOS tube, and the output end thereof is connected to the second voltage, the input end of the fourth branch is connected to the first end of the second voltage-degenerated MOS tube, and the output end of the fourth branch is connected to the second voltage; The input end of the load module is connected to the first voltage, and the output end thereof is connected to the second end of the second voltage degradation MOS tube; The third ends of the first voltage-degradation MOS tube and the second voltage-degradation MOS tube both receive a third voltage, and the base of the first voltage-degradation MOS tube receives the first voltage, and the base of the second voltage-degradation MOS tube receives the second voltage; The type of the first voltage-degeneration MOS tube is the same as the type of the transistor used in the first current mirror module, and the type of the second voltage-degeneration MOS tube is the same as the type of the transistor used in the second current mirror module.

2. The circuit structure with improved hot carrier effect according to claim 1, characterized in that: The first current mirror module includes the first branch formed by the first PMOS tube, the second PMOS tube and the first resistor, and the second branch formed by the third PMOS tube and the fourth PMOS tube. In this case, the first voltage-degraded MOS tube is a PMOS tube, the first end of which is the source, the second end of which is the drain, and the third end of which is the gate, wherein: The source of the first PMOS tube is connected to the first voltage as the input end of the first branch, the gate thereof is connected to the drain of the second PMOS tube and the gate of the third PMOS tube, the base thereof is connected to the first voltage, the drain thereof is connected to the source of the second PMOS tube, the drain of the second PMOS tube is connected to the first end of the first resistor, the gate thereof is connected to the second end of the first resistor and the gate of the fourth PMOS tube, the base thereof is connected to the first voltage, and the second end of the first resistor is connected to the second voltage through the current source; The source and base of the third PMOS tube are connected to the first voltage, and the drain thereof is connected to the source of the fourth PMOS tube. The base of the fourth PMOS tube is connected to the first voltage, and the drain thereof is connected to the source of the first voltage-degraded MOS tube.

3. The circuit structure with improved hot carrier effect according to claim 2, characterized in that: The second current mirror module includes the third branch formed by the second resistor, the first NMOS tube and the second NMOS tube, and the fourth branch formed by the third NMOS tube and the fourth NMOS tube. In this case, the second voltage-degenerated MOS tube is an NMOS tube, whose first end is a source, whose second end is a drain, and whose third end is a gate, wherein: The first end of the second resistor serves as the input end of the third branch, and is connected to the drain of the first voltage-degenerated MOS transistor, and the second end of the second resistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the first end of the second resistor and the gate of the third NMOS transistor, the base of the first NMOS transistor is connected to the second voltage, the source of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the source of the first NMOS transistor and the gate of the fourth NMOS transistor, and the source and base of the second NMOS transistor are connected to the second voltage. The drain of the third NMOS tube serves as the input end of the fourth branch, is connected to the source of the second voltage-degenerated MOS tube, has a base connected to the second voltage, and has a source connected to the drain of the fourth NMOS tube. The base and source of the fourth NMOS tube are connected to the second voltage.

4. The circuit structure with improved hot carrier effect according to claim 1, characterized in that: The load module includes a fifth PMOS tube, a sixth PMOS tube and a third resistor, the source and base of the fifth PMOS tube are connected to the first voltage, the gate thereof is connected to the drain of the sixth PMOS tube, the drain thereof is connected to the source of the sixth PMOS tube, the base of the sixth PMOS tube is connected to the first voltage, the drain thereof is connected to the first end of the third resistor, and the gate thereof is connected to the second end of the third resistor.

5. The circuit structure with improved hot carrier effect according to claim 1, characterized in that: The threshold voltage Vth of the first voltage-degraded MOS transistor and the second voltage-degraded MOS transistor is: Where Vth0 represents the threshold voltage without liner bias effect, γ represents the body effect coefficient, represents the Fermi potential, and VSB represents the source-substrate voltage.

6. The circuit structure with improved hot carrier effect according to claim 5, characterized in that: The current formula of the first voltage-degraded MOS tube and the second voltage-degraded MOS tube in the linear region is expressed as: Wherein, Id represents drain current, μ represents carrier mobility, Cox represents gate oxide capacitance density, W represents channel width, L represents channel length, Vgs represents gate-source voltage, Vth represents threshold voltage, and Vds represents drain-source voltage.

7. The circuit structure with improved hot carrier effect according to claim 6, characterized in that: A width-to-length ratio of the first voltage-degradation MOS transistor and the second voltage-degradation MOS transistor is greater than or equal to 2.

8. The circuit structure with improved hot carrier effect according to any one of claims 1 to 7, characterized in that: The first voltage has a value range of 2V to 5.5V, and the second voltage has a value range of 2V to 5.5V.

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