Vehicle-mounted safety platform clock synchronization method and device for multi-core CPU and medium

Abstract

The invention relates to a vehicle-mounted safety platform clock synchronization method and device for a multi-core CPU and a medium, and the method comprises the steps: enabling an application core and a platform core in each CPU to keep clock synchronization through sharing a memory and utilizing inter-core communication when a first clock interrupt signal in each period is generated; enabling the platform cores of the other CPUs to keep clock synchronization with the platform core of the first CPU by directly connecting a serial port and utilizing communication between the CPUs; and through the TSN module, the other MPBs and the first MPB are kept in clock synchronization by utilizing communication between the MPBs. Compared with the prior art, clock synchronization among multiple cores in a single CPU, clock synchronization among multiple CPUs and clock synchronization among MPBs are controlled respectively, and clock synchronization of the vehicle-mounted safety platform is achieved.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization, and in particular to a method, device and medium for synchronizing the clock of a vehicle-mounted safety platform for a multi-core CPU. Background Art

[0002] With the rapid economic development, the flow of railway passenger and freight traffic is increasing day by day. Railway transportation is facing multiple challenges such as improving operational efficiency, ensuring passenger safety, and reducing environmental pollution. In order to meet these challenges, railway operators and equipment manufacturers are constantly developing and deploying more advanced train control systems to increase train speed while ensuring high safety and reliability.

[0003] The on-board safety platform is the core of the train control system. It is responsible for processing data from train sensors and IO acquisition boards, and monitoring the train's operating status in real time, including speed, braking system, door status, etc., to ensure that the train runs under safe conditions. Today's on-board platforms tend to be multi-core, which can handle multiple tasks at the same time and can use resources efficiently. The use of a multi-core CPU on-board platform can flexibly allocate different cores to handle different tasks according to different needs and functions, thereby improving system performance and providing faster data processing speeds and higher data throughput. At the same time, the multi-core CPU on-board platform integrates multiple computing resources on a single chip, greatly reducing the number of chips, which not only improves the efficiency of the chip, but also reduces the power consumption of the on-board system.

[0004] When it comes to the safety-critical functions of the train control system, the onboard platform must respond within strict time limits. In order to meet real-time requirements, its processing tasks are often periodic to ensure that the system can predict and guarantee the execution time of the task. For the onboard safety platform that uses a multi-core CPU, each core needs to handle different periodic tasks. If there is no accurate clock to ensure the accuracy and relevance of the data, the train control system will make wrong decisions. At the same time, the onboard platform often uses a two-by-two voting redundancy technology. If the clock is not synchronized between the boards, it is difficult to ensure the consistency of the input and output data, which will cause the train control system to operate at a downgraded level, greatly reducing the availability and reliability of the onboard safety platform. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a method, device and medium for clock synchronization of a vehicle-mounted safety platform for a multi-core CPU, so as to support clock synchronization of a multi-core CPU of a vehicle-mounted safety platform.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A method for synchronizing a clock of a vehicle-mounted safety platform for a multi-core CPU, the method comprising:

[0008] When the first clock interrupt signal of each cycle is generated, the application cores and platform cores in each CPU are synchronized by inter-core communication through shared memory; the platform cores of the remaining CPUs are synchronized by inter-CPU communication through direct serial ports; the remaining MPBs are synchronized by inter-MPB communication through the TSN module;

[0009] The platform core is any core in a multi-core CPU, the remaining cores are application cores, the first CPU is any CPU in an MPB, and the first MPB is any MPB among all MPBs.

[0010] Furthermore, the clock interrupt signal is generated by an FPGA in an MPU, and the board of the MPU includes an MPB.

[0011] Furthermore, each of the cycles is composed of the same number of the clock interrupt signals.

[0012] Furthermore, the main resources on the MPB include a channel module and a TSN module.

[0013] Furthermore, the channel module includes a multi-core CPU and an FPGA.

[0014] Furthermore, the process of inter-core communication includes:

[0015] When the first clock interrupt signal of each cycle is generated, the platform core in the CPU sends a Clock message to the application core in the CPU through shared memory, so that the application core re-accumulates the cycle clock count, updates the cycle number of the application main task and starts a new cycle, thereby maintaining clock synchronization with the platform core.

[0016] Furthermore, the process of inter-CPU communication includes:

[0017] When the first clock interrupt signal of each cycle is generated, the platform core of the first CPU is used to send a Clock message to the platform cores of the remaining CPUs through a direct serial port, so that the platform cores of the remaining CPUs re-accumulate the cycle clock count, update the cycle number of the application main task and start a new cycle, thereby maintaining clock synchronization with the platform core of the first CPU.

[0018] Furthermore, the process of inter-MPB communication includes:

[0019] When the first clock interrupt signal of each cycle is generated, the first MPB sends a SYNC message to the remaining MPBs through the TSN module. If the remaining MPBs are in a situation where clock synchronization is required when receiving the SYNC message, the running time and cycle number of the current cycle of the remaining MPBs are recorded and filled in the ACK message;

[0020] The SYNC message and the ACK message are used to calculate the period deviation between the first MPB and the remaining MPBs, and clock synchronization between the MPBs is performed according to the period deviation.

[0021] Furthermore, the scenarios where clock synchronization is required include:

[0022] The number of task cycles reaches the fixed number of cycles;

[0023] The interruption duration error of the first MPB is accumulated and counted until the accumulation reaches a threshold;

[0024] The interruption duration errors of the remaining MPBs are accumulated and counted until the accumulation reaches a threshold.

[0025] Furthermore, the cumulative counting process includes: when any platform core receives a clock interrupt signal, the difference between the time when the interrupt signal is received this time and the time when the interrupt signal was received last time is subtracted from the standard interrupt signal generation time interval to obtain the interrupt duration error, and the error is accumulated.

[0026] Furthermore, the formula for calculating the period deviation between the first MPB and the remaining MPBs includes:

[0027]

[0028] Where, diff is the period deviation, t c is the cycle length of the platform core main task, Δt1 is twice the message transmission delay, Δt2 is the running time of the remaining MPBs in the current cycle, N l is the cycle number of the platform core main task in the first MPB, N f It is the cycle number of the platform core main task in the remaining MPBs.

[0029] Furthermore, the value of Δt1 is the difference between the time when the first CPU of the first MPB receives the ACK message and the time when the first CPU of the first MPB sends the SYNC message.

[0030] Furthermore, the value of Δt2 is the difference between the time when the first CPU of the remaining MPBs receives the SYNC message and the start time of the current main task cycle of the first CPU of the remaining MPBs.

[0031] Furthermore, the process of performing clock synchronization between MPBs according to the period deviation includes:

[0032] Determine whether the cycle deviation is greater than the interval time of the clock interrupt signal. If so, continue to synchronize the clock. Otherwise, there is no need to synchronize the clock.

[0033] Determine whether the current cycle number of the first MPB is greater than the cycle numbers of the remaining MPBs recorded in the ACK message. If so, add 1 to the cycle clock count of the remaining MPBs, that is, notify the remaining MPBs to add 1 to the cycle clock count. Otherwise, continue with the subsequent process.

[0034] Determine whether half of the difference between the time when the first CPU of the first MPB receives the ACK message and the time when the first CPU of the first MPB sends the SYNC message is greater than the running time of the current cycle of the remaining MPBs recorded in the ACK message; if so, add 1 to the cycle clock count of the remaining MPBs, that is, notify the remaining MPBs to add 1 to the cycle clock count; otherwise, subtract 1 from the cycle clock count of the remaining MPBs, that is, notify the remaining MPBs to subtract 1 from the cycle clock count.

[0035] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the above-mentioned method for synchronizing the clock of a vehicle-mounted safety platform for a multi-core CPU are implemented.

[0036] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the above-mentioned method for synchronizing the clock of a vehicle-mounted safety platform for a multi-core CPU.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] 1. The present invention controls the clock synchronization between multiple cores in a single CPU, the clock synchronization between multiple CPUs in an MPB, and the clock synchronization between MPBs from small to large, and reduces the clock synchronization error in a layered nested manner to achieve the clock synchronization of the vehicle safety platform;

[0039] 2. In the present invention, multiple MPBs use TSN as the medium and adjust and synchronize the clocks through the confirmation mechanism of SYNC and ACK messages. The clock deviation between the MPBs is kept within an allowable range, which provides a guarantee for the hot standby redundancy of the vehicle platform and increases the availability of the platform. At the same time, the clock adjustment between the MPBs does not need to be performed every cycle, which reduces the burden on the TSN bus and the main processing tasks and improves the data processing efficiency of the vehicle safety platform.

[0040] 3. In the multi-core CPU of the present invention, the platform core sends clock messages to the other two application cores through inter-core communication to achieve clock synchronization of multi-core processing tasks. The clock message transmission is performed in the shared memory inside the CPU, which ensures that the deviation of the clocks between tasks is very small and has good scalability.

[0041] 4. In the present invention, within the MPB, the first CPU sends clock messages to the other CPUs through the direct serial port every cycle to achieve clock synchronization between channels. The internal direct serial port has the advantages of low transmission delay and low bit error rate. The clock synchronization is performed between the channels every cycle, which provides a guarantee for the vehicle-mounted platform to adopt the two-out-of-two voting technology and ensures the reliability of the platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a structural diagram of the main computing board of the present invention;

[0043] Figure 2 This is a diagram of the multi-core CPU structure in the channel module of the present invention;

[0044] Figure 3 This is a CPU structure diagram of a dual-channel module in an MPB of the present invention;

[0045] Figure 4 This is a processing flow chart of clock synchronization between MPBs of the present invention. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] Example 1

[0048] This embodiment intends to disclose a clock synchronization method for a multi-core CPU in a vehicle safety platform, and provide a clock synchronization solution to support the clock synchronization of a multi-core CPU in a vehicle safety platform.

[0049] In this embodiment, the clock synchronization of the vehicle safety platform is mainly aimed at the cycle start time of the MPU (main processing unit) in the system. The MPU board includes the MPB (main processing board), such as Figure 1 As shown, the main resources on MPB are:

[0050] CH1 module (channel 1 module): includes 1 CPU and 1 FPGA (programmable logic device). The CPU has 3 cores. The platform core is used to run the MPU software, and the other two application cores are used to run the application software.

[0051] CH2 module (channel 2 module): includes 1 CPU and 1 FPGA (programmable logic device). The CPU has 3 cores. The platform core is used to run the MPU software, and the other two application cores are used to run the application software.

[0052] TSN module: used for communication between MPB and other boards.

[0053] The FPGAs of different channel modules use the MSI (Message Signaled Interrupt) communication mechanism to transmit messages, while the FPGA and CPU in the same channel module are connected to the local bus through GPIO (General Purpose Input / Output), and the TSN module is connected to the channel module through RGMII (Reduced Gigabit Media Independent Interface, data interface).

[0054] The scenario used in this embodiment is a train control system that adopts a two-by-two-out-of-two system. In the train control system that adopts a two-by-two-out-of-two system, the clock synchronization method of the on-board safety platform of the multi-core CPU needs to implement clock synchronization including: clock synchronization between multiple cores in a single CPU in a channel module, clock synchronization between CPUs of dual channel modules in an MPB, and clock synchronization between MPBs.

[0055] The three clock synchronizations that need to be implemented are all performed when the first clock interrupt signal of each cycle is generated. The clock interrupt signal is generated by the FPGA. The FPGA of each channel of the MPU tick A safety clock interrupt signal is issued, and the MPU will count the interrupt duration for error checking. Whenever the main processing task on the platform core receives the interrupt signal, it accumulates the cycle clock count of the main task, and clears and accumulates again after reaching a fixed count value N, thereby controlling the task cycle length.

[0056] The platform core is any core in a multi-core CPU, the remaining cores are application cores, the first CPU is any CPU in an MPB, and the first MPB is any MPB among all MPBs.

[0057] The structure of multiple cores in a single CPU in the channel module is as follows Figure 2 As shown in the figure, the clock synchronization process between multiple cores in a single CPU in a channel module includes:

[0058] When the first clock interrupt signal of each cycle is generated, the application core and the platform core in the CPU are synchronized through shared memory and inter-core communication.

[0059] Among them, a shared memory that can be accessed by multiple cores is allocated in the CPU. The specific process of the inter-core communication includes using the platform core in the CPU to send a Clock message to the application core in the CPU through the shared memory when the first clock interrupt signal of each cycle is generated, so that the application core re-accumulates the cycle clock count, updates the cycle number of the application main task and starts a new cycle, thereby maintaining clock synchronization with the platform core.

[0060] The specific structure of the dual-channel module CPU in MPB is as follows: Figure 3 As shown in the figure, the clock synchronization process between the dual-channel module CPUs in the MPB includes:

[0061] When the first clock interrupt signal of each cycle is generated, the platform cores of the remaining CPUs are synchronized with the platform core of the first CPU by using the direct serial port (UART, Universal Asynchronous Receiver and Transmitter) and inter-CPU communication;

[0062] The process of communication between CPUs includes:

[0063] When the first clock interrupt signal of each cycle is generated, the platform core of the first CPU is used to send a Clock message to the platform cores of the remaining CPUs through a direct serial port, so that the platform cores of the remaining CPUs re-accumulate the cycle clock count, update the cycle number of the application main task and start a new cycle, thereby maintaining clock synchronization with the platform core of the first CPU.

[0064] The clock synchronization process between MPBs includes:

[0065] When the first clock interrupt signal of each cycle is generated, the first MPB sends a SYNC message to the remaining MPBs through the TSN module. If the remaining MPBs are in a situation where clock synchronization is required when receiving the SYNC message, the running time and cycle number of the current cycle of the remaining MPBs are recorded and filled in the ACK message;

[0066] Calculate the period deviation between the first MPB and the remaining MPBs using the SYNC message and the ACK message, and perform clock synchronization between the MPBs based on the period deviation;

[0067] Scenarios where clock synchronization is required include:

[0068] The number of task cycles reaches the fixed number of cycles;

[0069] The interruption duration error of the first MPB is accumulated and counted until the accumulation reaches a threshold;

[0070] The interruption duration errors of the remaining MPBs are accumulated and counted until the accumulation reaches a threshold;

[0071] The cumulative counting process includes: when any platform core receives a clock interrupt signal, the difference between the time when the interrupt signal is received this time and the time when the interrupt signal is received last time is subtracted from the standard interrupt signal time interval to obtain the interrupt duration error, and the error is accumulated;

[0072] The formula for calculating the period deviation of the first MPB from the remaining MPBs includes:

[0073]

[0074] Where, diff is the period deviation, t c is the period length of the platform core main task, Δt1 is twice the message transmission delay, N l is the period number of the platform core main task in the first MPB, N f is the period sequence number of the platform core main task in the remaining MPBs;

[0075] In the formula, the value of Δt1 is equal to the difference between the time when the first CPU of the first MPB receives the ACK message and the time when the first CPU of the first MPB sends the SYNC message;

[0076] The value of Δt2 is equal to the difference between the time when the first CPU of the remaining MPB receives the SYNC message and the time when the current main task cycle of the first CPU of the remaining MPB starts.

[0077] If the clock synchronization process between the above-mentioned MPBs is applied to an actual two-by-two train control system, then during the operation of the on-board platform, the clock synchronization of all MPBs is based on a manually selected MPB, i.e., the first MPB mentioned above. The clocks of the remaining MPBs are adjusted according to the deviation from the clock of this MPB. This MPB is referred to as MPB_Leader in the following example, and the remaining MPBs are referred to as MPB_Follower.

[0078] The processing flow of clock synchronization between MPBs is as follows: Figure 4 As shown:

[0079] Step 1: MPB_Leader sends a SYNC message to MPB_Follower;

[0080] Step 2: After receiving SYNC, MPB_Follower records the running time and cycle number of the current cycle;

[0081] Step 3: MPB_Follower fills the running time and cycle number in the ACK message to reply to MPB_Leader;

[0082] Step 4: MPB_Leader calculates the message transmission delay based on the received ACK message time;

[0083] Step 5: Calculate the cycle deviation based on the message transmission delay and the running time of MPB_Follower;

[0084] Step 6: Determine whether the cycle deviation is greater than one T tick If it is greater than, go to the next step, otherwise MPB_Follower does not need to adjust the clock;

[0085] Step 7: MPB_Leader determines whether its current cycle number is greater than the cycle number of MPB_Follower recorded in the ACK message. If so, it notifies the MPB_Follower to increase the cycle clock count by 1, otherwise it goes to the next step;

[0086] Step 8: Determine whether the message transmission delay is greater than the running time of the MPB_Follower in the current cycle recorded in the ACK message. If so, notify the MPB_Follower to increase the cycle clock count by 1; otherwise, notify the MPB_Follower to decrease the cycle clock count by 1.

[0087] Example 2

[0088] Based on Example 1, this embodiment provides an electronic device, including: one or more processors and a memory, wherein the memory stores one or more programs, and the one or more programs include instructions for executing the aforementioned vehicle-mounted safety platform clock synchronization method for a multi-core CPU.

[0089] At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the clock synchronization method for the vehicle-mounted safety platform for multi-core CPUs. Of course, in addition to the software implementation, the present invention does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0090] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0091] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0092] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for synchronizing a clock of a multi-core CPU vehicle safety platform, characterized in that: The method comprises: When the first clock interrupt signal of each cycle is generated, the application cores and platform cores in each CPU are synchronized by inter-core communication through shared memory; the platform cores of the remaining CPUs are synchronized by inter-CPU communication through direct serial ports; the remaining MPBs are synchronized by inter-MPB communication through the TSN module; The platform core is any core in a multi-core CPU, the remaining cores are application cores, the first CPU is any CPU in an MPB, and the first MPB is any MPB among all MPBs.

2. The method for synchronizing a clock of a vehicle-mounted safety platform for a multi-core CPU according to claim 1, characterized in that: The clock interrupt signal is generated by the FPGA in the MPU, and the board of the MPU includes an MPB.

3. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 2, characterized in that: Each of the cycles is composed of the same number of the clock interrupt signals.

4. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 2, characterized in that: The main resources on the MPB include channel modules and TSN modules.

5. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 4, characterized in that: The channel module includes a multi-core CPU and an FPGA.

6. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 1, characterized in that: The inter-core communication process includes: When the first clock interrupt signal of each cycle is generated, the platform core in the CPU sends a Clock message to the application core in the CPU through shared memory, so that the application core re-accumulates the cycle clock count, updates the cycle number of the application main task and starts a new cycle, thereby maintaining clock synchronization with the platform core.

7. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 1, characterized in that: The process of inter-CPU communication includes: When the first clock interrupt signal of each cycle is generated, the platform core of the first CPU is used to send a Clock message to the platform cores of the remaining CPUs through a direct serial port, so that the platform cores of the remaining CPUs re-accumulate the cycle clock count, update the cycle number of the application main task and start a new cycle, thereby maintaining clock synchronization with the platform core of the first CPU.

8. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 1, characterized in that: The process of inter-MPB communication includes: When the first clock interrupt signal of each cycle is generated, the first MPB sends a SYNC message to the remaining MPBs through the TSN module. If the remaining MPBs are in a situation where clock synchronization is required when receiving the SYNC message, the running time and cycle number of the current cycle of the remaining MPBs are recorded and filled in the ACK message; The SYNC message and the ACK message are used to calculate the period deviation between the first MPB and the remaining MPBs, and clock synchronization between the MPBs is performed according to the period deviation.

9. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 8, characterized in that: The scenarios where clock synchronization is required include: The number of task cycles reaches the fixed number of cycles; The interruption duration error of the first MPB is accumulated and counted until the accumulation reaches a threshold; The interruption duration errors of the remaining MPBs are accumulated and counted until the accumulation reaches a threshold.

10. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 9, characterized in that: The cumulative counting process includes: when any platform core receives a clock interrupt signal, the difference between the time when the interrupt signal is received this time and the time when the interrupt signal was received last time is subtracted from the standard interrupt signal generation time interval to obtain the interrupt duration error, and the error is accumulated.

11. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 8, characterized in that: The formula for calculating the period deviation between the first MPB and the remaining MPBs includes: Where, diff is the period deviation, t c is the cycle length of the platform core main task, Δt1 is twice the message transmission delay, Δt2 is the running time of the remaining MPBs in the current cycle, N l is the cycle number of the platform core main task in the first MPB, N f It is the cycle number of the platform core main task in the remaining MPBs.

12. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 11, characterized in that: The value of Δt1 is the difference between the time when the first CPU of the first MPB receives the ACK message and the time when the first CPU of the first MPB sends the SYNC message.

13. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 11, characterized in that: The value of Δt2 is the difference between the time when the first CPU of the remaining MPBs receives the SYNC message and the start time of the current main task cycle of the first CPU of the remaining MPBs.

14. The method for synchronizing a vehicle-mounted safety platform clock for a multi-core CPU according to claim 1, characterized in that: The process of performing clock synchronization between MPBs according to the period deviation includes: Determine whether the cycle deviation is greater than the interval time of the clock interrupt signal. If so, continue to synchronize the clock. Otherwise, there is no need to synchronize the clock. Determine whether the current cycle number of the first MPB is greater than the cycle numbers of the remaining MPBs recorded in the ACK message. If so, add 1 to the cycle clock count of the remaining MPBs. Otherwise, continue with the subsequent process. Determine whether half of the difference between the time when the first CPU of the first MPB receives the ACK message and the time when the first CPU of the first MPB sends the SYNC message is greater than the running time of the current cycle of the remaining MPBs recorded in the ACK message; if so, add 1 to the cycle clock count of the remaining MPBs; otherwise, subtract 1 from the cycle clock count of the remaining MPBs.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the vehicle-mounted safety platform clock synchronization method for a multi-core CPU as described in any one of claims 1-14 are implemented.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the on-board safety platform clock synchronization method for a multi-core CPU are implemented as described in any one of claims 1 to 14.

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