NAND FLASH bad block management method, system and device and flash memory

Abstract

The invention discloses a NAND FLASH bad block management method, system and device and a flash memory. The method comprises the following steps: acquiring corresponding storage blocks according to logic addresses; whether the storage block is a bad block or not is judged, and the bad block is a storage block with a poor storage function; if the storage block is a non-bad block, keeping the logic address of the storage block unchanged; if the storage block is a bad block, the logic address of the bad block is exchanged with the logic address of a preset replacement storage block, and the preset replacement storage block is the storage block which is low in use frequency and good in storage function. According to the method and the device, the logical address of the bad block is replaced with the logical address of the preset replacement storage block, so that the use frequency of the bad block is reduced, the NAND FLASH with the bad block can reach the production standard, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and in particular to a NAND FLASH bad block management method, system, device and flash memory. Background Art

[0002] With the rapid development of storage technology, memory has been widely used in various electronic devices. NAND FLASH, as a non-volatile memory, is widely used due to its small size, low power consumption, fast read and write speed and other advantages. The storage structure of NAND FLASH is composed of multiple storage blocks. Therefore, during the production or long-term use of NAND FLASH, some storage blocks will have poor storage function, making these storage blocks bad blocks. In the production test of NAND FLASH, if bad blocks appear, NAND FLASH will be treated as bad blocks, which will significantly reduce the yield of NAND FLASH. If you want to make NAND FLASH with bad blocks meet the production standards, you need to manage the bad blocks of NAND FLASH.

[0003] The existing NAND FLASH bad block management method is to add additional virtual blocks inside the NAND FLASH to physically repair the bad blocks so that the NAND FLASH with bad blocks meets the production standard. However, the addition of virtual blocks causes the problem of high NAND FLASH production cost.

[0004] Therefore, there is still an urgent need for a method that can reduce the production cost of NAND FLASH. Summary of the invention

[0005] The main purpose of the present invention is to provide a NAND FLASH bad block management method, system, device and host to solve the existing defect of adding additional virtual blocks inside the NAND FLASH to repair the bad blocks in a physical way, which has high production costs.

[0006] To achieve the above object, the present invention proposes a NAND FLASH bad block management method, the NAND FLASH bad block management method comprising:

[0007] Obtain corresponding storage blocks according to each logical address;

[0008] Determining whether the storage block is a bad block, wherein the bad block is a storage block with poor storage function;

[0009] If the storage block is not a bad block, the logical address of the storage block is maintained unchanged;

[0010] If the storage block is a bad block, the logical address of the bad block is exchanged with the logical address of a preset replacement storage block, wherein the preset replacement storage block is a storage block with low usage frequency and good storage function.

[0011] In some embodiments, the NAND FLASH includes a latch block, and the latch block includes a plurality of latches; before exchanging the logical address of the bad block with the logical address of the preset replacement storage block, the method further includes:

[0012] Determining whether there is an idle latch in the latch block;

[0013] When the idle latch exists in the latch block, the logical address of the bad block is written into the idle latch.

[0014] In some embodiments, exchanging the logical address of the bad block with the logical address of a preset replacement storage block includes:

[0015] Obtaining the logical address of the bad block;

[0016] Assigning the logical address of the bad block to the preset replacement storage block, and obtaining the logical address of the preset replacement storage block;

[0017] The logical address of the preset replacement storage block is assigned to the bad block.

[0018] In some embodiments, after determining whether there is an idle latch in the latch block, the method further includes:

[0019] When the idle latch does not exist in the latch block, the logic address of the bad block is written into the idle latch after waiting for the idle latch to exist in the latch block.

[0020] In some embodiments, determining whether the storage block is a bad block includes:

[0021] Erasing original data of the storage block and writing test data into the storage block;

[0022] Reading the storage block to obtain read data, and determining whether the read data is consistent with the test data;

[0023] If the read data is consistent with the test data, determining that the storage block is a non-bad block;

[0024] If the read data is inconsistent with the test data, the storage block is determined to be a bad block.

[0025] In some embodiments, the NAND FLASH further includes an information block; before acquiring the corresponding storage block according to each logical address, the method further includes:

[0026] Acquire a bad block address from the information block, wherein the bad block address is a logical address of an initial bad block, and the initial bad block is a storage block with poor storage function that occurs during NAND FLASH production testing;

[0027] The bad block address is exchanged with the logical address of the preset replacement storage block.

[0028] In some embodiments, before determining whether the storage block is a bad block, the method further includes:

[0029] Sort the logical addresses corresponding to the storage blocks of the NAND FLASH in ascending order;

[0030] The determining whether the storage block is a bad block comprises:

[0031] Whether each of the storage blocks is a bad block is determined in sequence according to the ascending sorting.

[0032] The present invention also proposes a NAND FLASH bad block management system, which includes a management module and multiple storage blocks; the NAND FLASH bad block management system can execute any one of the above-mentioned NAND FLASH bad block management methods.

[0033] The present invention also provides a NAND FLASH bad block management device, comprising:

[0034] at least one processor; and,

[0035] a memory communicatively connected to the at least one processor; wherein,

[0036] The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the above-mentioned methods for managing NAND FLASH bad blocks.

[0037] The present invention further provides a flash memory, comprising a flash memory body and the NAND FLASH bad block management system as described above; the management module and the plurality of storage blocks are both arranged in the flash memory body.

[0038] The present invention sets a storage block with low usage frequency and good storage function inside a NAND FLASH as a preset replacement storage block, thereby replacing the logical address of a bad block with the logical address of the preset replacement storage block; when the NAND FLASH is in use, the usage frequency of the bad block becomes the usage frequency of the preset replacement storage block; the usage frequency of the bad block is reduced, so that the NAND FLASH with bad blocks can meet the production standard without increasing virtual blocks, thereby reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a process for managing a NAND FLASH bad block according to the present invention;

[0040] Figure 2 Another schematic diagram of the process of managing a NAND FLASH bad block according to the present invention;

[0041] Figure 3 Another schematic diagram of the process of managing a NAND FLASH bad block according to the present invention;

[0042] Figure 4 Another schematic diagram of the process of managing a NAND FLASH bad block according to the present invention;

[0043] Figure 5 Another schematic diagram of the process of managing a NAND FLASH bad block according to the present invention;

[0044] Figure 6 It is a structural schematic diagram of the management system of NAND FLASH bad blocks of the present invention;

[0045] Figure 7 It is a schematic diagram of the structure of a NAND FLASH bad block management device according to an embodiment of the present invention.

[0046] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0047] The scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0049] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0050] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0051] To achieve the above object, the present invention proposes a NAND FLASH bad block management method, the NAND FLASH bad block management method comprising:

[0052] Step S110, obtaining a corresponding storage block according to each logical address;

[0053] Step S120, determining whether the storage block is a bad block, wherein a bad block is a storage block with poor storage function;

[0054] Step S130, if the storage block is not a bad block, the logical address of the storage block is maintained unchanged;

[0055] Step S140: If the storage block is a bad block, the logical address of the bad block is exchanged with the logical address of a preset replacement storage block, wherein the preset replacement storage block is a storage block with low usage frequency and good storage function.

[0056] In this embodiment, refer to Figure 1 and Figure 6The NAND FLASH bad block management method is applied to the NAND FLASH bad block management system. Wherein, NAND FLASH may refer to SPI NAND Flash (Serial Peripheral Interface NAND Flash). The NAND FLASH bad block management system may include a management module and a plurality of storage blocks, wherein the storage block and the preset replacement storage block in this embodiment are Figure 6 In the illustrations, storage blocks are used for illustration. In this embodiment, the execution subject of the method steps is the management module.

[0057] It can be understood that in this embodiment, the preset replacement storage block is a storage block with low usage frequency and good storage function; the preset replacement storage block is obtained by investigating and counting the usage of a large number of NAND FLASH. Of course, the preset replacement storage block can be obtained in other ways, for example: through market surveys in various ways, and the various ways may include investigating NAND FLASH in the second-hand market, returning visits to users who purchase and use NAND FLASH, sending questionnaires to users who use NAND FLASH, etc.

[0058] The management module first obtains each logical address, and then obtains the storage block corresponding to each logical address according to each logical address.

[0059] When the management module obtains the storage block corresponding to each logical address, it will test the storage block to determine whether the storage block is a bad block, wherein the bad block is a storage block with poor storage function.

[0060] If the management module determines that the storage block is not a bad block, the logical address of the storage block will be maintained unchanged. If the storage block is a bad block, the logical address of the bad block will be exchanged with the logical address of the preset replacement storage block; wherein the preset replacement storage block is a storage block with low usage frequency and good storage function. After the logical address of the bad block is exchanged with the logical address of the preset replacement storage block, the logical address of the preset replacement storage block can point to the bad block, so that the frequency of use of the bad block can be reduced during the use of the NAND FLASH, so that the NAND FLASH with bad blocks can meet the production standards and reduce production costs.

[0061] Among them, in NAND FLASH, the occurrence of bad blocks is unavoidable. The causes of bad blocks can be roughly divided into two types: one is caused during the manufacturing of the storage block, and the other is caused during the use of the storage block; for example:

[0062] The causes during manufacturing may be: During the manufacturing process of the memory block, due to the complexity of the semiconductor manufacturing process, physical defects may occur, thus forming bad blocks; for example: During the photolithography, etching, doping and other processes of the memory block, tiny dust particles may fall on the surface of the memory block, causing damage to the memory block structure; these damaged memory blocks may not be able to store or read data normally, thus forming bad blocks.

[0063] The damage may be caused during use: In the first case, the storage block may be affected by electrical stress and thermal stress; excessive voltage or current may break through the insulation layer of the storage block, causing damage to the storage block, thus forming a bad block. In the second case, the long-term high temperature environment or frequent temperature changes of the storage block may also cause the internal material to expand or contract, causing physical damage, thus forming a bad block. In the third case, NAND FLASH has a limited number of erase and write cycles (P / E Cycles, Program / Erase Cycles); each data write and erase operation will cause a certain amount of wear on the storage block; as the number of erase and write times increases, the insulation layer of the storage block will gradually become thinner, which may eventually cause the storage block to fail, thus forming a bad block.

[0064] This embodiment can manage bad blocks that appear during production testing of NAND FLASH; without adding virtual blocks, NAND FLASH with bad blocks can meet production standards, thereby reducing production costs. It can also manage bad blocks that appear during long-term use of NAND FLASH, reduce the probability of NAND FLASH calling bad blocks when in use, thereby reducing the probability of data errors that appear during use of NAND FLASH, thereby extending the service life of NAND FLASH.

[0065] In some embodiments, the NAND FLASH includes a latch block, which includes a plurality of latches; before exchanging the logical address of the bad block with the logical address of the preset replacement storage block, the method further includes:

[0066] Step S150, determining whether there is an idle latch in the latch block;

[0067] Step S151, when there is an idle latch in the latch block, write the logical address of the bad block into the idle latch.

[0068] In this embodiment, refer to Figure 2Before executing step S140, the management module must first determine whether there is an idle latch in the NAND FLASH. The NAND FLASH includes a latch block, and the latch block includes multiple latches. The management module determines whether there is an idle latch in the latch block; wherein the idle latch is a latch in an idle state. When there is an idle latch in the latch block, the management module will write the logical address of the bad block into the idle latch.

[0069] In some embodiments, exchanging the logical address of the bad block with the logical address of the preset replacement storage block in the foregoing step includes:

[0070] Step S160, obtaining the logical address of the bad block;

[0071] Step S161, assigning the logical address of the bad block to a preset replacement storage block, and obtaining the logical address of the preset replacement storage block;

[0072] Step S162, assigning the logical address of the preset replacement storage block to the bad block.

[0073] In this embodiment, refer to Figure 3 , after the management module writes the logical address of the bad block into the idle latch. The logical address of the bad block is stored in the idle latch. The management module can directly obtain the logical address of the bad block from the idle latch. Then the management module assigns the logical address of the bad block to the preset replacement storage block, so that the logical address of the bad block points to the preset replacement storage block; the management module also obtains the logical address of the preset replacement storage block at the same time. Finally, the management module assigns the logical address of the preset replacement storage block to the bad block, so that the logical address of the preset replacement storage block points to the bad block. Since the erase and read operation of NAND FLASH is determined according to the logical address selection storage block; the use frequency of the preset replacement storage block is low, which means that the call frequency of the logical address of the preset replacement storage block is low. When the logical address of the preset replacement storage block points to the bad block, the use frequency of the bad block will be reduced, thereby reducing the probability of data errors when the NAND FLASH is erased and read.

[0074] In some embodiments, after determining whether there is an idle latch in the latch block, the method further includes:

[0075] When there is no free latch in the latch block, the logic address of the bad block is written into the free latch after waiting for the free latch to exist in the latch block.

[0076] In this embodiment, when there is no free latch in the latch block, the management module will not proceed to the next step, but wait for the latch block to have a free latch. After waiting for the latch block to have a free latch, the management module will write the logical address of the bad block into the free latch.

[0077] In some embodiments, the foregoing step of determining whether a storage block is a bad block includes:

[0078] Step S170, erasing the original data of the storage block and writing the test data into the storage block;

[0079] Step S171, reading the storage block to obtain read data, and determining whether the read data is consistent with the test data;

[0080] Step S172, if the read data is consistent with the test data, the storage block is determined to be a good block;

[0081] Step S173: if the read data is inconsistent with the test data, the storage block is determined to be a bad block.

[0082] In this embodiment, refer to Figure 4 When the management module executes step S120, it determines whether the storage block is a bad block by judging the erase operation of the storage block. The management module first erases the original data of the storage block, wherein the original data refers to the data stored in the storage block before the erase operation is performed. After the original data is completely erased, the test data needs to be written into the storage block, wherein the test data can be custom data.

[0083] After writing the test data into the storage block, the management module also needs to read the storage block to obtain the read data. After obtaining the read data, the read data will be compared with the test data to determine whether the read data is consistent with the test data.

[0084] If the management module determines that the read data is consistent with the test data, it will determine that the storage block is a normal block. At this time, it can be determined that there is no problem with the storage block. If it is determined that the read data is inconsistent with the test data, it will determine that the storage block is a bad block. At this time, it can be determined that there is a problem with the storage block.

[0085] In some embodiments, the NAND FLASH further includes an information block; before obtaining the corresponding storage block according to each logical address, the above also includes:

[0086] Step S180, obtaining a bad block address from the information block, wherein the bad block address is a logical address of an initial bad block, and the initial bad block is a storage block with poor storage function that occurs during NAND FLASH production testing;

[0087] Step S181, swapping the bad block address with the logical address of a preset replacement storage block.

[0088] In this embodiment, refer to Figure 5Before executing step S110, the management module will first obtain the bad block address from the information block. NAND FLASH also includes an information block. Among them, the bad block address is the logical address of the initial bad block, and the initial bad block is a storage block with poor storage function that appears during the production test of NAND FLASH. When producing NAND FLASH, a small number of bad blocks will appear. These bad blocks are determined as initial bad blocks. When the NAND FLASH is produced, the initial bad blocks can be tested out; after the initial bad block is tested out, the logical address (bad block address) corresponding to the initial bad block will be stored in the information block.

[0089] The management module obtains the bad block address from the information block and then directly exchanges the bad block address with the logical address of the preset replacement storage block, so that the NAND FLASH can avoid the detection of the initial bad block during use, and improve the management efficiency of the NAND FLASH bad block.

[0090] In some embodiments, before determining whether a storage block is a bad block, the method further includes:

[0091] Sort the logical addresses corresponding to each storage block of the NAND FLASH in ascending order;

[0092] Determine whether a storage block is a bad block, including:

[0093] According to the ascending sorting, it is determined in sequence whether each storage block is a bad block.

[0094] In this embodiment, the management module needs to sort the logical addresses before executing step S120. The management module sorts the logical addresses corresponding to each storage block of the NAND FLASH in ascending order, so that subsequent judgments can be performed one by one in an orderly manner. The management module can judge whether each storage block is a bad block in order according to the ascending order; judging each storage block one by one in an orderly manner can prevent confusion in judging each storage block (some storage blocks are judged multiple times, and some storage blocks are not judged), and improve the accuracy of judging whether a storage block is a bad block.

[0095] The present invention sets a storage block with low usage frequency and good storage function inside the NAND FLASH as a preset replacement storage block, thereby replacing the logical address of the bad block with the logical address of the preset replacement storage block; the bad blocks that appear in the NAND FLASH during production testing can be managed; the NAND FLASH with bad blocks can meet the production standards without adding virtual blocks, thereby reducing production costs. The bad blocks that appear in the NAND FLASH during long-term use can also be managed, reducing the probability of the NAND FLASH calling the bad blocks when in use, thereby reducing the probability of data errors in the NAND FLASH when in use, thereby extending the service life of the NAND FLASH.

[0096] The present invention also provides a NAND FLASH bad block management system, which includes a management module and multiple storage blocks; the NAND FLASH bad block management system can execute any one of the above-mentioned NAND FLASH bad block management methods.

[0097] In this embodiment, see Figure 6 The management system of NAND FLASH bad blocks includes a management module and a plurality of storage blocks. The management module and the plurality of storage blocks are both arranged inside the NAND FLASH.

[0098] The present invention also provides a NAND FLASH bad block management device, see Figure 7 , Figure 7 It is a structural schematic diagram of a NAND FLASH bad block management device in a hardware operating environment involved in an embodiment of the present invention.

[0099] The NAND FLASH bad block management device of the embodiment of the present invention may be a processor capable of executing the NAND FLASH bad block management method; there is at least one processor. Figure 7As shown, the NAND FLASH bad block management device may include: a processor 1001 (e.g., a CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0100] Those skilled in the art will understand that Figure 7 The structure of the NAND FLASH bad block management device shown in the figure does not constitute a limitation on the NAND FLASH bad block management device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0101] like Figure 7 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0102] exist Figure 7 In the NAND FLASH bad block management device shown, the network interface 1004 is mainly used to connect to the background server and communicate data with the background server; the user interface 1003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 1001 can be used to call the computer program stored in the memory 1005. When the computer program is called and executed by the processor 1001, the steps of the above-mentioned NAND FLASH bad block management method are implemented.

[0103] The present invention further provides a flash memory, comprising a flash memory body and the NAND FLASH bad block management system as described above; the management module and the plurality of storage blocks are both arranged in the flash memory body.

[0104] In this embodiment, the flash memory may be NAND FLASH, and the flash memory includes a flash memory body and a management system for NAND FLASH bad blocks. The management module and the plurality of storage blocks are both arranged in the flash memory body.

[0105] Based on the computer program proposed in the above embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the NAND FLASH bad block management method described in the above embodiment is implemented.

[0106] The present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the NAND FLASH bad block management method as described in any one of the above technical solutions are implemented.

[0107] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A method for managing NAND FLASH bad blocks, characterized in that: The NAND FLASH bad block management method comprises: Obtain corresponding storage blocks according to each logical address; Determining whether the storage block is a bad block, wherein the bad block is a storage block with poor storage function; If the storage block is not a bad block, the logical address of the storage block is maintained unchanged; If the storage block is a bad block, the logical address of the bad block is exchanged with the logical address of a preset replacement storage block, wherein the preset replacement storage block is a storage block with low usage frequency and good storage function.

2. The NAND FLASH bad block management method according to claim 1, characterized in that: The NAND FLASH includes a latch block, and the latch block includes a plurality of latches; before exchanging the logical address of the bad block with the logical address of the preset replacement storage block, the method further includes: Determining whether there is an idle latch in the latch block; When the idle latch exists in the latch block, the logical address of the bad block is written into the idle latch.

3. The NAND FLASH bad block management method according to claim 2, characterized in that: The step of exchanging the logical address of the bad block with the logical address of a preset replacement storage block comprises: Obtaining the logical address of the bad block; Assigning the logical address of the bad block to the preset replacement storage block, and obtaining the logical address of the preset replacement storage block; The logical address of the preset replacement storage block is assigned to the bad block.

4. The NAND FLASH bad block management method according to claim 2, characterized in that: After determining whether there is an idle latch in the latch block, the method further includes: When the idle latch does not exist in the latch block, the logic address of the bad block is written into the idle latch after waiting for the idle latch to exist in the latch block.

5. The NAND FLASH bad block management method according to claim 1, characterized in that: The determining whether the storage block is a bad block comprises: Erasing original data of the storage block and writing test data into the storage block; Reading the storage block to obtain read data, and determining whether the read data is consistent with the test data; If the read data is consistent with the test data, determining that the storage block is a non-bad block; If the read data is inconsistent with the test data, the storage block is determined to be a bad block.

6. The NAND FLASH bad block management method according to claim 1, characterized in that: The NAND FLASH also includes an information block; before obtaining the corresponding storage block according to each logical address, it also includes: Acquire a bad block address from the information block, wherein the bad block address is a logical address of an initial bad block, and the initial bad block is a storage block with poor storage function that occurs during NAND FLASH production testing; The bad block address is exchanged with the logical address of the preset replacement storage block.

7. The NAND FLASH bad block management method according to claim 1, characterized in that: Before determining whether the storage block is a bad block, the method further includes: Sort the logical addresses corresponding to the storage blocks of the NAND FLASH in ascending order; The determining whether the storage block is a bad block comprises: Whether each of the storage blocks is a bad block is determined in sequence according to the ascending sorting.

8. A NAND FLASH bad block management system, characterized in that: The NAND FLASH bad block management system comprises a management module and a plurality of storage blocks; the NAND FLASH bad block management system can execute the NAND FLASH bad block management method according to any one of claims 1 to 7.

9. A NAND FLASH bad block management device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the NAND FLASH bad block management method according to any one of claims 1 to 7.

10. A flash memory, characterized in that: It comprises a flash memory body and a NAND FLASH bad block management system as claimed in claim 8; the management module and the plurality of storage blocks are both arranged in the flash memory body.

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