Control circuit, control device and processor

Abstract

The invention provides a control circuit, a control device and a processor, which are applied to the technical field of computers, and the control circuit comprises a loop module which is used for obtaining loop information corresponding to each layer of loop logic according to a currently executed nested loop instruction, executing the current layer of loop logic and storing the loop information corresponding to the current layer of loop logic; the cache module is used for storing loop information corresponding to the target layer loop logic in each layer of loop logic and writing loop information corresponding to the remaining layer loop logic in each layer of loop logic into the memory module; the memory module is used for storing loop information corresponding to the residual layer loop logic; the area of the memory module is smaller than that of the cache module, and the storage capacity of the memory module is larger than that of the cache module; and the control module is used for controlling the circulation module, the cache module and the memory module to execute respective corresponding operations. By adopting the control circuit, nested loop logic of any layer can be realized by hardware resources with smaller area.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a control circuit, a control device and a processor. Background Art

[0002] At present, processors are commonly used in autonomous driving chips, robot chips, artificial intelligence (AI) chips, neural network processors (NPU, Neural network Processing Unit), neural network accelerators, central processing units (CPU, Central Processing Unit), graphics processing units (GPU, Graphics Processing Unit), cloud computing chips, etc. Taking autonomous driving chips as an example, the core of autonomous driving technology is perception, decision-making, and execution. In the process of perception and planning, neural network calculations are usually required, and the efficient calculation of related operators in the neural network determines the perception delay and decision-making efficiency, which are important indicators for evaluating autonomous driving technology.

[0003] The loop instruction is one of the commonly used instructions in the processor. There are currently two main ways to implement the loop instruction in the processor. One is the soft loop method, which specifically implements the loop instruction function through a combination of multiple instructions such as branch instructions. The other is the hard loop method, which implements the loop instruction function through a proprietary hardware structure, specifically by setting a corresponding hardware structure for each layer of loop to achieve multi-layer loops.

[0004] However, the above two methods of implementing the loop instruction function cannot take into account both hardware resources and the implementation of deep nested loop functions. Summary of the invention

[0005] The present invention provides a control circuit, a control device and a processor to solve the defect that the method of realizing the loop function in the prior art cannot take into account both hardware resources and the realization of deep nested loop functions, and achieves the purpose of realizing loop logic of any level of nesting with smaller area of ​​hardware resources.

[0006] In a first aspect, the present invention provides a control circuit, the control circuit comprising: A loop module, used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, loop body ending position and current execution state of the current layer of loop logic; A cache module is connected to the loop module and is used to store loop information corresponding to the target layer loop logic in each layer loop logic, and write loop information corresponding to the remaining layer loop logic in each layer loop logic into the memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer loop logic, and the remaining layer loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; A memory module connected to the cache module, used to store loop information corresponding to the loop logic of the remaining layers; the area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is greater than the storage capacity of the cache module; The control module is connected to the circulation module, the cache module and the memory module respectively, and is used to control the circulation module, the cache module and the memory module to perform respective corresponding operations.

[0007] According to a control circuit provided by the present invention, the above-mentioned loop module includes a plurality of loop submodules, each loop submodule corresponding to executing a layer of loop logic, and the above-mentioned cache module includes a first data interface corresponding to the plurality of loop submodules one by one; Each loop submodule is connected to the cache module via a corresponding first data interface, and is used to write loop information corresponding to the target layer loop logic into the cache module via each first data interface, and / or read loop information corresponding to the target layer loop logic in the cache module.

[0008] According to a control circuit provided by the present invention, the cache module is specifically used for

[0009] A first stack push control signal sent by a receiving control module; the first stack push control signal is sent by the control module when it is determined that the number of loop logics at each layer is greater than the number of the plurality of loop sub-modules; Acquire loop information corresponding to each layer of loop logic from the loop module according to the first stack push control signal, determine multiple target layer loop logics located in the outer layer from each layer of loop logic, and push the loop information of each target layer loop logic into the information stack of the cache module in sequence according to a preset order; When the number of target layer loop logics pushed into the information stack reaches a depth threshold, the receiving control module sends a first write data control signal, and according to the first write data control signal, the loop information of the target layer loop logic at the bottom of the information stack is used as the loop information of the remaining layer loop logic and written into the memory module until the loop information of multiple target layer loop logics is pushed into the information stack and / or written into the memory module.

[0010] According to a control circuit provided by the present invention, the control module is specifically used for

[0011] When the number of loop logics at each layer is greater than the number of multiple loop submodules, a second stack push control signal is sent to the loop module; the second stack push control signal is used to instruct the loop module to send the loop information corresponding to the target layer loop logic to the cache module, so that the cache module stacks the loop information of the target layer loop logic; When the number of target layer loop logics pushed into the information stack reaches the depth threshold, a second write data control signal is sent to the memory module; the second write data control signal is used to instruct the memory module to write the loop information of the remaining layers of loop logic sent by the cache module into the memory area.

[0012] According to a control circuit provided by the present invention, the control module is also used

[0013] When a new nested loop instruction is obtained and the multiple loop sub-modules are all occupied, the new nested loop instruction is allocated to the loop sub-module that executes the outermost loop logic among the multiple loop sub-modules; When multiple loop sub-modules execute the inner-nested loop logic of each layer of loop logic and determine that the new nested loop instruction is not the nested loop instruction corresponding to the inner-nested loop logic of each layer of loop logic, send a pop control signal to the cache module; the pop control signal is used to instruct the cache module to return the loop information of the target layer loop logic to the idle loop sub-module among the multiple loop sub-modules; When the number of target layer loop logics in the cache module is less than the depth threshold, a read data control signal is sent to the cache module; the above-mentioned read data control signal is used to instruct the cache module to read the loop information of the remaining layers of loop logic in the memory module and push the loop information of the remaining layers of loop logic into the bottom of the information stack of the cache module.

[0014] According to a control circuit provided by the present invention, the target layer loop logic is specifically one or more layers of loop logic located closest to the outer layer of the current layer loop logic, and the remaining layer loop logic is specifically one or more layers of loop logic located farthest from the outer layer of the current layer loop logic.

[0015] According to a control circuit provided by the present invention, the read and write efficiency of the cache module is higher than the read and write efficiency of the memory module.

[0016] According to a control circuit provided by the present invention, the above-mentioned memory module includes a second data interface; The cache module is connected to the memory module via a second data interface, and is specifically used to write loop information corresponding to the remaining layer loop logic into the memory module via the second data interface, and / or read loop information corresponding to the remaining layer loop logic in the memory module.

[0017] In a second aspect, the present invention further provides a control device, the control device comprising: A loop module, used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, loop body ending position and current execution state of the current layer of loop logic; A cache module is used to store loop information corresponding to a target layer loop logic in each layer loop logic, and write loop information corresponding to remaining layers loop logic in each layer loop logic into a memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer loop logic, and the remaining layers loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; A memory module, used to store loop information corresponding to the loop logic of the remaining layers; the area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is greater than the storage capacity of the cache module; The control module is used to control the loop module, the cache module and the memory module to perform their respective operations.

[0018] In a third aspect, the present invention further provides a processor, which includes the control circuit of the first aspect.

[0019] The control circuit, control device and processor provided by the present invention include a loop module, a cache module, a memory module and a control module, wherein the loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic, the cache module is connected to the loop module, and is used to store the loop information of the target layer of loop logic in each layer of loop logic and write the loop information of the remaining layers of loop logic in each layer of loop logic into the memory module, the memory module is connected to the cache module, and is used to store the loop information of the remaining layers of loop logic, and the control module is respectively connected to the cache module. The loop module, the cache module and the memory module are connected to control the loop module, the cache module and the memory module to perform corresponding operations; wherein the loop information of the current layer loop logic includes at least one of the loop body starting position, the loop body ending position and the current execution state of the current layer loop logic, the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer loop logic, and the remaining loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; the area of ​​the memory module is smaller than the area of ​​the cache module and the storage capacity of the memory module is larger than the storage capacity of the cache module. Since the control circuit can store the loop information of all loop logics remaining in the nested loop instruction in the memory module with larger capacity and smaller area, the corresponding loop information can be obtained from the memory module when the loop module executes any layer loop logic, so that the loop function of any nested layer can be realized with smaller hardware memory resources; in addition, while realizing the loop function of any nested layer, the loop information of the loop logic outside the current layer loop logic can be stored in the cache module with limited capacity and higher read-write efficiency, so that the loop efficiency when realizing the loop function of any nested layer can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is one of the schematic diagrams of the control circuit provided by the present invention.

[0022] Figure 2 This is the second schematic diagram of the control circuit provided by the present invention.

[0023] Reference numerals: 10: control circuit; 110: circulation module; 120: cache module; 130: memory module; 140: control module; 1100: circulation submodule; 1200: first data interface; 1300: second data interface. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] At present, there are two main ways to implement the operation of loop instructions in the processor. One is the soft loop method, which specifically implements the loop instruction function through a combination of multiple instructions such as branch instructions; the core loop body in this method has only 2 instructions, and 5 instructions need to be executed each time a loop is executed, which will cause a serious decrease in the efficiency of instruction execution, resulting in low loop efficiency. The other method is the hard loop method, which implements the loop instruction function through a proprietary hardware structure, specifically by setting a corresponding hardware structure for each layer of loop to realize multi-layer loops. This method requires 2 instructions to be executed each time a loop is executed, and its loop efficiency is high, but each layer of loop must have a corresponding hardware structure. Due to limitations such as area resources, it is impossible to achieve deep loop nesting, resulting in limited support for scenarios such as multi-layer loops / function calls. It can be seen that the above two methods cannot take into account both hardware resources and the realization of deep nested loop functions. Based on this, the embodiment of the present invention provides a control circuit, a control device and a processor that can solve this technical problem.

[0026] Combine the following Figure 1-Figure 2 A control circuit according to an embodiment of the present invention is described.

[0027] Figure 1 is one of the schematic diagrams of the control circuit 10 provided by the present invention, see Figure 1As shown, the control circuit 10 includes a loop module 110, a cache module 120, a memory module 130 and a control module 140, wherein the loop module 110 is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, the loop body ending position and the current execution state of the current layer of loop logic; the cache module 120 is connected to the loop module 110, and is used to store the loop information corresponding to the target layer of loop logic in each layer of loop logic, and write the loop information corresponding to the remaining layers of loop logic in each layer of loop logic into the memory module 130. ; The target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer of loop logic, and the remaining layer loop logic is the remaining loop logic in each layer of loop logic except the current layer loop logic and the target layer loop logic; the memory module 130 is connected to the cache module 120, and is used to store loop information corresponding to the remaining layer loop logic; the area of ​​the memory module 130 is smaller than the area of ​​the cache module 120, and the storage capacity of the memory module 130 is greater than the storage capacity of the cache module 120; the control module 140 is respectively connected to the loop module 110, the cache module 120 and the memory module 130, and is used to control the loop module 110, the cache module 120 and the memory module 130 to perform their respective operations.

[0028] Among them, the loop module 110 (which can be recorded as a loop module) is connected to the cache module 120 and the control module 140. When the processor executes the current nested loop instruction, the loop nesting program corresponding to the nested loop instruction can be obtained. The loop nesting program may include multiple layers of loop logic (i.e., multiple loops), and the loop information corresponding to each layer of loop logic can be obtained. Here, the loop information of each layer of loop logic can include the loop body starting position of the loop logic of this layer (i.e., the starting pc, pc refers to the program counter instruction counter), the loop body end position (i.e., the ending pc) and the current execution state. The current execution state refers to the current number of loops of the loop logic of this layer, that is, the number of loops currently executed.

[0029] The loop module 110 may include an execution unit and a storage unit, wherein the execution unit may execute some layers of loop logic in the multi-layer loop logic of the above loop nested program, where the loop logic currently executed by the execution unit of the loop module 110 may be recorded as the current layer loop logic, where the number of layers of the current layer loop logic is the same as the number of hardware logic loops supported by the loop module 110. The storage unit in the loop module 110 may be, for example, an internal register, which may store loop information required by the loop module 110 to execute the current layer loop logic, such as loop information corresponding to the current layer loop logic.

[0030] For example, assuming that the multi-layer loop logic included in the above loop nesting program is 5 layers, that is, 5 layers of nested loops, the 5-layer loop nesting program can be illustrated as follows: {

[0031] loop1(0, 1, 2)

[0032] loop2(0, 1, 2)

[0033] loop3(0, 1, 2)

[0034] loop4(0, 1, 2)

[0035] loop5(0, 1, 2)

[0036] a=a+1

[0037] }

[0038] The cache module 120 may be a cache area composed of a stack, which has a larger area but a smaller storage capacity. The memory module 130 may be a DDR (Double Data Rate Synchronous Dynamic Random Access Memory), or other memory, which has a smaller area and a larger storage capacity and can store more data or information.

[0039] The cache module 120 is connected to the loop module 110. When the execution unit of the loop module 110 executes the current layer loop logic, it can store the loop information corresponding to the current layer loop logic in the corresponding storage unit. Generally, the number of layers of the current layer loop logic is the number of hardware logic loops supported by the loop module 110, which is less than the number of layers of multi-layer loop logic included in the loop nested program. That is to say, the hardware resources of the loop module 110 are limited, and all layers of loop logic cannot be fully executed at present. At this time, the loop information of one or more layers of loop logic outside the current layer loop logic (these are loop logics that are not currently executed) can be sent to the cache module 120, so that the cache module 120 stores the loop information of one or more layers of loop logic outside the current layer loop logic in its own storage. At the same time, the cache module 120 is also connected to the memory module 130. Since the storage capacity of the cache module 120 is relatively small, in order to avoid overflow of the cache module 120, the cache module 120 can write part of the loop information of one or more layers of loop logic outside the current layer of loop logic obtained from the loop module 110 into the memory module 130 for storage.

[0040] The loop information of the layer loop logic stored in the cache module 120 can be recorded as the loop information of the target layer loop logic, and the loop information of the layer loop logic stored in the memory module 130 can be recorded as the loop information of the remaining layer loop logic. It can be understood that what is stored in the memory module 130 here is all the layer loop logic except the current layer loop logic and the target layer loop logic. The area of ​​the memory module 130 is smaller than that of the cache module 120, and the storage capacity is larger than that of the cache module 120. Therefore, the loop information of more layers of loop logic can be stored without occupying too much hardware area and resources. When the loop module 110 needs to execute the loop logic of any nested layer, the loop module 110 can obtain the loop information of the required layer from the memory module 130 through the cache module 120, so that the loop logic function of any nested layer can be realized with a memory module 130 of a smaller area, taking into account both hardware resources and the realization of deep nested loop functions.

[0041] Further, as an optional embodiment, the target layer loop logic is specifically one or more layers of loop logic located closest to the current layer loop logic, and the remaining layer loop logic is specifically one or more layers of loop logic located farthest from the current layer loop logic.

[0042] Continuing to take the above-mentioned 5-layer loop nesting program as an example, assuming that the current layer loop logic currently executed by the loop module 110 is loop5 and loop4, then the target layer loop logic stored in the above-mentioned cache module 120 is loop3 and loop2, and loop1 is stored in the memory module 130. Loop3 and loop2 are the loop logic layers closest to loop4 and loop5. After the loop module 110 executes loop5 and loop4, loop3 and loop2 will generally be executed in sequence. Therefore, storing loop3 and loop2 in the cache module 120 can facilitate the loop module 110 to quickly obtain the required loop information from the cache module 120 during the loop process, thereby improving the memory access speed. At the same time, loop1 is the loop logic layer farthest from loop4 and loop5. Storing the loop information of these farthest loop logic layers in the memory module 130 can facilitate the rapid acquisition of the corresponding loop information when executing these loop logic layers, thereby realizing the loop function of any nested layers.

[0043] In addition, as an optional embodiment, the read and write efficiency of the above-mentioned cache module 120 is higher than the read and write efficiency of the memory module 130, which can facilitate the loop module 110 to efficiently read or write data in the cache module 120, improve the memory access speed and efficiency, and thereby improve the efficiency of the entire loop instruction execution.

[0044] Furthermore, the control module 140 (which can be referred to as the Ctrl module) is connected to the loop module 110, the cache module 120 and the memory module 130. The control module 140 can control the loop module 110, the cache module 120 and the memory module 130 to perform corresponding operations, where the operation can be the control module 140 performing control operations such as reading data / obtaining data, writing data / storing data, etc. For example, the control module 140 can send a nested loop instruction and loop information of each layer of loop logic to the loop module 110, control the execution unit of the loop module 110 to execute the current layer loop logic and store the loop information of the current layer loop logic, control the cache module 120 to store the loop information of the target layer loop logic and write the loop information of the remaining layers of loop logic to the memory module 130, etc.

[0045] In this embodiment, the control circuit includes a loop module, a cache module, a memory module and a control module, wherein the loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic. The cache module is connected to the loop module and is used to store the loop information of the target layer of loop logic in each layer of loop logic and write the loop information of the remaining layers of loop logic in each layer of loop logic into the memory module. The memory module is connected to the cache module and is used to store the loop information of the remaining layers of loop logic. The control module is respectively connected to the loop module, the cache module and the memory module and is used to control the loop module, the cache module and the memory module to perform corresponding operations; wherein the loop information of the current layer of loop logic includes at least one of the starting position of the loop body of the current layer of loop logic, the ending position of the loop body and the current execution state; the target layer of loop logic is one or more layers of loop logic in each layer of loop logic located outside the current layer of loop logic; the remaining loop logic is the remaining loop logic in each layer of loop logic except the current layer of loop logic and the target layer of loop logic; the area of ​​the memory module is smaller than the area of ​​the cache module and the storage capacity of the memory module is larger than the storage capacity of the cache module. Since the control circuit can store the loop information of all remaining loop logics in the nested loop instructions in a memory module with larger capacity and smaller area, the corresponding loop information can be obtained from the memory module when the loop module executes any layer of loop logic, thereby realizing the loop function of any nested layer with smaller hardware memory resources; in addition, while realizing the loop function of any nested layer, the loop information of the loop logic of the outer layer of the current layer of loop logic can be stored in a cache module with limited capacity and higher read and write efficiency, which can improve the loop efficiency when realizing the loop function of any nested layer.

[0046] Figure 2 This is a second schematic diagram of the control circuit 10 provided by the present invention, see Figure 2As shown, the above-mentioned loop module 110 includes multiple loop sub-modules 1100, each loop sub-module 1100 corresponds to executing a layer of loop logic, and the above-mentioned cache module 120 includes a first data interface 1200 corresponding to the multiple loop sub-modules 1100; each loop sub-module 1100 is connected to the cache module 120 through the corresponding first data interface 1200, and is used to write the loop information corresponding to the target layer loop logic into the cache module 120 through each first data interface 1200, and / or read the loop information corresponding to the target layer loop logic in the cache module 120.

[0047] Among them, the above-mentioned multiple loop submodules 1100 can be loop submodule 0, loop submodule 1, loop submodule 2, ..., loop submodule ..., loop submodule n in sequence, and these n loop submodules can all be recorded as loop submodules 1100, wherein n is greater than 1, and is the number of hardware logic loops supported by the loop module 110, which is generally a limited number, that is, the resources of the hardware loop logic module are limited. The cache module 120 can be provided with a first data interface 1200 equal to the number of loop submodules 1100 (or it can also be greater than the number of loop submodules 1100). Similarly, each loop submodule 1100 can also be provided with a data interface corresponding to the first data interface 1200. These first data interfaces 1200 are respectively connected to a data interface on a loop submodule 1100, so that each loop submodule 1100 can directly access the cache module 120 through its corresponding first data interface 1200, thereby improving the memory access speed of the loop submodule 1100.

[0048] In addition, as an optional embodiment, each loop submodule 1100 includes a storage unit and an execution unit. The execution unit can execute one layer of loop logic, and the storage unit can be used to store loop information required when the corresponding execution unit executes the loop logic.

[0049] Optionally, continue to see Figure 2 As shown, the above-mentioned memory module 130 includes a second data interface 1300; the above-mentioned cache module 120 is connected to the memory module 130 through the second data interface 1300, and is specifically used to write the loop information corresponding to the remaining layer loop logic into the memory module 130 through the second data interface 1300, and / or read the loop information corresponding to the remaining layer loop logic in the memory module 130.

[0050] Among them, a second data interface 1300 may be provided on the memory module 130, and a data interface corresponding to the second data interface 1300 may also be provided on the corresponding cache module 120, so that the cache module 120 can be connected to the memory module 130 through the second data interface 1300 to perform read operations and write operations on the memory module 130. Providing an interface here can facilitate the cache module 120 to accurately read data / information from the memory module 130 or to accurately write data / information in the memory module 130.

[0051] In this embodiment, the circulation module includes a plurality of circulation submodules, and the cache module is provided with a plurality of data interfaces connected to the circulation submodules one by one, so that each circulation submodule can directly access the cache module through its corresponding data interface, thereby improving the access speed of the circulation submodule to the cache module, thereby improving the circulation efficiency. In addition, the memory module is provided with a data interface corresponding to the cache module, so that the cache module can accurately read data / information from the memory module or accurately write data / information in the memory module.

[0052] The following embodiment describes the situation of stacking in the cache module 120 .

[0053] In some embodiments, the cache module 120 is specifically used to

[0054] A first stack push control signal sent by the receiving control module 140 is sent by the control module 140 when it is determined that the number of loop logics at each layer is greater than the number of the plurality of loop submodules 1100; Obtain loop information corresponding to each layer of loop logic from the loop module 110 according to the first stack push control signal, determine multiple target layer loop logics located in the outer layer from each layer of loop logic, and push the loop information of each target layer loop logic into the information stack of the cache module 120 in sequence according to a preset order; When the number of target layer loop logics pushed into the information stack reaches a depth threshold, the receiving control module 140 sends a first write data control signal, and according to the first write data control signal, the loop information of the target layer loop logic at the bottom of the information stack is used as the loop information of the remaining layer loop logic and written into the memory module 130, until the loop information of multiple target layer loop logics is pushed into the information stack and / or written into the memory module 130.

[0055] Optionally, the control module 140 is specifically configured to:

[0056] When the number of loop logics at each layer is greater than the number of the multiple loop submodules 1100, a second stack push control signal is sent to the loop module 110; the second stack push control signal is used to instruct the loop module 110 to send the loop information corresponding to the target layer loop logic to the cache module 120, so that the cache module 120 stacks the loop information of the target layer loop logic; When the number of target layer loop logics pushed into the information stack reaches the depth threshold, a second write data control signal is sent to the memory module 130; the second write data control signal is used to instruct the memory module 130 to write the loop information of the remaining layers of loop logic sent by the cache module 120 into the memory area.

[0057] The cache module 120 may include an information stack for storing loop information of the target layer loop logic. The information stack has a first-in-last-out feature, that is, the loop information that first enters the information stack is read out last.

[0058] When executing the nested loop instruction, the above-mentioned control module 140 can determine whether the total number of layers of loop logic is greater than the number of multiple loop sub-modules 1100. If not, it means that each loop sub-module 1100 can execute all layers of loop logic; if the total number of layers is greater than the number of multiple loop sub-modules 1100, it means that each loop sub-module 1100 cannot execute all layers of loop logic. Then, the control module 140 can send a push instruction to the cache module 120 and the loop module 110, instructing the loop module 110 to push the loop information of the loop logic outside the current layer of loop logic into the information stack of the cache module 120.

[0059] When pushing the stack, the loop information of the outermost loop logic may be pushed into the information stack first, and then the loop information of the inner loop logic adjacent to the outermost layer may be pushed into the information stack. During the stacking process, the control module 140 may continuously determine whether the number of target layer loop logics pushed into the information stack of the cache module 120 reaches the depth threshold. If the depth threshold is reached, the target layer loop logic at the bottom of the stack is used as the remaining layer loop logic and its loop information is written into the memory module 130. Then, the loop information of the target loop logic may continue to be pushed into the information stack of the cache module 120. When the number of pushed target layer loop logics reaches the depth threshold, the new target layer loop logic at the bottom of the stack is used as the remaining layer loop logic and its loop information is written into the memory module 130. The loop is iterated in this way until the loop information of the target layer loop logic of the same number as the depth threshold is stored in the information stack of the cache module 120, and the loop information of all the remaining layers of loop logic in each layer is written into the memory module 130. In addition, the depth threshold refers to the depth of the information stack of the cache module 120, that is, the amount of loop information of the loop logic that can be pushed into the stack.

[0060] For example, continuing to take the above-mentioned 5-layer loop nesting program as an example, assuming that the current layer loop logic currently executed by the loop module 110 is loop5 and loop4, assuming that the depth threshold of the information stack of the cache module 120 is 2, the loop module 110 can first push loop1 into the information stack of the cache module 120, and then push loop2 into the information stack, and after loop2 is pushed in, write loop1 at the bottom of the stack into the memory module 130, and then push loop3 into the information stack. When the nested loop instruction is actually executed, if loop5 is executed, loop3 can be read in the information stack and returned to the loop module 110 for execution, and loop1 in the memory module 130 is read to the bottom of the information stack.

[0061] In this embodiment, a push instruction is sent to the loop module and the cache module through the control module to control the loop module to push the loop information of the outermost loop logic into the information stack of the cache module in sequence, and when the loop information of the target layer loop logic stored in the information stack reaches the depth threshold, the loop information of the target layer loop logic at the bottom of the stack is written into the memory module in sequence. This can facilitate the accurate storage of the loop information of some loop logic layers close to the current layer loop logic in the cache module, improve the loop efficiency, and can accurately store the loop information of all remaining loop logics in the memory module, so as to accurately implement the loop function of any nested layer.

[0062] The following embodiment describes the situation of popping in the cache module 120 .

[0063] In some embodiments, the control module 140 is also used to

[0064] When a new nested loop instruction is acquired and the multiple loop sub-modules 1100 are all occupied, the new nested loop instruction is allocated to the loop sub-module 1100 that executes the outermost loop logic among the multiple loop sub-modules 1100; When the multiple loop sub-modules 1100 execute the inner-nested loop logic of each layer of loop logic and determine that the new nested loop instruction is not the nested loop instruction corresponding to the inner-nested loop logic of each layer of loop logic, a pop control signal is sent to the cache module 120; the pop control signal is used to instruct the cache module 120 to return the loop information of the target layer loop logic to the idle loop sub-module 1100 among the multiple loop sub-modules 1100; When the number of target layer loop logics in the cache module 120 is less than the depth threshold, a read data control signal is sent to the cache module 120; the above-mentioned read data control signal is used to instruct the cache module 120 to read the loop information of the remaining layers of loop logic in the memory module 130 and push the loop information of the remaining layers of loop logic into the bottom of the information stack of the cache module 120.

[0065] Among them, after the control module 140 obtains the new nested loop instruction, it can first determine whether all the loop sub-modules 1100 of the loop module 110 are occupied. If all are occupied, the new nested loop instruction is assigned to the loop sub-module 1100 that executes the outermost loop logic. At the same time, a stack push control signal can also be sent to the loop sub-module 1100 to instruct the loop sub-module 1100 to push the loop information of the loop logic layer corresponding to the new nested loop instruction into the information stack of the cache module 120.

[0066] At the same time, after executing the outermost loop logic, the above-mentioned multiple loop sub-modules 1100 will continue to execute the corresponding inner nested loop logic. If a new nested loop instruction is obtained at this time, the control module 140 can determine whether the loop logic layer corresponding to the new nested loop instruction is the inner nested loop logic corresponding to the currently executed nested loop instruction. If not, the control module 140 can send a pop control signal to the cache module 120 to instruct the cache module 120 to return the loop information of the inner nested loop logic corresponding to the currently executed nested loop instruction to the loop sub-module 1100 for execution, specifically, it can be returned to the idle sub-modules in each loop sub-module 1100.

[0067] After returning the loop information of the inner nested loop logic in the information stack of the cache module 120 (i.e., the loop information of the target layer loop logic) to the idle loop submodule 1100, if the control module 140 determines that the number of loop logic layers of the loop information stored in the information stack is less than the depth threshold, it can send a read data control signal and the address of the memory module 130 to the cache module 120, so that the cache module 120 can read the loop information of the outer nested loop logic corresponding to the currently executed nested loop instruction in the memory module 130 corresponding to the address, so as to return it to the loop submodule 1100 for use next time. Here, after the cache module 120 reads the loop information of the outer nested loop logic corresponding to the currently executed nested loop instruction in the memory module 130, it can store the read loop information at the bottom of the information stack, so as to ensure that the loop logic layers from the top of the stack to the bottom of the stack are successively close to the loop logic layers currently executed, thereby improving the memory access efficiency.

[0068] In this embodiment, when a new nested loop instruction is obtained and the current loop instruction has not been executed, a pop control signal is sent to the cache module to instruct the cache module to return the inner loop logic to the loop module for execution, and when the loop information stored in the cache module is less than the depth threshold, part of the loop information is read from the memory module and stored at the bottom of the stack of the cache module. This makes it easier for the loop module to obtain the loop information of the inner loop logic from the cache module for loop execution, thereby improving the loop efficiency. At the same time, the loop information of part of the loop logic layer can be obtained from the memory module to the cache module, thereby further improving the loop efficiency while realizing the loop function of any nested layer.

[0069] For example, assuming that the number of hardware loop logic copies of the loop module is 2 (i.e., it includes two loop sub-modules), the depth threshold of the cache module is 2 (i.e., the cache module can store loop information of at most two loop logic layers), assuming that the cache module is recorded as stack, and the memory module is recorded as ddr. Continuing to take the above 5-layer loop nesting program as an example, the PC jumps corresponding to the loop nesting program are: 1->2->3->4->5->6->6->5->6->6->4->5->6->6->5->6->6->3->4->5->6->6->5->6->6->4->5->6->6->5->6->6->2->3->4->5->6->6->5->6->6->4->5->6->6->5->6->6->3->4->5->6->6->5->6->6->4->5->6->6->5->6->6->6, where 1 to 6 are the 1st to 6th lines of the above loop nesting program, the first line is loop1 (0, 1, 2), and the sixth line is a=a+1.

[0070] Based on the above loop nested program and the above PC jump sequence, some hardware behaviors of the processor are described as follows: Execute program line 1: loop1 enters loop hardware; Execute program line 2: loop2 enters loop hardware; Execute line 3 of the program: loop3 enters the loop hardware, and loop1 information is pushed onto the stack; Execute line 4 of the program: loop4 enters the loop hardware, and loop2 information is pushed onto the stack; Execute the 5th line of the program: loop5 enters the loop hardware, loop3 information is pushed onto the stack, and loop1 information enters the ddr; Execute the 6th line of the program: a=a+1 (loop1=0, loop2=0, loop3=0, loop4=0, loop5=0); Execute the 6th line of the program: a=a+1, (loop1=0, loop2=0, loop3=0, loop4=0, loop5=1); Execute line 5 of the program: loop5 enters the loop hardware; Execute the 6th line of the program: a=a+1 (loop1=0, loop2=0, loop3=0, loop4=1, loop5=0); Execute the 6th line of the program: a=a+1, (loop1=0, loop2=0, loop3=0, loop4=1, loop5=1); loop4 ends; loop3's loop information is popped out of the stack and enters the hardware loop; the stack is in a pre-empty state, loop1's loop information is read from ddr, and loop1's loop information is read from ddr and enters the bottom of the stack; ......

[0071] Execute line 4 of the program: loop4 enters the loop hardware; Execute line 5 of the program: loop5 enters the loop hardware, and loop information of loop3 is pushed onto the stack; Execute the 6th line of the program: a=a+1 (loop1=1, loop2=1, loop3=1, loop4=0, loop5=0); Execute line 6 of the program: a=a+1 (loop1=1, loop2=1, loop3=1, loop4=0, loop5=1); Execute line 5 of the program: loop5 enters the loop hardware; Execute the 6th line of the program: a=a+1 (loop1=1, loop2=1, loop3=1, loop4=1, loop5=0); Execute the 6th line of the program: a=a+1, (loop1=1, loop2=1, loop3=1, loop4=1, loop5=1); loop1 execution ends; loop3's loop information is popped off the stack, the stack is in a pre-empty state, loop1's loop information is read from ddr and entered the bottom of the stack, loop2's loop information is popped off the stack, and loop1's loop information is popped off the stack.

[0072] From the above description, it can be seen that the technical solution of the present invention can store the remaining unstored loop information of each layer of loop logic through the memory module, which is a memory with a small area and large storage capacity, so that any layer of loop logic can be implemented with a small area cost.

[0073] The control device provided by the present invention is described below. The control device described below and the control circuit described above can be referenced to each other.

[0074] In some embodiments, a control device is provided, the control device comprising: A loop module, used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, loop body ending position and current execution state of the current layer of loop logic; A cache module is used to store loop information corresponding to a target layer loop logic in each layer loop logic, and write loop information corresponding to remaining layers loop logic in each layer loop logic into a memory module; the target layer loop logic is one or more layers of loop logic located outside the current layer loop logic in each layer loop logic, and the remaining layers loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; A memory module, used to store loop information corresponding to the loop logic of the remaining layers; the area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is greater than the storage capacity of the cache module; The control module is used to control the loop module, the cache module and the memory module to perform their respective operations.

[0075] In this embodiment, the control device includes a loop module, a cache module, a memory module and a control module, wherein the loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic, and is used to store the loop information of the target layer of loop logic in each layer of loop logic and write the loop information of the remaining layers of loop logic in each layer of loop logic into the memory module, and is used to store the loop information of the remaining layers of loop logic, and the control module is used to control the loop module, the cache module and the memory module to perform corresponding operations; wherein the loop information of the current layer of loop logic includes at least one of the starting position of the loop body of the current layer of loop logic, the ending position of the loop body and the current execution state, the target layer of loop logic is one or more layers of loop logic in each layer of loop logic located outside the current layer of loop logic, and the remaining loop logic is the remaining loop logic in each layer of loop logic except the current layer of loop logic and the target layer of loop logic; the area of ​​the memory module is smaller than the area of ​​the cache module and the storage capacity of the memory module is larger than the storage capacity of the cache module. Since the control device can store the loop information of all loop logics remaining in the nested loop instructions in a memory module with a larger capacity and a smaller area, the corresponding loop information can be obtained from the memory module when the loop module executes any layer of loop logic, thereby realizing the loop function of any nested layer with smaller hardware memory resources; in addition, while realizing the loop function of any nested layer, the loop information of the loop logic of the outer layer of the current layer of loop logic can be stored in a cache module with limited capacity and high read and write efficiency, which can improve the loop efficiency when realizing the loop function of any nested layer.

[0076] It should be noted here that the above-mentioned control device provided in the embodiment of the present invention can realize all the functions realized by the above-mentioned control circuit embodiment and can achieve the same technical effect. The parts and beneficial effects that are the same as those in the control circuit embodiment will not be described in detail here.

[0077] In some embodiments, the present invention further provides a processor, which may include the control circuit 10 described above.

[0078] In this embodiment, the processor may include a control circuit, which includes a loop module, a cache module, a memory module and a control module, wherein the loop module is used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic, and is used to store the loop information of the target layer of loop logic in each layer of loop logic and write the loop information of the remaining layers of loop logic in each layer of loop logic into the memory module, and is used to store the loop information of the remaining layers of loop logic, and the control module is used to control the loop module, the cache module and the memory module to perform corresponding operations; wherein the loop information of the current layer of loop logic includes at least one of the starting position of the loop body of the current layer of loop logic, the ending position of the loop body and the current execution state, the target layer of loop logic is one or more layers of loop logic in each layer of loop logic located outside the current layer of loop logic, and the remaining loop logic is the remaining loop logic in each layer of loop logic except the current layer of loop logic and the target layer of loop logic; the area of ​​the memory module is smaller than the area of ​​the cache module and the storage capacity of the memory module is larger than the storage capacity of the cache module. Since the control circuit of the processor can store the loop information of all remaining loop logics in the nested loop instructions in a memory module with larger capacity and smaller area, the corresponding loop information can be obtained from the memory module when the loop module executes any layer of loop logic, thereby realizing the loop function of any nested layer with smaller hardware memory resources; in addition, while realizing the loop function of any nested layer, the loop information of the loop logic of the outer layer of the current layer of loop logic can be stored in a cache module with limited capacity and higher read and write efficiency, which can improve the loop efficiency when realizing the loop function of any nested layer.

[0079] It should be noted that the above-mentioned processor provided in the embodiment of the present invention can realize all the functions realized by the above-mentioned control circuit embodiment and can achieve the same technical effect. The parts and beneficial effects that are the same as those in the control circuit embodiment will not be described in detail here.

[0080] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0081] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A control circuit, characterized in that: include: A loop module, used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, loop body ending position and current execution state of the current layer of loop logic; A cache module, connected to the loop module, for storing loop information corresponding to the target layer loop logic in each layer loop logic, and writing loop information corresponding to the remaining layers loop logic in each layer loop logic into the memory module; the target layer loop logic is one or more layers of loop logic in each layer loop logic that are located outside the current layer loop logic, and the remaining layers loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; A memory module, connected to the cache module, and used to store loop information corresponding to the loop logic of the remaining layers; The area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is greater than the storage capacity of the cache module; The control module is connected to the circulation module, the cache module and the memory module respectively, and is used to control the circulation module, the cache module and the memory module to perform respective corresponding operations.

2. The control circuit according to claim 1, characterized in that: The loop module includes a plurality of loop submodules, each loop submodule corresponding to executing a layer of loop logic, and the cache module includes a first data interface corresponding to the plurality of loop submodules one by one; Each of the loop sub-modules is connected to the cache module via a corresponding first data interface, and is used to write the loop information corresponding to the target layer loop logic into the cache module via each of the first data interfaces, and / or read the loop information corresponding to the target layer loop logic in the cache module.

3. The control circuit according to claim 2, characterized in that: The cache module is specifically used for receiving a first stack push control signal sent by the control module; the first stack push control signal is sent by the control module when it is determined that the number of loop logics at each layer is greater than the number of the plurality of loop sub-modules; Acquire loop information corresponding to each layer of loop logic from the loop module according to the first stack push control signal, determine multiple target layer loop logics located in the outer layer from each layer of loop logic, and push the loop information of each target layer loop logic into the information stack of the cache module in sequence according to a preset order; When the number of the target layer loop logics pushed into the information stack reaches a depth threshold, the first write data control signal sent by the control module is received, and according to the first write data control signal, the loop information of the target layer loop logic at the bottom of the information stack is used as the loop information of the remaining layer loop logic and written into the memory module until the loop information of the multiple target layer loop logics are all pushed into the information stack and / or written into the memory module.

4. The control circuit according to claim 3, characterized in that: The control module is specifically used for When the number of loop logics at each layer is greater than the number of the multiple loop sub-modules, a second stack push control signal is sent to the loop module; the second stack push control signal is used to instruct the loop module to send the loop information corresponding to the target layer loop logic to the cache module, so that the cache module stacks the loop information of the target layer loop logic; When the number of the target layer loop logic pushed into the information stack reaches the depth threshold, a second write data control signal is sent to the memory module; the second write data control signal is used to instruct the memory module to write the loop information of the remaining layers of loop logic sent by the cache module into the memory area.

5. The control circuit according to any one of claims 2 to 4, characterized in that: The control module is also used When a new nested loop instruction is acquired and the plurality of loop sub-modules are all occupied, the new nested loop instruction is allocated to a loop sub-module that executes an outermost loop logic among the plurality of loop sub-modules; When the multiple loop submodules execute the inner-nested loop logic of each layer of loop logic and determine that the new nested loop instruction is not a nested loop instruction corresponding to the inner-nested loop logic of each layer of loop logic, sending a pop control signal to the cache module; The pop control signal is used to instruct the cache module to return the loop information of the target layer loop logic to an idle loop submodule among the multiple loop submodules; When the number of target layer loop logics in the cache module is less than a depth threshold, a read data control signal is sent to the cache module; the read data control signal is used to instruct the cache module to read the loop information of the remaining layers of loop logic in the memory module and push the loop information of the remaining layers of loop logic into the bottom of the information stack of the cache module.

6. The control circuit according to any one of claims 1 to 3, characterized in that: The target layer loop logic is specifically one or more layers of loop logic located closest to the outer layer of the current layer loop logic, and the remaining layer loop logic is specifically one or more layers of loop logic located farthest from the outer layer of the current layer loop logic.

7. The control circuit according to any one of claims 1 to 3, characterized in that: The read and write efficiency of the cache module is higher than that of the memory module.

8. The control circuit according to any one of claims 1 to 3, characterized in that: The memory module includes a second data interface; The cache module is connected to the memory module via the second data interface, and is specifically used to write the loop information corresponding to the remaining layer loop logic into the memory module via the second data interface, and / or read the loop information corresponding to the remaining layer loop logic in the memory module.

9. A control device, characterized in that: include: A loop module, used to obtain loop information corresponding to each layer of loop logic according to the currently executed nested loop instruction, and execute the current layer of loop logic and store the loop information corresponding to the current layer of loop logic; the loop information of the current layer of loop logic includes at least one of the loop body starting position, loop body ending position and current execution state of the current layer of loop logic; A cache module, used to store loop information corresponding to a target layer loop logic in each layer loop logic, and write loop information corresponding to remaining layers loop logic in each layer loop logic into a memory module; the target layer loop logic is one or more layers of loop logic in each layer loop logic that are located outside the current layer loop logic, and the remaining layers loop logic is the remaining loop logic in each layer loop logic except the current layer loop logic and the target layer loop logic; A memory module, used for storing loop information corresponding to the loop logic of the remaining layers; The area of ​​the memory module is smaller than the area of ​​the cache module, and the storage capacity of the memory module is greater than the storage capacity of the cache module; The control module is used to control the circulation module, the cache module and the memory module to perform respective corresponding operations.

10. A processor, characterized in that: Comprising the control circuit according to any one of claims 1 to 8.

Images