ARM many-core instruction conversion memory access optimization method based on reinforcement learning

Abstract

The invention discloses an ARM many-core instruction conversion memory access optimization method based on reinforcement learning, and the method comprises the steps: constructing a many-core instruction pre-distribution model based on reinforcement learning, and pre-converting a to-be-converted instruction into a first ARM instruction when an executable file is loaded and executed in a dynamic instruction conversion manner; adjusting a pre-conversion result of the to-be-converted instruction for a calculation core determined by the to-be-converted instruction according to an ARM system state on the basis of a many-core instruction pre-distribution model, constructing a pre-fetch instruction according to a virtual address of the to-be-converted instruction, determining a write-in position of the pre-fetch instruction, converting the to-be-converted instruction into an instruction sequence composed of the pre-fetch instruction and an ARM instruction, and storing the instruction sequence in the ARM system. According to the method, the memory access delay is reduced, the overall performance of the system is improved, and especially for a memory intensive program, the multi-core and cache advantages of an ARM many-core system can be better utilized.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to an ARM multi-core instruction conversion memory access optimization method based on reinforcement learning. Background Art

[0002] With the growing demand for heterogeneous computing, using ARM many-core systems to execute traditional x86 programs has become an important way to expand computing capabilities. ARM many-core systems usually refer to systems with more than 64 computing cores. However, when x86 programs are executed in ARM many-core systems by dynamic instruction conversion, x86 and ARM have different instruction set architectures, and memory access problems will be faced during the instruction conversion process. In particular, when performing conversion in ARM many-core (more than 64 cores) systems, existing conversion methods are difficult to fully utilize its powerful multi-core and cache architecture advantages, which will lead to a decrease in execution performance when the program is executed across architectures. Summary of the invention

[0003] In view of this, the present invention provides an ARM multi-core instruction conversion memory access optimization method based on reinforcement learning, and uses reinforcement learning to implement x86 memory access instruction conversion based on computing core scheduling.

[0004] The present invention provides an ARM multi-core instruction conversion memory access optimization method based on reinforcement learning, which specifically includes the following steps:

[0005] Step 1: Establish a many-core instruction pre-allocation model based on reinforcement learning, where the environment is an ARM many-core system, the state is the utilization of the computing core, the action is to allocate instructions to the selected computing core, and the reward function is a reward function based on the utilization of the computing core. The training of the many-core instruction pre-allocation model is completed; load and execute the executable file in the ARM many-core system through dynamic instruction conversion, and extract the current instructions to be converted of the memory access instruction type;

[0006] Step 2: Use the many-core instruction pre-allocation model to calculate the first computing core to which the current instruction to be converted needs to be allocated and the first address range corresponding to it according to the current ARM many-core system state;

[0007] Step 3: pre-convert the current instruction to be converted into a first ARM instruction to obtain its first memory address. If the first ARM instruction is assigned to the first computing core, execute step 4; otherwise, assign the first ARM instruction to the first computing core and then execute step 4;

[0008] Step 4: construct a first prefetch instruction based on the first memory address and the prefetch distance, the memory address of the first prefetch instruction is set to the second memory address, the second memory address includes the first virtual page number and the second page offset, and the second page offset is smaller than the first page offset; convert the current instruction to be converted into an instruction sequence formed by the first prefetch instruction and the first ARM instruction.

[0009] Furthermore, the reward function in step 1 is calculated as follows: ,in, To calculate the average utilization of the core, U i is the utilization of the i-th computing core, n is the total number of computing cores, is the standard deviation of utilization, is the coefficient for adjusting the influence of standard deviation.

[0010] Furthermore, the state of the many-core instruction pre-allocation model includes the ARM many-core system state and ARM instruction characteristics, wherein the ARM many-core system state includes cache hit rate, computing core utilization and computing core instruction queue length, and the ARM instruction characteristics include memory access range and computing resource requirements.

[0011] Furthermore, the reward function is calculated as follows: , where w1, w2, w3, w4 and w5 are all weight coefficients and w1+w2+w3+w4+w5=1, R1 is the cache hit rate reward, R2 is the computing core utilization reward, R3 is the computing core instruction queue length reward, R4 is the memory access range reward, and R5 is the computing resource demand reward.

[0012] Furthermore, the cache hit rate reward is calculated as follows: , where H is the current cache hit rate, H max is the theoretical maximum cache hit rate.

[0013] Furthermore, the calculation method of the instruction queue length reward of the computing core is: , where Q i is the instruction queue length of the i-th computing core, Q max The maximum allowed length of the command queue.

[0014] Furthermore, the calculation method of the computing resource demand reward is: , where C1 is the computing resource requirement of the instruction and C2 is the available computing resources of the allocated computing core.

[0015] Furthermore, the method of allocating the first ARM instruction to the first computing core in step 3 is: obtain the first virtual page in the ARM virtual memory where the first ARM instruction is located, record the first virtual page number and the offset within the first page, and the first virtual page corresponds to the first physical page; determine the second physical page in the first address range, and modify the page table entry related to the first virtual page in the page table to a mapping relationship from the first virtual page to the second physical page, copy the data of the first physical page to the second physical page, and then clear the first physical page.

[0016] Furthermore, the pre-fetch distance in step 4 is determined according to the cache hierarchy of the ARM architecture, and is set to a larger value when the cache hit rate of the ARM many-core system is low.

[0017] Furthermore, in step 4, the difference between the second intra-page offset and the first intra-page offset is increased.

[0018] Beneficial effects:

[0019] The present invention constructs a many-core instruction pre-allocation model based on reinforcement learning. When loading and executing an executable file in a dynamic instruction conversion manner, the instruction to be converted is first pre-converted into a first ARM instruction. At the same time, based on the many-core instruction pre-allocation model, the computing core determined for the instruction to be converted according to the ARM system state is adjusted for the pre-conversion result of the instruction to be converted. Then, a pre-fetch instruction is constructed according to the virtual address of the instruction to be converted, the write position of the pre-fetch instruction is determined, and the instruction to be converted is converted into an instruction sequence consisting of the pre-fetch instruction and the ARM instruction, thereby reducing memory access latency and improving the overall performance of the system. In particular, for memory-intensive programs, the multi-core and cache advantages of the ARM many-core system can be better utilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic flow chart of an ARM multi-core instruction conversion memory access optimization method based on reinforcement learning provided by the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below with reference to the accompanying drawings and with reference to the embodiments.

[0022] The present invention provides an ARM many-core instruction conversion memory access optimization method based on reinforcement learning, the core idea of ​​which is: constructing a many-core instruction pre-allocation model based on reinforcement learning, first pre-converting the instruction to be converted into a first ARM instruction when loading and executing an executable file in a dynamic instruction conversion manner, and at the same time adjusting the pre-conversion result of the instruction to be converted according to the computing core determined by the ARM system state for the instruction to be converted based on the many-core instruction pre-allocation model, and then constructing a pre-fetch instruction according to the virtual address of the instruction to be converted, determining the write position of the pre-fetch instruction, and converting the instruction to be converted into an instruction sequence consisting of the pre-fetch instruction and the ARM instruction.

[0023] The present invention provides an ARM multi-core instruction conversion memory access optimization method based on reinforcement learning, the specific process is as follows Figure 1 As shown, the specific steps include:

[0024] Step 1: Establish a multi-core instruction pre-allocation model based on reinforcement learning, which is used to pre-determine the ARM computing core to which the ARM instruction will be allocated; the environment of the multi-core instruction pre-allocation model is the ARM system, the state is the utilization of the ARM system computing core, the action is to allocate the ARM instruction to the selected ARM computing core, and the reward function is a reward function based on the computing core utilization; the training method of the reinforcement learning model is used to complete the training of the multi-core instruction pre-allocation model. In the ARM system, the executable file is loaded and executed through dynamic instruction conversion to initialize the page table mapping relationship.

[0025] Reasonable instruction scheduling should keep the utilization of each computing core balanced, avoiding the situation where some cores are idle and some cores are overloaded, thereby improving the overall utilization of the computing core. Therefore, the present invention designs a reward function R according to the utilization of the computing core, and the calculation method is: ,in, To calculate the average utilization of the core, U i is the utilization of the i-th computing core, n is the total number of computing cores, is the standard deviation of utilization, is the coefficient for adjusting the influence of standard deviation.

[0026] In order to further improve the accuracy of instruction allocation, the present invention adopts ARM system status and ARM instruction characteristics as the status of the many-core instruction pre-allocation model, wherein the ARM system status includes cache hit rate, computing core utilization, instruction queue length of the computing core, etc., and the ARM instruction characteristics include parameters such as memory access range and computing resource requirements.

[0027] Therefore, the reward function of the many-core instruction pre-allocation model is: , where w1, w2, w3, w4 and w5 are all weight coefficients and w1+w2+w3+w4+w5=1, R1 is the cache hit rate reward, R2 is the computing core utilization reward, R3 is the computing core instruction queue length reward, R4 is the memory access range reward, and R5 is the computing resource demand reward.

[0028] Specifically, the higher the cache hit rate, the better the system performance. The calculation method of cache hit rate reward is: , where H is the current cache hit rate, H max is the theoretical maximum cache hit rate.

[0029] The length of the command queue should be kept within a reasonable range. Too long will cause congestion. The calculation method of the command queue length reward is: , where Q i is the instruction queue length of the i-th computing core, Q max The maximum allowed length of the instruction queue.

[0030] The calculation method of memory access range reward is: R4=M, where M is the overlap ratio between the actual memory access range of the instruction and the cache coverage range.

[0031] The calculation method for computing resource demand rewards is: , where C1 is the computing resource requirement of the instruction and C2 is the available computing resources of the allocated computing core.

[0032] ‌Page table mapping‌ refers to the process of mapping virtual addresses to physical addresses. In a computer system, in order to implement virtual memory, the operating system uses a page table to record the mapping relationship between virtual addresses and physical addresses.

[0033] Step 2: Get the current instruction to be converted. If the current instruction to be converted is a memory access instruction, execute step 3; otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7.

[0034] Step 3, obtain the current ARM system state, use the multi-core instruction pre-allocation model trained in step 1 to calculate the computing core to which the current instruction to be converted needs to be allocated according to the current ARM system state, record the computing core as the first computing core, and record the memory address range corresponding to the first computing core as the first address range.

[0035] Step 4: pre-convert the current instruction to be converted into a first ARM instruction to obtain its first memory address and the first virtual page in the ARM virtual memory where it is located, record the first virtual page number and the first page offset of the first virtual page, and record the physical page corresponding to the first virtual page as the first physical page;

[0036] If the first physical page is not within the first address range, determine the second physical page in the first address range, and modify the page table entry related to the first virtual page in the page table to a mapping relationship from the first virtual page to the second physical page, copy the data of the first physical page to the second physical page, and then clear the first physical page; otherwise, keep the mapping relationship in the page table unchanged.

[0037] Step 5: Determine the prefetch distance for data prefetching according to the cache hierarchy of the ARM architecture. If the cache hit rate of the current ARM system is low, increase the prefetch distance and execute step 6; otherwise, keep the prefetch distance unchanged and execute step 6.

[0038] Step 6: construct a first prefetch instruction based on the first memory address and the prefetch distance, the memory address of the first prefetch instruction is set to the second memory address, the second memory address includes the first virtual page number and the second page offset, and the second page offset is smaller than the first page offset; convert the current instruction to be converted into an instruction sequence formed by the first prefetch instruction and the first ARM instruction.

[0039] In addition, in order to improve the cache hit rate, the difference between the offset in the second page and the offset in the first page may be further increased, so that the memory data to be processed can be loaded into the cache earlier.

[0040] Step 7: If the executable file is executed and the conversion is completed, then the process ends; otherwise, proceed to step 2.

[0041] Example:

[0042] In this embodiment, an ARM many-core instruction conversion memory access optimization method based on reinforcement learning provided by the present invention is adopted to realize the efficient execution of x86 architecture executable files on the ARM many-core system, including the following steps:

[0043] S1. Instruction analysis and marking: deeply analyze the input x86 assembly code and mark memory access instructions and operations. The specific steps are as follows:

[0044] The following is a piece of assembly code containing typical x86 memory access instructions, for example:

[0045] section.data

[0046] arraydb1,2,3,4,5,6,7,8,9,10

[0047] section.text

[0048] global_start

[0049] _start:

[0050] moveax,[array] (changed to address f)

[0051] addeax,1

[0052] mov[array],eax

[0053] movebx,[array+4]

[0054] subebx,2

[0055] mov[array+8],ebx

[0056] jmploop_start

[0057] loop_start:

[0058] movecx,10

[0059] loop_iteration:

[0060] movedx,[array+ecx]

[0061] addedx,3

[0062] mov[array+ecx],edx

[0063] looploop_iteration

[0064] Parse the input x86 instructions, identify memory access instructions such as moveax,[array], mov[array],eax, etc., and mark the memory address and operation type they access.

[0065] For the above code, through analysis, it can be determined that moveax, [array] and movedx, [array + ecx] are read operations, while mov [array], eax and mov [array + 8], ebx are write operations.

[0066] S2, address remapping, mapping the x86 memory address to the ARM memory space and dynamically adjusting it according to the ARM many-core system. The specific steps are as follows:

[0067] S2.1. Map x86 memory addresses to ARM memory space, taking into account the cache hierarchy and core distribution of the ARM many-core architecture. Assume that the ARM many-core system has 128 cores, divided into 16 groups, each with 8 cores. Each core group has its own L1 and L2 caches and shares the L3 cache.

[0068] S2.2, dynamic address mapping algorithm includes:

[0069] S2.2.1. Initialize the mapping table.

[0070] Create a mapping table to store the mapping information from x86 addresses to ARM addresses. For the initial mapping, divide the entire x86 memory space into multiple regions, each corresponding to an ARM core group. For example, map the low address region of x86 to the memory space of core group 0, map the slightly higher address region to the memory space of core group 1, and so on.

[0071] For the starting address of the array, assuming it is in the low address area, it is mapped to the L2 cache association area of ​​core group 0, initially mapped to ARM address 0x80000000.

[0072] S2.2.2 Core group load monitoring. Use hardware performance counters to monitor the load of each core group, including cache hit rate, memory bandwidth usage, and instruction execution rate. For example, the L2 cache hit rate H0, memory bandwidth B0, and instruction execution rate I0 of core group 0 are continuously obtained through hardware performance counters.

[0073] S2.2.3. Dynamically adjust mapping

[0074] During program execution, the mapping is dynamically adjusted according to the core group load. If the load of core group 0 is too high, for example, the cache hit rate H0 is lower than a certain threshold TH1, or the memory bandwidth B0 exceeds a certain threshold TH2, some address mappings are migrated to the core group with lighter load.

[0075] For addresses such as array+4, array+8, etc., calculate their offsets relative to array. When the mapping of arrays needs to be adjusted, map them to the corresponding positions of the new core group according to the offsets. For example, if array is migrated from core group 0 to core group 1, array+4 will be mapped to the corresponding position of core group 1 according to its offset, while considering cache line alignment, assuming that the cache line size is 64 bytes, to ensure that the mapped address is aligned to the cache line boundary.

[0076] For dynamic addresses, such as array+ecx in loop_iteration, the core group to be mapped is dynamically selected based on the value of ecx and the current load of the core group. In each iteration, the load of the core group is checked. If the load of core group 0 is high and the load of core group 2 is low, array+ecx is mapped to the corresponding position of core group 2 and the mapping table is updated at the same time.

[0077] Using a dynamic address mapping algorithm, the mapping address is adjusted in real time according to the core group's load and cache status, and frequently accessed addresses are mapped to core groups with lighter loads and higher cache hit rates, thereby improving cache utilization.

[0078] S3, instruction conversion, convert x86 instructions into ARM instructions and add prefetch instructions. The specific steps are as follows:

[0079] The result of converting the example x86 instruction in step 1 to ARM instruction is as follows:

[0080] .data

[0081] array:.byte1,2,3,4,5,6,7,8,9,10

[0082] .text

[0083] .global_start

[0084] _start:

[0085] ldrr0,[r1]; corresponds to moveax,[array]

[0086] addr0,#1

[0087] strr0,[r1]; corresponds to mov[array],eax

[0088] ldrr2,[r1,#4]; corresponds to movebx,[array+4]

[0089] subr2,#2

[0090] strr2,[r1,#8]; corresponds to mov[array+8],ebx

[0091] bloop_start_arm

[0092] loop_start_arm:

[0093] movr3,#10

[0094] loop_iteration_arm:

[0095] ldrr4,[r1,r3]; corresponds to movedx,[array+ecx]

[0096] addr4,#3

[0097] strr4,[r1,r3]; corresponds to mov[array+ecx],edx

[0098] subsr3,r3,#1

[0099] bneloop_iteration_arm

[0100] During the conversion process, the conversion is performed according to the characteristics of the ARM instruction set, while taking into account the memory access characteristics. The detailed steps for adding prefetch instructions based on the address remapping results are as follows:

[0101] S3.1, Address analysis. During instruction conversion, for each memory access instruction, query the mapping table generated in the address remapping stage to obtain its mapping address in the ARM architecture. For example, for moveax,[array] corresponding to ldrr0,[r1], find the ARM mapping address of array 0x80000000.

[0102] S3.2, prefetch distance determination. Determine the prefetch distance based on the cache hierarchy and performance data of the ARM architecture. For example, if the prefetch unit of the L2 cache can prefetch data with a distance of 128 bytes, for ldrr0, [r1], add a prefetch instruction to prefetch data near [r1].

[0103] S3.3, Prefetch instruction insertion. Insert prefetch instructions before the corresponding memory access instructions. For ldrr0, [r1], insert pld [r1, #0] to prefetch the data at [r1]. For ldrr2, [r1, #4], insert pld [r1, #4] to prefetch the data at [r1+4]. For ldrr4, [r1, r3] in the loop, insert pld [r1, r3] to prefetch the data at [r1+r3] before each iteration.

[0104] S3.4. Dynamically adjust prefetching. Combine hardware performance counters, such as cache miss rate and memory latency data, to dynamically adjust the prefetch distance and timing. If the cache miss rate is high, increase the prefetch distance or advance the insertion position of the prefetch instruction. For example, if the cache miss rate caused by pld[r1,#4] is still high, adjust it to pld[r1,#8] or insert the prefetch instruction at an earlier position.

[0105] For memory access instructions, prefetch instructions are added based on the address remapping results.

[0106] S4. Dynamically allocate instruction blocks to core groups of ARM many-cores according to performance indicators, using a core allocation method based on reinforcement learning. The specific steps are as follows:

[0107] S4.2. Model initialization.

[0108] State representation. Define the system state, including the load state of the core group and the characteristics of the instruction block. For example, state S can be represented as:

[0109] {core_group_0:{H0,B0,Q0},core_group_1:{H1,B1,Q1},instruction_block:{memory_range,resource_demand}}.

[0110] Action space definition. Defining an action space is the process of assigning instruction blocks to different core groups. For example, action A can be assigning instruction blocks to core group 0, core group 1, etc.

[0111] Reward function design. Design a reward function to determine rewards based on system performance indicators. If the system performance improves after assigning instruction blocks to core groups, a positive reward is given; otherwise, a negative reward is given. For example, the reward function R can be calculated based on the change in cache hit rate and the change in execution time.

[0112] Reinforcement learning training. Use reinforcement learning algorithms, such as Q-learning or deep reinforcement learning algorithms, for training. The agent selects action A based on the current state S, observes the reward function R and the new state S' after executing the action, and updates the strategy. For example, in the initial state, the instruction block is assigned to core group 0 according to the strategy, the performance indicator changes are observed, and the strategy is updated according to the reward function, so that the agent learns the optimal core allocation strategy.

[0113] S4.2. Dynamic adjustment.

[0114] During program execution, the core allocation strategy is continuously implemented using reinforcement learning agents. The state S is updated based on real-time performance data, and actions A are selected based on the learned strategy to dynamically adjust the allocation of instruction blocks.

[0115] For the above optimized instruction blocks, evaluate their memory access range and frequency. For example, for the loop_iteration_arm instruction block, which mainly accesses array and its nearby addresses, it is assigned to core group 0 according to the address remapping information.

[0116] Continuously monitor the performance indicators of the core group, such as cache hit rate, memory bandwidth usage, and instruction execution latency. If core group 0 encounters a performance bottleneck, migrate some instruction blocks to other core groups.

[0117] Adopting a core allocation strategy based on reinforcement learning, dynamically adjusting the allocation of instruction blocks according to the performance feedback and task characteristics of the core group, and achieving optimal utilization of core resources. Using hardware performance counters, real-time performance data is collected to provide a basis for core allocation decisions, thereby improving the adaptability and performance of the system.

[0118] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing ARM multi-core instruction conversion memory access based on reinforcement learning, characterized in that: The specific steps include: Step 1: Establish a many-core instruction pre-allocation model based on reinforcement learning, where the environment is an ARM many-core system, the state is the utilization of the computing core, the action is to allocate instructions to the selected computing core, and the reward function is a reward function based on the utilization of the computing core. The training of the many-core instruction pre-allocation model is completed; load and execute the executable file in the ARM many-core system through dynamic instruction conversion, and extract the current instructions to be converted of the memory access instruction type; Step 2: Use the many-core instruction pre-allocation model to calculate the first computing core to which the current instruction to be converted needs to be allocated and the first address range corresponding to it according to the current ARM many-core system state; Step 3: pre-convert the current instruction to be converted into a first ARM instruction to obtain its first memory address. If the first ARM instruction is assigned to the first computing core, execute step 4; otherwise, assign the first ARM instruction to the first computing core and then execute step 4; Step 4: construct a first prefetch instruction based on the first memory address and the prefetch distance, wherein the memory address of the first prefetch instruction is set to a second memory address, wherein the second memory address includes a first virtual page number and a second page offset, and the second page offset is smaller than the first page offset; The current instruction to be converted is converted into an instruction sequence formed by a first prefetch instruction and a first ARM instruction.

2. The ARM multi-core instruction conversion memory access optimization method according to claim 1, characterized in that: The calculation method of the reward function in step 1 is: ,in, To calculate the average utilization of the core, U i is the utilization of the i-th computing core, n is the total number of computing cores, is the standard deviation of utilization, is the coefficient for adjusting the influence of standard deviation.

3. The ARM multi-core instruction conversion memory access optimization method according to claim 1, characterized in that: The state of the many-core instruction pre-allocation model includes the ARM many-core system state and ARM instruction characteristics, wherein the ARM many-core system state includes cache hit rate, computing core utilization and computing core instruction queue length, and the ARM instruction characteristics include memory access range and computing resource requirements.

4. The ARM multi-core instruction conversion memory access optimization method according to claim 3, characterized in that: The reward function is calculated as follows: , where w1, w2, w3, w4 and w5 are all weight coefficients and w1+w2+w3+w4+w5=1, R1 is the cache hit rate reward, R2 is the computing core utilization reward, R3 is the computing core instruction queue length reward, R4 is the memory access range reward, and R5 is the computing resource demand reward.

5. The ARM multi-core instruction conversion memory access optimization method according to claim 4, characterized in that: The calculation method of the cache hit rate reward is: , where H is the current cache hit rate, H max is the theoretical maximum cache hit rate.

6. The ARM multi-core instruction conversion memory access optimization method according to claim 4, characterized in that: The calculation method of the instruction queue length reward of the computing core is: , where Q i is the instruction queue length of the i-th computing core, Q max The maximum allowed length of the command queue.

7. The ARM multi-core instruction conversion memory access optimization method according to claim 4, characterized in that: The calculation method of the computing resource demand reward is: , where C1 is the computing resource requirement of the instruction and C2 is the available computing resources of the allocated computing core.

8. The ARM multi-core instruction conversion memory access optimization method according to claim 1, characterized in that: The method of allocating the first ARM instruction to the first computing core in step 3 is: obtain the first virtual page in the ARM virtual memory where the first ARM instruction is located, record the first virtual page number and the offset within the first page, and the first virtual page corresponds to the first physical page; determine the second physical page in the first address range, and modify the page table entry related to the first virtual page in the page table to a mapping relationship from the first virtual page to the second physical page, copy the data of the first physical page to the second physical page, and then clear the first physical page.

9. The ARM multi-core instruction conversion memory access optimization method according to claim 1, characterized in that: The pre-fetch distance in step 4 is determined according to the cache hierarchy of the ARM architecture, and is set to a larger value when the cache hit rate of the ARM many-core system is low.

10. The ARM multi-core instruction conversion memory access optimization method according to claim 1, characterized in that: In step 4, the difference between the second intra-page offset and the first intra-page offset is increased.

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