Task scheduling method and related device

Abstract

The invention discloses a task scheduling method and a related device. According to the technical scheme disclosed by the invention, the task and the scheduling strategy are generated on the host side; the host side can directly issue the task and the task scheduling strategy to the equipment side; the device side controls the task to be issued to the processor core according to the scheduling strategy so that the processor core can execute the task; in this way, through cooperation between the host side and the equipment side, the task scheduling process is completed with low delay overhead.

Description

Technical Field

[0001] The present disclosure generally relates to the field of artificial intelligence technology. More specifically, the present disclosure relates to a task scheduling method and related devices. Background Art

[0002] Heterogeneous computing systems integrate different types of processors into the same computing system, allowing multiple processors to play their respective computing advantages and achieve higher computing performance. In heterogeneous computing systems, scheduling strategies directly affect the utilization of hardware resources on the device side and the waiting time of tasks, thereby affecting the execution speed of programs.

[0003] In the existing technology, generating a better scheduling strategy often requires more time overhead. How to speed up the task scheduling process in order to utilize a scheduling algorithm with better performance has become a technical problem. In view of this, it is urgent to provide a task scheduling solution to facilitate task scheduling with lower delay overhead. Summary of the invention

[0004] In order to at least solve one or more technical problems described in the above background technology section, the present disclosure proposes the following technical solutions and multiple embodiments thereof.

[0005] In the first aspect, the present disclosure discloses a task scheduling method, which is applied to the device side of a heterogeneous computing device, including: receiving tasks and scheduling policies related to the tasks from a host side, wherein the scheduling policies are generated on the host side; and sending the tasks to the processor core on the device side according to the scheduling policies to facilitate the execution of the tasks.

[0006] In the second aspect, the present disclosure also discloses a task scheduling method performed by a heterogeneous computing device, which includes a host side and a device side; the method includes: on the host side: generating and sending tasks and scheduling policies related to the tasks; on the device side: receiving tasks and scheduling policies; and sending tasks to the processor core on the device side according to the scheduling policies to facilitate the execution of tasks.

[0007] In a third aspect, the present disclosure further discloses a heterogeneous computing device, including a device side and a host side; wherein the host side is configured to: generate and send tasks and scheduling policies related to the tasks; the device side is configured to: receive tasks and scheduling policies; and send tasks to the processor core on the device side according to the scheduling policies to facilitate the execution of the tasks.

[0008] The task scheduling method and heterogeneous computing device disclosed in the present disclosure can directly send the task to the device side after generating the task, and then the host side generates and sends the scheduling strategy; the device side sends the task to the processor core according to the scheduling strategy so that the processor core can execute the task; in this way, the scheduling strategy is generated on the host side, and the interception of the task is executed on the device side, and through the coordinated cooperation between the host side and the device side, the task scheduling process is completed with a lower delay overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0010] Figure 1 An exemplary structural schematic diagram of a board in some embodiments of the present disclosure is shown.

[0011] Figure 2 An exemplary structural diagram of a combined processing device in some embodiments of the present disclosure is shown.

[0012] Figure 3 An exemplary structural diagram of a computing device in some embodiments of the present disclosure is shown.

[0013] Figure 4 An exemplary structural diagram of a processor core in some embodiments of the present disclosure is shown.

[0014] Figure 5 An exemplary schematic diagram is shown when a processor core in some embodiments of the present disclosure intends to write data into a processor core of another cluster.

[0015] Figure 6 An exemplary structural diagram of a heterogeneous computing system in some embodiments of the present disclosure is shown.

[0016] Figure 7 An exemplary schematic diagram of a software stack in some embodiments of the present disclosure is shown.

[0017] Figure 8 An exemplary schematic diagram of a reinforcement learning scheduling algorithm in some embodiments of the present disclosure is shown.

[0018] Fig. 9 An exemplary flow chart of a task scheduling method in some embodiments of the present disclosure is shown.

[0019] Fig.10 An exemplary schematic diagram of a task scheduling method in some embodiments of the present disclosure is shown.

[0020] Fig.11 An exemplary schematic diagram of a device-side queue in some embodiments of the present disclosure is shown.

[0021] Fig.12 An exemplary schematic diagram of using the PG algorithm for task scheduling in some embodiments of the present disclosure is shown.

[0022] Fig.13 An exemplary schematic diagram of the Event mechanism in some embodiments of the present disclosure is shown.

[0023] Fig.14 An exemplary schematic diagram of a host-side queue and a device-side queue in some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0025] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0027] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0028] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. In order to clearly explain the technical solution disclosed in the present disclosure, the following first introduces the relevant hardware implementation and related technical terms of the embodiment of the present disclosure.

[0029] Figure 1 FIG. 1 shows an exemplary structural diagram of a board 10 in some embodiments of the present disclosure. Figure 1 As shown, the board 10 includes a chip 101, which is a system-on-chip, or a system on chip (SoC), which integrates one or more combined processing devices. The combined processing device is an artificial intelligence computing unit that supports various deep learning and machine learning algorithms to meet the intelligent processing needs in complex scenarios in the fields of computer vision, speech, natural language processing, data mining, etc. In particular, deep learning technology is widely used in the field of cloud intelligence. A notable feature of cloud-based intelligent applications is the large amount of input data, which places high demands on the storage capacity and computing power of the platform. The board 10 of this embodiment is suitable for cloud-based intelligent applications and has huge off-chip storage, on-chip storage, and powerful computing power.

[0030] The chip 101 is connected to an external device 103 via an external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. The data to be processed can be transmitted from the external device 103 to the chip 101 via the external interface device 102. The calculation result of the chip 101 can be transmitted back to the external device 103 via the external interface device 102. According to different application scenarios, the external interface device 102 can have different interface forms, such as a PCIe interface.

[0031] The board 10 also includes a storage device 104 for storing data, which includes one or more storage units 105. The storage device 104 is connected to the control device 106 and the chip 101 through a bus and transmits data. The control device 106 in the board 10 is configured to control the state of the chip 101. To this end, in an application scenario, the control device 106 may include a microcontroller unit (MCU).

[0032] Figure 2 FIG. 2 shows an exemplary structural diagram of a combined processing device in some embodiments of the present disclosure. Figure 2 As shown, the combined processing device 20 includes a computing device 201 , an interface device 202 , a processing device 203 and a storage device 204 .

[0033] The computing device 201 is configured to execute user-specified operations, and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0034] The interface device 202 is used to transmit data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 can obtain input data from the processing device 203 via the interface device 202 and write it into the storage device on the computing device 201 chip. Further, the computing device 201 can obtain control instructions from the processing device 203 via the interface device 202 and write them into the control cache on the computing device 201 chip. Alternatively or optionally, the interface device 202 can also read data in the storage device of the computing device 201 and transmit it to the processing device 203.

[0035] The processing device 203, as a general processing device, performs basic controls including but not limited to data handling, starting and / or stopping the computing device 201. Depending on the implementation, the processing device 203 can be a central processing unit (CPU), a graphics processing unit (GPU) or one or more types of processors in other general and / or special processors, which include but are not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing device 201 disclosed in the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are integrated and considered together, the two are regarded as forming a heterogeneous multi-core structure.

[0036] The memory 204 is used to store data to be processed, and may be DRAM or DDR memory, and is typically 16 GB or larger in size, and is used to store data of the computing device 201 and / or the processing device 203 .

[0037] Figure 3The following is a schematic diagram of an exemplary structure of a computing device 201 in some embodiments of the present disclosure. In these embodiments, the computing device 201 is implemented as a multi-core intelligent processor. The computing device 201 is used to process input data such as computer vision, speech, natural language, and data mining. Figure 3 The computing device 201 in the embodiment adopts a multi-core hierarchical structure design. The computing device 201 is a system on chip, which includes multiple clusters, and each cluster includes multiple processor cores. In other words, the computing device 201 is composed of a hierarchy of system on chip - cluster - processor core.

[0038] At the system-on-chip level, Figure 3 As shown, the computing device 201 includes an external storage controller 301 , a peripheral communication module 302 , an on-chip interconnect module 303 , a synchronization module 304 , and multiple clusters 305 .

[0039] There can be multiple external storage controllers 301. Figure 3 2 are shown in the figure as an example, which are used to respond to access requests issued by the processor core and access external storage devices, such as Figure 2 DRAM 204 in the chip, thereby reading data from outside the chip or writing data to outside the chip. The peripheral communication module 302 is used to receive control signals from the processing device 203 through the interface device 202 to start the computing device 201 to perform tasks. The on-chip interconnect module 303 connects the external storage controller 301, the peripheral communication module 302 and multiple clusters 305 to transmit data and control signals between each module. The synchronization module 304 is a global synchronization barrier controller (GBC) used to coordinate the working speed of each cluster to ensure information synchronization. Multiple clusters 305 are the computing core of the computing device 201. Figure 3 Four clusters 305 are shown as examples. With the development of hardware, the computing device 201 disclosed herein may also include 8, 16, 64, or even more clusters 305. The clusters 305 are used to efficiently execute deep learning algorithms.

[0040] At the cluster level, Figure 3 As shown, each cluster 305 includes a plurality of processor cores (IPU cores) 306 and a memory core (MEM core) 307 .

[0041] The figure shows four processor cores 306 as an example, but the present disclosure does not limit the number of processor cores 306 .

[0042] Figure 4The schematic diagram of the exemplary structure of the processor core in some embodiments of the present disclosure is shown. Each processor core 306 includes three modules: a control module 41 , a computing module 42 and a storage module 43 .

[0043] The control module 41 is used to coordinate and control the operation of the computing module 42 and the storage module 43 to complete the deep learning task, and includes an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. The instruction fetch unit 411 is used to obtain instructions from the processing device 203, and the instruction decode unit 412 decodes the obtained instructions and sends the decoding results to the computing module 42 and the storage module 43 as control information.

[0044] The operation module 42 includes a vector operation unit 421 and a matrix operation unit 422. The vector operation unit 421 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear changes; the matrix operation unit 422 is responsible for the core calculation of the deep learning algorithm, namely matrix multiplication and convolution.

[0045] The storage module 43 is used to store or move related data, including a neuron RAM (NRAM) 431, a weight RAM (WRAM) 432, an input / output direct memory access module (IODMA) 433, and a move direct memory access module (MVDMA) 43. NRAM 331 is used to store feature maps and intermediate results calculated by the processor core 306; WRAM 432 is used to store the weights of the deep learning network; IODMA 433 controls the memory access between NRAM 431 / WRAM 432 and DRAM 204 through the broadcast bus 309; MVDMA 434 is used to control the memory access between NRAM 431 / WRAM 432 and SRAM 308.

[0046] Back to Figure 3 The storage core 307 is mainly used for storage and communication, that is, to store shared data or intermediate results between the processor cores 306, and to perform communication between the cluster 305 and the DRAM 204, communication between the clusters 305, and communication between the processor cores 306. In other embodiments, the storage core 307 has the ability of scalar operation and is used to perform scalar operation.

[0047] The storage core 307 includes a shared memory unit (SRAM) 308, a broadcast bus 309, a cluster direct memory access module (cluster direct memory access, CDMA) 310 and a global direct memory access module (global direct memory access, GDMA) 311. The SRAM 308 plays the role of a high-performance data transfer station. The data reused between different processor cores 306 in the same cluster 305 does not need to be obtained from the DRAM 204 by each processor core 306, but is transferred between the processor cores 306 through the SRAM 308. The storage core 307 only needs to quickly distribute the reused data from the SRAM 308 to multiple processor cores 306, so as to improve the efficiency of inter-core communication and greatly reduce on-chip and off-chip input / output access.

[0048] The broadcast bus 309, CDMA 310 and GDMA 311 are respectively used to perform communication between processors 306, communication between clusters 305 and data transmission between clusters 305 and DRAM 204. They will be described below.

[0049] The broadcast bus 309 is used to complete high-speed communication between the processor cores 306 in the cluster 305. The broadcast bus 309 of this embodiment supports inter-core communication modes including unicast, multicast and broadcast. Unicast refers to point-to-point (i.e., single processor core to single processor core) data transmission, multicast is a communication mode of transmitting a copy of data from SRAM 308 to specific processor cores 306, and broadcast is a communication mode of transmitting a copy of data from SRAM 308 to all processor cores 306, which is a special case of multicast.

[0050] CDMA 310 is used to control memory access to SRAM 308 between different clusters 305 within the same computing device 201 . Figure 5 An exemplary schematic diagram is shown when a processor core in some embodiments of the present disclosure intends to write data to a processor core of another cluster, to illustrate the working principle of CDMA 310. In this application scenario, the same computing device includes multiple clusters. For the convenience of explanation, only cluster 0 and cluster 1 are shown in the figure. Cluster 0 and cluster 1 each include multiple processor cores. Also for the convenience of explanation, cluster 0 in the figure only shows processor core 0, and cluster 1 only shows processor core 1. Processor core 0 intends to write data to processor core 1.

[0051] First, processor core 0 sends a unicast write request to write data into the local SRAM0. CDMA0 acts as the master and CDMA1 acts as the slave. The master pushes the write request to the slave, that is, the master sends the write address AW and write data W to transfer the data to SRAM1 of cluster 1. Then the slave sends a write response B in response. Finally, processor core 1 of cluster 1 sends a unicast read request to read the data from SRAM1.

[0052] Back to Figure 3 , GDMA311 cooperates with the external memory controller 301 to control the memory access from the SRAM308 of the cluster 305 to the DRAM204, or reads data from the DRAM204 to the SRAM308. As can be seen from the above, the communication between the DRAM204 and the NRAM431 or WRAM432 can be realized through two channels. The first channel is to directly connect the DRAM204 and the NRAM431 or WRAM432 through the IODMA433; the second channel is to first transmit the data between the DRAM204 and the SRAM308 through the GDMA311, and then transmit the data between the SRAM308 and the NRAM431 or WRAM432 through the MVDMA434. Although it seems that the second channel requires more components to participate and the data flow is longer, in fact, in some embodiments, the bandwidth of the second channel is much greater than the first channel, so the communication between the DRAM204 and the NRAM431 or WRAM432 may be more efficient through the second channel. The embodiment of the present disclosure can select the data transmission channel according to its own hardware conditions.

[0053] In other embodiments, the functions of GDMA311 and IODMA433 can be integrated into the same component. For the convenience of description, this disclosure regards GDMA311 and IODMA433 as different components. For those skilled in the art, as long as the functions they implement and the technical effects they achieve are similar to those of this disclosure, they belong to the protection scope of this disclosure. Furthermore, the functions of GDMA311, IODMA433, CDMA310, and MVDMA434 can also be implemented by the same component. Similarly, as long as the functions they implement and the technical effects they achieve are similar to those of this disclosure, they belong to the protection scope of this disclosure.

[0054] Heterogeneous computing systems

[0055] Heterogeneous computing systems integrate different types of processors into the same computing system, so that multiple processors can play their respective computing advantages and achieve higher computing performance. Generally speaking, heterogeneous computing systems include a host side and a device side, and the processors on the host side and the device side have different instruction set architectures. Among them, the device side is equipped with multiple processor cores to provide powerful parallel computing capabilities. The host side is mainly responsible for running the operating system and various applications, and coordinating the working order and synchronization relationship between the processor cores on the device side. The host side can use a central processing unit (CPU), a field programmable gate array (FPGA), etc., and the device side can use an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a neural network processor (NPU), a machine learning processor (MLU), a tensor processor (TPU) and a graphics processor (GPU). In some embodiments, a heterogeneous computing system can be obtained by combining a CPU and a board 10 . In these embodiments, the CPU is connected to the board 10 as an external device 103 via an external interface device 102 .

[0056] Figure 6 FIG. 2 shows an exemplary structural diagram of a heterogeneous computing system in some embodiments of the present disclosure. Figure 6 As shown, the heterogeneous computing system includes a host side and a device side, and the two establish a communication connection through the PCIe interface, so that the host side sends tasks to be executed and data to be calculated to the device side, and the device side returns the calculation results to the host side. Further observing the internal structure of the device side, it includes multiple processor cores with computing capabilities, and the processor cores can process computing tasks in parallel; for example, taking the board 10 used on the device side as an example, the multiple processor cores 306 in the board 10 can process computing tasks in parallel. Figure 6 In the heterogeneous computing system shown, only the components related to the present embodiment are shown. It is obvious to a person skilled in the art that the heterogeneous computing system may also include common components different from the components shown in the figure, including but not limited to a controller on the host side and an arithmetic logic unit (ALU).

[0057] Software Stack

[0058] A large number of processor cores on the device side provide powerful parallel computing capabilities. In order to effectively utilize the parallel computing capabilities on the device side, a software stack consisting of multiple layers is formed to support the development of applications. Figure 7 An exemplary schematic diagram of a software stack in some embodiments of the present disclosure is shown. Figure 7 As shown, the software stack may include a framework layer, an acceleration library layer, a runtime layer, a driver layer, and an application programming interface (API) layer provided by the framework layer, the acceleration library layer, the runtime layer, and the driver layer. It can be understood that the framework layer, the acceleration library layer, the runtime layer, and the driver layer provide specific implementations for the corresponding API layer, and the API layer is used to provide a calling interface to the upper layer.

[0059] In such Figure 7 In the software stack shown, the Driver layer is responsible for the low-level interaction between the host side and the device side (including establishing hardware connections between the host side and the device side, initializing hardware devices on the device side, and directly accessing the hardware on the device side). As a bridge between the host side and the device side, the Driver layer includes two parts: the host side Driver layer and the device side Driver layer; above the Driver layer is the Driver API layer. The runtime layer is built on the Driver API layer, which shields the complex details of the underlying hardware on the device side and implements methods for device management, memory processing, and thread management; above the runtime layer is the Runtime API layer. The acceleration library layer is built on the Runtime API layer, which further shields the details of the underlying hardware on the device side and provides implementation methods for specific algorithms (such as fast Fourier transform); above the acceleration library layer is the acceleration library API layer. The framework layer shields the underlying technical details such as gradient calculation to help developers design more complex applications; above the framework layer is the framework layer API. Common deep learning frameworks include TensorFlow, PyTorch, Keras, Caffe, MXNet, and Theano.

[0060] Scheduling strategies and scheduling algorithms

[0061] In a heterogeneous computing system composed of a host side and a device side, the host side is good at executing control-intensive programs such as searching, parsing, and sorting, while the device side is more suitable for data-intensive programs in the reasoning / training scenarios of artificial intelligence (AI) models or other scenarios containing a large number of matrix operations. When running a program on the device side of a heterogeneous computing system, the host side first needs to split the program into multiple tasks, and then send the tasks to the device side, and the device side can send the tasks received from the host side to the processor core of the device side for processing. Specifically, a task scheduler can be set on the device side, and the task scheduler on the device side can send the tasks sent by the host side to the processor core of the device side for processing according to the scheduling strategy; for example, taking the board 10 used on the device side as an example, the host side transmits the tasks to be executed and the scheduling strategy to the board 10 through the external interface device 102, and the control device 106 of the board 10 is provided with a task scheduler, and the task scheduler controls the processor core 306 in the chip 101 to execute the task according to the scheduling strategy.

[0062] Generally speaking, the scheduling of a large number of tasks is a cyclic iterative process, and the scheduling of all tasks is completed through multiple scheduling rounds; in some embodiments, in each scheduling round, the scheduling strategy is used to determine the number of tasks to be issued in the current scheduling round and which processor cores to issue these tasks to, so as to reduce the task waiting time and efficiently utilize the parallel computing capabilities of the device side; in other embodiments, multiple task queues are used to store tasks to be executed. In these embodiments, the scheduling strategy is used to determine which task queue is selected in the current scheduling round to issue tasks, and how many tasks are issued to the selected task queue. Furthermore, the scheduling strategy can be generated by the host side or the device side based on the deployed scheduling algorithm. It can be understood that the scheduling algorithm directly affects the waiting time and execution time of the task, thereby affecting the execution speed of the program.

[0063] At present, there are two common scheduling algorithms: heuristic scheduling algorithms and reinforcement learning scheduling algorithms. Heuristic scheduling algorithms usually use experience and heuristic rules to find the local optimal solution that meets specific goals, and are suitable for workloads with uniformly distributed task durations and a single task.

[0064] Figure 8 An exemplary schematic diagram of a reinforcement learning scheduling algorithm in some embodiments of the present disclosure is shown. It should be noted that: Figure 8 The intelligent agent shown may be a parameterized policy network, which may be a neural network model including an input layer, an output layer, and two hidden layers. For those skilled in the art, policy networks with different structures may be designed according to actual needs, and this disclosure does not limit this. Figure 8As shown in the figure, the reinforcement learning scheduling algorithm generates scheduling strategies through the continuous interaction between the agent and the environment. The agent uses the observed environmental state as input, calculates the action probability distribution for the action space, and then selects actions according to the probability to obtain output. In the task scheduling scenario: the environment can be regarded as the execution process of the task on the device side, and the environmental state can include the execution status of the task and the usage status of the device; the action corresponds to the scheduling strategy; the action space corresponds to the scheduling strategy space, which is a collection of scheduling strategies.

[0065] At a time step of the reinforcement learning scheduling algorithm, the agent first takes the environment state as input to select the scheduling strategy for the current time step, and then inputs the scheduling strategy into the environment; the device side can schedule tasks according to the output scheduling strategy, and after sending the tasks to the processor core according to the scheduling strategy, the environment state and the reward for the scheduling strategy of the current time step can be observed from the environment; the state and reward are fed back to the agent to adjust the method for generating subsequent scheduling strategies.

[0066] It can be understood that the reinforcement learning scheduling algorithm can adjust the scheduling strategy in time according to the changes in workload. When facing dynamic mixed and diverse workloads, it can learn the best scheduling strategy online to maximize the resource utilization on the device side. Generally speaking, the quality of the scheduling strategy generated by the reinforcement learning scheduling algorithm is better than that of the heuristic scheduling algorithm. However, the reinforcement learning scheduling algorithm, especially the deep reinforcement learning scheduling algorithm, requires a lot of training for the policy network and has a slow convergence speed; moreover, the reasoning speed of the reinforcement learning scheduling algorithm is slower than the policy generation speed of the heuristic scheduling algorithm, resulting in an increase in the overall delay.

[0067] Therefore, how to speed up the task scheduling process so as to utilize a scheduling algorithm with better performance becomes a technical problem. In view of this, the present disclosure proposes a task scheduling method so as to achieve task scheduling with lower delay overhead through the cooperation between the host side and the device side. Fig. 9 An exemplary flow chart of a task scheduling method in some embodiments of the present disclosure is shown, and the method is applied to the device side of a heterogeneous computing device, such as Fig. 9 As shown, the method includes: step 901, receiving a task and a scheduling policy related to the task from the host side, wherein the scheduling policy is generated on the host side; step 902, sending the task to the processor core on the device side according to the scheduling policy to facilitate the execution of the task.

[0068] Fig.10 An exemplary schematic diagram of a task scheduling method in some embodiments of the present disclosure is shown. Fig.10As shown, the host side can split the code program to be executed (shown as Procedure in the figure) to obtain multiple tasks, and generate a scheduling strategy for the task according to the scheduling algorithm. In some embodiments, the code program refers to a program for training a deep learning model; in other embodiments, the code program refers to a program for reasoning using a deep learning model; through the communication connection between the host side and the device side, the host side first sends the task to the device side, and then sends the scheduling strategy to the device side, the device side receives the task and the scheduling strategy, and then sends the task to the processor core for processing according to the scheduling strategy.

[0069] It can be understood that in the task scheduling method disclosed in this disclosure, the tasks and scheduling strategies are generated on the host side; the host side can directly send the tasks to the device side without intercepting the tasks; after the device side receives the scheduling strategy, it controls the tasks to be sent to the processor core for processing according to the scheduling strategy. In this way, through the coordination between the host side and the device side, the task scheduling process is completed with a lower delay overhead.

[0070] Optionally, the host side of the disclosed embodiment can directly send the task to the device side without intercepting the task. In these embodiments, the host side and the device side see the same task almost at the same time, but the difference is that the device side intercepts the task and schedules the task according to the scheduling strategy. It should be pointed out that for learning scheduling algorithms such as reinforcement learning scheduling algorithms, because there is a large time overhead in the reasoning of the model, intercepting the task on the host side, then generating a scheduling strategy based on the scheduling algorithm and then sending the task will inevitably increase the delay in task sending. According to the task scheduling method disclosed in the present disclosure, a complex scheduling algorithm can be deployed on the host side of a heterogeneous computing system, and the host side can quickly send the task to the device side, and generate a scheduling strategy based on the scheduling algorithm; after receiving the task and the scheduling strategy, the device side sends the task according to the scheduling strategy; in this way, through the adjustment of the task scheduling process, a pipeline parallel execution between "sending the task from the host side to the device side" and "generating a scheduling strategy on the host side" is formed in the whole process, thereby accelerating the task scheduling process and adapting to the introduction of complex reinforcement learning scheduling algorithms into task scheduling scenarios.

[0071] In addition, in the cross-stream scenario, the Event mechanism of the Driver layer on the device side implements order preservation between tasks by placing events (placeEvent) and waiting for events (waitEvent). If the host side controls the dispatching of tasks according to the scheduling strategy, on the one hand, the logic code implemented by Event needs to be moved from the Driver layer on the device side to the host side, which will undoubtedly involve a large amount of engineering tasks; on the other hand, the host side needs to dispatch the placeEvent task first, and then dispatch the waitEvent task, which will increase the program running time. According to the method disclosed in the present disclosure, the host side can directly send the task to the device side after generating the task, and the order preservation between tasks can be implemented based on the Event of the Driver layer on the device side, thereby avoiding the problems described in the above two aspects.

[0072] Furthermore, in some embodiments, the host side splits the code program to be executed into multiple tasks, and sends the task to the device side after recording the basic information of the task. After receiving the task and scheduling strategy, the device side sends the task to the processor core for processing according to the scheduling strategy. In these embodiments, the host side can generate a scheduling strategy based on the recorded basic information of the task. The basic information of the task includes but is not limited to: the execution duration of the task, the number of processor cores required to execute the task, the index of the task, and other attributes that can identify the task.

[0073] As Figure 7 As shown, when developing applications, programmers can write applications based on the framework layer API, or based on the acceleration layer API, Runtime API, or even Driver API. To ensure that tasks issued by applications written in different ways can be scheduled by the scheduling algorithm, the scheduling algorithm must be deployed on the software path that all four methods pass through, such as the Driver API layer on the host side, the Driver layer on the host side, and the Driver layer on the device side. Since the Driver layer runs in kernel state, it is very sensitive to software overhead, and it is a time-consuming project to implement a set of library functions that a scheduling algorithm relies on in kernel state, therefore, in some embodiments, the scheduling strategy is generated at the driver application programming interface layer on the host side.

[0074] It can be understood that the driver application programming interface layer on the host side is the DriverAPI layer mentioned above. Regardless of whether the program is written based on the framework layer API, acceleration layer API, RuntimeAPI or DriverAPI, the DriverAPI layer is the necessary software path. Then, after the scheduling algorithm is deployed at the DriverAPI layer, no matter whether the program is written based on any approach, after the program is split into tasks, the tasks can be sent to the device side for execution according to the deployed scheduling algorithm; that is to say, the scheduling algorithm deployed at the DriverAPI layer can uniformly support programs written based on all approaches, and realize the scheduling optimization and integration of programs written by all approaches, thereby introducing the scheduling algorithm into heterogeneous computing systems with higher development efficiency.

[0075] In some embodiments, the device side intercepts the task before sending the task to the processor core of the device side.

[0076] It is understandable that when there are a large number of tasks, directly sending all tasks to the processor core on the device side will cause multiple tasks to try to occupy the same processor core, resulting in each task being unable to obtain sufficient computing resources to run efficiently, which will significantly reduce the execution speed of the tasks. Therefore, in this case, the device side needs to intercept the tasks. The so-called interception means not continuing to send tasks, waiting for other tasks to be executed before sending the intercepted tasks. In some embodiments, the device side suspends sending the intercepted tasks to the processor core; in other embodiments, the interception of tasks is achieved by placing the tasks on the device side in a waiting queue. In these embodiments, the tasks in the waiting queue wait for other tasks to be executed before being sent.

[0077] In some embodiments, intercepting tasks on the device side includes: establishing at least one device side queue for recording tasks; storing tasks received from the host side in at least one device side queue to facilitate sending tasks on the device side to the processor core on the device side.

[0078] Fig.11 An exemplary schematic diagram of a device side queue in some embodiments of the present disclosure is shown, such as Fig.11 As shown, in some embodiments, multiple device-side queues for recording tasks are maintained on the device side, and intercepted tasks can be stored in the device-side queues. The tasks in each device-side queue can adopt a first-in-first-out (FIFO) strategy, so that the task that first enters the queue is placed at the front of the queue, and subsequent tasks are arranged in sequence behind. When the tasks in the device-side queue need to be sent to the processor core, the tasks are selected from the front of the queue for sending.

[0079] In some embodiments, before sending the task to the processor core of the device side, the device side determines whether to intercept the task according to the scheduling policy.

[0080] It is understandable that the host side can select a scheduling algorithm to generate a scheduling policy, thereby sending tasks to the device side in advance, and then sending the scheduling policy to the device side. In this case, it can be determined according to the scheduling policy which tasks can be sent to the processor core on the device side for execution and which tasks need to be intercepted.

[0081] In some embodiments, the device side determines whether to intercept the task based on the scheduling strategy, including: when the resource utilization on the device side is higher than the first predetermined threshold, intercepting the task; when the resource utilization on the device side is not higher than the first predetermined threshold, sending the task to the processor core on the device side.

[0082] It is understandable that the device side is configured with hardware resources including computing devices and storage devices, and resource utilization refers to the degree to which these hardware devices are effectively utilized. Resource utilization can be calculated by the ratio of the amount of hardware resources actually used to the total amount of hardware resources owned by the device. In some embodiments, the device side resource utilization refers to the proportion of processor cores on the device side that are being used to execute tasks to all processor cores. In some embodiments, a first predetermined threshold is set for the device side resource utilization. When the device side resource utilization is not higher than the first predetermined threshold, it means that there are currently more idle processor cores on the device side, and the computing resources are not efficiently utilized, so that the task can be directly sent to the processor core on the device side without interception; when the device side resource utilization is higher than the first predetermined threshold, it means that there is currently a higher operating load on the device side, so the task can be intercepted.

[0083] In some embodiments, when the resource utilization on the device side is higher than a second predetermined threshold, the scheduling strategy is generated by the host side based on a reinforcement learning scheduling algorithm; when the resource utilization on the device side is not higher than the second predetermined threshold, the scheduling strategy is generated by the host side based on a heuristic scheduling algorithm.

[0084] It is understandable that the reinforcement learning scheduling algorithm and the heuristic scheduling algorithm have their own advantages and disadvantages. The heuristic scheduling algorithm generates scheduling strategies based on simple rules, and can quickly obtain approximate optimal solutions under limited computing resources. However, when faced with multiple mixed tasks, the heuristic scheduling algorithm cannot adjust the scheduling strategy or scheduling parameters in time according to the changes in the workload, resulting in delayed fluctuations in the workload and decreased resource utilization on the device side; the reinforcement learning scheduling algorithm can cope with more complex workloads, but the reasoning speed of the reinforcement learning scheduling algorithm is relatively slow, resulting in an increase in the delay in task issuance. Therefore, the disclosed embodiment proposes a scheduling method that integrates the reinforcement learning scheduling algorithm and the heuristic scheduling algorithm, and adopts different scheduling algorithms for different workloads. When there are more idle processor cores on the device side (that is, the resource utilization on the device side is low), the heuristic scheduling algorithm is adopted to generate a scheduling strategy so that the task can be issued as soon as possible; when there are fewer idle processor cores on the device side (that is, the resource utilization on the device side is high), the device side is not sensitive to the speed of task issuance. At this time, the host side can adopt the reinforcement learning scheduling algorithm to generate a scheduling strategy. In this scenario, although the reasoning speed of the reinforcement learning scheduling algorithm is slow and there is a delay in the scheduling strategy, this delay is acceptable to the device side, and the scheduling strategy generated based on the reinforcement learning scheduling algorithm is better than the heuristic scheduling algorithm and can be more suitable for the current scenario. In some embodiments, after multiple rounds of scheduling using the reinforcement learning scheduling algorithm, if the resource utilization rate on the device side is not higher than the second predetermined threshold, the host side can switch the method for generating the scheduling strategy from the reinforcement learning scheduling algorithm to the heuristic scheduling algorithm.

[0085] Among them, when the resource utilization rate on the device side is not higher than the second predetermined threshold, the reinforcement learning scheduling algorithm can obtain the basic information of the tasks in the host side queue, and the basic information of the tasks includes but is not limited to: the execution time of the tasks, the number of processor cores required to execute the tasks, the index of the tasks, and other attributes that can identify the tasks. Afterwards, the reinforcement learning scheduling algorithm can perform inference calculations based on the basic information of these tasks to obtain a scheduling strategy. The reinforcement learning scheduling algorithm can be obtained through training.

[0086] Fig.12 An exemplary schematic diagram of using a policy gradient (PG) algorithm for task scheduling in some embodiments of the present disclosure is shown. The embodiments of the present disclosure can train a reinforcement learning scheduling algorithm based on the PG algorithm. Fig.12As shown, the device side uses n+1 device side queues (Queue) to record tasks. In the entire task scheduling process, m+1 loops (Loop) are used to complete the scheduling of all tasks. Each loop traverses all queues in turn and schedules the tasks in the queues. It can be understood that as tasks are issued, the number of tasks in each queue gradually decreases. Therefore, each loop only schedules tasks for queues containing remaining tasks. Fig.12 obj i,j represents the process of scheduling the j+1th queue in the i+1th cycle, that is, a scheduling round; further, Fig.12 The right half of the dispatch unit (ObjCell) shows obj i,j specific process.

[0087] Understandably, Fig.12 The ObjCell in corresponds to a time step of the PG algorithm. A trajectory in the PG algorithm can include multiple ObjCells. As can be seen from the figure, at a time step, the PG algorithm: first observes the state of the task (State, S), takes S as input, uses the policy network to calculate the scheduling strategy probability distribution (p) of the scheduling strategy space and selects the scheduling strategy (a) according to probability; executes the scheduling strategy, and after sending the task to the processor core according to the scheduling strategy, obtains the reward (r) for the scheduling strategy (a) of the current time step; the t in the dotted box (meaning that it may exist) in the figure represents the trajectory termination identifier. If the trajectory termination identifier is observed at the current time step, the policy network can be updated according to the reward recorded in the current trajectory and the scheduling strategy probability distribution, and the updated policy network can be used to schedule the tasks of the next trajectory. Repeat the above process until the policy network converges and obtains a trained policy network. When the resource utilization rate on the device side is higher than the second predetermined threshold, the trained policy network can infer the scheduling strategy.

[0088] In some embodiments, using a heuristic scheduling algorithm to generate a scheduling strategy includes: first, determining a feasible scheduling strategy space, that is, a set of all feasible scheduling strategies; and then randomly selecting a scheduling strategy from the scheduling strategy space. In some embodiments, using a heuristic scheduling algorithm to generate a scheduling strategy includes: setting the number of tasks to be sent according to the number of idle processor cores and the size of the task; sending tasks to idle processor cores according to the number of tasks to be sent; in these embodiments, the size of the task can be measured according to the number of processor cores required to execute the task. After determining the number of processor cores required to execute each task (a), the number of idle processor cores (b) is divided by the number of processor cores and rounded down, that is, ( represents rounding down) as the number of tasks to be issued; then, For example, the heuristic scheduling algorithm can set the number of tasks to be sent according to an empirical value, and send the tasks in a queue on a device side to the processor core according to the number of tasks to be sent.

[0089] In some embodiments, the second predetermined threshold is set based on experience, for example, the second predetermined threshold is set to a value between 60% and 70%. In other embodiments, a set of test cases are prepared in advance, and the test cases are run under the heuristic scheduling algorithm and the reinforcement learning scheduling algorithm, respectively, and the performance indicator data under the two scheduling algorithms are recorded, and then the appropriate second predetermined threshold is determined based on the performance indicator data; wherein the performance indicator data includes but is not limited to: device-side resource utilization, service quality indicators reflecting fairness, and program execution time.

[0090] In some embodiments, when the resource utilization on the device side is higher than a second predetermined threshold, the method for scheduling tasks further includes: the device side feeds back resource contention information to the host side, so that the host side generates a scheduling strategy based on a reinforcement learning scheduling algorithm; further, after the host side generates a scheduling strategy based on the reinforcement learning scheduling algorithm, the device side can receive the scheduling strategy so as to send the task to the processor core on the device side according to the scheduling strategy.

[0091] If the resource utilization rate on the device side is higher than the second predetermined threshold, it indicates that the resources on the device side are tight and there is resource contention. At this time, the device side can send a resource contention signal to the host side to feed back resource contention information to the host side, and then the host side can start the reinforcement learning scheduling algorithm to generate a scheduling strategy based on the resource contention information.

[0092] In some embodiments, the device side sends the task to the processor core of the device side according to the scheduling policy, including: identifying the dependency relationship between tasks; and sending the task to the processor core of the device side according to the scheduling policy and the dependency relationship.

[0093] It is understood that the dependencies between tasks include data dependencies, which means that one task can only be executed after another task is completed. The placeEvent and waitEvent times in the Event mechanism of the device-side Driver layer can effectively manage the dependencies between tasks. Fig.13 An exemplary schematic diagram of the Event mechanism in some embodiments of the present disclosure is shown, such as Fig.13As shown, there are 3 tasks sent from the host side in the device side queue i, which are i1, i2, and i3 in order of execution. There are another 3 tasks sent from the host side in the device side queue j, which are j1, j2, and j3 in order of execution. Among these 6 tasks, there is a dependency relationship between i1 and j1, that is, j1 needs to be executed after i1 is executed. According to the Event mechanism, a placeEvent task is added between i1 and i2 to indicate whether i1 has been executed; a waitEvent task is added in front of j1 to indicate whether j1 can be sent; further, when the waitEvent task is still in the device side queue, j1 cannot be sent, and needs to wait for task i1 in queue i and the placeEvent task to be sent before the waitEvent task can be sent. Only after that can j1 be sent.

[0094] Therefore, in some embodiments, the device side can identify the dependencies between tasks, and then add placeEvent tasks and waitEvent tasks to the task queue based on the dependencies between the tasks. When issuing tasks to a queue according to the scheduling policy, if there is a placeEvent task in the tasks to be issued according to the scheduling policy, and the waitEvent task associated with the placeEvent task has not yet been issued, it is necessary to suspend the issuance of tasks in the queue, and wait for the waitEvent task associated with the placeEvent task to be issued before restarting the issuance of tasks in the queue.

[0095] In some embodiments, after sending the tasks in the device side to the processor core of the device side, the device side can also generate a synchronization update signal based on the sent tasks, and the synchronization update signal is used to synchronously update the device side queue and the host side queue set on the host side.

[0096] Fig.14 FIG. 2 shows an exemplary schematic diagram of a host-side queue and a device-side queue in some embodiments of the present disclosure. Fig.14 As shown, after the host side splits the program into multiple tasks, the host side generates multiple host side queues to record the tasks. The host side generates a scheduling policy for the tasks in the host side queue, so that the host side queue and the scheduling policy can be sent to the device side together; or, the host side first sends the host side queue to the device side, and after the scheduling policy is generated, the scheduling policy is sent to the device side.

[0097] As mentioned above, the task scheduling process needs to go through multiple scheduling rounds. After the device side issues the task according to the current scheduling strategy, the host side generates the next round of scheduling strategy again. Therefore, during the task execution process, it is necessary to maintain the consistency of the device side queue and the host side queue. Therefore, it is necessary to synchronize the device side queue and the host side queue after the task is issued on the device side. In some embodiments, after the device side issues a part of the task to the processor core for processing, a synchronization update signal is sent to the host side, and the host side deletes the corresponding task from the host side queue according to the synchronization update signal, and then generates a new scheduling strategy again according to the updated host side queue, thereby ensuring that the task execution process is carried out in an orderly manner. In some embodiments, the synchronization update signal includes information about the task being issued, such as an index of the task or other attributes that can uniquely identify the task.

[0098] The present disclosure also discloses a task scheduling method performed by a heterogeneous computing device, which includes a host side and a device side; the method includes: on the host side: generating and sending tasks and scheduling policies related to the tasks; on the device side: receiving tasks and scheduling policies; and sending tasks to the processor core on the device side according to the scheduling policies to facilitate the execution of tasks.

[0099] Corresponding to the task scheduling method disclosed in the present disclosure as described above, the present disclosure discloses the following embodiments of the task scheduling method executed by a heterogeneous computing device:

[0100] In some embodiments, the scheduling policy is generated at the driver application programming interface layer on the host side.

[0101] In some embodiments, before sending the task to the processor core on the device side, the process includes, on the device side: intercepting the task.

[0102] In some embodiments, before sending the task to the processor core on the device side, the process includes: on the device side: determining whether to intercept the task according to a scheduling policy.

[0103] In some embodiments, determining whether to intercept a task based on a scheduling policy includes, on the device side: when the resource utilization on the device side is higher than a first predetermined threshold, intercepting the task; and when the resource utilization on the device side is not higher than the first predetermined threshold, sending the task to the processor core on the device side.

[0104] In some embodiments, intercepting tasks includes, on the device side: establishing a device side queue for recording tasks; storing received tasks in the device side queue to facilitate sending the tasks in the device side to the processor core of the device side.

[0105] In some embodiments, the method further includes: when the resource utilization on the device side is higher than a second predetermined threshold, the host side generates a scheduling strategy based on a reinforcement learning scheduling algorithm; and when the resource utilization on the device side is not higher than the second predetermined threshold, the host side generates a scheduling strategy based on a heuristic scheduling algorithm.

[0106] In some embodiments, when the resource utilization rate on the device side is higher than a second predetermined threshold, the method further includes: the device side sends resource contention information; the host side receives the resource contention information to generate a scheduling strategy based on a reinforcement learning scheduling algorithm.

[0107] In some embodiments, sending tasks to a processor core on a device side according to a scheduling policy includes, on the device side: identifying dependencies between tasks; and sending tasks to a processor core on the device side according to the scheduling policy and the dependencies.

[0108] In some embodiments, the method further includes: establishing a host side queue for recording tasks on the host side; after sending the tasks on the device side to the processor core on the device side, including on the device side: generating a synchronization update signal according to the sent tasks, which is used to synchronously update the device side queue and the host side queue.

[0109] In some embodiments, generating and sending a task on the host side includes, on the host side: using a host side queue to record information about the task; and sending the task to the device side. It is understandable that the host side only records the basic information of the task, and does not intercept the task, that is, the task will be quickly sent to the device side according to the original normal process while being recorded by the host side. It can be considered that the host side and the device side see the same task passing almost at the same time, and record it successively. The difference is that the device side intercepts the task and schedules the task according to the scheduling strategy. In this way, the task scheduling process is accelerated through the coordination of the host side and the device side. Further, the present disclosure discloses a heterogeneous computing device, including a device side and a host side; wherein the host side is configured to: generate and send tasks and scheduling strategies related to the tasks; the device side is configured to: receive tasks and scheduling strategies; and send tasks to the processor core of the device side according to the scheduling strategy to facilitate the execution of tasks.

[0110] In summary, the specific functions implemented by the heterogeneous computing device and the task scheduling method performed by the heterogeneous computing device provided in the embodiments of this specification can be explained in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments, so they will not be repeated here.

[0111] It should be pointed out that the task scheduling method proposed in this disclosure deploys a reinforcement learning model at the DriverAPI layer on the host side, and only records but does not intercept all tasks that pass through, and only intercepts tasks on the device side. The host side outputs scheduling decisions based on the reinforcement learning model and sends the decision information to the device side, and the device side issues tasks based on the scheduling decision information. In this way, through the collaboration between the user-state-based host side and the kernel-state-based device side, the reinforcement learning scheduling algorithm can be introduced with only minor changes to the existing implementation method, and the delay overhead can be controlled within a small range.

[0112] It should be noted that in the disclosed embodiments, the scheduled tasks can be computing tasks obtained by disassembling applications in various fields, and the data involved can be of various types. For example, the relevant fields can be machine translation, sentiment analysis, text summarization, text classification, named entity recognition, etc. in natural language processing (NLP), and the corresponding data types can include text data, vocabulary embedding, sentence structure, etc.; the relevant fields can be facial recognition, image classification, target detection, image segmentation, etc. in computer vision (CV), and the corresponding data types can include pixel data, image features, etc.; the relevant fields can be intelligent assistants, automatic subtitle generation, speech to text conversion, etc. in speech recognition (ASR), and the corresponding data types can include audio signals, spectrograms, etc.; the relevant fields can also be generative AI applications, which refer to artificial intelligence technologies that use complex algorithms, models, and rules to learn from large-scale data sets to create new original content, such as but not limited to the ability to create text, pictures, sounds, videos, and codes, etc.; the corresponding data types can include image data, audio data, video data, voice data, text data, document data, etc.

[0113] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art may appreciate the parts that are not described in detail in a certain embodiment of the present disclosure, and may also refer to the relevant descriptions of other embodiments.

Claims

1. A task scheduling method, applied to a device side of a heterogeneous computing device, comprising: receiving a task and a scheduling policy associated with the task from a host side, wherein the scheduling policy is generated on the host side; and The task is sent to the processor core on the device side according to the scheduling strategy to facilitate execution of the task.

2. The method according to claim 1, wherein: The scheduling strategy is generated at the driver application programming interface layer on the host side.

3. The method according to claim 1, further comprising: Before sending the task to the processor core on the device side, the task is intercepted.

4. The method according to claim 1, further comprising: Before sending the task to the processor core on the device side, it is determined whether to intercept the task according to the scheduling policy.

5. The method according to claim 4, wherein: Determining whether to intercept the task according to the scheduling strategy includes: When the device-side resource utilization rate is higher than a first predetermined threshold, intercepting the task; and When the resource utilization rate on the device side is not higher than a first predetermined threshold, the task is sent to the processor core on the device side.

6. The method according to any one of claims 3 to 5, wherein: Intercepting the task includes: Establishing a device-side queue for recording the tasks; The received tasks are stored in the device side queue, so as to facilitate sending the tasks in the device side to the processor core of the device side.

7. The method according to any one of claims 1 to 6, further comprising: When the resource utilization rate on the device side is higher than a second predetermined threshold, the scheduling strategy is generated by the host side based on a reinforcement learning scheduling algorithm; as well as When the resource utilization rate on the device side is not higher than the second predetermined threshold, the scheduling strategy is generated by the host side based on a heuristic scheduling algorithm.

8. The method according to claim 7, wherein: When the device-side resource utilization is higher than a second predetermined threshold, the method further includes: The resource contention information is fed back to the host side so that the host side can generate the scheduling strategy based on the reinforcement learning scheduling algorithm.

9. The method according to claim 1, wherein: Sending the task to the processor core on the device side according to the scheduling strategy includes: identifying dependencies between the tasks; According to the scheduling strategy and the dependency relationship, the task is sent to the processor core on the device side.

10. The method according to claim 6, wherein: After sending the task in the device side to the processor core of the device side, the method includes: According to the issued task, a synchronous update signal is generated for synchronously updating the device-side queue and the host-side queue arranged on the host side.

11. A task scheduling method performed by a heterogeneous computing device, the heterogeneous computing device comprising a host side and a device side; the method comprising: On the host side: generating and sending tasks and scheduling policies related to the tasks; On the device side: Receiving the task and the scheduling strategy; The task is sent to the processor core on the device side according to the scheduling strategy to facilitate execution of the task.

12. The method according to claim 11, wherein: The scheduling strategy is generated at the driver application programming interface layer on the host side.

13. The method according to claim 11, wherein: Before sending the task to the processor core on the device side, the process includes: The task is intercepted.

14. The method according to claim 11, wherein: Before sending the task to the processor core on the device side, the process includes: Whether to intercept the task is determined according to the scheduling strategy.

15. The method according to claim 14, wherein: Determining whether to intercept the task according to the scheduling policy includes, on the device side: When the resource utilization rate on the device side is higher than a first predetermined threshold, intercepting the task; as well as When the resource utilization rate on the device side is not higher than a first predetermined threshold, the task is sent to the processor core on the device side.

16. The method according to any one of claims 13 to 15, wherein: Intercepting the task includes, on the device side: Establishing a device-side queue for recording the tasks; The received tasks are stored in the device side queue, so as to facilitate sending the tasks in the device side to the processor core of the device side.

17. The method according to any one of claims 11 to 16, further comprising: When the resource utilization rate on the device side is higher than a second predetermined threshold, the host side generates the scheduling strategy based on a reinforcement learning scheduling algorithm; as well as When the resource utilization rate on the device side is not higher than the second predetermined threshold, the host side generates the scheduling strategy based on a heuristic scheduling algorithm.

18. The method according to claim 17, wherein: When the device-side resource utilization is higher than a second predetermined threshold, the method further includes: The device side sends resource contention information; The host side receives the resource contention information so as to generate the scheduling strategy based on the reinforcement learning scheduling algorithm.

19. The method according to claim 11, wherein: Sending the task to the processor core on the device side according to the scheduling strategy includes, on the device side: identifying dependencies between the tasks; According to the scheduling strategy and the dependency relationship, the task is sent to the processor core on the device side.

20. The method of claim 16, further comprising: The host side establishes a host side queue for recording the task; After the task in the device side is sent to the processor core of the device side, the method further includes: generating a synchronous update signal on the device side according to the sent task, so as to synchronously update the queue on the device side and the queue on the host side.

21. The method according to claim 20, wherein: Generating and sending tasks on the host side includes: Using the host-side queue to record information of the task; and The task is sent to the device side.

22. A heterogeneous computing device, comprising a device side and a host side; wherein: The host side is configured to: generate and send tasks and scheduling strategies related to the tasks; The device side configuration is: receiving the task and the scheduling policy; and The task is sent to the processor core on the device side according to the scheduling strategy to facilitate execution of the task.

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