Turbo product code-oriented decoding method and system

Abstract

The invention provides a Turbo product code-oriented decoding method and system, and relates to the technical field of communication, and the method comprises the steps: initializing a Turbo product code decoder; obtaining channel information to be decoded; quantizing the channel information into signed character type data; transmitting the quantized channel information to a GPU (Graphics Processing Unit) in an asynchronous transmission mode; respectively updating the channel information according to rows and columns through a Chase algorithm by utilizing an intra-frame parallelism degree consistent with the size of a GPU thread block until the maximum number of iterations is reached, and finishing the updating of the soft output information; performing hard decision according to the channel information and the updated soft output information; transmitting the hard decision result to a host memory of the CPU in an asynchronous transmission mode; and after decoding of all code words is completed, resource release is carried out. According to the invention, the decoding process with low delay, high throughput rate and high reliability can be realized, and the resource utilization rate and the decoding efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a decoding method and system for Turbo product codes. Background Art

[0002] Turbo product code is an error correction coding method based on a two-dimensional check matrix. Turbo product code has strong error correction capability, a large minimum Hamming distance, and can maintain good error correction effect under high code rate conditions. By selecting different component codes and adjusting the size of the matrix, the code rate of Turbo product code can be flexibly changed. At the same time, Turbo product code can perform rows and columns in parallel during encoding and decoding, which is very suitable for parallel processing architecture, and can give full play to the parallel computing capabilities of modern high-speed processors and hardware platforms to improve coding efficiency.

[0003] Using GPU as a general hardware platform and combining it with the decoding process of Turbo product codes to perform parallel processing of rows and columns can meet the requirements of modern communication systems for high reliability, high speed and low latency, which is of great significance for promoting the development of communication systems towards high performance and intelligence.

[0004] Traditional communication systems are developed based on dedicated hardware, with high operation and maintenance costs and long development cycles. In recent years, general-purpose processors (such as CPUs and GPUs) have developed into multi-core processors with powerful computing resources. However, in measurement and control communications, the signal transmission distance is long, the attenuation is large, and it is susceptible to noise and interference, resulting in low coding efficiency and high resource consumption. It is difficult to meet the requirements of low latency and high throughput. Especially when multiple tasks are carried out simultaneously, the processing power of traditional dedicated hardware often becomes a bottleneck. In dynamic measurement and control tasks, resource utilization efficiency is low, it cannot flexibly adapt to sudden demands, and lacks scalability and adaptability. Summary of the invention

[0005] In order to solve the problem that the traditional communication system in the prior art is mainly developed based on dedicated hardware, in the measurement and control communication, the signal transmission distance is long, the attenuation is large, and it is easily affected by noise and interference, resulting in low coding efficiency, high resource consumption, and difficulty in meeting the requirements of low latency and high throughput. Especially when multiple tasks are performed simultaneously, the processing capacity of traditional dedicated hardware often becomes a bottleneck. In dynamic measurement and control tasks, the resource utilization efficiency is low, it cannot flexibly adapt to sudden demands, and lacks scalability and adaptability. In view of the above problems, the present invention provides a decoding method and system for Turbo product codes.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect

[0008] An embodiment of the present invention provides a decoding method for Turbo product codes, comprising:

[0009] S1: Initialize Turbo product code decoder;

[0010] S2: Obtain channel information to be decoded;

[0011] S3: quantize the channel information into signed character data;

[0012] S4: Transmit the quantized channel information to the GPU via asynchronous transmission;

[0013] S5: using the intra-frame parallelism consistent with the GPU thread block size, the soft output information is iteratively updated row by row and column by column according to the channel information through the Chase algorithm until the maximum number of iterations is reached;

[0014] S6: making a hard decision on the decoding result according to the channel information and the updated soft output information;

[0015] S7: transmitting the hard decision result to the host memory of the CPU via asynchronous transmission;

[0016] S8: After decoding of all codewords is completed, resources are released.

[0017] Second aspect

[0018] An embodiment of the present invention provides a decoding system for Turbo product codes, comprising:

[0019] processor;

[0020] A memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the decoding method for Turbo product codes according to the first aspect is implemented.

[0021] The third aspect

[0022] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the decoding method for Turbo product codes according to the first aspect is implemented.

[0023] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0024] In the present invention, the Turbo product code decoder is first initialized, then the channel information to be decoded is obtained, and the channel information is quantized into signed character data and stored in the GPU. The intra-frame parallelism consistent with the GPU thread block size is used to update the channel information by row and column respectively through the Chase algorithm until the maximum number of iterations is reached, the update of the soft output information is completed, and the soft output information is transmitted to the host memory of the CPU through an asynchronous transmission method, so that after the decoding of all code words is completed, the resources are released. A low-latency, high-throughput and high-reliability decoding process is achieved, resource utilization and decoding efficiency are improved, operation and maintenance costs and resource consumption are reduced, and memory access bandwidth and memory access efficiency are greatly improved, so as to well adapt to the diversified and dynamic measurement and control task requirements, improve communication quality and system reliability, and ensure the stable operation of measurement and control communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram of a decoding method for Turbo product codes provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of an overall decoding architecture of a decoding method for Turbo product codes provided by an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of storing a test sequence in bits according to an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of using inter-frame and intra-frame parallelism provided by an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the structure of a decoding system for Turbo product codes provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0032] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0033] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0034] Reference Manual Attached Figure 1 , shows a flowchart of a decoding method for Turbo product codes provided in an embodiment of the present invention.

[0035] The embodiment of the present invention provides a decoding method for Turbo product codes, which can be implemented by a decoding device for Turbo product codes, and the decoding device for Turbo product codes can be a terminal or a server. The processing flow of the decoding method for Turbo product codes can include the following steps:

[0036] S1: Initialize the Turbo product code decoder.

[0037] A turbo product code decoder is a hardware or software module specifically used to decode turbo product codes (TPC). Turbo product codes are an efficient error correction coding method that combines two or more simple codes (usually linear component codes) in a Cartesian product manner to improve the error correction capability in data transmission. The function of the decoder is to receive data interfered by noise in the channel and recover the codeword closest to the original information through a specific decoding algorithm (such as the Chase algorithm or the soft decision algorithm).

[0038] It should be noted that initializing the Turbo product code decoder ensures that the entire decoding process can run in an efficient and reliable environment. By reasonably configuring computing resources, loading necessary parameters, and optimizing the parallel computing environment, it provides stable technical support for subsequent complex decoding operations, while significantly improving decoding efficiency and result accuracy. This process not only ensures the stability and flexibility of the Turbo product code decoder, but also lays the foundation for its efficient application in actual communication systems.

[0039] In a possible implementation, S1 specifically includes:

[0040] S101: Initialize Turbo product code parameters, where the Turbo product code parameters specifically include the number of frames processed in parallel for a single asynchronous stream, component code length, information length, the number of Chase algorithm error positions, the number of iterations, and the number of asynchronous streams.

[0041] Among them, asynchronous stream is a parallel computing mechanism in GPU, which allows different computing tasks to be executed independently in different streams without blocking each other. The number of frames processed in parallel refers to the number of coded frames that can be processed in parallel in an asynchronous stream. The code length of the component code refers to the length of each component code (usually N), that is, the number of bits contained in each row or column in the check matrix. The information length refers to the length of the original information bit, that is, the number of data information bits before encoding. The Chase algorithm is a decoding algorithm that focuses on error correction at the most unreliable position. The number of iterations refers to the maximum number of cycles in which rows and columns alternately update the soft output information during the decoding process of Turbo product codes. The number of asynchronous streams refers to the number of asynchronous streams that exist at the same time. Each stream can process one or more coded frames in parallel.

[0042] S102: Allocate memory space and video memory space for the channel information and the decoding result of the channel information respectively.

[0043] Among them, channel information refers to the modulated or encoded data received from the communication channel, including signals that may be interfered by noise during transmission. The decoding result is the output data generated by the Turbo product code decoder through an iterative decoding process based on the channel information and the rules of the Turbo product code. It is usually the decoded codeword or original data information. The memory space refers to the memory (RAM) in the CPU host, which is used to store channel information, decoding results and intermediate data. The video memory space refers to the storage space on the GPU, which is used to store data at high speed and support parallel computing.

[0044] S103: Initialize the Alpha parameter and the Beta parameter, and store the Alpha parameter and the Beta parameter in a constant memory.

[0045] Among them, the Alpha parameter and the Beta parameter are weight parameters used to update the soft information of the Turbo product code, which affect the iterative calculation process of the channel information and the soft output information. Constant Memory is a special memory type of GPU, which is used to store global data that remains unchanged during operation and can be accessed by all threads.

[0046] S104: Load the check matrix of the Turbo product code from the file, and allocate the check matrix to the constant memory of the GPU.

[0047] The check matrix is ​​the core mathematical description of the Turbo product code, which defines the constraints in the codeword. The check matrix can be used to check whether a codeword complies with the coding rules.

[0048] S105: Generate an error image of the Turbo product code, and store the error image in a constant memory of the GPU.

[0049] The error pattern (Error Pattern / Image) is a predefined data structure or table used to assist the Turbo product code decoding process, which describes the possible error distribution and its corresponding correction information.

[0050] S106: Configuring a parallel execution environment of a GPU for a Turbo product code decoder.

[0051] It should be noted that by initializing various parameters, allocating memory resources and configuring the GPU parallel environment, efficient basic support is provided for the entire Turbo product code decoding process. By reasonably allocating memory and video memory space, the data transmission bottleneck between the CPU and GPU is significantly reduced. The Alpha, Beta parameters and check matrix are stored in the GPU constant memory, reducing the delay in GPU thread access to data. At the same time, configuring the GPU parallel execution environment makes thread allocation more reasonable and fully utilizes the computing power of the GPU. In addition, preloading the check matrix and error image helps to quickly correct errors in the channel information in subsequent iterations, improving the accuracy and efficiency of decoding.

[0052] In a possible implementation, S106 specifically includes: creating parallel threads, and setting the corresponding number of GPU thread blocks and the number of GPU thread blocks according to row soft output information or column soft output information of the Turbo product code check matrix.

[0053] It should be noted that by efficiently utilizing the parallel computing power of GPU, the computational efficiency, resource utilization and decoding accuracy of Turbo product code decoding are optimized. At the same time, this configuration enhances the flexibility and scalability of the decoder, and can adapt to different hardware platforms and data sizes, which is a key step in the implementation of high-performance decoding algorithms.

[0054] S2: Obtain channel information to be decoded.

[0055] It should be noted that the core task of decoding is to perform error correction based on channel information, and obtaining the channel information to be decoded clarifies the input source and content of the decoder, ensuring that subsequent calculations have a reliable data basis.

[0056] S3: Quantize the channel information into signed character data.

[0057] Among them, signed character data is a fixed-point format (such as char or int8), usually ranging from -128 to 127, which is used to represent the quantized value of channel information. By quantizing the channel information into signed character data, the overhead of data storage and transmission is effectively reduced, while retaining the key confidence characteristics of the channel information. This optimization reduces the data transmission delay between the host and the GPU, and provides an efficient data input path for subsequent parallel decoding. In addition, quantization processing can also improve the storage efficiency of GPU calculations, allowing more data to be loaded into shared memory, accelerating the decoding process and reducing the occupation of hardware resources.

[0058] It should be noted that the present invention quantizes the channel information of the host end to 8 bits, that is, the data type of the channel information is signed character data.

[0059] Reference Manual Attached Figure 2 , showing a schematic diagram of the overall decoding architecture of a decoding method for Turbo product codes provided in an embodiment of the present invention.

[0060] Figure 2In , h_input is the channel information stored in the host memory, which indicates the data received from the communication channel as the input of the data to be decoded. h_output is the decoding result stored in the host memory, which indicates the output data returned from the GPU after the decoding is completed. The CPU is responsible for controlling the entire process, including initializing decoding parameters, managing GPU resources, and sending control signals. The PCIe bus represents the data transmission channel between the host and the GPU, which is used to transfer data from the CPU to the GPU's video memory, or from the GPU back to the host memory. d_input represents the channel information in the GPU global memory, which is a copy of h_input transmitted to the GPU through PCIe and is used for decoding calculation. d_output is the decoding result in the GPU global memory, which is the result data after the decoding is completed and is transmitted back to the CPU from the GPU. c_H refers to the Turbo product code check matrix constant memory, which is used to check whether the data meets the coding rules. c_Alpha and c_Beta: respectively represent the alpha parameter and beta parameter used in the decoding process, which are the weight values ​​for dynamically adjusting the soft output information in the iteration. c_Table is an error pattern table, which is used to quickly locate the error position from the verification results, so as to update the soft output information. sh_soft_out[N][N] stores two-dimensional soft output information (N×N size). This is the main storage area for soft output information in each iteration and is frequently accessed to update the soft output value. sh_channel[N][N] refers to the storage of channel information, which is a local copy of the channel data and is used to complete the update in combination with the soft output information. Each thread in the GPU register corresponds to a register block, which mainly stores intermediate data related to the thread. test_set[2^p] refers to the storage of test sequences. Each row generates 2^p test sequences for simulating error modes. p_set[p] stores the p least reliable position indexes. Syndrome stores the verification results (such as parity check) and is used to determine whether the test sequence meets the rules of the check matrix. correlation[2^p] is the correlation of the test sequence, which is used to evaluate the reliability of the candidate test sequence and the competing codeword. p_sort[2^p] is the result of sorting the correlation, which is used to select the best candidate codeword or competing codeword.

[0061] The h_input channel information in the host memory is asynchronously transferred to the global memory of the GPU through the PCIe bus and stored as d_input. Then the CPU initializes constant parameters such as c_H, c_Alpha, c_Beta, and c_Table, and transfers them to the constant memory of the GPU. At the same time, the channel information is loaded from d_input to the shared memory sh_channel[N][N] and initialized to the initial value of the soft output information. The soft output information is initialized in the shared memory sh_soft_out[N][N]. At the same time, register resources are allocated for storing intermediate data (such as test_set, p_set, etc.), and the alpha and beta parameters corresponding to the current iteration number are read from the constant memory c_Alpha and c_Beta. The soft output information sh_soft_out[N][N] is read row by row, and the soft output value is updated using the channel information sh_channel[N][N] and the alpha parameter. In the shared memory sh_soft_out, the p positions with the smallest confidence are searched in parallel row by row and stored in the register p_set. Generate 2^p test sequences according to p_set, and calculate the correlation correlation[2^p] of the test sequences row by row, and store the results in the register. Sort the test sequences in p_sort according to their correlation, select candidate codewords and competing codewords, and if there is no competing codeword, use beta to update the soft output information; otherwise, update the soft output information based on the correlation of the candidate codeword and the competing codeword. Transpose the updated soft output information sh_soft_out in the shared memory to support the next round of iterative updates by column. Until the maximum number of iterations is reached. Make a hard decision on the final updated soft output information, generate the decoding result, and store it in the global memory d_output. Finally, transfer d_output back to the host memory through the PCIe bus and store it as h_output. Release the global memory and shared memory resources in the GPU, notify the CPU that the task is completed, and close the asynchronous transmission stream. Make full use of the parallel computing capability and multi-level storage structure of the GPU, significantly improving the speed and efficiency of decoding.

[0062] S4: Transmit the quantized data to be decoded to the GPU via asynchronous transmission.

[0063] Among them, the asynchronous transmission mode refers to a mode of data transmission between the host (CPU) and the device (GPU). The quantized data to be decoded is the quantized soft information data received from the channel, which represents the confidence of each bit and is used in the Turbo product code decoding process.

[0064] It should be noted that the quantized channel information is transmitted from the host memory to the GPU memory through asynchronous transmission, which greatly improves the data transmission efficiency. Asynchronous transmission enables data transmission and GPU calculation to be carried out in parallel, reducing the idle time of system resources, thereby improving the overall computing throughput.

[0065] Reference Manual Attached Figure 3 , showing a schematic diagram of storing a test sequence in bits provided by an embodiment of the present invention.

[0066] Figure 3 In the example, test sequence 1, test sequence 2, and test sequence 8 represent a possible error pattern or candidate sequence for error correction in Turbo product code decoding. The length of the test sequence is 64 bits, corresponding to the code length of the Turbo product code component code. These test sequences are generated by the Chase algorithm and are used to check the least reliable bit in the decoding process. The numbers from 1 to 64 represent the bit positions in each test sequence. The test sequence has a total of 64 bits, and each bit corresponds to a bit position. uint64_t is an unsigned long integer type that can store 64-bit binary numbers. test_set[1], test_set[2], and test_set[8] all represent a combination of 64 binary bits. 101000110...10 is a binary representation. Each test sequence is finally stored in uint64_t in binary form. And each bit (0 or 1) in the binary number corresponds to a bit value of the test sequence.

[0067] In Turbo product code decoding, we first need to find the most unreliable bit position through the confidence value. According to the position of the most unreliable bit, a set of test sequences is generated through the Chase algorithm, and the generated test sequences are stored in binary form. During the decoding process, the generated test sequences are compared with the actual signal, and the optimal sequence is selected by calculating the correlation. The test sequences are used to correct error bits and improve the accuracy of Turbo product code decoding. Through compact storage methods and parallelization strategies, the efficiency of test sequence generation and use is improved, and the performance and accuracy of Turbo product code decoding are ultimately enhanced.

[0068] In a possible implementation manner, after S4 and before S5, the following further includes:

[0069] Register storage resources are allocated for the test sequence, the least reliable position index of the test sequence, the space required for the sorting process storage index, the verification result and the correlation, and the soft output information and channel information are stored in the shared memory space as unsigned short integer or half floating point type.

[0070] Initialize the channel information and soft output information in the shared memory. Specifically, the char data of the channel information is converted into a floating point number and multiplied by a decimal, and then stored in the channel information shared memory in a half floating point form.

[0071] It should be noted that by allocating register storage resources for key data (such as test sequence, least reliable position index, sorting storage index, verification result and correlation), the access delay and resource competition between threads are greatly reduced, thereby improving computing efficiency. At the same time, storing soft output information and channel information in shared memory space as unsigned short integer or half floating point type can effectively reduce memory usage and optimize GPU memory bandwidth utilization.

[0072] Reference Manual Attached Figure 4 , showing a schematic diagram of using inter-frame and intra-frame parallelism provided by an embodiment of the present invention.

[0073] Figure 4 In , codeword 1, codeword 2, and codeword x all represent multiple codewords to be decoded (i.e., the encoded data blocks to be transmitted). These codewords are the input data of the Turbo product code decoding process. Each codeword is a 64×64 two-dimensional matrix, i.e., a component code with a code length of 64. The 57×57 grid area represents the part of each codeword that needs to be actually decoded, which is a 57×57 submatrix. Thread block 1, thread block 2, and thread block x all represent that each thread block corresponds to a codeword, which means that each codeword is assigned to a thread block on the GPU for parallel processing. T1, T2, T3, and T64 all represent threads in a thread block. Each thread block contains 64 threads, and each thread is responsible for processing a row of data (row update) or a column of data (column update) in a codeword matrix.

[0074] Figure 4 The two levels of parallelism of Turbo product code parallel decoding are demonstrated, inter-frame parallelism and intra-frame parallelism. Inter-frame parallelism utilizes the multi-thread block capability of GPU and can process multiple codewords simultaneously, thus significantly improving throughput. Intra-frame parallelism fully utilizes the parallel capability within the thread block, with each thread processing a row or a column, reducing serial calculations and improving the decoding efficiency and throughput of Turbo product codes.

[0075] S5: Using the intra-frame parallelism that is consistent with the GPU thread block size, the soft output information is iteratively updated row by row and column by column according to the channel information through the Chase algorithm until the maximum number of iterations is reached.

[0076] Among them, intra-frame parallelism refers to the matching of the thread block size configured on the GPU with the parallelism of the soft output information processing within the frame. The Chase algorithm is a soft-input and soft-output algorithm in Turbo product code decoding, which is used to generate test sequences and perform error correction. Soft output information refers to the signal quality evaluation value output by the decoder or receiver, which reflects the probability or confidence that each bit or symbol is a specific value (such as 0 or 1), rather than a hard decision. Row-by-row update and column-by-column update are key steps in the Turbo product code decoding process. The soft output information in the row and column directions of the check matrix is ​​iteratively updated respectively. The maximum number of iterations is used to limit the computational complexity and avoid infinite loops.

[0077] It should be noted that by utilizing the intra-frame parallelism of the GPU thread block size and the efficient error correction mechanism of the Chase algorithm, the soft output information is updated row by row and column by column until the number of iterations reaches the preset value. This method fully utilizes the parallel computing capability of the GPU, allowing each row or column to be updated simultaneously, greatly improving the throughput of Turbo product code decoding.

[0078] In a possible implementation, S5 specifically includes:

[0079] S501: Read parameter alpha, parameter beta, soft output information and channel information from the register.

[0080] Among them, the register is a high-speed storage unit on the GPU chip, which is used to store data that needs to be accessed quickly, such as alpha, beta, the least reliable position index, etc. The parameter alpha is used to control the weight of the soft output information and channel information update. The parameter beta is used to adjust the soft output information in the competition codeword selection, and plays a default correction role when the competition codeword cannot be determined.

[0081] S502: Convert the channel information and the soft output information into floating point data, update the soft output information by using the parameter alpha, and convert the updated soft output information into half floating point data and store it in the shared memory.

[0082] S503: Calculate the soft output information in the shared memory in parallel by row, generate a preset number of least reliable position indexes, and store the least reliable position indexes in a register.

[0083] The row-wise parallel computing refers to updating the check matrix of the Turbo product code row by row. By utilizing the parallel capability of the GPU, each row is processed simultaneously by a thread block, and the least reliable position index is the bit with the lowest confidence.

[0084] It should be noted that those skilled in the art can set the size of the preset number according to actual conditions, and the present invention does not limit this.

[0085] S504: Generate a test sequence of soft output information according to the least reliable position index, and update the soft output information.

[0086] The test sequence refers to generating possible error pattern combinations based on the least reliable position index. The test sequence is used to simulate possible error distributions and detect and correct errors through the constraints of the check matrix.

[0087] S505: Calculate the test sequence correlation according to the test sequence and update the soft output information.

[0088] The test sequence correlation refers to selecting the optimal test sequence and updating the soft output information according to the test sequence correlation.

[0089] S506: Determine whether the corresponding bits of the candidate test sequence and the remaining test sequences are the same. If they are the same, determine the contention codeword and update the soft output information; otherwise, use the beta value to update the soft output information.

[0090] Among them, the candidate test sequence is calculated based on the correlation of the test sequence to select the possible correct bit state. The remaining test sequence refers to the remaining test sequence after excluding the candidate test sequence, which is used for further detection and analysis. The competitive codeword reflects the optimal path for updating the soft output information.

[0091] S507: Parallel transposition of the updated soft output information.

[0092] S508: Repeat steps S501-S507 until the maximum number of iterations is reached, and the update of the soft output information is completed.

[0093] It should be noted that the Chase algorithm uses the unreliable position of soft output information to generate test sequences, effectively reducing the complexity of error correction and improving the accuracy of decoding. The alternating row and column update process combined with the efficient thread management of the GPU not only ensures the real-time decoding, but also reduces the cost of hardware resources, providing a low-latency, high-performance solution for modern high-reliability communication systems.

[0094] In a possible implementation manner, S504 specifically includes:

[0095] S5041: Generate a test sequence for each row according to the least reliable position index.

[0096] S5042: Update the bit value of the test sequence to update the soft output information.

[0097] It should be noted that by focusing on the most unreliable position to generate a test sequence, the computational complexity is significantly reduced, the specificity of error correction is improved, more accurate error correction is achieved, and the convergence of soft output information is accelerated.

[0098] In a possible implementation manner, S505 specifically includes:

[0099] Calculate the check result of each test sequence and determine whether the check result meets the rules of the check matrix. If so, correct the error position by querying the error pattern table; otherwise, update the correlation value of each test sequence and update the soft output information according to the correlation value.

[0100] It should be noted that by calculating the verification results of the test sequence and judging whether the rules of the check matrix are met, the error position can be quickly located and corrected, greatly improving the accuracy of error correction. When the verification is successful, the error position is directly corrected through the error pattern table, reducing the number of iterations and improving the decoding efficiency; when the verification fails, the correlation value is used to further update the soft output information to make it closer to the true value, and gradually optimize the decoding result. This design not only ensures the efficiency of error correction, but also improves the robustness of decoding, and can adapt to complex channel environments.

[0101] In a possible implementation manner, S506 specifically includes:

[0102] Determine the competing codeword based on the candidate test sequence and the remaining test sequences, and judge whether the competing codeword exists. If so, update the soft output information by combining the correlation value of the candidate codeword and the competing codeword. Otherwise, use the beta value to update the soft output information.

[0103] It should be noted that by determining the competing codewords through the candidate test sequences and the remaining test sequences, and adopting different update strategies according to whether they exist, the accuracy and robustness of the soft output information update can be significantly improved. When the competing codeword exists, updating the codewords based on the correlation values ​​of the candidate codewords and the competing codewords helps to optimize the error correction path and make the soft output information closer to the true value, thereby improving the accuracy of decoding; when the competing codeword does not exist, the beta value is used for updating to ensure that the soft output information can be adjusted in each round of iteration to avoid stagnation or non-convergence.

[0104] S6: Make a hard decision on the decoding result according to the channel information and the updated soft output information.

[0105] Among them, the hard decision is the final clear decision made based on the soft output information, which converts the continuous value (such as confidence) into a discrete value. By iteratively updating the soft output information, the decoder fully exploits the redundant information contained in the received signal and channel information, making the final hard decision closer to the actual transmitted bit value, thereby reducing the bit error rate.

[0106] S7: The hard decision result is transmitted to the host memory of the CPU via asynchronous transmission.

[0107] The soft output information refers to the final output of the Turbo product code decoding process, which is the original data information restored after multiple iterations and error correction.

[0108] It should be noted that the transmission of soft output information from the GPU to the host memory through asynchronous transmission significantly improves the efficiency of the entire decoding system. The asynchronous transmission method avoids the blockage between GPU calculation and data transmission, allowing data transmission and subsequent tasks to be performed in parallel. After the soft output information is transmitted back to the host in a timely manner, it is convenient for real-time application processing, such as supporting low-latency data recovery in high-reliability communication scenarios (such as satellite communications or measurement and control systems).

[0109] S8: After decoding of all codewords is completed, resources are released.

[0110] The resources refer to the system resources used in the Turbo product code decoding process, and the resource release specifically includes the release of CPU memory space and GPU video memory space, as well as the destruction of asynchronous streams.

[0111] In a specific embodiment, the overall decoding process of the Turbo product code high-speed parallel GPU decoder mainly includes a decoding initialization process, a Turbo product code parallel decoding process and a resource release process.

[0112] The Turbo product code decoder initialization process mainly includes setting the main working parameters of the Turbo product code decoder and allocating related storage space.

[0113] Turbo product code parallel decoding process: In the decoding stage, the present invention adopts inter-frame and intra-frame parallelism, and the intra-frame parallelism is the component code length N, that is, N rows of soft output information or N columns of soft output information corresponding to the check matrix are updated simultaneously. The Turbo product code decoding process of the GPU of the present invention mainly includes initializing d_input using the channel information h_input in the memory; allocating on-chip shared memory and register resources for the soft output information and channel information before decoding, completing the iterative update of the soft output information; making a hard decision based on the iteratively updated soft output information and channel information, and then assigning the hard decision result to d_output; and finally passing d_output to h_output.

[0114] Resource release process: When the Turbo product code decoder completes the decoding of the required codeword, the memory space h_input, h_output and the video memory space d_input, d_output allocated for the initialization process are released, and the created asynchronous stream is destroyed.

[0115] In the present invention, the inter-frame and intra-frame parallelism is adopted in the parallel decoding process of Turbo product code, and the intra-frame parallelism is the component code length N. In order to improve the memory access efficiency, on-chip resources are allocated for soft output information and channel information and half floating point type is used for storage. In the iterative decoding process, the test sequence, the least reliable position index of the test sequence, the space required for the storage index of the sorting process, the verification result and the correlation are all stored in the register. In particular, the test sequence and the verification result are stored in a bit-by-bit manner, which greatly improves the memory access bandwidth.

[0116] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0117] In the present invention, the Turbo product code decoder is first initialized, then the channel information to be decoded is obtained, and the channel information is quantized into signed character data and stored in the GPU. The intra-frame parallelism consistent with the GPU thread block size is used to update the channel information by row and column respectively through the Chase algorithm until the maximum number of iterations is reached, the update of the soft output information is completed, and the soft output information is transmitted to the host memory of the CPU through an asynchronous transmission method, so that after the decoding of all code words is completed, the resources are released. A low-latency, high-throughput and high-reliability decoding process is achieved, resource utilization and decoding efficiency are improved, operation and maintenance costs and resource consumption are reduced, and memory access bandwidth and memory access efficiency are greatly improved, so as to well adapt to the diversified and dynamic measurement and control task requirements, improve communication quality and system reliability, and ensure the stable operation of measurement and control communication.

[0118] Reference Manual Attached Figure 5 , showing a schematic structural diagram of a decoding system for Turbo product codes provided by the present invention.

[0119] The present invention further provides a decoding system 20 for Turbo product codes, which is applied to the above-mentioned decoding method for Turbo product codes, comprising:

[0120] Processor 201.

[0121] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, a decoding method for Turbo product codes according to the method embodiment is implemented.

[0122] The decoding system 20 for Turbo product codes provided by the present invention can execute the above-mentioned decoding method for Turbo product codes and achieve the same or similar technical effects. To avoid repetition, the present invention will not describe them in detail.

[0123] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0124] In the present invention, the Turbo product code decoder is first initialized, then the channel information to be decoded is obtained, and the channel information is quantized into signed character data and stored in the GPU. The intra-frame parallelism consistent with the GPU thread block size is used to update the channel information by row and column respectively through the Chase algorithm until the maximum number of iterations is reached, the update of the soft output information is completed, and the soft output information is transmitted to the host memory of the CPU through an asynchronous transmission method, so that after the decoding of all code words is completed, the resources are released. A low-latency, high-throughput and high-reliability decoding process is achieved, resource utilization and decoding efficiency are improved, operation and maintenance costs and resource consumption are reduced, and memory access bandwidth and memory access efficiency are greatly improved, so as to well adapt to the diversified and dynamic measurement and control task requirements, improve communication quality and system reliability, and ensure the stable operation of measurement and control communication.

[0125] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0126] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0127] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0128] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0129] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0130] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0131] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0132] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0133] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0134] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0136] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0137] An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, a decoding method for Turbo product codes as described in the method embodiment is implemented.

[0138] A computer-readable storage medium provided by the present invention can implement the steps and effects of the decoding method for Turbo product codes in the above method embodiment, and to avoid repetition, the present invention will not go into details.

[0139] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0140] In the present invention, the Turbo product code decoder is first initialized, then the channel information to be decoded is obtained, and the channel information is quantized into signed character data and stored in the GPU. The intra-frame parallelism consistent with the GPU thread block size is used to update the channel information by row and column respectively through the Chase algorithm until the maximum number of iterations is reached, the update of the soft output information is completed, and the soft output information is transmitted to the host memory of the CPU through an asynchronous transmission method, so that after the decoding of all code words is completed, the resources are released. A low-latency, high-throughput and high-reliability decoding process is achieved, resource utilization and decoding efficiency are improved, operation and maintenance costs and resource consumption are reduced, and memory access bandwidth and memory access efficiency are greatly improved, so as to well adapt to the diversified and dynamic measurement and control task requirements, improve communication quality and system reliability, and ensure the stable operation of measurement and control communication.

[0141] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0142] There are a few points to note:

[0143] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0144] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0145] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0146] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A decoding method for Turbo product codes, characterized in that: include: S1: Initialize the Turbo product code decoder; S2: Obtain channel information to be decoded; S3: quantizing the channel information into signed character data; S4: Transmit the quantized channel information to the GPU via asynchronous transmission; S5: using the intra-frame parallelism consistent with the GPU thread block size, and performing iterative updates on the soft output information by row and by column according to the channel information through the Chase algorithm, until a maximum number of iterations is reached; S6: performing hard decision on the decoding result according to the channel information and the updated soft output information; S7: transmitting the hard decision result to the host memory of the CPU through asynchronous transmission; S8: After decoding of all codewords is completed, resources are released.

2. The decoding method for Turbo product codes according to claim 1, characterized in that: The S1 specifically includes: S101: Initializing Turbo product code parameters, wherein the Turbo product code parameters specifically include the number of frames processed in parallel by a single asynchronous stream, component code length, information length, number of Chase algorithm error positions, number of iterations, and number of asynchronous streams; S102: Allocate memory space and video memory space for channel information and a decoding result of the channel information respectively; S103: Initializing Alpha parameters and Beta parameters, and storing the Alpha parameters and the Beta parameters in a constant memory; S104: Loading the check matrix of the Turbo product code from a file, and allocating the check matrix to the constant memory of the GPU; S105: Generate an error image of the Turbo product code, and store the error image in a constant memory of a GPU; S106: configuring a parallel execution environment of a GPU for the Turbo product code decoder.

3. The decoding method for Turbo product codes according to claim 1, characterized in that: The S106 is specifically as follows: Create parallel threads, and set the corresponding number of GPU thread blocks and the number of GPU thread blocks according to the row soft output information or column soft output information of the Turbo product code check matrix.

4. The decoding method for Turbo product codes according to claim 1, characterized in that: The step after S4 and before S5 also includes: Allocate register storage resources for the test sequence, the least reliable position index of the test sequence, the space required for the sorting process storage index, the verification result and the correlation, respectively, and store the soft output information and the channel information in the shared memory space in the form of unsigned short integer or half floating point type; Initialize the channel information and soft output information in the shared memory. Specifically, the initialization is to convert the char data of the channel information into a floating point number and multiply it by a decimal, and store it in the channel information shared memory in a half floating point form.

5. The decoding method for Turbo product codes according to claim 1, characterized in that: The S5 specifically includes: S501: Reading the parameter alpha, the parameter beta, the soft output information and the channel information of the register; S502: converting the channel information and the soft output information into floating point data, updating the soft output information by using the parameter alpha, and converting the updated soft output information into half floating point data and storing it in a shared memory; S503: Calculate the soft output information in the shared memory in parallel by row, generate a preset number of least reliable position indexes, and store the least reliable position indexes in the register; S504: generating a test sequence of the soft output information according to the least reliable position index, and updating the soft output information; S505: Calculate the test sequence correlation according to the test sequence and update the soft output information; S506: Determine whether the corresponding bits of the candidate test sequence and the remaining test sequence are the same, if they are the same, determine the contention codeword and update the soft output information; otherwise, use the beta value to update the soft output information; S507: Parallel transposition of the updated soft output information; S508: Repeat steps S501-S507 until the maximum number of iterations is reached, completing the update of the soft output information.

6. The decoding method for Turbo product codes according to claim 5, characterized in that: The S504 specifically includes: S5041: Generate a test sequence for each row according to the least reliable position index; S5042: Update the bit value of the test sequence to update the soft output information.

7. The decoding method for Turbo product codes according to claim 5, characterized in that: The S505 is specifically as follows: Calculate the check result of each test sequence, determine whether the check result satisfies the rule of the check matrix, if yes, correct the error position by querying the error pattern table; otherwise, update the correlation value of each test sequence, and update the soft output information according to the correlation value.

8. The decoding method for Turbo product codes according to claim 5, characterized in that: The S506 is specifically as follows: Determine the competing codeword according to the candidate test sequence and the remaining test sequences, and judge whether the competing codeword exists. If so, update the soft output information by combining the correlation value of the candidate codeword and the competing codeword. Otherwise, update the soft output information by using the beta value.

9. A decoding system for Turbo product codes, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the decoding method for Turbo product codes according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, a decoding method for Turbo product codes as claimed in any one of claims 1 to 8 is implemented.

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