Memory access method and device, electronic equipment and chip

Abstract

The invention provides a memory access method and device, electronic equipment and a chip, and the method comprises the steps: determining a corresponding physical address according to a to-be-accessed logic address of a first processor; wherein the physical address indicates at least one storage unit in the memory pool, at least two memory groups are arranged in the memory pool, and any storage unit comprises storage areas in the at least two memory groups; and according to the sorting sequence of the at least two memory groups, sequentially accessing the storage areas in each memory group in any storage unit. Compared with parallel memory access in the prior art, the memory access of the application supports parallel access of the plurality of processors of the memory banks in the multi-memory pool, and each processor can access the storage areas in different memory banks in the storage unit, so that the memory access parallelism is improved, and the memory access efficiency is improved. And thus, the memory access efficiency and performance in the multiprocessor system are improved.

Description

Technical Field

[0001] The present application relates to the technical field of digital circuit design, and in particular to a memory access method, device, electronic device and chip. Background Art

[0002] Currently, in multi-processor systems, multiple processors use a single bus port in turn through arbitration to access a memory pool. In related art, when multiple processors use a single bus port in turn through arbitration to access a memory pool, the system only supports one processor accessing the memory, resulting in low access efficiency and severely limiting the system's processing power and efficiency. Summary of the Invention

[0003] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] To this end, the present application proposes a memory access method, device, electronic device and chip, which determine the corresponding physical address based on the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, and at least two memory groups are provided in the memory pool, and any storage unit includes storage areas within at least two memory groups; according to the sorting order of at least two memory groups, the storage areas within each memory group in any storage unit are accessed sequentially, supporting parallel access by at most the number of processors in the memory groups in the memory pool, and each processor can access storage areas in different memory groups in the storage unit, thereby improving the parallelism of memory access, and thereby improving the memory access efficiency and performance in the multi-processor system.

[0005] In one aspect, an embodiment of the present application provides a memory access method, including:

[0006] Determining a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool being provided with at least two memory groups, and any of the storage units including storage areas within the at least two memory groups;

[0007] According to the sorting order of the at least two memory groups, the storage areas in each of the memory groups in any one of the storage units are accessed sequentially.

[0008] Another embodiment of the present application provides a memory access device, including:

[0009] a first determining module, configured to determine a corresponding physical address based on a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool being provided with at least two memory groups, and any of the storage units including storage areas within the at least two memory groups;

[0010] The first access module is configured to sequentially access storage areas within each of the memory groups in any one of the storage units according to a sorting order of the at least two memory groups.

[0011] Another embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method described in the above aspect is implemented.

[0012] Another aspect of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the aforementioned aspect is implemented.

[0013] Another embodiment of the present application provides a chip, which includes a processing circuit configured to execute the method described in the above aspect.

[0014] Another embodiment of the present application provides a computer program product having a computer program stored thereon, which implements the method described in the above aspect when the program is executed by a processor.

[0015] The memory access method, device, electronic device and chip proposed in the present application determine the corresponding physical address according to the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, at least two memory groups are provided in the memory pool, and any storage unit includes storage areas in at least two memory groups; and the storage areas in each memory group in any storage unit are accessed sequentially according to the sorting order of the at least two memory groups. Compared with the parallel access to memory in the related art, the memory access of the present application supports parallel access by at most processors equal to the number of memory groups in the memory pool, and each processor can access storage areas in different memory groups in the storage unit, thereby improving the parallelism of memory access, and thus improving the memory access efficiency and performance in the multi-processor system.

[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a multi-processor access memory provided by this application;

[0019] Figure 2 A flowchart of a memory access method provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of a storage unit in a memory pool provided by this application;

[0021] Figure 4 A schematic diagram of the structure of a storage unit in another memory pool provided by this application;

[0022] Figure 5 A flowchart of another memory access method provided in an embodiment of the present application;

[0023] Figure 6 A flowchart of another memory access method provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of the structure of a storage unit in another memory pool provided by this application;

[0025] Figure 8 A flowchart of another memory access method provided in an embodiment of the present application;

[0026] Figure 9 A flowchart of another memory access method provided in an embodiment of the present application;

[0027] Figure 10 A schematic diagram of the structure of a memory access device provided in an embodiment of the present application;

[0028] Figure 11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0029] Figure 12 This is a schematic diagram of the structure of a chip proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0031] In the related art, when multiple processors use a single bus port to access the memory pool in turn through arbitration, the system only supports one processor to access the memory. Figure 1 As shown in the figure, in a system with three processors, processor M1 needs to write data, while processors M2 and M3 need to read data. If only one set of ports is designed for the memory pool—one for writing data and one for reading data—and the memory pool has no other special design, then at any moment, only one of processors M1, M2, or M3 can access the memory to read or write data, and it is impossible to support more than two processors accessing the memory in parallel.

[0032] Since it is impossible to support more than two processors to access the memory in parallel, the access efficiency is low and the processing capacity and efficiency of the system are severely limited.

[0033] The memory access method, device, electronic device, and chip according to the embodiments of the present application are described below with reference to the accompanying drawings.

[0034] Figure 2 A flowchart of a memory access method provided in an embodiment of the present application.

[0035] As an implementation manner, the memory access method of the embodiment of the present application can be configured in a memory access device, and the memory access device can be applied to any electronic device so that the electronic device can perform a memory access function.

[0036] Among them, the electronic device can be any device with computing capabilities, such as a mobile terminal. The mobile terminal can be, for example, a mobile phone, tablet computer, personal digital assistant, wearable device, or other hardware device with various operating systems, touch screens and / or display screens.

[0037] As another implementation method, the memory access method of the embodiment of the present application can also be executed by a chip with processing capabilities, including a central processing unit (CPU), an application-specific integrated circuit (ASIC), a microprocessor (Digital Signal Processor, DSP), a field programmable gate array (Field-Programmable Gate Array, FPGA), a system on a chip (System On A Chip, SOC), a reduced instruction set computer RISC (Reduced Instruction Set Computer, reduced instruction set computer), etc., which are not listed one by one here.

[0038] like Figure 2As shown, the method may include the following steps:

[0039] Step 201, determining a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas in at least two memory groups.

[0040] The first processor may be a processor that needs to access the memory pool among multiple processors that share the memory pool.

[0041] In an embodiment of the present application, at least two memory groups can be set in the memory pool, wherein any memory group can be, for example, a single-port memory group, or a pseudo-dual-port memory group, and the port type of the memory group can be selected and determined according to actual needs.

[0042] In a possible implementation of the embodiment of the present application, the number of memory groups to be set in the memory pool may be determined according to the total number of processors sharing the memory pool.

[0043] As a possible implementation, when the total number of processors sharing the memory pool is n, the number of memory groups set in the memory pool is m, where the value of m is determined by an exponential function with the target value as the base, and both m and n are positive integers, and m is greater than n.

[0044] The target value may be pre-set, such as 2, 3, etc., and this application does not impose any restrictions on this.

[0045] As an example, assuming the total number of processors in the shared memory pool is 3 and the target value is 2, the number of memory groups set in the memory pool can be 2. 2 Assuming the total number of processors in the shared memory pool is 6 and the target value is 2, the number of memory groups set in the memory pool can be 2. 3 indivual.

[0046] In an embodiment of the present application, a storage unit can be used as a basic unit of memory allocation to manage and allocate storage areas in a memory pool, and the number of storage units in the memory pool can be, but is not limited to, one. When at least two memory groups are provided in the memory pool, any storage unit can include storage areas within the at least two memory groups.

[0047] As an example, assuming that the memory pool includes 1024 storage units and 8 memory groups are set in the memory pool, each storage unit includes the storage area within the 8 memory groups. For example, assuming that there is a storage unit a, the position of the storage unit a in the memory pool is as follows: Figure 3 shown.

[0048] In the embodiment of the present application, the physical address can be used to indicate at least one storage unit in the memory pool. It should be noted that the present application does not limit the number of storage units indicated by the physical address.

[0049] In an embodiment of the present application, the corresponding physical address can be determined based on the logical address to be accessed by the first processor. As an example, the corresponding physical address can be determined based on the mapping relationship between the logical address to be accessed by the first processor and the logical address.

[0050] Step 202 : sequentially access the storage areas in each memory group in any storage unit according to the sorting order of at least two memory groups.

[0051] In an embodiment of the present application, each memory group in the at least two memory groups set in the memory pool may have a corresponding sorting order, so that the storage area in each memory group in any storage unit can be accessed sequentially according to the sorting order of each memory group in the memory pool.

[0052] Still Figure 3 For example, assuming that there is a storage unit a in the memory pool, and the number of memory groups set in the memory pool is 8, and in sorting order, the memory groups are bank0, bank1, bank2, bank3, bank4, bank5, bank6, and bank7. Then, the storage areas in each memory group of the storage unit a can be accessed sequentially according to the above sorting, that is, the storage area in bank0 of the storage unit a is accessed first, and then the storage area in bank1 of the storage unit a is accessed, and then the storage area in bank2 of the storage unit a is accessed, and then the storage area in bank3 of the storage unit a is accessed, and so on.

[0053] It should be noted that when the number of memory groups set in a memory pool is m, the memory pool can support parallel access by up to m processors, ensuring that each memory group is accessed by a different processor. For example, when the number of memory groups set in a memory pool is 8, the memory pool can support parallel access by up to 8 processors. For another example, when the number of memory groups set in a memory pool is 16, the memory pool can support parallel access by up to 16 processors. This allows for parallel access by more than two processors, improving access efficiency.

[0054] In a possible implementation of an embodiment of the present application, when the physical address indicates that there are multiple storage units in the memory pool, the storage areas in each memory group in the corresponding storage unit can be accessed sequentially according to the sorting order of the multiple storage units and the sorting order of at least two memory groups.

[0055] As an example, assuming that the physical address indicates that the storage units in the memory pool include storage unit a and storage unit b, the memory groups set in the memory pool are storage group 1 and storage group 2 respectively, the sorting order of the storage units is storage unit b, storage unit a, and the sorting order of the memory groups is storage group 1, memory group 2. Then, according to the sorting order of the memory groups, the storage areas of storage unit b within each memory group are accessed sequentially first, and then the storage areas of storage unit a within each memory group are accessed sequentially. This maintains the atomicity and consistency of memory access, helping to maintain the orderliness of memory management and data consistency.

[0056] Optionally, the storage area within each memory group in any storage unit can be at least two rows of storage areas. As an example, assuming that the size of each storage unit in the memory pool is 2KB, the number of memory groups set in the memory pool is 8, the bit width of each memory group is 128 bits, and the width of each storage unit is the 128-bit bit width of the memory group, then the storage area of ​​each storage unit within each memory group is 16 rows of storage areas, that is, 8*16*128 bits = 2048 bytes = 2KB.

[0057] It should be noted that the number of row storage areas included in the storage area in each memory group in the above storage unit is only exemplary. In actual applications, it can be set as needed, and this application does not impose any limitation on this.

[0058] In a possible implementation of an embodiment of the present application, when the storage area in each memory group in any memory cell is at least two rows of storage areas, for any memory cell, at least two rows of storage areas in each memory group can be accessed sequentially according to the sorting order of the at least two memory groups.

[0059] As an example, Figure 4As shown, assuming that there is a memory cell a, the memory groups are bank0, bank1, bank2, and bank3 in the corresponding sorting order. The storage area of ​​the memory cell a in the above memory groups is 4 row storage areas. The row storage areas in each memory group can be accessed sequentially according to the sorting order of each memory group. That is, according to the above sorting order, the 4 row storage areas of the memory cell a in bank0 are accessed first, then the 4 row storage areas of the memory cell a in bank1 are accessed, then the 4 row storage areas of the memory cell a in bank2 are accessed, and finally the 4 row storage areas of the memory cell a in bank3 are accessed.

[0060] In the memory access method of the embodiment of the present application, the corresponding physical address is determined according to the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, at least two memory groups are provided in the memory pool, and any storage unit includes storage areas in at least two memory groups; according to the sorting order of the at least two memory groups, the storage areas in each memory group in any storage unit are accessed sequentially. Compared with the parallel access to memory in the related art, the memory access of the present application supports parallel access by at most the number of processors of the memory groups in the memory pool, and each processor can access storage areas in different memory groups in the storage unit, thereby improving the parallelism of memory access, thereby improving the memory access efficiency and performance in the multi-processor system.

[0061] It is understandable that when the first processor accesses the storage area in each memory group in the storage unit, there may be a situation where multiple processors access the same memory group. In such a situation where there is an access conflict, the present application also proposes a memory access method.

[0062] Based on the above embodiments, Figure 5 A flowchart of another memory access method provided in an embodiment of the present application is shown as follows: Figure 5 As shown, the method may further include the following steps:

[0063] Step 501 : When accessing a first target memory bank among at least two memory banks, if there is an access conflict with at least one second processor, determine the priority of the first processor and the second processor.

[0064] In an embodiment of the present application, any memory group in the memory pool may have a corresponding arbitrator. Thus, when a first processor accesses a first target memory group among at least two memory groups, if there is an access conflict with at least one second processor, the priority of the first processor and the second processor can be determined by the arbitrator corresponding to the first target memory group.

[0065] In one embodiment of the present disclosure, the priority between the first processor and the second processor may be determined based on a preset processor priority rule. For example, the priority between the first processor and the second processor may be set by a fixed priority arbiter. For example, the priority between the first processor and the second processor may be set by a round-robin priority arbiter.

[0066] It should be noted that this application does not limit the number of second processors that have access conflicts with the first processor.

[0067] Step 502: Access the first target memory group in sequence according to priority.

[0068] As an example, the first processor and the second processor may be sorted according to their priorities, so that the processors may access the first target memory group in sequence according to the corresponding sorting order.

[0069] As a possible implementation method, when a high-priority processor among the first processor and at least one second processor accesses the first target memory group, the access of the low-priority processor can be blocked; and when the high-priority processor completes the access, the low-priority processor is allowed to access the first target memory group.

[0070] Therefore, when the first target memory group is accessed by a high-priority processor among the first processor and at least one second processor, the access of the low-priority processor is blocked, which can ensure that the access of the high-priority processor will not be interfered with. Then, when the access of the high-priority processor is completed, the access block for the low-priority processor is released, and the low-priority processor is allowed to access the first target memory group. This can effectively solve the performance degradation problem caused by resource conflicts and maintain the stability and efficiency of the system.

[0071] In the memory access method of an embodiment of the present application, when accessing a first target memory bank among at least two memory banks, if there is an access conflict with at least one second processor, the priority of the first processor and the second processor is determined by an arbiter corresponding to the first target memory bank; the first target memory bank is accessed sequentially according to the priority. By resolving access conflicts based on priority rules by the arbiter, it is possible to ensure orderly and efficient access to shared resources in a multi-processor system, thereby improving system performance and stability.

[0072] Based on the above embodiments of this application, Figure 6 A flowchart of another memory access method provided in an embodiment of the present application is shown as follows: Figure 6 As shown, the method comprises the following steps:

[0073] Step 601, determining a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas in at least two memory groups.

[0074] The execution process of step 601 can refer to the execution process of any embodiment of the present application and will not be repeated here.

[0075] Step 602 : For any memory cell, determine the access order of each row of memory areas in the memory cell according to the order of at least two rows of memory areas in each memory group in the memory cell.

[0076] As a possible implementation, for any memory cell, the access order of each row of memory areas in the memory cell may be determined according to the order of at least two rows of memory areas in each memory group in the memory cell and the order of the memory groups.

[0077] As an example, Figure 7 As shown, assuming that there is a storage unit a, the memory groups are bank0, bank1, bank2, and bank3 in the corresponding sorting order. The storage areas in the storage unit a that are in the above-mentioned memory groups are 2 row storage areas. The 2 row storage areas in bank0 are row 01 and row 02 in the corresponding sorting order, the 2 row storage areas in bank1 are row 11 and row 12 in the corresponding sorting order, the 2 row storage areas in bank2 are row 21 and row 22 in the corresponding sorting order, and the 2 row storage areas in bank3 are row 31 and row 32 in the corresponding sorting order. According to the sorting of at least two row storage areas in each memory group in the storage unit and the sorting order of each memory group, it can be determined that the access order of each row storage area in the storage unit is: row 01, row 11, row 21, row 31, row 02, row 12, row 22, and row 32.

[0078] Step 603 : When it is determined that the target row storage area needs to be accessed according to the access sequence, the target row storage area in each memory group is accessed sequentially according to the sorting order of the at least two memory groups.

[0079] The target row storage area may be each row storage area in the storage unit.

[0080] In the memory access method of the embodiment of the present application, for any memory cell, the access order of each row storage area in the memory cell is determined according to the sorting of at least two corresponding rows of storage areas within each memory group in the memory cell. When a target row storage area is determined to be accessed based on the access order, the target row storage area in each memory group is sequentially accessed according to the sorting order of the at least two memory groups. By determining the access order, orderly control of the access process is achieved, which helps to improve the performance stability and reliability of the multi-processing system.

[0081] In the case where the physical address also indicates the second target memory group in at least two memory groups, in order to clearly illustrate how the storage areas in each memory group in any storage unit are sequentially accessed according to the sorting order of at least two memory groups in the above embodiments of the present application, the present application also proposes a memory access method.

[0082] Based on the above embodiments of this application, Figure 8 A flowchart of another memory access method provided in an embodiment of the present application is shown as follows: Figure 8 As shown, the method comprises the following steps:

[0083] Step 801, determining a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas in at least two memory groups.

[0084] The execution process of step 801 can refer to the execution process of any embodiment of the present application and will not be repeated here.

[0085] Optionally, the logical address is carried in the write instruction.

[0086] In the case where the logical address is carried in a write instruction, in order to clearly illustrate how to determine the corresponding physical address based on the logical address to be accessed by the first processor, in a possible implementation method of an embodiment of the present application, in response to the write instruction, an idle storage unit is allocated from the storage unit list according to the size of the data block to be written carried by the write instruction; and the physical address is determined based on the encoding of the logical address and the allocated storage unit.

[0087] The storage unit list may be a data structure such as a queue or a linked list, and the storage unit list may be used to indicate free storage units in the storage pool.

[0088] It is understood that any storage unit in the storage pool may have a corresponding code to uniquely identify the storage unit. For example, when the circuit is initialized, 0, 1, 2, 3, etc. may be used as the code of each storage unit in sequence.

[0089] In an embodiment of the present application, in response to a write instruction, an idle storage unit may be allocated from the storage unit list according to the size of the data block to be written carried in the write instruction.

[0090] In order to clearly illustrate how free storage units are allocated from the storage unit list based on the size of the data block to be written carried by the write instruction, as a possible implementation method, in response to the write instruction, the number of storage units to be allocated can be determined based on the size of the data block to be written carried by the write instruction and the size of each storage unit; and based on the number of storage units to be allocated, free storage units are allocated from the storage unit list.

[0091] As an example, assuming that the storage unit list uses a first-in-first-out queue to save free storage units, the size of the data block to be written carried by the write instruction is 6KB, and the size of each storage unit is 2KB, then the number of storage units to be allocated can be determined to be 3 based on the size of the data block to be written carried by the write instruction. Based on this number, the first 3 storage units in the first-in-first-out queue are allocated.

[0092] In related technologies, the allocation of storage space for different business data to be written is fixed and cannot be allocated on demand, or can only be statically configured through registers, which lacks flexibility and leads to insufficient utilization of memory resources. However, this application determines the allocated storage unit based on the size of the data block to be written, which can realize the dynamic application and allocation of required storage space according to actual needs, so that memory resources can be used efficiently.

[0093] In an embodiment of the present application, a physical address can be determined based on a logical address and an encoding of an allocated storage unit. As an example, a physical address can be generated based on a logical address carried by a write instruction and an encoding of an allocated storage unit. For example, the encoding of a memory group to be accessed from at least two memory groups is determined based on bits [2:0] of the logical address carried by the write instruction, and a physical address is generated based on the determined encoding of the memory group to be accessed and the encoding of the allocated storage unit.

[0094] In a possible implementation of the embodiment of the present application, after allocating free storage units from the storage unit list according to the size of the data block to be written carried by the write instruction, the correspondence between the allocated storage units and the logical addresses can be saved.

[0095] In the case where the logical address is carried in a read instruction, in order to clearly illustrate how the corresponding physical address is determined based on the logical address to be accessed by the first processor, as a possible implementation method, in response to the read instruction, the corresponding code is queried based on the logical address carried by the read instruction; wherein the correspondence between the logical address and the code is stored when the storage unit is allocated; and based on the logical address and the code, the physical address is determined.

[0096] The code can be used to uniquely identify the storage unit.

[0097] It is understood that the storage space of any storage unit may be released. Therefore, in one possible implementation of the embodiment of the present application, when at least one storage unit is released, the status of the at least one storage unit can be updated from occupied to free in the storage unit list. In this way, the status of the storage unit is updated so that the availability of the storage unit can be determined based on the status of the storage unit, thereby maintaining the continuous and efficient operation of the system.

[0098] Step 802 : for any storage unit, sequentially access storage areas in each memory group in the storage unit according to the sorting order of at least two memory groups and starting from the second target memory group.

[0099] As an example, for storage unit a, assuming that the sorting order of each memory group is bank0, bank1, bank2, and bank3, when the second target memory group indicated by the physical address is bank1, bank1 can be used as the starting point, and the storage areas in bank1, bank2, and bank3 in the storage unit a can be accessed sequentially according to the sorting order of each memory group.

[0100] In the memory access method of the embodiment of the present application, for any memory cell, the memory regions within each memory group of the memory cell are sequentially accessed according to the sort order of at least two memory groups, starting from the second target memory group. This further optimizes the access process to the memory regions within each memory group, improves the flexibility and specificity of the access process, and helps ensure the consistency and accuracy of data during the access process.

[0101] In the case where the physical address also indicates a third target memory group and a fourth target memory group in at least two memory groups, in order to clearly illustrate how the storage areas in each memory group in any storage unit are sequentially accessed according to the sorting order of at least two memory groups in the above embodiments of the present application, the present application also proposes a memory access method.

[0102] Based on the above embodiments of this application, Figure 9 A flowchart of another memory access method provided in an embodiment of the present application is shown as follows: Figure 9 As shown, the method comprises the following steps:

[0103] Step 901, determining a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any storage unit includes storage areas in at least two memory groups.

[0104] The execution process of step 901 can refer to the execution process of any embodiment of the present application and will not be repeated here.

[0105] Step 902 : for any storage unit, sequentially access storage areas in each memory group in the storage unit according to the sorting order of at least two memory groups, starting from the third target memory group and ending at the fourth target memory group.

[0106] As an example, for storage unit a, assuming that the sorting order of each memory group is bank0, bank1, bank2, and bank3, when the physical address also indicates that the third target memory group is bank0 and the fourth target memory group is bank2, then bank1 can be used as the starting point and bank2 as the center, and the storage areas in bank0, bank1, and bank2 in the storage unit a can be accessed sequentially according to the sorting order of each memory group.

[0107] In a possible implementation of an embodiment of the present application, when the storage areas in each memory group in a storage unit are at least two row storage areas, and the physical address also indicates a first row storage area in a third target memory group in any storage unit and a second row storage area in the fourth target memory group in the storage unit, for the storage unit, the first row storage area in the third target memory group in the storage unit can be used as the starting point, and the second row storage area in the fourth target memory group in the storage unit can be used as the end point; according to the sorting order of each memory group, based on the starting point and the end point, the access order of each row storage area in the storage unit is determined, and each row storage area is accessed sequentially according to the access order.

[0108] As an example, Figure 7For explanation, it is assumed that there is a storage unit a, and the memory groups are bank0, bank1, bank2, and bank3 in the corresponding sorting order. The storage area in the storage unit a in the above memory groups is 2 row storage areas, the 2 row storage areas in bank0 are row 01 and row 02, the 2 row storage areas in bank1 are row 11 and row 12, the 2 row storage areas in bank2 are row 21 and row 22, and the 2 row storage areas in bank3 are row 31 and row 32. Assume that the physical address also indicates that the storage unit a is in the third target In the case of row 11 of the first row storage area in the memory group bank1, and row 22 of the second row storage area in the memory cell a in the fourth target memory group bank2, row 11 of the memory cell a in bank1 can be used as the starting point, and row 22 of the memory cell a in bank2 can be used as the end point; according to the sorting order of each memory group, based on the starting point and the end point, the access order of each row storage area in the memory cell can be determined as: row 11, row 21, row 31, row 02, row 12, row 22, and each row storage area can be accessed in sequence according to this access order.

[0109] In the memory access method of the embodiment of the present application, for any memory cell, sequential access is performed based on the sort order of at least two memory groups, starting from the third target memory group and ending at the fourth target memory group. This further optimizes the access process to the memory areas within each memory group, improving the flexibility and specificity of the access process and facilitating data consistency and accuracy during the access process.

[0110] In order to implement the above embodiment, the embodiment of the present application also proposes a memory access device.

[0111] Figure 10 A schematic structural diagram of a memory access device provided in an embodiment of the present application.

[0112] like Figure 10 As shown, the device may include:

[0113] The first determination module 1001 is used to determine the corresponding physical address according to the logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in the memory pool, at least two memory groups are provided in the memory pool, and any storage unit includes storage areas within at least two memory groups.

[0114] The first access module 1002 is configured to sequentially access storage areas within each memory group in any storage unit according to a sorting order of at least two memory groups.

[0115] Furthermore, in one implementation of the embodiment of the present application, the apparatus may further include:

[0116] The second determining module is configured to determine the priority of the first processor and the second processor if there is an access conflict with at least one second processor when accessing a first target memory bank among the at least two memory banks.

[0117] The second access module sequentially accesses the first target memory group according to the priority.

[0118] In one implementation of the embodiment of the present application, the second access module is configured to:

[0119] When a processor with a high priority among the first processor and at least one second processor accesses the first target memory group, blocking access to a processor with a low priority;

[0120] When the access by the processor with a high priority is completed, the access by the processor with a low priority to the first target memory group is allowed.

[0121] In one implementation of the embodiment of the present application, the storage area in each memory group in any storage unit is at least two rows of storage areas; the first access module 1002 is configured to:

[0122] For any storage unit, determining an access order of each row of storage areas in the storage unit according to the order of at least two rows of storage areas in any memory group in the storage unit;

[0123] When it is determined that the target row storage area needs to be accessed according to the access sequence, the target row storage area in each memory group is accessed sequentially according to the sorting order of the at least two memory groups.

[0124] In one implementation of the embodiment of the present application, the storage area in each memory group in any storage unit is at least two rows of storage areas; the first access module 1002 is configured to:

[0125] For any memory cell, at least two rows of storage areas in each memory group are accessed sequentially according to the sorting order of the at least two memory groups.

[0126] In one implementation of the embodiment of the present application, the physical address further indicates a second target memory group; the first access module 1002 is configured to:

[0127] According to the sorting order of at least two memory groups, starting from the second target memory group, storage areas in each memory group in any storage unit are accessed sequentially.

[0128] In one implementation of the embodiment of the present application, the physical address further includes a third target memory group and a fourth target memory group; the first access module 1002 is configured to:

[0129] For any storage unit, according to the sorting order of at least two memory groups, the storage areas in each memory group of the storage unit are sequentially accessed starting from the third target memory group and ending at the fourth target memory group.

[0130] In one implementation of the embodiment of the present application, the logical address is carried in the write instruction; the first determining module 1001 is configured to:

[0131] In response to a write instruction, allocating an idle storage unit from the storage unit list according to the size of the data block to be written carried in the write instruction;

[0132] Based on the logical address and the encoding of the allocated storage unit, a physical address is determined.

[0133] In one implementation of the embodiment of the present application, the logical address is carried in the read instruction; the first determining module 1001 is configured to:

[0134] In response to a read instruction, querying a corresponding code according to the logical address; wherein the correspondence between the logical address and the code is stored when the storage unit is allocated;

[0135] Based on the logical address and the encoding, the physical address is determined.

[0136] In one implementation of the embodiment of the present application, the apparatus may further include: an updating module configured to:

[0137] In response to the release of the at least one storage unit, a status of the at least one storage unit is updated from occupied to free in the storage unit list.

[0138] In one implementation of an embodiment of the present application, when the total number of processors sharing a memory pool is n, the number of memory groups set in the memory pool is m, where the value of m is determined by an exponential function with a target value as the base, and both m and n are positive integers, and m is greater than n.

[0139] The present application proposes a memory access device, wherein a corresponding physical address is determined based on a logical address to be accessed by a first processor; wherein the physical address indicates at least one storage unit in a memory pool, wherein the memory pool is provided with at least two memory groups, and any storage unit includes storage areas within at least two memory groups; and wherein the storage areas within each memory group in any storage unit are accessed sequentially according to the sorting order of the at least two memory groups. Compared to the parallel access memory in the related art, the memory access of the present application supports parallel access by at most processors equal to the number of memory groups in the memory pool, and each processor can access storage areas within different memory groups in the storage unit, thereby improving the parallelism of memory access and thereby improving the memory access efficiency and performance in a multi-processor system.

[0140] In order to implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above method embodiments is implemented.

[0141] In order to implement the above embodiments, the present application further proposes a computer program product on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiments is implemented.

[0142] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method described in the above method embodiments is implemented.

[0143] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. For example, the electronic device 1100 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0144] Reference Figure 11 , the electronic device 1100 may include one or more of the following components: a processing component 1102 , a memory 1104 , a power component 1106 , a multimedia component 1108 , an audio component 1110 , an input / output (I / O) interface 1112 , a sensor component 1114 , and a communication component 1116 .

[0145] The processing component 1102 generally controls the overall operation of the electronic device 1100, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 1102 may include one or more modules to facilitate interaction between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate interaction between the multimedia component 1108 and the processing component 1102.

[0146] The memory 1104 is configured to store various types of data to support operations on the electronic device 1100. Examples of such data include instructions for any application or method operating on the electronic device 1100, contact data, phone book data, messages, pictures, videos, etc. The memory 1104 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0147] The power component 1106 provides power to the various components of the electronic device 1100. The power component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1100.

[0148] The multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1108 includes a front camera and / or a rear camera. When the electronic device 1100 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0149] The audio component 1110 is configured to output and / or input audio signals. For example, the audio component 1110 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 1100 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 1104 or transmitted via the communication component 1116. In some embodiments, the audio component 1110 also includes a speaker for outputting audio signals.

[0150] I / O interface 1112 provides an interface between processing component 1102 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0151] The sensor assembly 1114 includes one or more sensors for providing various aspects of the status assessment of the electronic device 1100. For example, the sensor assembly 1114 can detect the open / closed state of the electronic device 1100, the relative positioning of components, such as the display and keypad of the electronic device 1100. The sensor assembly 1114 can also detect changes in the position of the electronic device 1100 or a component of the electronic device 1100, the presence or absence of user contact with the electronic device 1100, the orientation or acceleration / deceleration of the electronic device 1100, and changes in the temperature of the electronic device 1100. The sensor assembly 1114 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 1114 can also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1114 can also include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0152] The communication component 1116 is configured to facilitate wired or wireless communication between the electronic device 1100 and other devices. The electronic device 1100 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 1116 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1116 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0153] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, microprocessors, microprocessors, or other electronic components to perform the above-described methods.

[0154] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1104 including instructions, and the instructions can be executed by the processor 1120 of the electronic device 1100 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0155] In order to implement the above embodiments, the present application further proposes a chip, including: the chip includes a processing circuit, and the processing circuit is configured to execute the method provided in the above embodiments.

[0156] Figure 12 This is a schematic diagram of the structure of a chip proposed in the embodiment of this application. Figure 12 The structure of the chip 1200 is shown, but is not limited thereto.

[0157] The chip 1200 includes a processing circuit 1201 , which is configured to execute any of the above methods.

[0158] In some embodiments, chip 1200 further includes one or more interface circuits 1202. Optionally, interface circuit 1202 is connected to memory 1203. Interface circuit 1202 can be used to receive signals from memory 1203 or other devices, and interface circuit 1202 can be used to send signals to memory 1203 or other devices. For example, interface circuit 1202 can read instructions stored in memory 1203 and send the instructions to processing circuit 1201.

[0159] In some embodiments, the interface circuit 1202 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1201 performs the other steps.

[0160] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0161] In some embodiments, the chip 1200 further includes one or more memories 1203 for storing instructions. Alternatively, all or part of the memories 1203 may be located outside the chip 1200.

[0162] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0163] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0164] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0165] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0166] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0167] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0168] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0169] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A memory access method, characterized in that: The method comprises: Determine a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any of the storage units includes a storage area in the at least two memory groups; According to the sorting order of the at least two memory groups, the storage areas in any one of the storage units and within each of the memory groups are accessed sequentially.

2. The method according to claim 1, characterized in that The method further comprises: When accessing a first target memory group among the at least two memory groups, if there is an access conflict with at least one second processor, determining the priority of the first processor and the second processor; The first target memory groups are accessed sequentially according to the priority levels.

3. The method according to claim 2, characterized in that The accessing the first target memory group in sequence according to the priority level comprises: When a processor with a high priority among the first processor and the at least one second processor accesses the first target memory group, blocking access to a processor with a low priority; When the access by the high-priority processor is completed, the access by the low-priority processor to the first target memory group is allowed.

4. The method according to any one of claims 1 to 3, characterized in that: The storage area in each of the memory groups in any of the storage units is at least two rows of storage areas; The step of sequentially accessing the storage areas in each of the memory groups in any of the storage units according to the sorting order of the at least two memory groups comprises: For any of the storage units, determining an access order of each row of storage areas in the storage unit according to the order of at least two rows of storage areas in the storage unit that are in any of the memory groups; When it is determined according to the access sequence that the target row storage area needs to be accessed, the target row storage area in each of the memory groups is accessed sequentially according to the sorting order of the at least two memory groups.

5. The method according to any one of claims 1 to 3, characterized in that: The storage area in each of the memory groups in any of the storage units is at least two rows of storage areas; The step of sequentially accessing the storage areas in each of the memory groups in any of the storage units according to the sorting order of the at least two memory groups comprises: For any of the storage units, the at least two rows of storage areas in each of the memory groups are accessed sequentially according to the sorting order of the at least two memory groups.

6. The method according to any one of claims 1 to 3, characterized in that: The physical address also indicates a second target memory bank; The step of sequentially accessing the storage areas in each of the memory groups in any of the storage units according to the sorting order of the at least two memory groups comprises: According to the sorting order of the at least two memory groups, starting from the second target memory group, the storage areas in any one of the storage units and in each of the memory groups are accessed sequentially.

7. The method according to any one of claims 1 to 3, characterized in that: The physical address also includes a third target memory group and a fourth target memory group; The step of sequentially accessing the storage areas in each of the memory groups in any of the storage units according to the sorting order of the at least two memory groups comprises: For any of the storage units, storage areas in each of the memory groups in the storage unit are accessed sequentially according to the sorting order of the at least two memory groups, starting from the third target memory group and ending at the fourth target memory group.

8. The method according to any one of claims 1 to 3, characterized in that: The logical address is carried in the write instruction; and the determining the corresponding physical address according to the logical address to be accessed by the first processor includes: In response to the write instruction, allocating a free storage unit from the storage unit list according to the size of the to-be-written data block carried by the write instruction; The physical address is determined based on the logical address and the encoding of the allocated storage unit.

9. The method according to claim 8, characterized in that The logical address is carried in the read instruction; and the determining the corresponding physical address according to the logical address to be accessed by the first processor includes: In response to the read instruction, query the corresponding code according to the logical address; wherein the corresponding relationship between the logical address and the code is stored when the storage unit is allocated; Based on the logical address and the encoding, the physical address is determined.

10. The method according to claim 8, characterized in that The method further comprises: In response to the release of the at least one storage unit, the status of the at least one storage unit is updated from occupied to free in the storage unit list.

11. The method according to any one of claims 1 to 3, characterized in that: When the total number of processors sharing the memory pool is n, the number of memory groups set in the memory pool is m, wherein the value of m is determined by an exponential function with a target value as a base, and both m and n are positive integers, and m is greater than n.

12. A memory access device, characterized in that: include: A first determination module is used to determine a corresponding physical address according to a logical address to be accessed by the first processor; wherein the physical address indicates at least one storage unit in a memory pool, the memory pool is provided with at least two memory groups, and any of the storage units includes a storage area in the at least two memory groups; The first access module is used to sequentially access the storage areas in each of the memory groups in any of the storage units according to the sorting order of the at least two memory groups.

13. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 12 is implemented.

14. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

15. A chip, characterized in that: The chip comprises a processing circuit configured to perform the method of any one of claims 1-12.

16. A computer program product, characterized in that The method comprises a computer program, and when the computer program is executed by a processor, the method implements the method according to any one of claims 1 to 12.

Images