Dynamic continuous address memory allocator based on two-layer binary tree vector

Abstract

The invention provides a dynamic continuous address memory allocator based on two-layer binary tree vectors, which comprises a top-layer vector table module, a sub-layer vector table module and a memory allocation module, wherein the top-layer vector table module comprises a plurality of top-layer vector groups, the sub-layer vector table module comprises a plurality of sub-layer vector groups, and the number of the top-layer vector groups is the same as that of the sub-layer vector groups; the free block positioning module is used for generating an OR gate binary tree structure from an input vector based on an OR gate, selecting a hierarchical vector of the OR gate binary tree based on the number of vectors distributed by an external request for outputting, and positioning to a free vector block; the first zero coordinate searching module is used for taking the hierarchical vector output by the free block positioning module as an input vector of the module, dividing the input vector into a plurality of groups, generating a plurality of groups of AND gate binary trees based on an AND gate, and searching a first zero vector coordinate; and the bit flipping module is used for flipping the distributed vector value to 1 and flipping the released vector value to 0 so as to finish occupation and release of the vector. The method has the beneficial effect that the memory access speed can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of address memory allocation, in particular to a dynamic continuous address memory allocator based on a two-layer binary tree vector. Background Art

[0002] With the rapid development of artificial intelligence technology, especially the breakthrough in the field of deep learning, the demand for computing resources, especially memory resources, has increased dramatically. Deep learning models contain a large number of weight parameters and activation functions, which need to be stored in memory and frequently accessed and updated. Traditional memory allocators are difficult to meet the high efficiency and the "memory wall" phenomenon occurs, resulting in the performance of the computing unit being limited by the memory access speed and unable to fully exert its computing power, forming a performance bottleneck. Summary of the invention

[0003] The present invention provides a dynamic continuous address memory allocator based on a two-layer binary tree vector, aiming to solve the problem of limited memory access speed.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a dynamic continuous address memory allocator based on a two-layer binary tree vector, comprising: a top-level vector table module, a sub-layer vector table module, a free block positioning module, a first zero coordinate search module and a bit flip module;

[0005] The top-level vector table module includes a plurality of top-level vector groups, the sub-layer vector table module includes a plurality of sub-layer vector groups, the number of the top-level vector groups is the same as the number of the sub-layer vector groups, and the top-level vector groups map the sub-layer vector groups to manage the sub-layer vectors in the sub-layer vector groups;

[0006] The idle block positioning module is used to generate an OR gate binary tree structure based on an OR gate for the input top-level vector or sub-layer vector, and select a level vector of the OR gate binary tree for output based on the number of vectors allocated by the external request, and locate the idle vector block;

[0007] The first zero coordinate search module is used to use the hierarchical vector output by the free block positioning module as the input vector of the module, divide the input vector into multiple groups and generate multiple groups of AND gate binary trees based on AND gates to find the first zero vector coordinates;

[0008] The bit flip module is used to flip the allocated vector value to 1 and flip the released vector value to 0, thereby completing the occupation and release of the vector.

[0009] Furthermore, each top-level vector group includes a top-level vector and an idle level; the top-level vector describes whether the corresponding sub-layer vector group can be used in the requested allocation; the idle level describes the level of the number of allocatable continuous idle vectors in the corresponding sub-layer vector group, indicating the maximum number of allocatable vectors in the corresponding sub-layer vector group.

[0010] Furthermore, the top-level vector table module includes 64 top-level vector groups; each top-level vector group includes a 1-bit top-level vector and a 3-bit idle level.

[0011] Furthermore, each sub-layer vector group includes multiple sub-layer vectors; each sub-layer vector is mapped to a physical memory space, and the physical memory space is managed by occupying and releasing the sub-layer vectors.

[0012] Furthermore, the sub-layer vector table module includes 64 groups of sub-layer vector groups, each sub-layer vector group includes 64 bits, and the entire sub-layer vector table is composed of 64×64=4096 1-bit vectors, with a total of 4k-bit sub-layer vectors.

[0013] Furthermore, each node of the AND gate binary tree consists of two bits, and the two bits respectively represent the result of ANDing the child nodes and the direction of the zero in the child nodes.

[0014] Furthermore, the idle block positioning module, in the output hierarchical vector, is zero, indicating that the vector block of its root node can allocate the number of continuous idle vectors required this time, thereby locating the idle vector block for allocation.

[0015] Furthermore, in the module for searching for the first zero coordinate, searching for the first zero vector coordinate includes: searching for the first zero for each group of AND gate binary trees, and outputting the zero-searching results for each group; obtaining the subscript of the first group of first zero vectors from each group of zero-searching results through a decoder with priority, and calculating the subscript of the first zero vector in the sub-layer vector group based on the hierarchical depth, thereby obtaining the allocated first zero vector coordinates.

[0016] Furthermore, in the bit flip module, the input vector is divided into 8 vector groups, each group having 8 vectors.

[0017] Furthermore, in the bit flipping module, the vector group includes a global group, a local group and a local mask group; in the global group, the 8 vectors corresponding to the bits that are 1 are all flipped; in the local group, the 8 vectors corresponding to the bits that are 1 are only partially flipped; in the local mask group, 8 bits are used to indicate whether the 8 vectors corresponding to the bits that are 1 in the local group are flipped.

[0018] The beneficial effects of the present invention are as follows: the memory allocator implements dynamic continuous vector allocation and release based on a two-layer binary tree vector, which can not only expand the number of vectors in each layer to manage a larger memory space, but also reduce the overhead of hardware resources and increase the main frequency through methods such as layering, grouping, algorithm optimization, resource sharing and time-space multiplexing. It has high memory allocation efficiency and speed and reduces memory fragmentation, and can provide an efficient memory management solution for scenarios with extremely high storage requirements such as core switching networks, deep learning, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the mechanisms shown in these drawings without paying any creative work.

[0020] Figure 1 This is an overall architecture diagram of a memory allocator according to an embodiment of the present invention;

[0021] Figure 2 This is a diagram of a binary tree structure of a 64-vector OR gate according to an embodiment of the present invention;

[0022] Figure 3 A double-value node and a zero-checking circuit diagram according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of group flipping according to an embodiment of the present invention;

[0024] Figure 5 4 is a system working flow diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0027] like Figure 1 As shown, an embodiment of the present invention is: a dynamic continuous address memory allocator based on a two-layer binary tree vector, comprising: a top-level vector table module, a sub-layer vector table module, a free block positioning module, a first zero coordinate search module and a bit flip module.

[0028] The top-level vector table module includes a plurality of top-level vector groups, the sub-layer vector table module includes a plurality of sub-layer vector groups, the number of the top-level vector groups is the same as the number of the sub-layer vector groups, and the top-level vector groups map the sub-layer vector groups to manage the sub-layer vectors in the sub-layer vector groups;

[0029] Each top-level vector group includes a top-level vector and an idle level; the top-level vector describes whether the corresponding sub-level vector group can be used in the request allocation; the idle level describes the level of the number of allocable continuous idle vectors in the corresponding sub-level vector group, indicating the maximum number of allocable vectors in the corresponding sub-level vector group. The top-level vector table module includes 64 top-level vector groups; each top-level vector group includes 1 bit of the top-level vector and 3 bits of the idle level.

[0030] Top-level vector table module: structure as follows Figure 1 As shown in, it is mainly composed of 64 groups of top-level vectors, namely 64 top-level vectors (TBVs) and free levels (FLs). Each TBV is 1 bit, which is used to describe whether the corresponding sub-layer vector group can be used in the requested vector allocation. The value of each TBV is updated according to the requested vector number Size and FL when requesting to allocate or release a vector. If the updated value is 1, it means it is not available, otherwise it is 0, which means it can be used. Each FL is 3 bits, which is used to describe the level of the number of allocable continuous free vectors in the corresponding sub-layer vector group, indicating the maximum number of allocable vectors in the group, with a value range of 0 to 7, where 7 means that no vector in the corresponding sub-layer vector group is free. When the value of FL[i] is not 7, the maximum number of continuous allocable vectors in the corresponding SBV is 2 6 - FL[i] .

[0031] The TBV is generated as follows:

[0032] 1. If FL[i] is 7, the generated TBV[i] is 1;

[0033] 2. If FL[i] is not 7, Size ≤ 64 and 2 6-FL[i] ≥Size, TBV[i] is 0, otherwise it is 1;

[0034] 3. If Size>64 and FL[i]=0, TBV[i] is 0, otherwise it is 1;

[0035] When the TBV vector input to the bit flip module flips, the corresponding FL change method is:

[0036] 1. If the number of flipped TBVs is 1, FL remains unchanged;

[0037] 2. If the request type is allocation and the number of TBVs to be flipped is multiple, the corresponding FLs except the last one remain unchanged and all others become 7. If TBV[4] to TBV[7] flip from 0 to 1, then FL[4]

[0038] ~FL[6] is set to 7, and FL[7] remains unchanged;

[0039] 3. If the request type is release and the number of TBVs to be flipped is multiple, the corresponding FLs except the last one will be changed to 0. If TBV[2]~TBV[3] flip from 1 to 0, then FL[2]

[0040] Set to 0, FL[3] remains unchanged;

[0041] Since the allocated or released vectors are continuous in space, if the number of vectors is greater than 64, there will be multiple groups of SBVs, that is, multiple TBVs that need to be flipped, such as TBV[i]~TBV[k]. Then, TBV[i]~TBV[k-1] will all need to be flipped. The above-mentioned method of updating FL can directly update FL[i]~FL[k-1], avoiding the bit flip module from updating FL[i]~FL[k] sequentially, thereby greatly improving the update efficiency.

[0042] For example, after initialization and power-on, all TBVs and FLs are 0. If a request is made to allocate 130 vectors, that is, 3 TBVs are involved in this allocation, the SBVs finally allocated are: SBV[2][1:0], SBV[1][63:0], SBV[0][63:0]. The above method can change the values ​​of FL[0] and FL[1] to 7. Since vector [1][0] in SBV[2] is occupied, the maximum number of consecutive zero vectors that can be allocated in SBV[2] is 32. From the formula (1) described below, we can get FL[2] = 1.

[0043] Each sub-layer vector group includes multiple sub-layer vectors; each sub-layer vector is mapped to a physical memory space, and the physical memory space is managed by occupying and releasing the sub-layer vector. The sub-layer vector table module includes 64 sub-layer vector groups, each sub-layer vector group includes 64 bits, and the entire sub-layer vector table is composed of 64×64=4096 1-bit sub-layer vectors, a total of 4k bit sub-layer vectors.

[0044] Sublayer vector table module: structure is as follows Figure 1 As shown in , it is mainly composed of 64 groups of sub-layer vectors, namely SBV[0] to SBV

[63] . Each group of SBV is a 64-bit vector. Each vector is mapped to a physical memory space. The memory allocator has a total of 4096 SBV vectors. By occupying and releasing these sub-layer vectors, the management of 4k physical memory spaces is achieved. SBV[i], TBV[i] and FL[i] correspond one to one. FL[i] is obtained according to the AND gate binary tree of SBV[i]:

[0045] FL[i]=6-ceil(log2(MACB))#(1)

[0046] Formula (1) can be used to update the corresponding FL with the updated SBV. In formula (1), ceil refers to rounding up, and MACB refers to the maximum number of allocable continuous zero vectors in SBV[i]. Figure 2 As shown (the shaded squares in the figure indicate that the vector value is 1, i.e. occupied), in the group vector SBV[i], i.e. level 6, vectors [2] to [9] are 0, i.e. free, and the rest are occupied. From the binary tree generated by the OR gate, we know that vectors [1] to [4] in level 5 are 0, vector [1] in level 4 is 0, and the vectors of all other nodes are 0. In the binary tree of the AND gate, the highest level where the zero vector is located is 4, and the number of vectors under any node of level 4 is 4, so MACB is 4, and FL[i] = 6-ceil(log2(4)) = 4.

[0047] The idle block positioning module is used to generate an OR gate binary tree structure based on an OR gate for the input top-level vector or sub-layer vector, and select a level vector of the OR gate binary tree for output based on the number of vectors allocated by an external request, and locate the idle vector block.

[0048] Wherein, in the output hierarchical vector, the free block positioning module has a zero indicating that the vector block of its root node can allocate the number of continuous free vectors required this time, thereby locating the free vector block for allocation.

[0049] Locate the free block module: the structure is as follows Figure 1As shown in , based on the 64 vectors input to the module, a binary tree structure is generated according to the OR gate. Combined with the number of vectors requested for positioning, LocSize, the module outputs the level L of the binary tree and the vector of level L. The calculation method of LocSize and level L is as follows (where n is an integer):

[0050]

[0051]

[0052] L = 6-ceil(log2(LocSize))#(4)

[0053] Based on the allocation concept of binary tree, the number of underlying vectors under each node is a power of 2, so the value of LocSize is equivalent to quantizing LSize to a power of 2 and then quantizing it upward. For example, when LSize = 12, the node vector of level 2 has 16 underlying vectors, which can just meet the size of LSize = 12 for allocation, so LocSize is a quantization method for LSize.

[0054] From formula (3) and (4), we know that when LSize is 1, there are 64 vectors of the output level L=6, i.e., the bottom layer vectors; when LSize is 2, there are 32 vectors of the output level L=5; when LSize is 3 or 4, there are 16 vectors of the output level L=4; when LSize is 5 to 8, there are 8 vectors of the output level L=3; when LSize is 9 to 16, there are 4 vectors of the output level L=2; when LSize is 17 to 32, there are 5 vectors of the output level L=1; when LSize is 33 to 64, there is 1 vector of the output level L=0. Based on formula (4), the multiplexer selects the vector of level L as the output vector. Since the number of vectors of each level is different, it is necessary to add zeros to the high bits of levels 0 to 5 to ensure that the number of output vectors is 64. Therefore, the level L and the vector of the level can be obtained according to the Size and the input vector source. The bottom layer vector under any node vector of the level L is a continuous vector, so the free block can be located.

[0055] For example, Figure 2 In the figure, the vector [1] in level 2 is the second vector from the left of level 2, and the underlying vectors below it are

[16] to

[31] . That is, a continuous area of ​​the underlying vectors can be located by the level vectors.

[0056] The first zero coordinate search module is used to use the hierarchical vector output by the free block positioning module as the input vector of the module, divide the input vector into multiple groups and generate multiple groups of AND gate binary trees based on AND gates to find the first zero vector coordinates;

[0057] Each node of the AND gate binary tree consists of two bits, and the two bits respectively represent the result of ANDing the sub-nodes and the direction of the zero in the sub-node.

[0058] Among them, in the module for searching the first zero coordinate, searching for the first zero vector coordinate includes: searching for the first zero of each group of AND gate binary trees, and outputting the zero-searching results of each group; obtaining the subscript of the first group of first zero vectors from each group of zero-searching results through a decoder with priority, and calculating the subscript of the first zero vector in the sub-layer vector group based on the hierarchical depth, thereby obtaining the allocated first zero vector coordinates.

[0059] Find the first zero coordinate module: The structure is as follows Figure 1 As shown in , the number of vectors input into the module by the positioning idle module is 64. The 64 vectors are divided into 4 groups. For each group of 16 vectors, a binary tree is generated according to the AND gate, and the first zero is searched. The zero-checking results of the four groups are output and shifted according to the group number and the level L of the input vector from the positioning idle block. Finally, the result of the lowest position group is output from the valid results of the splicing and shifting of each group through the multiplexer. The zero-checking circuit of each group is as follows Figure 3 As shown, the 16 vectors of each group are used to generate a binary tree according to the AND gate. The left value a of each node (except the bottom layer) is the result of the AND gate, and the right value b is the zero direction. When the value a of the left child of the node is 0, b is 0, otherwise b is 1. (i)(k) , b (i)(k) ) is a node (i is the height of the binary tree level where the node is located, k is the left-starting coordinate), and its child nodes are (a (i-1)(2k) , b (i-1)(2k) ) and (a (i-1)(2k+1) , b (i-1)(2k+1) ), then (a (i)(k) , b (i)(k) ) is expressed as:

[0060] a (i)(k) =a (i-1)(2k) AND a (i-1)(2k+1) #(5)

[0061] b (i)(k) =a (i-1)(2k) #(6)

[0062] Formulas (5) and (6) can be used to obtain the two values ​​(a, b) of each binary tree node. Since b represents the direction of the zero in the child node, the b of each level is used as the input signal of the multiplexer, and the selection result of the higher level is used as the selection signal of the multiplexer. The coordinates of the first zero vector in the 16 vectors in the group can be calculated; and the a value of the highest level is a (0)(0)The AND gate result of the group of 16 vectors indicates whether there is a zero vector in the group of vectors, that is, whether the coordinates of the first zero vector output by the zero-checking circuit of the group are valid. In this module, 4 groups of zero-checking circuits are used to search the 64 vectors in different intervals, which can reduce the length of the logic chain in the combinational logic circuit and achieve a higher circuit frequency.

[0063] The 4 groups of zero-checking circuits output 4 first zero coordinates to the splicing shift circuit respectively. The splicing circuit splices the 4 groups of first zero coordinates with the group number. The shift circuit shifts based on the level L. The representation method is as follows:

[0064] Splicing result = {group number of the group, the first zero coordinate of the group number}; shift result = splicing result << (6-L). Where << represents the left shift sign, and left shift (6-L) is equivalent to multiplying by 2 6-L .

[0065] The four groups of shift results are used as the input of the priority encoder, and the control signal of the priority encoder is a (0)(0) , group number 0 has the highest priority, followed by group number 1, and the first zero coordinate value found by the module is output in this order. If the source vector of the input positioning free block is TBV, the first zero coordinate value output by the vector of the positioning free block after being processed by this module will be stored in the high address register (HAddr); if the source vector of the input positioning free block is SBV, the first zero coordinate value output by the vector of the positioning free block after being processed by this module will be stored in the low address register (LAddr).

[0066] For example, when group number is 0 (its vector coordinates are in the interval [0, 15]) (0)(0) If it is 1, the output first zero coordinate is invalid. The first zero coordinate of the 16 vectors with group number 1 (whose vector coordinates are in the interval [16, 31]) is 3 and a (0)(0) When L=6, the splicing result output by the module is {2'b01, 4'b0011}=6'b010011=6'd19, and the shift result is equal to the splicing result, that is, the coordinate of the first zero element obtained by splicing group number 1 and coordinate 3 and then shifting is 19.

[0067] Therefore, the first zero search and splicing shift are performed through grouping to finally output the first zero coordinates. On the one hand, the grouping idea can reduce the length of the combinational logic chain and improve the system main frequency. On the other hand, the priority mechanism of the first zero can reduce memory fragmentation and improve memory utilization.

[0068] The bit flip module is used to flip the allocated vector value to 1 and flip the released vector value to 0, thereby completing the occupation and release of the vector.

[0069] Wherein, in the bit flip module, the input vector is divided into 8 vector groups, each group has 8 vectors. In the bit flip module, the vector groups include global group, local group and local mask group; in the global group, the 8 vectors corresponding to the bit that is 1 are all flipped; in the local group, the 8 vectors corresponding to the bit that is 1 are only partially flipped; in the local mask group, 8 bits are used to indicate whether the 8 vectors corresponding to the bit that is 1 in the local group are flipped.

[0070] Bit flip module: The bit flip module takes a vector from the top-level vector table or the sub-level vector table, and flips the vector according to the Size and the first zero coordinate (that is, the address Addr). If the request type is allocation, the vector value is flipped to 1, and if the request type is release, the vector value is flipped to 0. The internal combinational logic is implemented and the updated vector is output. In the bit flip module, the 64 input vectors are divided into 8 groups, each with 8 vectors, such as Figure 1 Global group and local group. In the global group, all 8 vectors corresponding to the bit that is 1 are flipped; in the local group, only some of the 8 vectors corresponding to the bit that is 1 are flipped. Due to the characteristics of binary tree allocation, there may be multiple consecutive bits that are 1 in the global group, but at most only one bit is 1 in the local group. The 8 bits of the local mask are used to indicate whether the 8 vectors corresponding to the bit that is 1 in the local group are flipped. The schematic diagram is shown as follows Figure 4 The algorithm for calculating the global group GlobalGroup, the local group LocalGroup, and the local mask LocalMask is as follows:

[0071]

[0072] LocalMask = 2 (CSize％8)+(CAddr％8) -2 CAddr％8 #(11)

[0073] In formulas (7) and (8), Size[12:0] is the number of vectors requested externally, which is 1 to 4096, and the range of CSize is 1 to 64. HAddr and LAddr are the high address and low address output by the zero-checking first coordinate module, respectively, and the range is 0 to 63. Depending on the input vectors from different sources, the value of CSize and CAddr is different. CSize indicates the number of vectors that need to be flipped among the 64 vectors input to the module, and CAddr indicates the address (subscript) of the first vector to be flipped.

[0074] In formulas (9), (10), and (11), the floor function is used to round down. In the circuit, the floor operation of dividing by 8 can be implemented by bit truncation, taking bits 3 and above, that is, [MSB:3], where MSB represents the highest bit; 2 nThe operation can be realized by shifting 1 left by n bits; the remainder operation on 8 can be realized by bit truncation, that is, taking only bits [2:0]. Based on addition, subtraction, shifting and truncation, formulas (9), (10) and (11) can be realized. After obtaining the global group GlobalGroup, the local group LocalGroup and the local mask LocalMask, the 64 vectors input to the module are judged and updated by the following methods:

[0075] 1. If the vector is in the 8 vectors corresponding to bit 1 in the global group GlobalGroup, the vector is flipped to 1 if the request type is allocation, and to 0 if the request type is release;

[0076] 2. If the vector is in the 8 vectors corresponding to bit 1 in the local group LocalGroup, and the position of the vector in the 8 vectors has a value of 1 in the local mask LocalMask, the vector is flipped to 1 if the request type is allocation, and to 0 if the request type is release;

[0077] 3. If 1 and 2 above are not true, the vector remains unchanged.

[0078] For example, when CSize=18 and CAddr=16, we can get: GlobalGroup=12, corresponding to binary 8'b00001100, that is, all vectors in groups [2] and [3] are flipped, and the corresponding input vectors

[16] to

[31] are flipped; LocalGroup=16, corresponding to binary 8'b00010000, that is, part of group [4] is flipped, LocalMask=3, corresponding to binary 8'b00000011, then vectors [0][1] of group [4], that is, input vectors

[32]

[33] are flipped. Figure 4 As shown, the input vectors

[16] ~

[33] can be flipped to realize the function of this module.

[0079] Therefore, the 64 vectors input to the module are grouped and flipped based on an algorithm that is more suitable for digital circuit implementation, which not only reduces the consumption of circuit resources but also reduces the delay of combinational logic. In the memory allocator, a bit flip module is used through resource sharing and different time and space multiplexing methods to achieve flipping and updating of top-level vectors and sub-level vectors with less circuit resource consumption.

[0080] The workflow of each module within the memory allocator is as follows Figure 5 As shown in the figure, the specific steps of the system workflow are as follows:

[0081] 1. The system is powered on and TBV, FL and SBV are initialized to zero;

[0082] 2. Wait for external request signal;

[0083] 3. If the request type is allocation and the request vector size does not exceed 64 (only one TBV and its corresponding 64 SBV vectors are required):

[0084] 3.1 In the top-level vector table module, TBV is updated based on the requested vector number Size and the value of FL, and TBV is output to the free block positioning module;

[0085] 3.2 Generate a binary tree based on TBV by OR gate in the positioning free block. Since the size is no more than 64, only the bottom 64 vectors of the binary tree need to be output to the module for finding the first zero coordinate;

[0086] 3.3 In the module for searching the first zero coordinate, if the zero vector cannot be found in each group, the memory allocator reports the allocation failure to the outside and returns to the process step 2 (waiting for the external request signal). If the zero vector is found, the lowest-order zero coordinate is output to the high-address register and the bit flip module;

[0087] 3.4 In the bit flip module, according to the request type of allocation, a certain vector of the TBV input to the module is flipped to 1, and the corresponding FL of the vector whose TBV is flipped is set to 7 in the top-level vector table module;

[0088] 3.5 At the same time as step 3.4, select SBV[HAddr] in the sub-layer vector table according to the first zero vector coordinate HAddr output in step 3.3 and output the SBV[HAddr] to the positioning free block;

[0089] 3.6 Generate a binary tree based on SBV by OR gate in the positioning free block, select a certain level vector of the binary tree according to formula (2)(3)(4), fill the high bit with zero, and then output 64 vectors to the module for finding the first zero coordinate;

[0090] 3.7 In the module for finding the first zero coordinate, each group searches for the coordinate of the first zero vector and outputs the lowest bit of the zero coordinate to the low address register LAddr and the bit flip module;

[0091] 3.8 In the bit flip module, according to the request type of allocation, the SBV part vector input to the module is flipped to 1, and the flipped SBV is updated to the sub-layer vector table and sent to the positioning free block;

[0092] 3.9 Generate a binary tree by the OR gate according to the updated SBV value in the positioning free block, calculate the FL value corresponding to the SBV based on the binary tree, and update the calculated FL value to the top-level vector table. This allocation is completed, and the output address is {HAddr, LAddr}, that is, the high address register concatenated with the low address register, and return to step 2 of the process (waiting for the external request signal);

[0093] 4. If the request type is allocation and the request vector size exceeds 64 (requires multiple TBVs and corresponding SBVs, such as Figure 5 Short-dashed branch):

[0094] 4.1 In the top-level vector table module, TBV is updated based on the requested vector number Size and the value of FL, and TBV is output to the free block positioning module;

[0095] 4.2 In the positioning free block, a binary tree is generated by an OR gate based on TBV. Since the size exceeds 64, a vector of a certain layer of the binary tree is selected according to formula (2), (3), (4), and the high-order zeros are filled and then 64 vectors are output to the module for finding the first zero coordinates.

[0096] 4.3 Same as step 3.3;

[0097] 4.4 In the bit flip module, according to the request type of allocation, multiple TBV vectors input to the module are flipped to 1, the corresponding FL of the vector whose TBV is flipped is set to 7 in the top-level vector table module, and the corresponding SBV of all the vectors whose TBV is flipped except the last one in the sub-layer vector table module is set to 1, and the corresponding SBV of the last one of the vectors whose TBV is flipped is output to the bit flip module for processing;

[0098] 4.5 In the bit flip module, according to the request type of allocation, the SBV part vector input to the module is flipped to 1, and the flipped SBV is updated to the sub-layer vector table and sent to the positioning free block;

[0099] 4.6 is the same as 3.9;

[0100] 5. If the request type is release (such as Figure 5 Long and short dashed line branches):

[0101] 5.1 In the top-level vector table, update TBV based on the requested vector number Size and the value of FL, and output TBV to the bit flip module;

[0102] 5.2 In the bit flip module, according to the type of request being release, flip a single or multiple TBV vectors to 0, set the corresponding FL of the vector whose TBV is flipped to 0 in the top-level vector table module, set the corresponding SBV of all the vectors whose TBV is flipped except the last one in the sub-layer vector table module to 0, and output the corresponding SBV of the last one of the vectors whose TBV is flipped to the bit flip module for processing;

[0103] 5.3 In the bit flip module, according to the request type of release, the relevant vector in the SBV input to the module is flipped to 0, and the flipped SBV is updated to the sub-layer vector table and sent to the positioning free block;

[0104] 5.4 Generate a binary tree by the OR gate according to the updated SBV value in the located free block, calculate the FL value corresponding to the SBV based on the binary tree, and update the calculated FL value to the top-level vector table. Complete this release and return to step 2 of the process (wait for the external request signal).

[0105] Based on the above workflow, when the number of vectors allocated by the external request does not exceed 64, it can be completed in 8 cycles; when the number of vectors allocated by the external request exceeds 64, it can be completed in 6 cycles; when the external request releases the vector, it can be completed in 4 cycles.

[0106] In summary, the memory allocator implements dynamic continuous address (vector) allocation and release based on a two-layer binary tree vector. It can not only expand the number of vectors in each layer to manage a larger memory space, but also reduce the overhead of hardware resources and increase the main frequency through methods such as layering, grouping, algorithm optimization, resource sharing and time-space multiplexing. It has high memory allocation efficiency and speed and reduces memory fragmentation, providing an efficient memory management solution for scenarios with extremely high storage requirements such as core switching networks and deep learning.

[0107] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dynamic continuous address memory allocator based on a two-layer binary tree vector, characterized in that: include: Top-level vector table module, sub-layer vector table module, free block positioning module, first zero coordinate search module and bit flip module; The top-level vector table module includes a plurality of top-level vector groups, the sub-layer vector table module includes a plurality of sub-layer vector groups, the number of the top-level vector groups is the same as the number of the sub-layer vector groups, and the top-level vector groups map the sub-layer vector groups to manage the sub-layer vectors in the sub-layer vector groups; The idle block positioning module is used to generate an OR gate binary tree structure based on an OR gate for the input top-level vector or sub-layer vector, and select a level vector of the OR gate binary tree for output based on the number of vectors allocated by the external request, and locate the idle vector block; The first zero coordinate search module is used to use the hierarchical vector output by the free block positioning module as the input vector of the module, divide the input vector into multiple groups and generate multiple groups of AND gate binary trees based on AND gates to find the first zero vector coordinates; The bit flip module is used to flip the allocated vector value to 1 and flip the released vector value to 0, thereby completing the occupation and release of the vector.

2. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: Each top-level vector group includes a top-level vector and an idle level; the top-level vector describes whether the corresponding sub-layer vector group can be used in the request allocation; the idle level describes the level of the number of allocatable continuous idle vectors in the corresponding sub-layer vector group, indicating the maximum number of allocatable vectors in the corresponding sub-layer vector group.

3. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 2, characterized in that: The top-level vector table module includes 64 top-level vector groups; each top-level vector group includes a 1-bit top-level vector and a 3-bit idle level.

4. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: Each sub-layer vector group includes multiple sub-layer vectors; each sub-layer vector is mapped to a physical memory space, and the physical memory space is managed by occupying and releasing the sub-layer vectors.

5. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 4, characterized in that: The sub-layer vector table module includes 64 groups of sub-layer vector groups, each sub-layer vector group includes 64 bits, and the entire sub-layer vector table is composed of 64×64=4096 1-bit sub-layer vectors, a total of 4k-bit sub-layer vectors.

6. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: Each node of the AND gate binary tree consists of two bits, and the two bits respectively represent the result of ANDing the child nodes and the direction of the zero in the child nodes.

7. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: The idle block positioning module, in the output hierarchical vector, is zero, indicating that the vector block of its root node can allocate the number of continuous idle vectors required this time, thereby locating the idle vector block for allocation.

8. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: In the module for searching for the first zero coordinates, searching for the first zero vector coordinates includes: searching for the first zero for each group of AND gate binary trees, and outputting the zero-searching results for each group; obtaining the subscript of the first group of first zero vectors from each group of zero-searching results through a decoder with priority, and calculating the subscript of the first zero vector in the sub-layer vector group based on the hierarchical depth, thereby obtaining the allocated first zero vector coordinates.

9. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 1, characterized in that: In the bit flip module, the input vector is divided into 8 vector groups, each group has 8 vectors.

10. The dynamic continuous address memory allocator based on two-layer binary tree vector as claimed in claim 9, characterized in that: In the bit flip module, the vector group includes a global group, a local group and a local mask group; in the global group, the 8 vectors corresponding to the bits that are 1 are all flipped; in the local group, the 8 vectors corresponding to the bits that are 1 are only partially flipped; in the local mask group, 8 bits are used to indicate whether the 8 vectors corresponding to the bits that are 1 in the local group are flipped.

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