Processor, operating method thereof, processing system, electronic device, and storage medium

Abstract

The embodiment of the invention relates to a processor, an operation method of the processor, a processing system, electronic equipment and a storage medium. The processor comprises a read-write unit, a first configuration register and a programmable function unit, the read-write unit is configured to read to-be-processed data from the outside of the processor and write the processed data to the outside of the processor; the first configuration register is configured to store first configuration information; the programmable function unit is configured to be programmed according to the first configuration information to achieve a data processing function corresponding to the first configuration information so as to process the to-be-processed data to obtain processed data. The processor can be flexibly configured according to actual application requirements, so that the processor can be suitable for various application scenes.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a processor and an operating method thereof, a processing system, an electronic device, and a storage medium. Background Art

[0002] With the development of electronic technology, it is increasingly difficult for central processing units (CPUs) to meet the ever-increasing demand for computing power. In order to obtain stronger computing power and better energy efficiency, a large number of processor designs have been proposed to replace CPUs in specific scenarios. However, these processors usually hardwareize the computing logic and can only meet the computing needs in specific scenarios. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a processor, comprising: a read-write unit, configured to read data to be processed from outside the processor and write processed data to outside the processor; a first configuration register, configured to store first configuration information; and a programmable function unit, configured to be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information, so as to process the data to be processed to obtain processed data.

[0004] At least one embodiment of the present disclosure provides a processor system, including: a first processor; and a second processor, including the processor provided by at least one embodiment of the present disclosure, wherein the first processor is communicatively connected to the second processor, and the first processor is configured to call the second processor to perform data processing.

[0005] At least one embodiment of the present disclosure provides a method for operating a processor, and the processor is the processor provided by at least one embodiment of the present disclosure, and the operating method includes: writing first configuration information to a first configuration register; a programmable functional unit is programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information, so as to process the data to be processed obtained by the read-write unit to obtain processed data.

[0006] At least one embodiment of the present disclosure provides an electronic device, including: a processor; and a memory, including one or more computer program instructions; wherein the one or more computer program instructions, when executed by the processor, implement an operating method of the processor provided by at least one embodiment of the present disclosure.

[0007] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the operating method of the processor provided by at least one embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0009] Figure 1 A diagram schematically showing an application scenario of a processor and an operating method thereof according to at least one embodiment of the present disclosure;

[0010] Figure 2 A structural block diagram of a processor according to at least one embodiment of the present disclosure is schematically shown;

[0011] Figure 3 A flowchart schematically illustrates an operating method of a processor according to at least one embodiment of the present disclosure;

[0012] Figure 4 A structural block diagram of a processor according to at least another embodiment of the present disclosure is schematically shown;

[0013] Figure 5 A structural block diagram of a processor according to at least another embodiment of the present disclosure is schematically shown;

[0014] Figure 6 A schematic diagram showing the structure of an interface conversion unit according to at least one embodiment of the present disclosure is shown;

[0015] Figure 7 The structure block diagram of the programmable function unit of at least one embodiment of the present disclosure is schematically shown;

[0016] Figure 8 Schematically shows a structural block diagram of a programmable function unit of at least another embodiment of the present disclosure;

[0017] Fig. 9 A structural block diagram of a processor according to at least another embodiment of the present disclosure is schematically shown;

[0018] Fig.10 A block diagram schematically shows a structure of a processing system according to at least one embodiment of the present disclosure;

[0019] Fig.11 A block diagram schematically showing a structure of an electronic device according to at least one embodiment of the present disclosure; and

[0020] Fig.12 A schematic diagram schematically illustrates a computer-readable storage medium according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0022] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0023] It is becoming increasingly difficult for CPUs to meet the increasing demands of computing examples in various fields. In order to obtain stronger computing power and better energy efficiency, a large number of processor (such as coprocessor) designs have been proposed to replace CPUs to provide computing power in specific scenarios. For example, heterogeneous computing architectures of CPU+coprocessors are becoming increasingly popular. These proposed processor designs often focus on the computing needs of specific scenarios. Compared with general-purpose CPUs, they have almost no additional redundant designs and can hardwareize computing logic to the greatest extent possible according to computing needs. Therefore, compared with general-purpose CPUs, they can provide higher computing power with the same resource overhead.

[0024] For example, these proposed processor designs first define application scenarios during the design phase, then decompose requirements based on the application scenarios and implement the decomposed requirements through design. In order to ensure the simplicity and efficiency of the processor design, the data processing modules of these processors usually adopt a highly customized design, so they can only process calculations in pre-defined application scenarios.

[0025] Given the high cost of chip design, for example, only a few application scenarios are worth developing corresponding processors. However, in reality, there are a large number of application scenarios that have an urgent need for processors with high computing power and low power consumption.

[0026] At least one embodiment of the present disclosure is intended to provide a processor and an operating method thereof, so that the processor can be flexibly configured according to actual application requirements, so that the processor can be applied to a variety of application scenarios, whether it is to perform processing operations alone or to operate as a coprocessor in conjunction with a CPU. Figure 1 The application scenarios of the processor and the operating method thereof provided by at least one embodiment of the present disclosure are described.

[0027] like Figure 1 As shown, the application scenario 100 may include a first processor 101, a second processor 102, a memory 103 and a bus 104. The first processor 101 and the second processor 102 may access the memory 103 through the bus 104, and the first processor 101 and the second processor 102 may be communicatively connected through the bus 104.

[0028] For example, the first processor 101 may be a CPU. The second processor 102 may be a graphics processor GPU, an artificial intelligence chip, etc. The second processor 102 may be used as a coprocessor, for example, to process a specific task. For example, the second processor 102 may be connected to the system bus of the first processor 101, and the first processor 101 executes the instruction stream to be executed. If the instruction to be executed is a coprocessor instruction, the first processor 101 sends the coprocessor instruction to the second processor 102 for execution, otherwise the first processor 101 executes the instruction to be executed; when executing the coprocessor instruction, the second processor 102 may, for example, directly or indirectly access the memory 103 through the first processor 101.

[0029] For example, when the first processor 101 and the second processor 102 are executing instructions respectively, the data required for executing the instructions can be read from the memory 103 through the bus 104, and the read data can be processed to obtain processed data. Subsequently, the first processor 101 and the second processor 102 can also write the processed data obtained by their respective processing into the memory 103 through the bus 104.

[0030] In one embodiment, the first processor 101 and the second processor 102 may be integrated into the same electronic device, which may be, for example, a smart phone, a tablet computer, a portable computer, a desktop computer, or a server.

[0031] It is understandable that, according to actual needs, in other application scenarios, the first processor 101 and the second processor 102 can also be independently set in different electronic devices to independently implement different data processing functions, and the present disclosure does not limit this.

[0032] For example, according to actual needs, the second processor 102 can be a processor provided by at least one embodiment of the present disclosure, in order to flexibly configure the data processing function of the second processor 102 through the operation method of the processor provided by at least one embodiment of the present disclosure, so that the second processor 102 can be applied to more application scenarios.

[0033] The following will be combined Figure 2~Figure 9 A processor and an operating method thereof provided by at least one embodiment of the present disclosure are described in detail.

[0034] Figure 2 The structure block diagram of the processor according to at least one embodiment of the present disclosure is schematically shown.

[0035] like Figure 2 As shown, the processor 200 of this embodiment includes a first configuration register 201 , a read / write unit 202 , and a programmable function unit 203 .

[0036] For example, the first configuration register 201 is in communication connection with the programmable function unit 203. The first configuration register 201 may store configuration information, and the programmable function unit 203 may be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information; for example, different configuration information may correspond to different data processing functions, such as image data, audio data, video data processing, etc.

[0037] In at least one embodiment, the first configuration register 201 may include multiple groups of registers, for example, each register in the multiple groups of registers has a unique access address. The first configuration register 201 can be read and written from outside the processor, and specifically, the first configuration register 201 can be read and written through the address to modify the configuration information stored in the first configuration register 201, and the modified configuration information can be passed to the programmable function unit 203 to correspondingly modify the data processing function of the programmable function unit 203. Through at least one embodiment, the flexible configuration of the data processing function of the processor 200 can be better realized.

[0038] In at least one embodiment, the first configuration register 201 may be a programmable configuration register, and the function of the first configuration register may be redefined in conjunction with a programmable functional unit.

[0039] In at least one embodiment, the information stored in the first configuration register 201 may be part of the first configuration information that enables the programmable function unit 203 to be programmed to have the corresponding data processing function, and the first configuration register 201 may be serially read and written multiple times from outside the processor 200. For example, each read and write operation only writes one information block of the first configuration information, and the written information block will be sent to the programmable function unit 203 in a timely manner. The information block written by each write operation except the first write operation may overwrite the information block stored in the first configuration register 201 that has been sent to the programmable function unit 203.

[0040] For example, the read / write unit 202 may also be connected to other devices outside the processor 200 in communication, so as to read the data to be processed from outside the processor. The read / write unit 202 may also be connected to the programmable function unit 203 in communication, so as to send the read data to be processed to the programmable function unit 203 for processing. The programmable function unit 203 may also send the processed data obtained by processing the data to be processed to the read / write unit 202, so that the read / write unit 202 sends the processed data to the outside of the processor.

[0041] In at least one embodiment, the read / write unit 202 can, for example, access a storage space outside the processor to read the data to be processed from the storage space and write the processed data to the storage space. In at least another embodiment, the read / write unit 202 can also access at least two storage spaces outside the processor to read the data to be processed from one of the storage spaces and write the processed data to another storage space. The storage space can be provided by, for example, a memory, a register, etc. The memory can be a random read / write memory, etc., which is not limited in the embodiments of the present disclosure.

[0042] In at least one embodiment, the read / write unit 202 may include a direct memory access (DMA) controller to perform DMA operations, so that the read / write unit 202 can complete the reading and writing of data by itself without the help of a CPU.

[0043] For example, the programmable function unit 203 may be implemented by a programmable circuit, and the function of the programmable circuit may be changed by reconfiguration. For example, the programmable function unit 203 may include a programmable logic device such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), and the programmable function unit 203 may program the programmable logic device based on the first configuration information, which is not limited in the present disclosure.

[0044] For example, the programmable functional unit 203 includes at least one programmable unit and one configuration unit, and the configuration unit is used to program the programmable unit based on the first configuration information so that the programmable unit implements the data processing function corresponding to the first configuration information.

[0045] For example, in addition to the programmable unit and the configuration unit, the programmable function unit may also include a programmable routing array. By programming the programmable routing array based on the first configuration information, the communication connection between the programmable unit and other units outside the programmable function unit 203 can be realized. At least one embodiment of the present disclosure provides a processor including a first configuration register and a programmable function unit, and can flexibly program the programmable function unit according to the first configuration information in different application scenarios, so that the programmable function unit has different data processing functions, effectively expanding the application scenarios applicable to the processor. The processor provided by at least one embodiment of the present disclosure, for example, can have high performance and low power consumption characteristics, and also have configuration flexibility.

[0046] In at least one embodiment of the present disclosure, the first configuration register may also store second configuration information. The programmable functional unit may configure itself according to the second configuration information. Exemplarily, the second configuration information may include data for configuring at least one of the logic gate circuits such as an AND gate, a NOT gate, an OR gate, a NAND gate, a NOR gate, and an XOR gate in the programmable functional unit to change the processing result obtained by the programmable functional unit processing the data to be processed. It is understandable that the type of the second configuration information is only used as an example to facilitate the understanding of the present disclosure, and the embodiments of the present disclosure are not limited to this.

[0047] Exemplarily, the first configuration register may include multiple groups of registers, a portion of the registers are configured to store the first configuration information, and another portion of the registers are configured to store the second configuration information.

[0048] At least one embodiment of the present disclosure can further improve the configuration flexibility of the data processing function of the programmable function unit by configuring the programmable function unit itself according to the second configuration information, so that the processor set up with the programmable function unit can meet the data processing requirements in more scenarios.

[0049] In at least one embodiment of the present disclosure, the programmable functional unit may also determine the programmed programming state during the process of being programmed according to the first configuration information. For example, the programming state may include an unprogrammed state, a programming state, a programming completion state, and a programming failure state. After determining the programming state, the programmable functional unit may feed back the programming state to the first configuration register. For example, the first configuration register may also save the programming state fed back by the programmable functional unit so as to read the programming state from outside the processor.

[0050] Exemplarily, the first configuration register may include at least two groups of registers, some of which are configured to store the first configuration information, and some of which are configured to store the programming state.

[0051] Exemplarily, the first configuration register may include at least three groups of registers, wherein the first part of the registers is configured to save the first configuration information, the second part of the registers is configured to save the second configuration information, and the third part of the registers is configured to save the programming state. For example, the first configuration register may include 32 groups of registers, one of which is configured to save the first configuration information, one of which is configured to save the programming state, and the remaining 30 groups of registers are configured to save the second configuration information. It is understandable that the information configured to be saved by the above-mentioned multiple groups of registers is only used as an example to facilitate understanding of the present disclosure, and the present disclosure does not limit this.

[0052] At least one embodiment of the present disclosure determines the programming status of the programmable functional unit and feeds back the programming status to the first configuration register, so as to facilitate reading the programming status from outside the processor, so as to determine whether to read and write the first configuration register from outside the processor based on the programming status, thereby facilitating adjustment of the first configuration information stored in the first configuration register to ensure completion of programming of the programmable functional unit.

[0053] Figure 3 The flowchart schematically shows the operation method of the processor of at least one embodiment of the present disclosure. Figure 2 ,right Figure 3 The described process is described in detail.

[0054] like Figure 3 As shown, the operating method 300 of the processor of this embodiment may include operations S310 to S320.

[0055] Operation S310: writing first configuration information into a first configuration register.

[0056] Operation S320: Control the programmable functional unit to be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information, so as to process the to-be-processed data acquired by the read-write unit to obtain processed data.

[0057] In at least one embodiment of the present disclosure, the operation method 300 can be executed by any module having a processing function outside the processor 200, and the module is in communication with the processor 200. The module can perform read and write operations on the first configuration register 201 from outside the processor 200, for example, by performing a write operation on the first configuration register, the first configuration information can be written into the first configuration register. The first configuration register can automatically send the saved first configuration information to the programmable function unit 203. For example, after the first configuration information is sent to the programmable function unit 203, the module can control the programmable function unit 203 to be programmed according to the first configuration information, and after the programming is completed, the configuration of the data processing function of the programmable function unit 203 can be completed.

[0058] After completing the configuration of the data processing function, the programmable function unit 203 can, for example, in response to receiving the data to be processed provided by the read / write unit 202, use the configured data processing function to process the data to be processed to obtain processed data.

[0059] In at least one embodiment of the present disclosure, in addition to the aforementioned read / write unit, the first configuration register, and the programmable function unit, the processor may further include an interface conversion unit. For example, the interface conversion unit may connect the read / write unit and the programmable function unit to perform data interface conversion between the read / write unit and the programmable function unit. By setting the interface conversion unit, the restrictions on the configuration of the programmable function unit such as data types may be reduced, which is conducive to realizing flexible configuration of the programmable function unit.

[0060] For example, the data interface conversion performed by the interface conversion unit may include at least one of the following: data format conversion, data bit width conversion, clock domain conversion, and the like.

[0061] For example, the interface conversion unit may include one or more queues. The queue may be, for example, a variable bit width first-in first-out queue, etc. For example, the bit width of the input data of the queue may be different from the bit width of the output data of the queue, the format of the input data of the queue may be different from the format of the output data of the queue, and / or the working clock (i.e., the clock domain) of the input data of the queue may be different from the working clock (i.e., the clock domain) of the output data of the queue.

[0062] For example, the number of queues included in the interface conversion unit can be determined according to the type of data and data volume actually required to be transmitted, and the present disclosure does not limit this.

[0063] Figure 4 The structure block diagram of the processor according to at least another embodiment of the present disclosure is schematically shown.

[0064] like Figure 4As shown, the processor 400 of this embodiment includes, in addition to a first configuration register 401 , a read / write unit 402 and a programmable function unit 403 , an interface conversion unit 404 and a clock management unit 405 .

[0065] The clock management unit 405 has a clock generation function, for example, and can generate at least two clock frequencies based on the source clock frequency. For example, the clock management unit 405 is responsible for taking the system clock as input to generate the clocks required by each functional unit in the processor.

[0066] For example, the at least two clock frequencies generated include a first clock frequency and a second clock frequency, the first clock frequency is provided to the programmable functional unit 403 and the interface conversion unit 404, and the second clock frequency is provided to other functional units in the processor 400 that are different from the programmable functional unit 403. For example, the second clock frequency can be provided to the read / write unit 402 and the interface conversion unit 404.

[0067] For example, the clock frequency of the system input clock is 1 GHz, and the clock management unit can generate two groups of homologous clocks. The clock frequency of one group of clocks is 1 GHz, which is provided to other functional units except the programmable functional unit 403. The clock frequency of the other group of clocks can be a divided frequency of 1 GHz, for example, it can be the same frequency (that is, the clock frequency is 0.5 GHz), 2 divided frequency (that is, the clock frequency is 0.5 GHz) or 4 divided frequency (that is, the clock frequency is 0.25 GHz), etc. The clock frequency of the other group of clocks is provided to the programmable functional unit 403 and the interface conversion unit 404. It can be understood that the above-mentioned clock frequencies are only used as examples to facilitate the understanding of the present disclosure, and the present disclosure does not limit this.

[0068] The interface conversion unit 404 may perform data interface conversion based on the provided first clock frequency and second clock frequency, for example.

[0069] For example, the input data of the interface conversion unit 404 may include data (such as data to be processed, etc.) read by the read / write unit 402 from outside the processor, the bit width of the input data may be N bits, and the clock frequency may be the clock frequency of the first clock. Accordingly, the output data of the interface conversion unit 404 may include data (such as data to be processed, etc.) that needs to be provided to the programmable function unit 403, then the bit width of the output data may be N bits, 2N bits, or 4N bits, and the corresponding clock frequency may be the clock frequency of the second clock, such as the same frequency, divided by two, or divided by four of the clock frequency of the first clock.

[0070] For example, the input data of the interface conversion unit 404 may also include processed data obtained by the programmable function unit 403 processing the data to be processed, the bit width of the input data may be N bit, 2N bit or 4N bit, and the corresponding clock frequency is the clock frequency of the second clock, for example, the same frequency, divided by two or divided by four of the clock frequency of the first clock. Accordingly, the output data of the interface conversion unit 404 may include the processed data provided to the read-write unit 402, the bit width of the output data may be N bit, and the clock frequency is the clock frequency of the first clock.

[0071] Figure 5 The structure block diagram of a processor according to at least another embodiment of the present disclosure is schematically shown.

[0072] In at least one embodiment of the present disclosure, a cache may be set in the processor, for example, for temporarily storing data copies so as to access the data more quickly. For example, the data copies temporarily stored in the cache may include one or more of data such as data to be processed, processed data, intermediate data generated during the process of processing the data to be processed by the programmable functional unit, and task commands obtained by the read / write unit from outside the processor.

[0073] Exemplarily, the programmable functional unit can access the cache through the aforementioned interface conversion unit to obtain cached data from the cache. For example, in addition to performing data interface conversion between the read / write unit and the programmable functional unit, the interface conversion unit can also perform data interface conversion between the programmable functional unit and the cache.

[0074] In at least one embodiment of the present disclosure, Figure 5 As shown, the processor 500 includes, in addition to a first configuration register 501 , a read / write unit 502 and a programmable function unit 503 , an interface conversion unit 504 , a clock management unit 505 and a cache 506 .

[0075] Compared to the aforementioned processor 400 , the clock management unit 505 is not only connected in communication with the read / write unit 502 , the interface conversion unit 504 , and the programmable function unit 503 , but is also connected in communication with the cache 506 to provide the generated second clock frequency to the cache 506 .

[0076] The cache 506 is in communication with the read / write unit 502. For example, the read / write unit 502 may write the task command and / or the data to be processed read from outside the processor into the cache 506 for the programmable function unit 503 to access and obtain.

[0077] The cache 506 is connected to the programmable function unit 503 via the interface conversion unit 504. The programmable function unit 503 can read the data stored in the cache 506, and can also write the intermediate data generated in the process of processing the data to be processed into the cache 506, so as to read the intermediate data from the cache 506 in the subsequent processing process. The programmable function unit 503 can also write the processed data obtained by processing the data to be processed into the cache 506 for reading by the read-write unit 502.

[0078] For example, the input data of the interface conversion unit 504 may also include data read from the cache 506, the bit width of the input data may be M bits, and the clock frequency may be the clock frequency of the first clock. Accordingly, the output data of the interface conversion unit 504 may include data that needs to be provided to the programmable function unit 503, and the bit width of the output data may be M bits, 2 M bits, or 4 M bits, and the corresponding clock frequency may be the clock frequency of the second clock, for example, the same frequency, divided by two, or divided by four of the clock frequency of the first clock.

[0079] For example, the input data of the interface conversion unit 504 may also include data (which may be processed data or intermediate data) provided by the programmable function unit 503 and need to be written into the cache 506. The bit width of the input data may be Mbit, 2Mbit or 4Mbit, and the corresponding clock frequency may be the clock frequency of the second clock, for example, the same frequency, divided by two or divided by four of the clock frequency of the first clock. Accordingly, the output data of the interface conversion unit 404 may include data written into the cache 506. The bit width of the output data may be Mbit, and the clock frequency may be the clock frequency of the first clock.

[0080] In at least one embodiment of the present disclosure, the cache space included in the cache can be divided into four parts, which are used to cache pre-read task commands (i.e., task commands read by the read-write unit from outside the processor), pre-read data to be processed, intermediate data generated in the process of processing the data to be processed by the programmable functional unit, and processed data obtained by processing the data to be processed. For example, compared with the intermediate data, the processed data does not need to be processed by the programmable functional unit and can be written outside the processor.

[0081] Figure 6 The structure block diagram of the interface conversion unit of at least one embodiment of the present disclosure is schematically shown.

[0082] like Figure 6 As shown, in at least one embodiment of the present disclosure, the interface conversion unit 604 may include a first group of queues 614 and a second group of queues 624 .

[0083] For example, the first group of queues 614 includes two queues. One side of the first queue of the two queues is connected to the read-write unit interface (for example, it can be a DMA interface) and the cache interface, for example, it can receive data with a bit width of 256 bits and a clock frequency of 1 GHz, and the data may include data to be processed. The other side of the first queue of the two queues is connected to the programmable function unit interface, for example, it can send data with a bit width of 256 bits, 512 bits or 1024 bits, and a clock frequency of 1 GHz with the same frequency, two-division or four-division, and the data may include data to be processed. One side of the second queue of the two queues is connected to the programmable function unit interface, for example, it can receive data with a bit width of 256 bits, 512 bits or 1024 bits, and a clock frequency of 1 GHz with the same frequency, two-division or four-division, and the data may include processed data. The other side of the second queue of the two queues is connected to the read-write unit interface (for example, it can be a DMA interface) and the cache interface, for example, it can send data with a bit width of 256 bits and a clock frequency of 1 GHz, and the data may include processed data.

[0084] For example, the second group of queues 624 includes two queues. One side of the first queue of the two queues is connected to the cache interface, for example, data with a bit width of 256 bits and a clock frequency of 1 GHz can be received, and the data may include intermediate data obtained by the programmable functional unit processing the data to be processed. The other side of the first queue of the two queues is connected to the programmable functional unit interface, for example, data with a bit width of 256 bits, 512 bits or 1024 bits and a clock frequency of 1 GHz with the same frequency, two-division or four-division can be sent, and the data may include intermediate data. One side of the second queue of the two queues is connected to the programmable functional unit interface, for example, data with a bit width of 256 bits, 512 bits or 1024 bits and a clock frequency of 1 GHz with the same frequency, two-division or four-division can be received, and the data may include intermediate data. The other side of the second queue of the two queues is connected to the cache interface, for example, data with a bit width of 256 bits and a clock frequency of 1 GHz can be sent, and the data may include intermediate data, so as to write the intermediate data into the cache.

[0085] It is understandable that if Figure 6 The interface conversion unit shown is only used as an example to facilitate understanding of the present disclosure. Based on actual needs, the interface conversion unit may include one or more groups of queues, and each group of queues may also include one or more queues. The present disclosure does not limit this.

[0086] The following will be combined Figure 7~Figure 8 The programmable functional unit included in the processor in at least one embodiment of the present disclosure is further expanded and described.

[0087] Figure 7 The structure block diagram of the programmable function unit according to at least one embodiment of the present disclosure is schematically shown.

[0088] In at least one embodiment of the present disclosure, the programmable function unit can be implemented based on a programmable routing array (PRA) and at least two programmable units, and the connection relationship between the at least two programmable units is configured through configuration information to achieve the purpose of configuring the data processing function of the programmable function unit. By setting at least two programmable units and a programmable routing array, the configuration of more complex data processing functions can be achieved.

[0089] In at least one embodiment, the programmable functional unit includes at least two programmable units, a programmable routing array, and a configuration unit. For example, Figure 7 The example in which the programmable functional unit 703 includes six instantiated programmable units 713 is used for description, but the present disclosure is not limited to this.

[0090] The six programmable units 713 are connected in communication via a programmable routing array 723. For example, the configuration unit 733 can be connected to the aforementioned first configuration register to receive configuration information sent by the first configuration register, and configure the programmable unit 713 and the programmable routing array 723 based on the configuration information. For example, by configuring the programmable routing array 723, the routing path of the signal can be configured to establish a connection between different programmable units so that data is transmitted between these programmable units. By configuring the programmable unit 713, the programmable unit 713 can be programmed to have a corresponding data processing function.

[0091] It is understandable that the six programmable units 713 have the same structure, but can have different data processing functions through configuration. According to actual needs, different configuration information can be provided from outside the processor to configure the programmable routing array 723 so that the programmable units involved in the routing path of the data can process the data according to the actual required data processing logic. In this way, when the processor including the programmable function unit 703 is applied in different scenarios, the data processing function of the programmable function unit can be adjusted by changing the configuration information, so that the processor can be applied to different scenarios.

[0092] For example, the programmable unit may include logic gate circuits such as an AND gate, a NOT gate, and a NAND gate, and the connection relationship between the gate circuits in the logic gate circuits may be adjusted through configuration.

[0093] In at least one embodiment of the present disclosure, the configuration unit 733 may be provided with a configuration management interface and a configuration data interface. The configuration data interface may, for example, receive first configuration information. The configuration management interface may, for example, be operated from outside the processor, and may also communicate with the aforementioned first configuration register via the configuration management interface to feed back the programming state of the programmable functional unit determined by the configuration unit 733 to the first configuration register.

[0094] The programmable routing array 723 may provide multiple interfaces, for example, at least one of a configuration register signal interface, a to-be-processed data receiving interface, a processed data sending interface, an intermediate data receiving interface, and an intermediate data sending interface. Some of these interfaces may be implemented by, for example, multiplexing the same physical interface, which is not limited in the present disclosure.

[0095] Exemplarily, the programmable routing array may include a programmable switching chip, whose message processing and forwarding logic is determined based on the first configuration information. Alternatively, the programmable routing array may be implemented by a storage unit and a configurable switch array, and the connection relationship of the interconnection lines connected to the configurable switch array is configured based on the first configuration information. The embodiment of the present disclosure does not limit the specific composition of the programmable routing array, as long as the programmable routing array can flexibly adjust the connection relationship between at least two programmable units based on the first configuration information, and can receive multiple input signals and output multiple output signals.

[0096] Figure 8 The structure block diagram of the programmable unit according to at least one embodiment of the present disclosure is schematically shown.

[0097] In at least one embodiment of the present disclosure, the programmable unit may be implemented, for example, by a lookup table (LUT). The lookup table is a storage structure that replaces runtime calculations with simple query operations, and may include, for example, a storage structure such as a static random access memory (SRAM). For example, the lookup table may store input combinations of a logic function and corresponding output results.

[0098] In at least one embodiment of the present disclosure, Figure 8 As shown, the programmable unit 813 may include a lookup table 8113 and a programmable combinatorial logic subunit 8114 .

[0099] For example, the lookup table 8113 may include, in addition to a memory, a circuit structure corresponding to the memory, and the circuit structure may be programmed to provide processing logic, such as receiving an input signal. For example, the lookup table may use the input signal as an address to access a corresponding location in the memory and read a pre-stored output value.

[0100] For example, the programmable combinational logic subunit 8123 may include a combinational logic circuit composed of logic gate circuits such as an AND gate and a NOT gate. The programmable combinational logic subcircuit can be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information using a lookup table. For example, the programmable combinational logic subunit 8123 can further process the output value read out of the lookup table 8113, and the data processing logic of the lookup table and the data processing logic of the programmable combinational logic subunit jointly implement the data processing function corresponding to the first configuration information. This embodiment can facilitate the implementation of complex data processing functions by setting a programmable combinational logic subunit in the programmable unit, and thus can further improve the flexible configuration of the data processing logic of the processor.

[0101] It is understandable that, according to the first configuration information provided based on actual needs, the data processing function can be implemented only via the lookup table. When a complex data processing function needs to be implemented, the data processing function can be implemented by combining the lookup table and the programmable combinational logic subunit by reconfiguring the first configuration information.

[0102] In at least one embodiment of the present disclosure, Figure 8 As shown, the programmable unit 813 may further include a storage subunit 8133. For example, the storage subunit may be implemented by a flip-flop or a latch, etc., and is configured to store data processed by the programmable combinational logic subunit 8123, such as caching or latching, etc., and the present disclosure does not limit this.

[0103] For example, the storage subunit can latch data at the edge of the clock to implement sequential logic by caching data processed by the programmable combinatorial logic subunit 8123. The sequential logic can be programmed based on the first configuration information, thereby affecting the logic of processing data.

[0104] Fig. 9 The structure block diagram of the processor according to at least another embodiment of the present disclosure is schematically shown.

[0105] In at least one embodiment of the present disclosure, the processor may further include a second configuration register. The second configuration register is configured to store general configuration information for the processor. The general configuration information may, for example, include a configuration for implementing the overall function of the processor. The configuration of the overall function may, for example, include at least one of queue management information configuration, low power mode configuration, security permission configuration, DMA parameter configuration, interface conversion unit parameter configuration, clock reset configuration management, etc.

[0106] For example, the second configuration register may be accessed by other units in the processor.

[0107] For example, in one embodiment, the general configuration information stored in the general configuration register is mainly used to configure the clock, reset, interrupt management, queue management, etc. of the processor.

[0108] In at least one embodiment of the present disclosure, the processor may further include a queue management unit. The queue management unit is configured to operate according to the general configuration information stored in the general configuration register, for example, it may control the read / write unit to read / write data, and control the programmable function unit to process data. The queue management unit may be communicatively connected with the read / write unit, the programmable function unit, and the interface conversion unit in the processor to control the operation of the units connected thereto.

[0109] For example, the queue management unit implements the management of one or more independent queues and is responsible for managing the full cycle management of the processor from receiving tasks, data reading, data processing, and data writing back.

[0110] For example, the queue management unit can support up to 64 queues working independently in parallel, and can configure the parameters of each queue and control the start and stop of the queue based on the common configuration information.

[0111] In at least one embodiment of the present disclosure, the workflow of the queue management unit may include first configuring a DMA controller to read a command according to a queue parameter. Then parsing the read command, controlling the DMA controller to read the data to be processed from the address space specified by the command. After reading the data to be processed, controlling the programmable function unit to process the data to obtain processed data. Then controlling the DMA controller to write the processed data back to the address space specified by the command.

[0112] like Fig. 9 As shown, the processor 900 of an embodiment of the present disclosure may include an interface conversion unit 904, a clock management unit 905, and a cache 906 in addition to a first configuration register 901, a read / write unit 902, and a programmable function unit 903. Furthermore, the processor 900 may also include a second configuration register 907 and a queue management unit 908.

[0113] The queue management unit 908 is at least connected to the read / write unit 902 and the interface conversion unit 904. The read / write unit 902 can be connected to the cache 906. The interface conversion unit 904 is connected to the read / write unit 902, the cache 906 and the programmable function unit 903 to perform data interface conversion between the read / write unit 902 and the programmable function unit 903, and between the cache 906 and the programmable function unit 903. Under the control of the queue management unit 908, the read / write unit 902 can read or write back data according to the specified address and data length. The read instruction can be sent to the queue management unit 908, or the instruction can be read in advance and written to the cache 906. The read data to be processed can be sent to the interface conversion unit 902 to be sent to the programmable function unit 903 after data interface conversion. The data to be processed can also be read in advance and written to the cache.

[0114] The first configuration register 901 is connected to the programmable function unit 903 to provide the first configuration information and the second configuration information to the programmable function unit 903. The clock management unit 905 can be connected to each unit in the processor 900 to provide a working clock to each unit.

[0115] For example, the first configuration register 901 may include one or more groups of configuration registers reserved for the programmable function unit 903. Taking the first configuration register including 32 groups of 32-bit registers as an example, 30 groups of registers are readable and writable, and a total of 32*30=960 signal lines can be connected to the programmable function unit 903. The 30 groups of registers can be used to store the second configuration information. Among the remaining two groups of registers, one group is used to implement the configuration function of the programmable function unit 903, for example, it can be used to store the first configuration information. The other group is used to store a determined programming state.

[0116] In at least one embodiment of the present disclosure, Fig. 9 As shown, the processor 900 may also be provided with a communication interface. The communication interface may serve as an external bus interface of the processor. The communication interface may be communicatively connected to the first configuration register and the read / write unit, and may be communicatively connected to the outside of the processor.

[0117] For example, the communication interface may include a master interface and a slave interface. The master interface and the slave interface may, for example, be an interface based on the Advanced Extensible Interface (AXI) protocol, etc. The bit widths of the master interface and the slave interface may be selected according to actual needs, and the present disclosure does not limit this. For example, the bit width of the slave interface may be 32 bits, and the bit width of the master interface may be 256 bits.

[0118] For example, the slave interface is connected to the first configuration register 901 and the second configuration register 907 for communication, so as to access the first configuration register 901 and the second configuration register 907 from outside the processor, so as to implement parameter configuration and status monitoring of the processor (e.g., monitoring the status of parameter delivery, monitoring the operating status of the processor), etc. For example, the configuration information stored in the first configuration register 901 can be obtained through the slave interface.

[0119] For example, the main interface is connected to the read / write unit 902 for communication, and the read / write unit 902 reads task commands and data to be processed from outside the processor via the main interface, and writes the processed data to outside the processor via the main interface.

[0120] In at least one embodiment of the present disclosure, the clock management unit 905 can also be used to generate a reset signal. For example, the clock management unit 905 is responsible for taking the system clock and reset as input, and generating the clock and reset signals required by each unit in the processor based on the general configuration information stored in the second configuration register 907. For example, the reset signal is ground-valid, and is obtained by performing an "AND" operation on the system reset and the output signal of the reset register in the second configuration register 907.

[0121] In at least one embodiment of the present disclosure, the processor may further include a customized function unit, through which a customized data processing function may be implemented, in order to improve the performance and energy efficiency of the processor in a specific scenario. For example, the customized function unit may be used to implement encryption and decryption algorithms, etc. For example, the data processing function that the customized function unit can implement may be pre-set, and the present disclosure does not limit this.

[0122] In at least one embodiment, the read / write unit, the queue management unit, the second configuration register, etc. may adopt a standard design scheme of a coprocessor general module.

[0123] At least one embodiment of the present disclosure can effectively improve the resource utilization of the processor and reduce power consumption by integrating the programmable functional unit into the processor. At least one embodiment of the present disclosure can solve the timing problem of programmable design by integrating the interface conversion unit, clock management unit, etc. into the processor, which is beneficial to the programmable implementation of the processor.

[0124] In at least one embodiment of the present disclosure, according to actual needs, the read / write unit and the queue management unit may also be programmable to further enhance the flexibility of the processor.

[0125] In at least one embodiment of the present disclosure, the programmable functional unit interface may adopt an asynchronous timing design, for example, the programmable functional unit and its upstream and downstream functional units operate under multiple independent asynchronous clocks.

[0126] Based on the processor provided by at least one embodiment of the present disclosure, at least one embodiment of the present disclosure further provides a processing system. Fig.10 The processing system is described in detail.

[0127] Fig.10 The structure block diagram of the processing system according to at least one embodiment of the present disclosure is schematically shown.

[0128] like Fig.10 As shown, the processing system 1000 of this embodiment includes a first processor 1001 and a second processor 1002 .

[0129] The first processor 1001 may include, for example, a CPU, etc. The second processor 1002 may include a processor provided by at least one embodiment of the present disclosure, such as a graphics processor, an artificial intelligence chip, etc., for example, working as a coprocessor. The first processor 1001 may be communicatively connected with the second processor 1002.

[0130] For example, the second processor 1002 can be used as a coprocessor to process a specific task relative to the first processor. The specific task may include, for example, an encryption and decryption task and / or a data reading and writing task. For example, the second processor 1002 can be called by the first processor 1001 to perform data processing and complete the specific task. In this way, the load of the first processor can be reduced, so that the processing system has higher performance and energy consumption ratio.

[0131] At least one embodiment of the present disclosure further provides an electronic device. Fig.11 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

[0132] For example, Fig.11 As shown, the electronic device 1100 includes a processor 1110 and a memory 1120. The memory 1120 is used to store non-temporary computer-readable instructions (e.g., one or more computer program modules). The processor 1110 is used to run the computer program instructions, and the computer program instructions are executed by the processor 1110 to perform the operation method of the processor provided in any embodiment of the present disclosure. The memory 1120 and the processor 1110 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0133] The processor 1110 may be a device with data processing capability and / or program execution capability, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU), and may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. For example, the central processing unit (CPU) may be an X86 or ARM architecture, etc. The processor 1110 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 1100 to perform desired functions.

[0134] For example, the memory 1120 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 1110 may run one or more computer program modules to implement various functions of the electronic device 1100. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0135] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 1100 can refer to the above description of the information processing method, which will not be repeated here.

[0136] At least some embodiments of the present disclosure also provide a non-transitory storage medium. Fig.12 A schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig.12 As shown, the storage medium 1200 non-temporarily stores computer-readable instructions 1201. When the non-temporary computer-readable instructions 1201 are executed by a computer (including a processor), the operating method of the processor provided by any embodiment of the present disclosure can be executed.

[0137] For example, one or more computer instructions may be stored on the storage medium 1200. Some of the computer instructions stored on the storage medium 1200 may be, for example, instructions for implementing one or more steps in the above-mentioned information processing method.

[0138] For example, the storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the storage medium 1200 may include the memory 1120 in the aforementioned electronic device 1100.

[0139] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding description of the information processing method in the above embodiments, which will not be repeated here.

[0140] There are a few points to note about this disclosure:

[0141] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0142] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.

[0143] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A processor, comprising: a read / write unit configured to read data to be processed from outside the processor and write processed data to outside the processor; A first configuration register is configured to store first configuration information; as well as The programmable functional unit is configured to be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information, so as to process the data to be processed to obtain the processed data.

2. The processor according to claim 1, wherein: The first configuration register is further configured to be readable and writable from outside the processor to modify the first configuration information, so as to correspondingly modify the data processing function of the programmable functional unit.

3. The processor of claim 1 , further comprising: The interface conversion unit is configured to connect the read-write unit and the programmable function unit to perform data interface conversion between the read-write unit and the programmable function unit.

4. The processor of claim 3, further comprising: A cache, configured to cache the data to be processed and the processed data; Wherein, the interface conversion unit is further configured to: perform data interface conversion between the programmable function unit and the cache.

5. The processor according to claim 4, wherein: The read / write unit is further configured to obtain a task command from outside the processor, and the cache is further configured to cache the task command.

6. The processor according to claim 3 or 4, wherein: The data interface conversion includes at least one of the following: data format conversion, data bit width conversion and clock domain conversion.

7. The processor of claim 6, further comprising: a clock management unit configured to generate at least two clock frequencies based on a source clock frequency; The at least two clock frequencies include a first clock frequency and a second clock frequency. The first clock frequency is provided to the programmable functional unit and the interface conversion unit, and the second clock frequency is provided to other functional units in the processor other than the programmable functional unit.

8. The processor of claim 1, wherein: The programmable functional unit comprises: at least two programmable units; A programmable routing array, wherein the at least two programmable units are communicatively connected via the programmable routing array; and The configuration unit is configured to configure the at least two programmable units and the programmable routing array based on the first configuration information to implement a data processing function corresponding to the first configuration information.

9. The processor of claim 8, wherein: The programmable unit comprises: A lookup table is configured to store input combinations of a logic function and corresponding output results, The programmable combinatorial logic subunit is configured to be programmed according to the first configuration information to use the lookup table to implement a data processing function corresponding to the first configuration information.

10. The processor of claim 9, wherein: The programmable unit also includes: The storage subunit is configured to latch the data processed by the programmable combinatorial logic subunit.

11. A processor according to claim 1 or 2, wherein: The first configuration register is further configured to store second configuration information; The programmable functional unit is further configured to configure itself according to the second configuration information.

12. The processor according to claim 1 or 2, further comprising a communication interface; wherein The communication interface is configured to be communicatively connected to the first configuration register and the read / write unit respectively, and is configured to be communicatively connected to the outside of the processor.

13. A processor according to claim 1 or 2, wherein: The programmable function unit is further configured to: determine a programming state programmed according to the first configuration information, and feed back the programming state to the first configuration register; The first configuration register is further configured to save the programming state so as to read the programming state from outside the processor.

14. The processor according to claim 1 or 2, further comprising: a second configuration register configured to store general configuration information for the processor; as well as The queue management unit is configured to work according to the general configuration information, and is configured to control the read-write unit to read and write data, and control the programmable function unit to process data.

15. The processor of claim 6, wherein: The interface conversion unit comprises: A queue, wherein the bit width of input data of the queue is a first bit width, and the working clock is a first clock frequency, and the bit width of output data of the queue is a second bit width, and the working clock is a second clock frequency, wherein the first bit width is different from the second bit width, and the first clock frequency is different from the second clock frequency.

16. The processor of claim 1, wherein: The read-write unit includes a direct memory access controller.

17. The processor according to claim 1, further comprising a custom function unit, wherein: The customized function unit is configured to implement customized data processing functions.

18. A processing system comprising: a first processor; as well as The second processor comprises the processor according to any one of claims 1 to 17, The first processor is communicatively connected to the second processor, and the first processor is configured to call the second processor to perform data processing.

19. A method for operating the processor of claim 1, comprising: Writing the first configuration information into the first configuration register; The programmable function unit is controlled to be programmed according to the first configuration information to implement a data processing function corresponding to the first configuration information, so as to process the data to be processed acquired by the read-write unit to obtain the processed data.

20. An electronic device, comprising: processor; as well as a memory including one or more computer program instructions; Wherein, when the one or more computer program instructions are executed by the processor, the method of claim 19 is implemented.

21. A computer-readable storage medium that non-transitorily stores computer-readable instructions, wherein: When the computer readable instructions are executed by a processor, the method of claim 19 is implemented.

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