Processor synchronization balancing method, system, device, equipment, medium and product

Abstract

The invention provides a processor synchronization balancing method, system and device, equipment, a medium and a product, and the method comprises the steps: distributing a first command in a first submission queue to a first processor; determining an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the core number of the first processor; on the basis of the number of the first commands processed by the first processor, progressively decreasing and updating the initial credit value to obtain an updated credit value; and when the updated credit value reaches a first preset value, carrying out synchronous balancing operation on the updated credit value of the first processor. According to the method disclosed by the invention, when the updated credit value reaches the first preset value, the updated credit value of the first processor is subjected to the synchronous balancing operation, so that the credit value in processing and the computing power transfer of the processors can be adaptively adjusted, the command processing among different processors is balanced, and the service quality of the processors is ensured.

Description

Technical Field

[0001] The present disclosure relates to the computer field, and in particular to a processor synchronization balancing method, system, device, equipment, medium and product. Background Art

[0002] With the rapid development of information technology, the central processing unit (CPU) has entered the multi-core era. Each core can process the same or different data processing tasks and coordinate with each other through interconnected information networks to achieve rapid data processing.

[0003] However, since the tasks assigned and run on each core are not completely symmetrical, different CPUs on the SSD may experience desynchronization and imbalance in the input / output (IO) commands during actual operation, which in turn causes large jitter in the IO commands on the server side, affecting the quality of service (QoS) of the IO commands. Summary of the invention

[0004] The present disclosure provides a processor synchronization balancing method, system, device, equipment, medium and product, which can adaptively adjust the credit value in processing and the transfer of processor computing power, so as to balance the command processing between different processors and ensure the service quality of the processor.

[0005] A first aspect embodiment of the present disclosure proposes a processor synchronization and balancing method, including: distributing a first command in a first submission queue to a first processor; determining an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; based on the number of completed processing of the first command by the first processor, decreasingly updating the initial credit value to obtain an updated credit value; when the updated credit value reaches a first preset value, performing a synchronization and balancing operation on the updated credit value of the first processor.

[0006] In some embodiments of the present disclosure, distributing the first command in the first submission queue to the first processor includes: distributing the first command to the first processor in sequence and evenly based on a polling algorithm.

[0007] In some embodiments of the present disclosure, determining the initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor includes: determining the initial credit value based on the ratio between the first queue depth of the first completion queue and the number of cores of the first processor.

[0008] In some embodiments of the present disclosure, when the update credit value reaches a first preset value, performing a synchronous balancing operation on the update credit value of the first processor includes: determining the remaining credit value of the second completion queue based on the head pointer value of the second completion queue, the tail pointer value of the second completion queue, and the second queue depth of the second completion queue, the second completion queue being a queue in the first completion queue whose update credit value reaches the first preset value; determining the total number of pending processes of the first processor based on the expected number of sends of the first processor and the completed number of sends of the first processor, wherein the expected number of sends is the number of commands that the first processor expects to send to the second completion queue, and the completed number of sends is the number of commands that the first processor has sent to the second completion queue; determining whether there is an available credit value in the second completion queue based on the remaining credit value and the total number of pending processes; and performing a synchronous balancing operation on the update credit value of the first processor based on whether there is an available credit value in the second completion queue.

[0009] In some embodiments of the present disclosure, determining the remaining credit value of the second completion queue based on the first pointer value of the second completion queue, the tail pointer value of the second completion queue, and the second queue depth of the second completion queue includes: when the first pointer value is greater than the tail pointer value, increasing the second queue depth to determine the remaining credit value; when the first pointer value is less than the tail pointer value, determining the remaining credit value based on the first pointer value and the tail pointer value; when the first pointer value is equal to the tail pointer value, determining the remaining credit value based on the first pointer value, the tail pointer value, and the second queue depth.

[0010] In some embodiments of the present disclosure, determining the total number of pending processes of the first processor based on the expected number of sends of the first processor and the number of completed sends of the first processor includes: determining the total number of pending processes based on the difference between the expected number of sends of the first processor and the number of completed sends of the first processor.

[0011] In some embodiments of the present disclosure, based on the remaining credit value and the total number to be processed, determining whether there is available credit value in the second completion queue includes: when the remaining credit value is greater than the total number to be processed, determining that there is available credit value in the second completion queue; when the remaining credit value is less than or equal to the total number to be processed, determining that there is no available credit value in the second completion queue.

[0012] In some embodiments of the present disclosure, based on whether there is an available credit value in the second completion queue, a synchronization and balancing operation is performed on the updated credit value of the first processor, including: when there is an available credit value, based on the remaining credit value, the total number of pending processes and the number of cores of the first processor, determining the reallocated credit value to distribute the reallocated credit value to the first processor; when there is no available credit value, the second processor stops sending commands to the second completion queue, and the second processor updates the first processor whose credit value reaches a first preset value.

[0013] In some embodiments of the present disclosure, determining the reallocated credit value based on the remaining credit value, the total number to be processed, and the number of cores of the first processor includes: determining the difference between the remaining credit value and the total number to be processed; and determining the ratio between the difference and the number of cores of the first processor as the reallocated credit value.

[0014] The second aspect of the present disclosure proposes a processor synchronization and balancing system, including: a first device, a first processor and a solid-state hard disk, the solid-state hard disk at least includes: a submission command arbitration module and a management module, and the first processor at least includes: a command sending synchronization and balancing module; wherein the first device is used to send a first submission queue to the submission command arbitration module; the submission command arbitration module is used to distribute the first command in the first submission queue to the first processor based on a polling algorithm; the management module is used to determine the initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor; and is used to decrementally update the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; the command sending synchronization and balancing module is used to perform synchronization and balancing operations on the updated credit value of the first processor when the updated credit value reaches a first preset value.

[0015] In some embodiments of the present disclosure, the first device is further configured to store the first command in a submission queue having free slots to generate a first submission queue.

[0016] The third aspect embodiment of the present disclosure proposes a processor synchronization and balancing device, including: a distribution unit, used to distribute a first command in a first submission queue to a first processor; a determination unit, used to determine an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; an update unit, used to decrementally update the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; and a balancing unit, used to perform a synchronization and balancing operation on the updated credit value of the first processor when the updated credit value reaches a first preset value.

[0017] The fourth aspect embodiment of the present disclosure proposes an electronic device, comprising: a processor and a memory for storing a computer program that can be run on the processor, wherein the processor, when used to run the computer program, executes the method described in the first aspect embodiment of the present disclosure.

[0018] The fifth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0019] The sixth aspect embodiment of the present disclosure proposes a computer program product, including a computer program, which implements the method described in the first aspect embodiment of the present disclosure when executed by a processor.

[0020] In summary, a processor synchronization and balancing method provided by the present disclosure includes: distributing the first command in the first submission queue to the first processor; determining the initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor; decreasingly updating the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; when the updated credit value reaches a first preset value, performing a synchronization and balancing operation on the updated credit value of the first processor. The method disclosed in the present disclosure can adaptively adjust the credit value in the processing and the transfer of processor computing power by performing a synchronization and balancing operation on the updated credit value of the first processor when the updated credit value reaches the first preset value, so as to balance the command processing between different processors and ensure the service quality of the processor.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. Figure 1 A flowchart of a processor synchronization balancing method provided by an embodiment of the present disclosure; Figure 2 A flowchart of another processor synchronization balancing method provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of a processor synchronization and balancing system provided by an embodiment of the present disclosure; Figure 4 A topological diagram of a processor synchronization and balancing system proposed in the present disclosure; Figure 5 An example flowchart of a processor synchronization balancing method provided by an embodiment of the present disclosure; Figure 6 An example flowchart of a processor synchronization balancing method provided by an embodiment of the present disclosure; Figure 7 An example flowchart of a processor synchronization balancing method provided by an embodiment of the present disclosure; Figure 8 A schematic diagram of the structure of a processor synchronization and balancing device provided by an embodiment of the present disclosure; Fig. 9A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0024] As the transmission speed of the high-speed serial computer expansion bus (Peripheral Component Interconnect express, PCIe) is getting faster and faster, in order to improve the concurrent processing capability of the host server, the CPU has long entered the multi-core era. When applying the non-volatile memory host controller interface (Non-VolatileMemory Express, NVMe) technology, a multi-queue method of high-concurrency read and write access to NVMe SSD is adopted, that is, the number of multiple queues created is determined by the minimum value of the number of cores of the server CPU and the number of queues supported by the NVMe solid-state drive (Solid State Disk or Solid State Drive, SSD). In this way, the multi-core CPU architecture will also be used on the NVMe SSD side to increase the concurrent processing capability. The task allocation on these CPUs directly affects the processing efficiency of NVMe commands from queues corresponding to different CPUs on the host side.

[0025] In the related art, different instances are processed by different CPU cores. For example, the IO command main task IO_Dispatcher_Task will be created on all cores to receive IO commands and perform event scheduling processing for various subtasks; some cores will create FTL Manager_Task to complete the mapping management of LBA logical addresses to PBA physical addresses and cache Buffer management tasks; some cores will be responsible for the garbage collection GC and wear leveling WearLeveling of flash memory blocks; some cores will run the front-end management Front_End_Task for the execution of management commands and the access processing of host devices; some cores will run the log management MemLog_Task to complete the storage and output of system logs, and some cores will run the out-of-band management NVMe_MI_Task to be responsible for the interactive management with the server's BMC. Each core has its own responsibilities and coordinates with each other through the interconnected information network. This multi-core architecture better guarantees the concurrent capability of IO data processing and the normal management and operation of the equipment.

[0026] However, since the tasks assigned and run on each core are not completely symmetrical, different CPUs on the SSD will experience desynchronization and imbalance in the IO commands during actual operation, which in turn causes large jitters in the IO commands on the server side, affecting the QoS of the IO commands (QoS refers to the ability to complete all requests with stable and consistent performance within a specified time. The more common SSD QoS quantitative indicators give the maximum latency with a reliability of 99% or 99.99%), resulting in consistency issues, which in turn affects the high service quality of the disk. In order to ensure QoS, a certain scheduling mechanism is required for the multi-core CPU on the SSD to process IO commands. The engineering applications that have been solved so far are mainly to prioritize different types of requests and distribute commands on the back-end Flash channel to reduce latency jitter. However, other factors that affect QoS consistency include Regarding the consistency of the IO commands from the disk by the CPU on the host side, if the consistency of the command completion message from the NVMe disk is good, the stability of the service provided is good. Therefore, the consistency of the IO command completion messages distributed on different cores on the NVMe SSD determines the consistency of the IO commands by the upper host. However, the different tasks and loads on different CPUs on the NVMe SSD will cause the IO commands on different CPUs to return at different speeds and have poor consistency.

[0027] In order to solve the technical problems existing in the related art, an embodiment of the present disclosure provides a processor synchronization balancing method.

[0028] The embodiments of the present disclosure will be described in detail below.

[0029] like Figure 1 As shown, an embodiment of the present disclosure provides a processor synchronization balancing method, comprising the following steps: Step 101: distribute a first command in a first submission queue to a first processor.

[0030] In some embodiments, the first submission queue is a submission queue sent by a first device to a device executing the method, wherein the first device is, for example, a host, a server, or other device, which is not limited in the present disclosure.

[0031] In some embodiments, the first command is any command contained in the first submission queue.

[0032] For example, the host puts the first command into the corresponding submission queue free entry through multiple submission queues SQ0, SQ1, SQ2...SQN to generate a first submission queue, wherein the first submission queue is a circular queue maintained by a head pointer Head and a tail pointer Tail.

[0033] In some embodiments, the first command may be distributed to the first processor in an evenly distributed manner; or the first command may be distributed to the first processor according to the capability of the first processor, which is not limited in the present disclosure.

[0034] Step 102 : determining an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor.

[0035] In some embodiments, the first completion queue is used to store instructions generated after the first processor completes processing the first command.

[0036] In some embodiments, the initial credit value of the first processor can be determined based on the first queue depth of the first completion queue and the number of cores of the first processor; for example, the ratio between the first queue depth of the first completion queue and the number of cores of the first processor is determined as the initial credit value.

[0037] It should be understood that each initial credit value corresponds to a first completion queue. In other words, a first submission queue may contain one or more initial credit values.

[0038] For example, based on the depth of the first completion queue #1 and the number of cores of the first processor, determine that the initial credit value allocated by the first completion queue #1 to the first processor #1 is 6; based on the depth of the first completion queue #2 and the number of cores of the first processor, determine that the initial credit value allocated by the first completion queue #2 to the first processor #1 is 10.

[0039] Step 103: based on the number of first commands processed by the first processor, the initial credit value is updated decrementally to obtain an updated credit value.

[0040] In some embodiments, the initial credit value is updated decrementally based on the number of times the first processor completes processing of the first command. For example, each time the first processor completes processing of the first command, the initial credit value corresponding to the first command is updated decrementally (such as subtracting 1 from the initial credit value corresponding to the first command).

[0041] Step 104: When the update credit value reaches a first preset value, a synchronization balancing operation is performed on the update credit value of the first processor.

[0042] In some embodiments, when the update credit value reaches a first preset value, it indicates that the first processor cannot continue to send commands to the first completion queue. At this time, in order to ensure synchronization and balance between the first processors, the update credit value of the first processor is synchronized and balanced.

[0043] In some embodiments, the synchronous balancing operation may include: when there is an available credit value, determining the reallocated credit value based on the remaining credit value, the total number to be processed and the number of cores of the first processor, so as to distribute the reallocated credit value to the first processor; when there is no available credit value, the second processor stops sending commands to the second completion queue, and the second processor updates the first processor whose credit value reaches a first preset value.

[0044] In summary, the processor synchronization and balancing method proposed in the present disclosure includes: distributing the first command in the first submission queue to the first processor; determining the initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor; decreasingly updating the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; when the updated credit value reaches a first preset value, performing a synchronization and balancing operation on the updated credit value of the first processor. The method disclosed in the present disclosure can adaptively adjust the credit value in the processing and the transfer of processor computing power by performing a synchronization and balancing operation on the updated credit value of the first processor when the updated credit value reaches the first preset value, so as to balance the command processing between different processors and ensure the service quality of the processor.

[0045] Figure 2 A flowchart of a processor synchronization balancing method proposed in the present disclosure is further shown. Figure 1 The illustrated embodiment further explains, Figure 2 The following steps may be included.

[0046] Step 201 : Distribute the first command to the first processor in sequence and evenly based on the polling algorithm.

[0047] In some implementations, the polling algorithm is, for example, a Round-Robin algorithm, but is not limited thereto and may also be other algorithms that can achieve average distribution.

[0048] Specifically, different first commands in the same first submission queue are evenly distributed to different first processors in turn and in a circular manner.

[0049] Specifically, different first commands in different first submission queues are evenly distributed to different first processors in turn and in a cycle.

[0050] Step 202 : determining an initial credit value based on a ratio between a first queue depth of a first completion queue and the number of cores of a first processor.

[0051] In some embodiments, when the first completion queue is created and initialized, the initial credit value allocated by the first completion queue to each first processor can be determined based on the first queue depth qSize of each first completion queue divided by the number of cores (number) of the first processor.

[0052] Optionally, the initial credit value may also be recorded in a preset memory variable, for example, in a variable remainingCplQEntries[MAX_CORES][MAX_CPL_QUEUES], where MAX_CORES is the number of cores of the first processor, and [MAX_CPL_QUEUES] is the total number of the first completion queue.

[0053] Step 203, based on the number of first commands processed by the first processor, the initial credit value is updated decrementally to obtain an updated credit value; In some embodiments, whenever the first processor completes processing of a first command (i.e., the first processor generates an IO command message according to the first command and sends the IO command message to a first completion queue), the initial credit value corresponding to the first completion queue in the first processor is decremented and updated.

[0054] For example, every time the first processor #1 sends an IO command message to the first completion queue #1, the initial credit value corresponding to the first completion queue #1 in the first process is reduced by 1, and the credit value after reduction by 1 is determined as the updated credit value.

[0055] In other words, when a first processor processes the first command internally and sends it to the corresponding first completion queue, the number of successful completion commands sent by the first processor is incremented, where the increment count variable can be set to sendCplqMsgCnt[MAX_CORES][MAX_CPL_QUEUES]++.

[0056] Step 204 : When the updated credit value reaches the first preset value, determine the remaining credit value of the second completion queue based on the head pointer value of the second completion queue, the tail pointer value of the second completion queue, and the second queue depth of the second completion queue.

[0057] In some embodiments, the first preset value may be 0, but is not limited thereto and may also be other preset values.

[0058] In some embodiments, the second completion queue is a queue in the first completion queue whose updated credit value reaches a first preset value.

[0059] In some embodiments, when the head pointer value is greater than the tail pointer value, the second queue depth is increased to determine the remaining credit value; Exemplarily, when Head = Tail, the total number of available credits (i.e., the remaining credit value) is the completion queue depth qSize, that is, cq_j_remainCredits = qSize, where cq_j_remainCredits is the remaining credit value.

[0060] In some embodiments, when the head pointer value is less than the tail pointer value, the remaining credit value is determined based on the head pointer value and the tail pointer value; Exemplarily, when Head > Tail, the total number of available credits cq_j_remainCredits is cq_head – cq_tail – 1, that is, cq_j_remainCredits = cq_head – cq_tail – 1, where cq_head is the value of the head pointer Head (i.e., the head pointer value), and cq_tail is the value of the tail pointer Tail (i.e., the tail pointer value).

[0061] In some embodiments, when the head pointer value is equal to the tail pointer value, the remaining credit value is determined based on the head pointer value, the tail pointer value, and the second queue depth; Exemplarily, when Head < Tail, the total number of available credits cq_j_remainCredits is qSize - (cq_tail - cq_head) – 1, that is, cq_j_remainCredits = qSize - (cq_tail – cq_head) - 1.

[0062] Step 205, determine the total number of tasks to be processed by the first processor based on the expected transmission count of the first processor and the completed transmission count of the first processor.

[0063] In some embodiments, the total number of tasks to be processed can be determined based on the difference between the expected transmission count and the completed transmission count.

[0064] In some embodiments, the expected transmission count is the number of commands that the first processor expects to send to the second completion queue, and the completed transmission count is the number of commands that the first processor has already sent to the second completion queue.

[0065] In some embodiments, the total number of tasks to be processed can be determined by the following formula:

[0066] Among them, cpu_m represents the first processor identified as m, cq_j represents the cq completion queue identified as j, otherCpusOutstandingIOSum represents the total number of pending transactions, gSqeRecv[cpu_m][cq_j] represents the expected number of sends, and sendCplgMsgCnt[cpu_m][cq_j] represents the number of completed sends.

[0067] It should be understood that when summing the difference counts of all first processors, the difference of the i-th first processor (ie, the first processor whose updated credit value reaches the first preset value) is not included, that is, m !=i.

[0068] It should be understood that, under normal circumstances, gSqeRecv[cpu_m][cq_j]≥sendCplgMsgCnt[cpu_m][cq_j], that is, the above difference will not be negative.

[0069] Step 206: Determine whether there is any available credit in the second completion queue based on the remaining credit and the total number to be processed.

[0070] In some embodiments, the remaining credit value may be compared with the total number to be processed to determine whether there is an available credit value in the second completion queue.

[0071] Specifically, when the remaining credit value is greater than the total number to be processed, it is determined that there is available credit value in the second completion queue; when the remaining credit value is less than or equal to the total number to be processed, it is determined that there is no available credit value in the second completion queue.

[0072] In some embodiments, if the remaining credit value is greater than the total number to be processed, that is, cq_j_remainCredits>otherCpusOutstandingIOSum, it means that the second completion queue has available credit value, that is, the i-th first processor (that is, the first processor whose updated credit value reaches the first preset value) can continue to send the IO command completion message of the second completion queue.

[0073] In some embodiments, if the remaining credit value is less than or equal to the total number to be processed, that is, cq_j_remainCredits<otherCpusOutstandingIOSum, it means that this second completion queue has no available credit value, that is, the second processor processes the IO commands of the second completion queue faster than the other first processor processes the IO commands of the second completion queue.

[0074] Step 207: Based on whether there are available credits in the second completion queue, perform a synchronization balancing operation on the updated credits of the first processor.

[0075] In some embodiments, when there are available credits, a reallocated credit is determined based on the remaining credits, the total number to be processed, and the number of cores of the first processor to distribute the reallocated credits to the first processor.

[0076] Specifically, the difference between the remaining credit value and the total number to be processed may be determined; and then the ratio between the difference and the number of cores of the first processor may be determined as the reallocated credit value.

[0077] For example, the update method of the reallocated credit value remainingCplQEntries[cpu_i][cplq_j] can be as follows: remainingCplQEntries[cpu_i][cplq_j]=(cq_j_remainCredits-otherCpusOutstandingIOSum) / MAX_CORES, Among them, cq_j_remainCredits represents the number of available credits, otherCpusOutstandingIOSum represents the total number to be processed, and MAX_CORES represents the number of cores of the first processor.

[0078] In some embodiments, when there is no available credit value, the second processor stops sending commands to the second completion queue, and the second processor is the first processor that updates the credit value to reach the first preset value.

[0079] In other words, when the second completion queue has no available credit value, it means that the second processor processes the IO commands of the second completion queue faster than other first processors process the IO commands of the second completion queue. In order to ensure the synchronization between the first processor and the second processor and the balance of IO load, it is necessary to stop the second processor from sending IO completion commands to the second completion queue, transfer the computing power of the second processor, and perform corresponding processing of IO commands and other tasks on other queues.

[0080] In summary, according to the processor synchronization and balancing method proposed in the present disclosure, the method includes: based on the polling algorithm, the first command is evenly distributed to the first processor in sequence; based on the ratio between the first queue depth of the first completion queue and the number of cores of the first processor, the initial credit value is determined; based on the number of first processors completing the processing of the first command, the initial credit value is decremented and updated to obtain an updated credit value; when the updated credit value reaches the first preset value, the remaining credit value of the second completion queue is determined based on the head pointer value of the second completion queue, the tail pointer value of the second completion queue and the second queue depth of the second completion queue; based on the remaining credit value and the total number to be processed, it is determined whether there is an available credit value in the second completion queue; based on whether there is an available credit value in the second completion queue, the updated credit value of the first processor is synchronized and balanced. In the present disclosure, by determining the remaining credit value and the total number to be processed, it is determined whether there is an available credit value in the second completion queue, so as to determine whether to perform credit value redistribution processing on the first processor or to perform computing power transfer processing on the first processor according to whether there is an available credit value, so as to balance the command processing between different processors and ensure the service quality of the processor.

[0081] Figure 3 Further showing a system block diagram of a processor synchronization and balancing system proposed in the present disclosure, which can be applied to Figure 1 or Figure 2 The method shown.

[0082] In some embodiments, the processor synchronization and balancing system 300 may include a first device 301, a first processor 302 and a solid state drive 303, the solid state drive 303 at least includes: a submission command arbitration module 3031 and a management module 3032, and the first processor 302 at least includes: a command sending synchronization and balancing module 3021.

[0083] In some embodiments, the first processor 302 and the solid state drive 303 are physically connected (ie, directly connected via an interface, a data cable, etc.).

[0084] In some embodiments, the first device 301 is communicatively connected to the first processor 302 , and the first processor 302 is communicatively connected to the solid state drive 303 .

[0085] In some embodiments, the first device 301 is configured to send a first submission queue to a submission command arbitration module; In some embodiments, the submission command arbitration module 3031 is used to distribute the first command in the first submission queue to the first processor based on a polling algorithm; In some embodiments, the management module 3032 is used to determine an initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor; and to decrementally update the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; In some embodiments, the command sending synchronization and balancing module 3021 is used to perform a synchronization and balancing operation on the update credit value of the first processor when the update credit value reaches a first preset value.

[0086] Optionally, in some embodiments, the first device 301 is further used to store the first command in a submission queue having free slots to generate a first submission queue.

[0087] The following is an exemplary description of the present disclosure: Figure 4 A topological diagram of a processor synchronization and balancing system proposed in the present disclosure includes the following contents: Step 1: The host puts the command into the corresponding free entry of the submission queue through multiple submission queues SQ0, SQ1, SQ2...SQN. The submission queue is a circular queue maintained by the head pointer Head and the tail pointer Tail. The SSD sends the internal completion IO command message to the completion queue through the corresponding completion queue CQ0, CQ1, CQ2...CQN. Each completion queue is also maintained by the head pointer Head and the tail pointer Tail. Step 2: The ASIC main control chip inside the SSD uses the Round-Robin method to complete the acquisition of commands from each submission queue and distribute the commands to each CPU (that is, the IO commands in the same submission queue SQ will be cyclically scheduled by the submission command arbitration module and evenly distributed to each CPU; the IO commands in different submission queues SQs will be cyclically scheduled by the submission command arbitration module to each CPU), and the number of IO submission commands will be counted automatically: gSqeRecv[MAX_CORES][MAX_SUB_QUEUES], Among them, MAX_CORES is the total number of CPU cores of CPU0 / CPU1… / CPUN, and MAX_SUB_QUEUES is the total number of SQ submission queues of SQ0 / SQ1… / SQN; Step 3. When initializing each queue inside the SSD, the initial credit value on each CPU for the flow control mechanism is completed according to the queue depth of each CQ completion queue during initialization. The initial value is selected as the queue depth qSize divided by the number of CPUs, that is, the method of evenly dividing the Credit value; in this way, when the host creates multiple pairs of queues, each CPU will have different initial transmission Credit values according to different queue depths and record them in the memory variable remainingCplQEntries[MAX_CORES][MAX_CPL_QUEUES].

[0088] Step 4. After a certain CPU processes the IO command obtained in Step 2 and performs internal IO command processing, it is sent to the corresponding CQ completion queue. The number of successfully sent completion commands on the current CPU is incremented by sendCplqMsgCnt[MAX_CORES][MAX_CPL_QUEUES]++, and at the same time, the transmission Credit value is decremented. Step 5. When the transmission Credit value of the completion commands of the j-th completion queue cq_j used by the i-th CPU is decremented to 0, that is, remainingCplQEntries[cpu_i][cplq_j] is 0 and there is no available credit value, an update operation for the remaining credit value of the completion queue is required. During the update process, the flow control synchronization and IO balancing operations between this CPU_i and other CPUs are completed. The update method is as follows: (1) The i-th CPU reads the total remaining credit value cq_j_remainCredits of the j-th completion queue, which is obtained from the sum of the head pointer Head value, tail pointer Tail value, and the depth qSize of the corresponding j-th completion queue. The determination method is as follows: When Head = Tail, the total number of available credit Credits is the queue depth qSize, that is, cq_j_remainCredits = qSize; When Head > Tail, the total number of available credit Credits cq_j_remainCredits is cq_head – cq_tail – 1, that is, cq_j_remainCredits = cq_head–cq_tail–1; When Head < Tail, the total number of available credit Credits cq_j_remainCredits is qSize - (cq_tail - cq_head) – 1, that is, cq_j_remainCredits = qSize-(cq_tail–cq_head)-1; (2) The i-th CPU calculates the total number of IO commands being executed in other CPUs, otherCpusOutstandingIOSum, and the calculation method is as follows:

[0089] Among them, cpu_m represents the cpu identified as m, cq_j represents the cq completion queue identified as j, and the i-th cpu is not included when the difference counts of all cpus are summed, that is, m != i; gSqeRecv[MAX_CORES][MAX_CQ_QUEUES] represents the number of initial IO commands distributed to each CPU and sent to the CQ completion queue, sendCplgMsgCnt[MAX_CORES][MAX_CQ_QUEUES] represents the format of the completion command that has been sent to the CQ completion queue. Under normal circumstances, gSqeRecv[cpu_m][cq_j]≥sendCplgMsgCnt[cpu_m][cq_j], that is, the above difference will not be negative.

[0090] (3) The i-th CPU completes the comparison and judgment of cq_j_remainCredits and otherCpusOutstandingIOSum: If cq_j_remainCredits>otherCpusOutstandingIOSum, it means that this completion queue has available remaining send credits, and the i-th CPU can continue to send the IO command completion message of the j-th completion queue. Then the remaining available credits remainingCplQEntries[cpu_i][cplq_j] are updated as follows: remainingCplQEntries[cpu_i][cplq_j]=(cq_j_remainCredits-otherCpusOutstandingIOSum) / MAX_CORES, If cq_j_remainCredits≤ otherCpusOutstandingIOSum, it means that this completion queue has no remaining available sending credits. The corresponding IO command processing on queue j on CPU_i is faster than the command processing on queue j on other CPUs. To ensure synchronization between different CPUs and balancing of IO load, it is necessary to stop sending IO completion commands on queue j on CPU_i, transfer CPU computing power, and perform corresponding processing of IO commands and other tasks on other queues.

[0091] Figure 5A flowchart of a processor synchronization balancing method proposed in the present disclosure, which is applied to Figure 4 The system shown is executed by the management module 3032 to implement flow control variable initialization, including the following steps: 1. Initialize the IO SQ to distribute IO commands in Round-Robin scheduling mode.

[0092] 2. Initialize the mapping relationship between the internal SQ and CQ based on the association relationship between the IO SQ and CQ created by the host.

[0093] 3.1. Initialize the initial value of the flow control credit of multiple queues on multiple CPUs: remainingCplQEntries[MAX_CORES][MAX_CPL_QUEUES].

[0094] 3.2. Initialize the parameters of the IO synchronization balancing module on multiple CPUs: gSqeRecv[MAX_CORES][MAX_CQ_QUEUES] and sendCplqMsgCnt[MAX_CORES][MAX_CQ_QUEUES].

[0095] Figure 6 A flowchart of a processor synchronization balancing method proposed in the present disclosure, which is applied to Figure 4 The system shown is executed by the first processor 302 to achieve synchronization balancing of the first processor 302, including the following steps: Step 1. CPU_i processes the IO command to be sent to CQ_j.

[0096] Step 2: CPU_i sends the processed IO command to its own transmission synchronization balancing module.

[0097] Step 3: Determine whether CPU_i exits sending to the cq_j queue. If so, proceed to step 4; if not, proceed to step 1.

[0098] Step 4: Complete inter-CPU synchronization / balancing by calculating the remaining credit value of the cq_j queue and processing other tasks of this CPU.

[0099] Step 5: CPU_j processes the IO command to be sent to CQ_j.

[0100] Step 6: CPU_j runs the processed IO command and sends it to its own command sending synchronization balancing module.

[0101] Step 3: Determine whether CPU_j exits sending to the cq_j queue. If so, proceed to step 4; if not, proceed to step 1.

[0102] Figure 7 A flowchart of a processor synchronization balancing method proposed in the present disclosure, which is applied to Figure 4 The system shown is executed by the above-mentioned sending synchronization equalization module 3031 to implement synchronization equalization of the first processor 302, including the following steps: Step 1: Increment the count according to the IO command identifier distributed by the Round-Robin submission command arbitration module, that is, gSqeRecv[cpu_i][cq_j]++.

[0103] Step 2: After the IO command is processed, it is sent to the corresponding cq_j completion queue.

[0104] Step 3: Determine whether the current cq_j completion queue has available Credit value, that is, determine whether remainingCplQEntries[cpu_i][cplq_j]>0. If so, proceed to step 4; otherwise, proceed to step 5.

[0105] Step 4, continue to increment the number of successfully sent commands on the current CPU: sendCplqMsgCnt[MAX_CORES][MAX_CPL_QUEUES]++, and decrement the available credit value: remainingCplQEntries[cpu_i][cplq_j]--.

[0106] Step 5: Update the available credit value credit on cpu_i for the cq_j queue: 1) Calculate the sum of outstanding IOs for the cq_j queue on other CPUs except cpu_i (m=0,...m!=i,…,m=MAX_CORES): otherCpusOutstandingIOSum = ∑( (gSqeRecv[cpu_m][cq_j]-sendCplqMsgCnt[cpu_m][cq_j])), cpu_m represents the cpu identified as m, cq_j represents the completion queue cq identified as j; 2) Read the current total remaining available credits of the cq_j queue: cq_j_remainCredits = {head, tail, qSize}, where head and tail are obtained by reading the CQ hardware queue register.

[0107] Step 6: Compare the total remaining available credits of the cq_j queue.

[0108] If cq_j_remainCredits>otherCpusOutstandingIOSum, go to step 7. If not, go to step 8. Step 7: Calculate the available credit value credit that can be used on cpu_i on cq_j.

[0109] The available credit value is: remainingCplQEntries[cpu_i][cplq_j] = (cq_j_remainCredits - otherCpusOutstandingIOSum ) / MAX_CORES Step 8: Exit sending, wait for the next IO to complete the scheduling of command sending, and complete the synchronization of CPU_i and other CPUs for cq_j command.

[0110] In order to implement the processor synchronization balancing method provided by the embodiment of the present disclosure, the embodiment of the present disclosure also provides a processor synchronization balancing device, such as Figure 8 As shown, the processor synchronization equalization device 800 includes: A distribution unit 801 is used to distribute the first command in the first submission queue to the first processor; A determining unit 802 is configured to determine an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; An updating unit 803 is used to update the initial credit value decrementally based on the number of first commands processed by the first processor to obtain an updated credit value; The balancing unit 804 is configured to perform a synchronous balancing operation on the update credit value of the first processor when the update credit value reaches a first preset value.

[0111] In some embodiments, the distribution unit 801 is further configured to: distribute the first command uniformly to the first processor in sequence based on a polling algorithm.

[0112] In some embodiments, the determining unit 802 is further configured to determine an initial credit value based on a ratio between a first queue depth of the first completion queue and the number of cores of the first processor.

[0113] In some embodiments, the balancing unit 804 is also used to: determine the remaining credit value of the second completion queue based on the head pointer value of the second completion queue, the tail pointer value of the second completion queue and the second queue depth of the second completion queue, the second completion queue being a queue in the first completion queue whose updated credit value reaches a first preset value; determine the total number of pending operations of the first processor based on the expected number of sends of the first processor and the number of completed sends of the first processor, wherein the expected number of sends is the number of commands that the first processor expects to send to the second completion queue, and the completed number of sends is the number of commands that the first processor has sent to the second completion queue; determine whether there is an available credit value in the second completion queue based on the remaining credit value and the total number of pending operations; and perform synchronous balancing operations on the updated credit value of the first processor based on whether there is an available credit value in the second completion queue.

[0114] In some embodiments, the balancing unit 804 is also used to: when the first pointer value is greater than the tail pointer value, determine the remaining credit value based on the second queue depth; when the first pointer value is less than the tail pointer value, determine the remaining credit value based on the first pointer value and the tail pointer value; when the first pointer value is equal to the tail pointer value, determine the remaining credit value based on the first pointer value, the tail pointer value and the second queue depth.

[0115] In some embodiments, the balancing unit 804 is further configured to determine the total number to be processed based on the difference between the expected number of transmissions of the first processor and the completed number of transmissions of the first processor.

[0116] In some embodiments, the balancing unit 804 is further used to: when the remaining credit value is greater than the total number to be processed, determine that there is an available credit value in the second completion queue; when the remaining credit value is less than or equal to the total number to be processed, determine that there is no available credit value in the second completion queue.

[0117] In some embodiments, the balancing unit 804 is further used to: when there is an available credit value, determine the reallocated credit value based on the remaining credit value, the total number to be processed and the number of cores of the first processor, so as to distribute the reallocated credit value to the first processor; when there is no available credit value, the second processor stops sending commands to the second completion queue, and the second processor updates the first processor whose credit value reaches the first preset value.

[0118] In some embodiments, the balancing unit 804 is further configured to: determine a difference between the remaining credit value and the total number to be processed; and determine a ratio between the difference and the number of cores of the first processor as the reallocated credit value.

[0119] In summary, the processor synchronization and balancing device proposed in the present disclosure includes: a distribution unit, which is used to distribute the first command in the first submission queue to the first processor; a determination unit, which is used to determine the initial credit value of the first processor based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor of the first processor; an update unit, which is used to decrementally update the initial credit value based on the number of completed processing of the first command by the first processor to obtain an updated credit value; and a balancing unit, which is used to synchronize and balance the updated credit value of the first processor when the updated credit value reaches a first preset value. The device of the present disclosure can adaptively adjust the credit value in the processing and the transfer of processor computing power by synchronized balancing the updated credit value of the first processor when the updated credit value reaches the first preset value, so as to balance the command processing between different processors and ensure the service quality of the processor.

[0120] It should be noted that: the processor synchronization balancing device provided in the above embodiment only uses the division of the above program modules as an example when performing processor synchronization balancing. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the processor synchronization balancing device is divided into different program modules to complete all or part of the processing described above. In addition, the processor synchronization balancing device provided in the above embodiment and the processor synchronization balancing method embodiment provided in the embodiment of the present disclosure belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0121] Fig. 9 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the electronic device 900 includes at least one processor 902; and a memory 901 communicatively connected to the at least one processor 902; wherein the memory 901 stores instructions that can be executed by the at least one processor 902, and the instructions are executed by the at least one processor 902 to implement the steps of the processor synchronization equalization method described in the embodiment of the present disclosure.

[0122] Optionally, the electronic device may specifically be a processor synchronization and balancing device in an embodiment of the present application, and the electronic device may implement the corresponding processes implemented by the processor synchronization and balancing device in each method in the embodiment of the present application, which will not be described in detail here for the sake of brevity.

[0123] It is understood that the electronic device also includes a communication interface 903. The various components in the electronic device are coupled together through a bus system 904. It is understood that the bus system 904 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Fig. 9 Various buses are labeled as bus system 904.

[0124] It can be understood that the memory 901 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAM bus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 901 described in the embodiment of the present invention is intended to include but is not limited to these and any other suitable types of memories.

[0125] The method disclosed in the above embodiment of the present disclosure can be applied to the processor 902, or implemented by the processor 902. The processor 902 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 902 or an instruction in the form of software. The above processor 902 may be a general-purpose processor, a DSP, or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 902 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in the memory 901, and the processor 902 reads the information in the memory 901 and completes the steps of the above method in combination with its hardware.

[0126] In an exemplary embodiment, the electronic device may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), FPGAs, general purpose processors, controllers, MCUs, microprocessors, or other electronic components to execute the aforementioned method.

[0127] The embodiment of the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to implement the steps of the processor synchronization equalization method described in the embodiment of the present disclosure when executed.

[0128] The embodiment of the present disclosure further provides a computer program product, including a computer program, which implements the steps of the processor synchronization equalization method described in the embodiment of the present disclosure when executed by a processor.

[0129] Optionally, the computer-readable storage medium can be applied to the processor synchronization and balancing device in the embodiments of the present application, and the computer instructions enable the computer to execute the corresponding processes implemented by the processor synchronization and balancing device in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0130] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0131] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0132] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0133] A person of ordinary skill in the art can understand that: all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, which, when executed, executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, disks or optical disks.

[0134] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0135] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A processor synchronization equalization method, characterized in that: The method comprises: Dispatching a first command in a first submission queue to a first processor; Determining an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; Based on the number of first processors that have completed processing of the first command, the initial credit value is updated decrementally to obtain an updated credit value; When the update credit value reaches a first preset value, a synchronous balancing operation is performed on the update credit value of the first processor.

2. The processor synchronization equalization method according to claim 1, characterized in that: The distributing the first command in the first submission queue to the first processor comprises: Based on a polling algorithm, the first commands are evenly distributed to the first processors in sequence.

3. The processor synchronization equalization method according to claim 1, characterized in that: The determining, based on the first completion queue corresponding to the first submission queue and the number of cores of the first processor, an initial credit value of the first processor includes: The initial credit value is determined based on a ratio between a first queue depth of the first completion queue and the number of cores of the first processor.

4. The processor synchronization equalization method according to any one of claims 1 to 3, characterized in that: When the update credit value reaches a first preset value, performing a synchronous balancing operation on the update credit value of the first processor includes: Determine a remaining credit value of the second completion queue based on a head pointer value of the second completion queue, a tail pointer value of the second completion queue, and a second queue depth of the second completion queue, the second completion queue being a queue in the first completion queue whose updated credit value reaches the first preset value; Determine the total number of pending commands of the first processor based on the expected number of sends of the first processor and the number of completed sends of the first processor, wherein the expected number of sends is the number of commands that the first processor is expected to send to the second completion queue, and the completed number of sends is the number of commands that the first processor has sent to the second completion queue; Based on the remaining credit value and the total number to be processed, determining whether there is an available credit value in the second completion queue, and obtaining a determination result; Based on the determination result, a synchronous balancing operation is performed on the updated credit value of the first processor.

5. The processor synchronization equalization method according to claim 4, characterized in that: The determining the remaining credit value of the second completion queue based on the head pointer value of the second completion queue, the tail pointer value of the second completion queue, and the second queue depth of the second completion queue includes: When the head pointer value is greater than the tail pointer value, increasing the second queue depth to determine the remaining credit value; When the first pointer value is less than the tail pointer value, determining the remaining credit value based on the first pointer value and the tail pointer value; When the head pointer value is equal to the tail pointer value, the remaining credit value is determined based on the head pointer value, the tail pointer value, and the second queue depth.

6. The processor synchronization equalization method according to claim 4, characterized in that: The determining, based on the expected number of transmissions of the first processor and the number of completed transmissions of the first processor, the total number of to-be-processed packets of the first processor comprises: The total number to be processed is determined based on a difference between the expected number of transmissions of the first processor and the completed number of transmissions of the first processor.

7. The processor synchronization equalization method according to claim 4, characterized in that: The determining whether there is an available credit value in the second completion queue based on the remaining credit value and the total number to be processed comprises: When the remaining credit value is greater than the total number to be processed, determining that the second completion queue has available credit values; When the remaining credit value is less than or equal to the total number to be processed, it is determined that no available credit value exists in the second completion queue.

8. The processor synchronization equalization method according to claim 4, characterized in that: The performing a synchronous balancing operation on the updated credit value of the first processor based on whether the second completion queue has an available credit value comprises: When the available credit value exists, determining a reallocated credit value based on the remaining credit value, the total number to be processed, and the number of cores of the first processor, so as to distribute the reallocated credit value to the first processor; When the available credit value does not exist, the second processor stops sending commands to the second completion queue, and the second processor is the first processor whose update credit value reaches the first preset value.

9. The processor synchronization equalization method according to claim 8, characterized in that: The determining of the reallocated credit value based on the remaining credit value, the total number to be processed, and the number of cores of the first processor comprises: determining a difference between the remaining credit value and the total to be processed; The ratio between the difference and the number of cores of the first processor is determined as the reallocated credit value.

10. A processor synchronization and balancing system, characterized in that: The system comprises: a first device, a first processor and a solid state hard disk, wherein the solid state hard disk comprises at least a command submission arbitration module and a management module, and the first processor comprises at least a command sending synchronization and balancing module; Wherein, the first device is used to send a first submission queue to the submission command arbitration module; The submission command arbitration module is used to distribute the first command in the first submission queue to the first processor based on a polling algorithm; The management module is configured to determine an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; for decreasing and updating the initial credit value based on the number of completed processings of the first command by the first processor to obtain an updated credit value; The command sending synchronization and balancing module is used to perform a synchronization and balancing operation on the update credit value of the first processor when the update credit value reaches a first preset value.

11. The processor synchronization and balancing system according to claim 10, characterized in that: The first device is further configured to store the first command in a submission queue having an idle slot to generate the first submission queue.

12. A processor synchronization equalization device, characterized in that: include: a distribution unit, configured to distribute a first command in a first submission queue to a first processor; a determining unit, configured to determine an initial credit value of the first processor based on a first completion queue corresponding to the first submission queue and the number of cores of the first processor; an updating unit, configured to update the initial credit value decrementally based on the number of times the first processor completes processing of the first command, so as to obtain an updated credit value; The balancing unit is used to perform a synchronous balancing operation on the update credit value of the first processor when the update credit value reaches a first preset value.

13. An electronic device, characterized in that: include: a processor and a memory for storing a computer program capable of being executed on the processor, Wherein, when the processor is used to run the computer program, it executes the processor synchronization and equalization method according to any one of claims 1-9.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the processor synchronization equalization method according to any one of claims 1-9.

15. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the processor synchronization equalization method according to any one of claims 1 to 9.

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