Memory fault detection system and method, server equipment and storage medium

Abstract

The invention provides a memory fault detection system and method, a server device and a storage medium, and relates to the field of memory fault detection.The system can be composed of a central processing unit, a management controller and a memory device, the central processing unit comprises a processor cache, the memory device comprises an error register, and the central processing unit and the management controller can monitor the memory device. And an error signal line is arranged between the central processing unit and the management controller. In the actual working process, when the central processing unit determines that the memory device has a memory error, an error signal can be sent to the management controller through the error signal line; when the management controller receives the error signal, the management controller can confirm the faulty memory device with the error according to the error register of the memory device, and can determine the faulty memory device information in combination with the preset memory device information in the processor cache, so that the memory fault reporting efficiency can be improved, and obvious interference to a central processing unit is avoided.

Description

Technical Field

[0001] The present invention relates to the field of memory fault detection, and in particular to a memory fault detection system, method, server equipment and storage medium. Background Art

[0002] As one of the main components in the server, the operating stability of the memory device and the timeliness of reporting errors have become one of the important indicators for measuring server stability. In related technologies, the processing of memory errors is integrated into the basic input and output system. Memory error reporting requires triggering a system interrupt under the system, transmitting error information to the basic input and output system, which integrates the received error information and then transmits it to the management controller by sending commands. This process is long and complicated, and the processor cannot perform other operations during the system interrupt, which will seriously affect the operating efficiency of the processor. Summary of the invention

[0003] The object of the present invention is to provide a memory fault detection system, method, server device and storage medium, which can directly transmit memory errors from a central processing unit to a management controller, and the management controller can determine faulty memory device information in combination with memory device information preset in a processor cache, thereby improving the efficiency of memory fault reporting and avoiding significant interference to the central processing unit.

[0004] In order to solve the above technical problems, the present invention provides a memory fault detection system, comprising:

[0005] A central processing unit, a management controller, and a memory device, wherein the central processing unit includes a processor cache, and the memory device includes an error register; the central processing unit is connected to the management controller and the memory device, and has an error signal line between the central processing unit and the management controller; the management controller is connected to the memory device;

[0006] The central processing unit is used to send an error signal to the management controller through an error signal line when determining that a memory error occurs in the memory device;

[0007] A management controller is used to obtain preset memory device information from a processor cache when an error signal is received; confirm a faulty memory device where an error occurs according to an error register of the memory device; determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information.

[0008] Optionally, the central processing unit is further configured to adjust the error signal from the first level value to the second level value when determining that a memory error occurs in the memory device;

[0009] The management controller is further used to enter the step of obtaining preset memory device information from the processor cache when it is determined that the error signal is adjusted from the first level value to the second level value.

[0010] Optionally, it also includes:

[0011] Basic input and output system, the basic input and output system is connected to the central processing unit and the memory device, and is used to obtain memory device information from each memory device when the server device is started, and write the memory device information into the processor cache.

[0012] Optionally, an error signal line is set between the central processing unit and the management controller via a general input and output interface.

[0013] Optionally, the central processing unit is further configured to send an error signal to the management controller via an error signal line in the general input and output interface when determining that a memory error of a correctable error type occurs in the memory device;

[0014] The management controller is further configured to generate and report an error log containing information about the faulty memory device when it is determined according to the error register of the faulty memory device that a memory error of a correctable error type occurs in the faulty memory device.

[0015] Optionally, it also includes a hardware monitoring module, which is connected to the central processing unit and the management controller and has an error signal line between the hardware monitoring module and the central processing unit; the hardware monitoring module includes an error status register for storing error status information corresponding to the error signal.

[0016] Optionally, it also includes a memory, which is connected to the central processing unit and the basic input and output system;

[0017] The central processing unit is further configured to send an error signal to the hardware monitoring module when determining that a memory error of an uncorrectable error type occurs in the memory device;

[0018] The hardware monitoring module is used to save the error status information to the error status register when receiving the error signal;

[0019] The management controller is further used to monitor the error status register, and when it is determined that the error status information is written in the error status register, enter the step of obtaining the preset memory device information from the processor cache; when it is determined that the faulty memory device has a memory error of an uncorrectable error type according to the error register of the faulty memory device, add an error mark to the faulty memory device information, and write the faulty memory device information into the memory; clear the error status information in the error status register, and trigger the server device to restart;

[0020] The basic input and output system is also used to obtain the faulty memory device information from the memory when the server device is started; and disable the faulty memory device according to the faulty memory device information.

[0021] Optionally, the management controller is further used to: write the faulty memory device information into the processor cache to report the faulty memory device information to the central processing unit; trigger a system interrupt, and write the faulty memory device information from the processor cache to the memory.

[0022] The present invention also provides a memory fault detection method, which is applied to the memory fault detection system described above, and the method comprises:

[0023] When the central processing unit determines that a memory error occurs in the memory device, it sends an error signal to the management controller via the error signal line;

[0024] When receiving the error signal, the management controller obtains preset memory device information from the processor cache;

[0025] The management controller identifies a faulty memory device in which an error occurs according to an error register of the memory device;

[0026] The management controller determines the faulty memory device information of the faulty memory device in the memory device information to perform fault processing according to the faulty memory device information.

[0027] The present invention also provides a server device, comprising the memory fault detection system described above.

[0028] The present invention also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are loaded and executed by a processor, the memory fault detection method described above is implemented.

[0029] The present invention provides a memory fault detection system, comprising: a central processing unit, a management controller, and a memory device, wherein the central processing unit includes a processor cache, and the memory device includes an error register; the central processing unit is connected to the management controller and the memory device, and has an error signal line between the central processing unit and the management controller; the management controller is connected to the memory device; the central processing unit is used to send an error signal to the management controller through the error signal line when determining that a memory error occurs in the memory device; the management controller is used to obtain preset memory device information from the processor cache when receiving the error signal; confirm the faulty memory device that has an error according to the error register of the memory device; determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information.

[0030] It can be seen that in the present invention, the memory fault detection system is composed of a central processing unit, a management controller, and a memory device. The central processing unit includes a processor cache, and the memory device includes an error register. Both the central processing unit and the management controller can monitor the memory device, and there is an error signal line between the central processing unit and the management controller. In the actual operation process, when the central processing unit determines that a memory error occurs in the memory device, it can send an error signal to the management controller through the error signal line without interrupting the system; and when the management controller receives the error signal, it can obtain the preset memory device information from the processor cache, and then confirm the faulty memory device that has an error according to the error register of the memory device, and then determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information. In this way, the fault information of the memory device can be simply and efficiently transmitted from the processor to the management controller without triggering a system interrupt, which can not only improve the transmission efficiency of the memory device fault information, but also avoid interference with the processor operation efficiency. The present invention also provides a memory fault detection method, an electronic device, and a computer-readable storage medium, which have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0032] Figure 1 A structural block diagram of a first memory fault detection system provided by an embodiment of the present invention;

[0033] Figure 2 A structural block diagram of a second memory fault detection system provided by an embodiment of the present invention;

[0034] Figure 3 A structural block diagram of a third memory fault detection system provided by an embodiment of the present invention;

[0035] Figure 4 A structural block diagram of a fourth memory fault detection system provided by an embodiment of the present invention;

[0036] Figure 5 A structural block diagram of a fifth memory fault detection system provided by an embodiment of the present invention;

[0037] Figure 6 A flow chart of a memory fault detection method provided by an embodiment of the present invention;

[0038] Figure 7 A schematic diagram of transmitting memory error information through CPLD provided by an embodiment of the present invention;

[0039] Figure 8 A flowchart of memory error processing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] As one of the main components of the server, the operating stability of the memory device and the timeliness of reporting after the error occurs have become one of the important indicators for measuring the stability of the server. In the related technology, memory errors include correctable errors (CE, Corrected Error) and uncorrectable errors (UCE, Uncorrectable Error). Correctable errors can be recovered by the memory device itself, while uncorrectable errors cannot be recovered by the memory device itself. The processing of memory errors is integrated into the basic input and output system (BIOS). Memory error reporting requires triggering a system interrupt under the system, transmitting error information to the basic input and output system, which integrates the received error information and then transmits it to the management controller by sending commands. This process is long and complicated, and the processor cannot perform other operations during the system interrupt, which will seriously affect the operating efficiency of the processor, especially when the memory error is a correctable error type, which will significantly affect the overall performance of the server.

[0042] In view of this, in order to solve the technical problem of how to efficiently report memory errors and avoid the impact of memory error reporting on system performance as much as possible, the present invention can provide a memory fault detection system, in which the central processing unit can directly transmit memory errors to the management controller, and the management controller can determine the faulty memory device information in combination with the memory device information preset in the processor cache, thereby improving the efficiency of memory fault reporting and avoiding significant interference to the central processing unit.

[0043] For easier understanding, please refer to Figure 1 , Figure 1This is a structural block diagram of the first memory fault detection system provided by an embodiment of the present invention. The system may include: a central processing unit, a management controller, and a memory device. Among them, the central processing unit includes a processor cache; the management controller may be a baseboard management controller (BMC, Baseboard Management Controller), an iLO manager (Integrated Lightout), a remote control card iDRAC (Integrated Dell Remote Access Controller), etc.; the memory device includes an error register (such as an AER register, Advanced Error Reporting, advanced error reporting), which is used to save the error information that occurs in the memory device. The central processing unit is connected to the management controller and the memory device, and the management controller is connected to the memory device. In addition, there is an error signal line between the central processing unit and the management controller. For example, the central processing unit can set an error signal pin (Error pin) and connect to the management controller through the pin.

[0044] It should be noted that this embodiment does not limit the specific hardware line (such as a bus) through which the central processing unit, the management controller, and the memory device are connected, nor does it limit the communication protocol through which the central processing unit, the management controller, and the memory device communicate. Reference may be made to relevant computer technologies. For example, the management controller may access the error register in the memory device through the MMBI channel (memory-mapped BMC interface). In addition, in addition to the above-mentioned error signal line, the management controller may also be connected to the central processing unit through other hardware lines.

[0045] In addition, this embodiment does not limit the hardware interface or circuit based on which the error signal line is implemented. For example, it can be implemented based on a general-purpose input / output interface (GPIO interface), or it can be implemented based on a combination of a programmable logic device (such as a complex programmable logic device CPLD) and an I2C bus (Inter-Integrated Circuit, synchronous serial bus).

[0046] The following are the specific uses of the central processing unit and management controller:

[0047] The central processing unit is used to send an error signal to the management controller through an error signal line when determining that a memory error occurs in the memory device;

[0048] A management controller is used to obtain preset memory device information from a processor cache when an error signal is received; confirm a faulty memory device where an error occurs according to an error register of the memory device; determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information.

[0049] It can be seen that in this embodiment, since an error signal line is provided between the central processing unit and the management controller, when the former detects that a memory error occurs in a memory device, an error signal can be directly sent to the latter through the error signal line. In addition, the memory device information of each memory device, such as memory capacity, memory topology information, etc., can be preset in the processor cache of the central processing unit. In this way, when the management controller receives the error signal, it can obtain the preset memory device information from the processor cache, and can confirm the faulty memory device where the error occurs according to the error register of each memory device, and then can determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information. Considering that the error signal line is implemented based on hardware, the central processing unit can quickly and efficiently transmit memory error information to the management controller based on the underlying hardware without suspending the system. In this way, the transmission efficiency of memory error information can be effectively improved, and when the memory error is a correctable error type, the impact on system performance can be effectively avoided.

[0050] It should be noted that the present embodiment does not limit the form of the error signal, and can be set according to actual application requirements. To reduce complexity, the error signal can be an ordinary level signal, having a first level value and a second level value. Among them, the first level value indicates that no memory error has occurred in the memory device, and the second level value indicates that a memory error has occurred in the memory device. The first level value can be, for example, a low level, and the second level value can be, for example, a high level. In this way, the central processing unit only needs to adjust the error signal from the first level value to the second level value to inform the management controller that a memory error has occurred in the memory device.

[0051] Based on this, the central processing unit is further used to adjust the error signal from the first level value to the second level value when determining that a memory error occurs in the memory device;

[0052] The management controller is further used to enter the step of obtaining preset memory device information from the processor cache when it is determined that the error signal is adjusted from the first level value to the second level value.

[0053] It should be noted that the present embodiment does not limit the time length for which the central processing unit keeps the error signal at the second level value, and can be set according to actual application requirements. For example, a first holding time length can be set for a correctable error type, and a second holding time length can be set for an uncorrectable error type, the first holding time length is shorter than the second holding time length, and the first holding time length can be set to a shorter value. In this way, the central processing unit can keep the second level value at different time lengths according to the memory error type to transmit different memory error types.

[0054] For further information, please refer to Figure 2 , Figure 2 This is a structural block diagram of the second memory fault detection system provided by an embodiment of the present invention. The system may also include a basic input and output system. The basic input and output system is connected to the central processing unit and the memory device, and can be used to obtain memory device information from each memory device when the server device is started, and write the memory device information into the processor cache.

[0055] In other words, the BIOS and the management controller can use the processor cache as a shared storage space and can pass memory device information through the processor cache. This ensures that the management controller can obtain reliable memory device information from the processor cache when troubleshooting a faulty memory device.

[0056] Based on the above embodiments, in the present invention, the memory fault detection system is composed of a central processing unit, a management controller, and a memory device. The central processing unit includes a processor cache, and the memory device includes an error register. Both the central processing unit and the management controller can monitor the memory device, and there is an error signal line between the central processing unit and the management controller. In the actual operation process, when the central processing unit determines that a memory error occurs in the memory device, it can send an error signal to the management controller through the error signal line without interrupting the system; and when the management controller receives the error signal, it can obtain the preset memory device information from the processor cache, and then confirm the faulty memory device that has an error according to the error register of the memory device, and then determine the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information. In this way, the fault information of the memory device can be simply and efficiently transmitted from the processor to the management controller without triggering a system interrupt, which can not only improve the transmission efficiency of the memory device fault information, but also avoid interference with the processor operation efficiency.

[0057] Based on the above embodiments, the reporting method of the correctable error type is introduced below. In this embodiment, considering that the correctable error type can be handled by the memory device itself and has little impact on the system as a whole, the central processing unit can transmit an error signal to the management controller in a relatively simple way when determining that the memory device encounters this type of memory error. Specifically, an error signal line is set between the central processing unit and the management controller through a universal input and output interface to reduce the reporting complexity of the correctable error type based on the simple structure and concise communication method of the universal input and output interface. The following is the processing method of the central processing unit and the management controller when facing a memory error of the correctable error type:

[0058] The central processing unit is further configured to send an error signal to the management controller via an error signal line in the general input and output interface when determining that a memory error of a correctable error type occurs in the memory device;

[0059] The management controller is further configured to generate and report an error log containing information about the faulty memory device when it is determined according to the error register of the faulty memory device that a memory error of a correctable error type occurs in the faulty memory device.

[0060] It can be seen that in this embodiment, when the central processing unit determines that a memory error of a correctable error type occurs in the memory device, the central processing unit can send an error signal to the management controller through the error signal line in the general input and output interface. The central processing unit can temporarily adjust the error signal from the first level value to the second level value. When the management controller determines that a memory error of a correctable error type occurs in the faulty memory device through the error register of the memory device, the management controller can simply generate and report an error log containing information about the faulty memory device.

[0061] Based on the above embodiment, the following describes the reporting method of uncorrectable error types. In this embodiment, considering that uncorrectable error types are serious faults for memory devices and central processing units, and may even cause the central processing unit to fail to work properly, it is necessary to use dedicated hardware to transmit memory error information of uncorrectable error types to the management controller. For easy understanding, please refer to Figure 3 , Figure 3 This is a structural block diagram of the third memory fault detection system provided by an embodiment of the present invention. The system may also include a hardware monitoring module, which is connected to the central processing unit and the management controller and has an error signal line between the hardware monitoring module and the central processing unit; the hardware monitoring module includes an error status register for storing error status information corresponding to the error signal.

[0062] It can be seen that in this embodiment, the central processing unit can transmit an error signal to the hardware monitoring module, and the hardware monitoring module continues to transmit the error signal to the management controller. The hardware monitoring module can include an error status register for storing the error status. In this way, when the central processing unit fails, the hardware monitoring module can replace the central processing unit to continue to transmit the error signal to the management controller, thereby improving the transmission reliability of memory error information of uncorrectable error types.

[0063] Furthermore, in order to prevent the failure memory device with uncorrectable error type from affecting the system, in this embodiment, the management controller can transmit the failure memory device information to the basic input and output system, and automatically trigger the system restart. During the system restart, the basic input and output system can disable the corresponding failure memory device according to the failure memory device information to avoid using the failure memory device. The following introduces the method of disabling the failure memory device.

[0064] For easier understanding, please refer to Figure 4 , Figure 4 This is a structural block diagram of the fourth memory fault detection system provided by an embodiment of the present invention. The system may also include a memory (e.g., NVRAM, Non-Volatile Random Access Memory), which is connected to the central processing unit and the basic input and output system; the hardware monitoring module includes an error status register. The following is the processing method of the central processing unit, the hardware monitoring module, the management controller, and the basic input and output system when facing an uncorrectable error type memory error:

[0065] The central processing unit is further configured to send an error signal to the hardware monitoring module when determining that a memory error of an uncorrectable error type occurs in the memory device;

[0066] The hardware monitoring module is used to save the error status information to the error status register when receiving the error signal;

[0067] The management controller is further used to monitor the error status register, and when it is determined that the error status information is written in the error status register, enter the step of obtaining the preset memory device information from the processor cache; when it is determined that the faulty memory device has a memory error of an uncorrectable error type according to the error register of the faulty memory device, add an error mark to the faulty memory device information, and write the faulty memory device information into the memory; clear the error status information in the error status register, and trigger the server device to restart;

[0068] The basic input and output system is also used to obtain the faulty memory device information from the memory when the server device is started; and disable the faulty memory device according to the faulty memory device information.

[0069] It can be seen that when the central processor determines that a memory error of an uncorrectable error type occurs in the memory device, it can send an error signal to the hardware monitoring module. For example, the central processor can adjust the error signal from the first level value to the second level value, and maintain the second level value for a long time. In this way, when the hardware monitoring module receives the error signal, it can save the error status information to the error status register so that the management controller can perceive it. Subsequently, the management controller can monitor the error status register, and when it is determined that the error status information has been written into the error status register, it starts to determine the faulty memory device and the corresponding faulty memory device information. Further, when the management controller determines that a memory error of an uncorrectable error type occurs in the faulty memory device according to the error register, in order to ensure that the faulty memory device is effectively disabled, an error mark can be added to the faulty memory device information, and the faulty memory device information can be written into a memory accessible to the basic input and output system to avoid the loss of the faulty memory device information when the system is powered off. After completing the storage of the faulty memory device information, the management controller can clear the error status information in the error status register and trigger the restart of the server device. Finally, when the basic input and output system restarts the server device, it can obtain the faulty memory device information from the memory and disable the faulty memory device according to the faulty memory device information. In this way, the automatic processing of uncorrectable error type memory errors can be achieved, thereby preventing the server from being inactivated and unable to work.

[0070] It should be noted that this embodiment does not limit how the management controller writes the faulty memory device information into the NVRAM processor. For example, the management controller may first write the faulty memory device information into the processor cache to report the faulty memory device information to the central processor. Subsequently, a system interrupt (such as SCI interrupt, System Control Interrupt, system control interrupt) may be triggered, and the faulty memory device information may be written from the processor cache into the memory.

[0071] Based on this, the management controller is also used to: write the faulty memory device information into the processor cache to report the faulty memory device information to the central processor; trigger a system interrupt, and write the faulty memory device information from the processor cache into the memory.

[0072] Finally, please refer to Figure 5 , Figure 5 This is a structural block diagram of the fifth memory fault detection system provided in an embodiment of the present invention, which fully demonstrates the entire structure of the memory fault detection system. For example, two sets of error signal lines can be implemented between the management controller and the central processing unit through the hardware monitoring module and GPIO to transmit different types of memory errors.

[0073] Based on the above embodiments, the memory fault detection method provided by the present invention is introduced below. Figure 6 , Figure 6 A flow chart of a memory fault detection method provided by an embodiment of the present invention. The method is applied to the above-mentioned memory fault detection system and may include:

[0074] S601, when the central processing unit determines that a memory error occurs in the memory device, the central processing unit sends an error signal to the management controller through an error signal line;

[0075] S602, when receiving the error signal, the management controller obtains preset memory device information from the processor cache;

[0076] S603, the management controller confirms the faulty memory device where an error occurs according to the error register of the memory device;

[0077] S604: The management controller determines the faulty memory device information of the faulty memory device in the memory device information, so as to perform fault processing according to the faulty memory device information.

[0078] It can be seen that the CPU can quickly and efficiently transmit memory error information to the management controller based on the underlying error signal line without suspending the system. In this way, the transmission efficiency of memory error information can be effectively improved, and when the memory error is a correctable error type, the impact on system performance can be effectively avoided.

[0079] Optionally, the method may further include:

[0080] When the central processing unit determines that a memory error occurs in the memory device, the error signal is adjusted from a first level value to a second level value;

[0081] When the management controller determines that the error signal is adjusted from the first level value to the second level value, the management controller enters the step of obtaining preset memory device information from the processor cache.

[0082] It can be seen that this embodiment can realize the transmission of memory error information through ordinary level signals, so as to improve processing efficiency and reduce processing complexity.

[0083] Optionally, the memory fault detection system further includes a basic input and output system, and the basic input and output system is connected to the central processing unit and the memory device; the method may further include:

[0084] When the server device is started, the basic input and output system obtains memory device information from each memory device and writes the memory device information into the processor cache.

[0085] It can be seen that the basic input and output system and the management controller can use the processor cache as a shared storage space and can transmit memory device information through the processor cache. In this way, it can ensure that the management controller can obtain reliable memory device information from the processor cache when troubleshooting a faulty memory device.

[0086] Optionally, an error signal line is set between the central processing unit and the management controller via a general input / output interface; the method may also include:

[0087] When the central processing unit determines that a memory error of a correctable error type occurs in the memory device, the central processing unit sends an error signal to the management controller via an error signal line in the general input and output interface;

[0088] When the management controller determines, according to the error register of the faulty memory device, that a memory error of a correctable error type occurs in the faulty memory device, the management controller generates and reports an error log containing information about the faulty memory device.

[0089] It can be seen that when the central processor determines that a memory device has a correctable error type of memory error, it can send an error signal to the management controller through the error signal line in the general input and output interface, which can reduce the complexity of reporting the correctable error type based on the simple structure and concise communication method of the general input and output interface. When the management controller determines that a faulty memory device has a correctable error type of memory error through the error register of the memory device, it can simply generate and report an error log containing the information of the faulty memory device.

[0090] Optionally, the memory fault detection system further includes a hardware monitoring module, which is connected to the central processing unit and the management controller and has an error signal line with the central processing unit; the hardware monitoring module includes an error status register for storing error status information corresponding to the error signal; the memory fault detection system further includes a memory, which is connected to the processor and the basic input and output system; the hardware monitoring module includes an error status register; the method may further include:

[0091] The central processing unit sends an error signal to the hardware monitoring module when determining that a memory error of an uncorrectable error type occurs in the memory device;

[0092] When the hardware monitoring module receives an error signal, it saves the error status information to the error status register;

[0093] The management controller monitors the error status register, and when it is determined that the error status information is written in the error status register, enters the step of obtaining preset memory device information from the processor cache;

[0094] When the management controller determines, based on the error register of the faulty memory device, that a memory error of an uncorrectable error type occurs in the faulty memory device, the management controller adds an error mark to the faulty memory device information and writes the faulty memory device information into the memory;

[0095] The management controller clears the error status information in the error status register and triggers the server device to restart;

[0096] When the server device is started, the basic input and output system obtains the faulty memory device information from the memory; and disables the faulty memory device according to the faulty memory device information.

[0097] It can be seen that this embodiment can realize automatic processing of uncorrectable error type memory errors through the mutual cooperation between the central processing unit, the hardware monitoring module, the management controller, and the basic input and output system, thereby avoiding server deactivation and inability to work.

[0098] Optionally, the method may further include:

[0099] The management controller writes the faulty memory device information into the processor cache to report the faulty memory device information to the central processor;

[0100] Trigger a system interrupt and write the faulty memory device information from the processor cache to the memory.

[0101] Based on the above embodiment, the memory fault detection method is fully introduced below based on a specific schematic diagram. Figure 7 , Figure 7 A schematic diagram of transmitting memory error information through CPLD provided by an embodiment of the present invention. In this schematic diagram, the mainboard CPLD provides a storage error type register and saves the state of the register to UFM (User Flash Memory) to ensure that the register filling is not lost when the system is powered off. The BMC communicates with the CPLD through the DBUS bus and the I2C bus.

[0102] The BMC registers the errortype attribute with DBUS in the cpld-manager service (CPLD management software) and monitors the current errortype attribute changes.

[0103] After the host detects an error, a long pull on the error pin indicates that the system triggers an uncorrectable memory error, and a short pull on the error pin indicates that the system triggers a correctable memory error.

[0104] BMC monitors the change of errortype attribute under cpldDBUS in oem-error-monitor (error monitoring software). When the errortype attribute change is detected, BMC reads the memory topology and error data in the AER register through the MMBI channel, confirms the faulty memory location and reports the log.

[0105] Please refer to Figure 8 , Figure 8 A flowchart of memory error processing provided by an embodiment of the present invention, log reporting and processing logic of correctable errors and uncorrectable errors on the BMC side:

[0106] Correctable error: When the BMC obtains the correctable error type according to the error type, the BMC reads the status of the AER register and the system memory topology structure stored in the shared memory through the MMBI channel to accurately locate the faulty memory location and report the log to notify the user, while clearing the errortype attribute value.

[0107] Uncorrectable error: When the BMC obtains the current error as an uncorrectable error type based on the error type, the BMC reads the state of the AER register and the system memory topology structure stored in the shared memory through the MMBI channel to accurately locate the faulty memory location and report the log to notify the user. At the same time, the memory is set to the disable state and the errortype attribute value is cleared to notify the system to restart. At this time, the faulty memory has been disabled, and the system can work normally after restarting, reducing the system performance degradation caused by long-term downtime on the HOST side.

[0108] An embodiment of the present invention further provides a server device, comprising the memory fault detection system described in the above embodiment.

[0109] Since the embodiments of the server device part correspond to the embodiments of the memory fault detection method part, please refer to the description of the above embodiments for the embodiments of the server device part, which will not be repeated here.

[0110] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the memory fault detection method described in the above embodiment when the computer program / instruction is executed by a processor.

[0111] Since the embodiments of the computer program product part correspond to the embodiments of the memory fault detection method part, please refer to the description of the embodiments of the memory fault detection method part for the embodiments of the computer program product part, and will not be repeated here.

[0112] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the memory fault detection method described in the above embodiment is implemented.

[0113] Since the embodiments of the computer-readable storage medium part correspond to the embodiments of the memory fault detection method part, the embodiments of the storage medium part refer to the description of the embodiments of the memory fault detection method part, which will not be repeated here.

[0114] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0115] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0116] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0117] The above is a detailed introduction to a memory fault detection system, method, server device and storage medium provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A memory fault detection system, characterized in that: include: A central processing unit, a management controller, and a memory device, wherein the central processing unit includes a processor cache, and the memory device includes an error register; The central processing unit is connected to the management controller and the memory device, and has an error signal line between the central processing unit and the management controller; the management controller is connected to the memory device; The central processing unit is configured to send an error signal to the management controller via the error signal line when determining that a memory error occurs in the memory device; The management controller is used to obtain preset memory device information from the processor cache when receiving the error signal; confirming a faulty memory device in which an error occurs according to an error register of the memory device; Faulty memory device information of the faulty memory device is determined in the memory device information, so as to perform fault processing according to the faulty memory device information.

2. The memory fault detection system according to claim 1, characterized in that: The central processor is further configured to adjust the error signal from the first level value to the second level value when determining that a memory error occurs in the memory device; The management controller is further configured to enter the step of obtaining preset memory device information from the processor cache when it is determined that the error signal is adjusted from the first level value to the second level value.

3. The memory fault detection system according to claim 1, characterized in that: Also includes: A basic input-output system is connected to the central processing unit and the memory device, and is used to obtain the memory device information from each memory device and write the memory device information into the processor cache when the server device is started.

4. The memory fault detection system according to claim 3, characterized in that: The error signal line is set between the central processing unit and the management controller via a general input and output interface.

5. The memory fault detection system according to claim 4, characterized in that: The central processor is further configured to send an error signal to the management controller via an error signal line in the general input / output interface when determining that a memory error of a correctable error type occurs in the memory device; The management controller is further configured to generate and report an error log containing information about the faulty memory device when it is determined, based on the error register of the faulty memory device, that a memory error of a correctable error type occurs in the faulty memory device.

6. The memory fault detection system according to claim 3, characterized in that: It also includes a hardware monitoring module, which is connected to the central processing unit and the management controller and has the error signal line between the hardware monitoring module and the central processing unit; the hardware monitoring module includes an error status register for storing error status information corresponding to the error signal.

7. The memory fault detection system according to claim 6, characterized in that: It also includes a memory, which is connected to the central processing unit and the basic input and output system; The central processing unit is further configured to send the error signal to the hardware monitoring module when determining that a memory error of an uncorrectable error type occurs in the memory device; The hardware monitoring module is used to save the error status information to the error status register when receiving the error signal; The management controller is further configured to monitor the error status register, and when determining that the error status information is written in the error status register, enter the step of obtaining the preset memory device information from the processor cache; when determining that the faulty memory device has a memory error of an uncorrectable error type according to the error register of the faulty memory device, add an error mark to the faulty memory device information, and write the faulty memory device information into the memory; Clearing the error status information in the error status register and triggering the server device to restart; The basic input and output system is further used to obtain the faulty memory device information from the memory when the server device is started; and disable the faulty memory device according to the faulty memory device information.

8. A memory fault detection method, characterized in that: Applied to the memory fault detection system according to any one of claims 1 to 7, the method comprising: When the central processing unit determines that a memory error occurs in the memory device, it sends an error signal to the management controller via the error signal line; When receiving the error signal, the management controller obtains preset memory device information from the processor cache; The management controller confirms a faulty memory device in which an error occurs according to an error register of the memory device; The management controller determines the faulty memory device information of the faulty memory device in the memory device information to perform fault processing according to the faulty memory device information.

9. A server device, characterized in that: Comprising a memory fault detection system as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the memory fault detection method according to claim 8 is implemented.

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