Prefetching parameter configuration and cache prefetching method and device and storage medium

Abstract

The embodiment of the invention provides a prefetching parameter configuration and cache prefetching method and device and a storage medium. In the embodiment of the invention, for the processor running the application, multiple prefetching parameter combinations supported by the processor are grouped, and optimization processing is carried out by taking each parameter space obtained by grouping as granularity based on the performance distribution model of the application, so that the search efficiency of the prefetching parameter combinations is improved, the search complexity is reduced, and the search efficiency is improved. The calculation cost is saved; and the value of the hardware module used for prefetching control in the processor is configured based on the optimized prefetching parameter combination, so that the processor can execute the prefetching operation more reasonably by using the optimized prefetching parameter combination, and the performance of the CPU for executing the prefetching operation is improved.

Description

Technical Field

[0001] The present application relates to the field of cloud storage technology, and in particular to a pre-fetch parameter configuration and cache pre-fetch method, device and storage medium. Background Art

[0002] Prefetching is a technology used by the central processing unit (CPU), which can be divided into software prefetching and hardware prefetching. Hardware prefetching is implemented by a dedicated hardware module (referred to as a prefetcher) inside the CPU. The prefetcher inside the CPU can extract instructions or data from slower storage media (such as memory) to faster storage media (such as cache) before they are actually needed, thereby improving CPU execution performance.

[0003] If the prefetch strategy is not well implemented, it is possible that the CPU execution performance will be reduced. Due to limited cache resources, if the prefetch judgment is wrong, useless data will be prefetched, which may cause subsequent useful data to be evicted from the cache, thereby increasing the system's power consumption and reducing the CPU execution performance. Therefore, how to make the CPU use a more reasonable prefetch strategy is a problem to be solved in the current prefetch mechanism. Summary of the invention

[0004] Multiple aspects of the present application provide a prefetch parameter configuration and cache prefetch method, device and storage medium, which are used to configure a prefetch parameter combination for a CPU to improve the performance of the CPU in executing prefetch operations.

[0005] An embodiment of the present application provides a prefetch parameter configuration method, comprising: determining a target application and a target processor responsible for running the target application, the target processor comprising a plurality of hardware modules for prefetch control, and value combinations between the plurality of hardware modules forming a plurality of prefetch parameter combinations; grouping the plurality of prefetch parameter combinations according to the number of the plurality of prefetch algorithms supported by the target processor to obtain a plurality of parameter spaces; optimizing the prefetch parameter combinations for the plurality of parameter spaces according to a performance distribution model of the target application to obtain a target prefetch parameter combination; configuring the values ​​of the plurality of hardware modules according to the target prefetch parameter combination so that the target processor performs a prefetch operation according to the target prefetch parameter combination.

[0006] An embodiment of the present application also provides a cache prefetch method, which is applied to a target processor running a target application, the target processor including multiple hardware modules for prefetch control, the values ​​of the multiple hardware modules being configured according to the prefetch parameter configuration method provided in the embodiment of the present application; the method including: reading the values ​​of the multiple hardware modules, combining the values ​​of the multiple hardware modules to form a target prefetch parameter combination for prefetch control; and performing a prefetch operation based on the target prefetch parameter combination during the running of the target application.

[0007] An embodiment of the present application also provides an electronic device, comprising: a memory and a processor; the memory is used to store a computer program; the processor is coupled to the memory and is used to execute the computer program to implement each step in the pre-fetch parameter configuration method provided in the embodiment of the present application.

[0008] An embodiment of the present application also provides a processor, which is responsible for running a target application. The processor includes: multiple hardware modules for prefetching control, the values ​​of the multiple hardware modules are configured according to the prefetching parameter configuration method provided in the embodiment of the present application, and the processor is used to implement the steps in the cache prefetching method provided in the embodiment of the present application.

[0009] The embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements each step in the prefetch parameter configuration method or cache prefetch method provided in the embodiment of the present application.

[0010] In an embodiment of the present application, for a processor running an application, multiple prefetch parameter combinations supported by the processor are grouped, and optimization processing is performed based on the performance distribution model of the application with each parameter space obtained by the grouping as the granularity, thereby improving the search efficiency of the prefetch parameter combination, reducing the search complexity, and saving computing costs; the value of the hardware module used for prefetch control in the processor is configured based on the optimized prefetch parameter combination, so that the processor can more reasonably perform prefetch operations with the optimized prefetch parameter combination, thereby improving the performance of the CPU in performing prefetch operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0012] Figure 1a A schematic diagram of an instruction pipeline of a processor core provided for an exemplary embodiment of the present application;

[0013] Figure 1b A schematic diagram of a pre-fetch register and its pre-fetch parameters provided for an exemplary embodiment of the present application;

[0014] Figure 1c A schematic diagram of a cache prefetching process provided for an exemplary embodiment of the present application;

[0015] Figure 2a A flowchart of a method for configuring pre-fetch parameters provided by an exemplary embodiment of the present application;

[0016] Figure 2b A state diagram of a task configuration interface provided for an exemplary embodiment of the present application;

[0017] Figure 2c A schematic diagram of a flow chart of optimizing a pre-fetch parameter combination for any parameter space provided by an exemplary embodiment of the present application;

[0018] Figure 3 A schematic diagram of a flow chart of a cache pre-fetching method provided for an exemplary embodiment of the present application;

[0019] Figure 4 A schematic diagram of the structure of a pre-fetch parameter configuration device provided by an exemplary embodiment of the present application;

[0020] Figure 5 A schematic diagram of the structure of a cache pre-fetching device provided for an exemplary embodiment of the present application;

[0021] Figure 6 A schematic structural diagram of an electronic device provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0023] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0024] Multiple applications are usually run on some traditional physical servers, and the CPU resources of the physical servers are shared by multiple applications. The memory access mode and read / write rules of applications are different, and choosing different prefetch strategies will have different performance effects on the applications. However, when multiple applications are running on a physical server, only one prefetch strategy can be configured for the CPU, which will lose sight of one thing while focusing on another. One prefetch strategy cannot bring performance advantages to all applications.

[0025] With the development of virtualization technology and cloud computing technology, various cloud computing scenarios have emerged, such as public cloud, private cloud, and hybrid cloud. In cloud computing scenarios, users can purchase or deploy virtualization instances, such as virtual machines, containers, cloud hosts, and Elastic Compute Service (ECS). In some application scenarios, independent physical operating environments and independent physical resources can be allocated to virtualized instances. For example, virtualized instances have independent computing resources, storage resources, and network resources. In some application scenarios, the independent computing resources of virtualized instances include one or more CPU resources. This provides conditions for controlling cache prefetching algorithms from the perspective of virtualized instances.

[0026] Furthermore, considering that virtualized instances are usually scheduled according to the cluster dimension in cloud computing scenarios, that is, the scheduled virtualized instances usually deploy the same application, and the various resources allocated to the virtualized instance mainly serve the same application, for example, the CPU allocated to the virtualized instance is responsible for running an application. On this basis, the CPU can be personalized for cache pre-fetching control from the application dimension in the virtualized instance, so that the CPU can perform pre-fetching operations more reasonably during the application running process, and pre-read data and / or instructions from the memory to the cache, or from the third-level cache to the second-level cache, or from the second-level cache to the first-level cache, to solve various problems encountered in the memory during the running of some applications, such as low cache hit rate, insufficient memory bandwidth resources, memory contention and other problems.

[0027] In this embodiment, the number of applications deployed in the virtualization instance is not limited, and it can be one or more. Regardless of the number of applications carried in the virtualization instance, for applications that can be assigned to independent processors, the scheme provided in the embodiment of the present application can be used to configure pre-fetch parameters for the processors assigned to them. In addition, it should be noted that in some application scenarios, the use of virtualization instances to carry applications can ensure that the applications have relatively independent physical resources (including independent processor resources) to a certain extent, but virtualization instances are not the only technical means that can ensure that applications have independent processor resources. All application scenarios in which applications exclusively occupy processor resources are applicable to the embodiments of the present application, and the application exclusively occupies processor resources by being carried in the virtualization instance is only an application scenario of the embodiments of the present application. Specifically, in the embodiments of the present application, the target application can be determined, and the target processor responsible for running the target application can be determined. The target processor refers to the processor exclusively occupied by the target application, and then based on this, from the dimension of the target application, a more suitable pre-fetch strategy is configured for the target processor. It is explained here that the target application can be assigned to one or more processors, and each processor can be implemented as the target processor in the embodiment of the present application when it is exclusively occupied by the target application.

[0028] In the embodiment of the present application, the cache system of the target processor core is a multi-level system divided according to tasks. In addition, the implementation structure of the core cache system of processors with different architectures, different models, and different manufacturers will be different, which is not limited in the embodiment of the present application. Processors of various architectures, various models, and various manufacturers are applicable to the embodiment of the present application as long as they support the hardware prefetching solution and need to perform prefetching control. The following is an exemplary display of a target processor core, such as Figure 1a As shown, the instruction pipeline of the target processor core includes but is not limited to the following stages: a fetch and decode (Fetch & Decode) stage, an execution (Execution) stage, and a commit and retire (Commit & Retire) stage.

[0029] Among them, the fetch and decode (Fetch & Decode) stage corresponds to the front-end sequential processing (In-Order FrontEnd) module, which includes but is not limited to the following hardware units: Branch Prediction Unit, Decode, Rename & Dispatch Unit, Level 1 Instruction-Cache (L1 I-Cache) Unit, Level 1 Instruction Translation Lookaside Buffer (L1-I-TLB) Unit. Among them, L1 I-Cache is used to store instructions; L1 D-Cache is used to store first-level cache data. L1-I-TLB is used to cache page table entries and determine the physical address of L1-level instructions.

[0030] The execution stage corresponds to the out-of-order back end module, which includes but is not limited to the following hardware units: issue queue, execution unit, load store unit, L1 data translation lookaside buffer (L1 data-TLB, L1 D-TLB) unit, L2 translation lookaside buffer (L2 TLB) unit and L1 data cache (Level 1 data-cache, L1 D-cache) unit. L2 TLB is used to cache page table entries and determine the physical address of L1 cache.

[0031] Among them, the Commit & Retire stage corresponds to the In-Order Instruction Retire module, which includes but is not limited to the following hardware units: Commit & Retire unit.

[0032] The fetch and decode (Fetch & Decode) stage and the execution (Execution) stage also correspond to the core interface (Core-Clure Interface) module, which includes a secondary cache (L2 Cache) unit. Figure 1a The target processor's last level cache (LLC), also known as level 3 cache, is not shown. For some target processors, LLC is optional.

[0033] Among them, the branch prediction unit is used to predict the address of the next instruction, for example, predicting which address the CPU will go to to prefetch instructions; the decoding, renaming and scheduling unit is mainly used to obtain instructions from the L1 I-Cache according to the address predicted by the branch prediction unit, identify the type of instructions, and rename the instructions, and write the renamed instructions into the emission queue in sequence. The execution unit is used to execute the instructions in the emission queue, and the load storage unit provides the data required for the instructions in the emission queue. The commit and exit unit is used to commit the execution results and exit.

[0034] In order to improve the performance of the target application, cache prefetching operations are involved in the above instruction pipeline process. Figure 1c As shown in the figure, the cache prefetching situations can be summarized into the following two types: one is to read data from the low-end storage in advance and write it into the high-end cache, referred to as cache read data, mainly including from L2 Cache->L1 I-Cache / L1 D-Cache, indicating reading instructions from L2Cache to L1 I-Cache or reading data from L2 Cache to L1 D-Cache, and from L2 TLB->L1 I-TLB / L1 D-TLB, indicating reading instruction mapping information from L2 TLB to L1 I-TLB or reading data mapping information from L2TLB to L1 D-TLB; the other is to write dirty pages in high-end storage back to low-end storage in advance, referred to as dirty page writeback, mainly including from L1 D-Cache->L2 Cache, indicating writing dirty pages in L1 D-Cache back to L2 Cache in advance, and from L1 I-TLB / L1 D-TLB->L2 TLB, indicating writing instruction mapping information in L1 I-TLB back to L2 in advance. TLB or write the data mapping information in L1 D-TLB back to L2 TLB in advance. In the embodiment of the present application, the main focus is on the case of cache reading data, that is, the case of pre-reading data from the low-end storage and writing it into the high-end cache.

[0035] In practical applications, there are two pre-fetching methods: soft and hard. Software pre-fetching can insert pre-fetch instructions into the program, use pre-fetch instructions to perform pre-fetching when encoding, or use optimized compilation options when compiling, and use pre-fetch instructions to improve the execution efficiency of the program. Hardware pre-fetching is implemented by a dedicated hardware pre-fetching module (such as a pre-fetcher) inside the target processor. The pre-fetcher is mainly used for data and / or instruction pre-fetching, that is, placing the data that may be used in the relevant cache in advance to wait for use in the relevant cache. In the embodiment of the present application, the hardware pre-fetching method is focused on.

[0036] The target processor supports multiple hardware prefetch algorithms, and different hardware prefetch algorithms are implemented by different prefetchers. Which hardware prefetch algorithm (or prefetcher) the target processor uses and how to use the hardware prefetch algorithm (or prefetcher) to prefetch data and / or instructions can be controlled by multiple hardware modules in the target processor for prefetch control. That is to say, in this embodiment, in addition to the prefetcher, the target processor also includes multiple hardware modules for cache prefetch control. In an optional implementation, the multiple hardware modules for prefetch control can be specifically implemented as multiple prefetch registers. Of course, it can also be other hardware structures other than prefetch registers, which is not limited to this. In the following embodiments of the present application, the multiple hardware modules for prefetch control in the target processor will be specifically implemented as multiple prefetch registers as an example for description.

[0037] The multiple prefetch registers in this embodiment refer to registers used to control cache prefetching of the target processor. It should be noted that the target processor will also include other registers, which are not limited in the embodiments of this application. Among them, each prefetch register is used to control a prefetch parameter, and different prefetch registers represent different prefetch parameters, that is, each prefetch register corresponds to a prefetch parameter, and a prefetch parameter has at least two values. For example, if the prefetch parameter corresponding to the prefetch register is represented by 1 bit (bit), there are two values ​​of the prefetch register: 0 and 1; if the prefetch parameter of the prefetch register is represented by 2 bits, there are four values ​​of the prefetch register: 00, 01, 10 and 11. For the same prefetch register, different values ​​are mutually exclusive, indicating that at the same time, the value of the prefetch register can only be one of them. The value combination between multiple prefetch registers forms a plurality of prefetch parameter combinations, and each prefetch parameter combination represents a prefetch strategy. For example, the prefetch parameter combination may include but is not limited to: which prefetch algorithm the target processor uses, which data to prefetch, when to start prefetching, where the prefetched data is stored, etc. This information can be given by the values ​​of different prefetch registers.

[0038] Optionally, the multiple prefetch registers included in the target processor can be classified according to the prefetch parameters represented. Specifically, the multiple prefetch registers can be divided into two types. One is a prefetch register representing a prefetch algorithm selection parameter, which is mainly used to select whether to use a certain prefetch algorithm (i.e., a prefetcher). It is explained here that the prefetch algorithm mentioned in the embodiment of the present application mainly refers to a hardware prefetch algorithm, i.e., a prefetch algorithm implemented by a prefetcher; the other is a prefetch register representing a prefetch operation execution control parameter, which is mainly used to control how the selected prefetcher performs the prefetch process. There are multiple prefetch registers of this type, which are used to provide different prefetch operation execution control parameters for the prefetcher, for example, determining which block of data the prefetcher prefetches, when to start prefetching data, the amount of prefetched data, the prefetch position, and the storage position of the prefetched data. Among them, the number of prefetch registers representing the prefetch algorithm selection parameter can be 1, and the number of prefetch registers representing the prefetch operation execution control parameter can be multiple, for example, 2, 3, or 10. Accordingly, a prefetch parameter combination, that is, a value combination of multiple prefetch registers, includes prefetch algorithm selection parameters and prefetch operation execution control parameters.

[0039] For example, in Figure 1b The situation of some prefetch registers included in the target processor is schematically given in FIG. The CMC_MIN_WAY register belongs to the prefetch register representing the prefetch algorithm selection parameter, indicating whether to select the Correlated Miss Caching (CMC) algorithm. The CMC algorithm is a hardware prefetch algorithm and a type of temporal prefetcher. It uses part of the L2 cache space to store historical miss information and uses this part of the miss information as metadata (meta) information to prefetch data. If data is prefetched from the memory to the L2 cache, how many bits in the L2 cache need to be reserved for data and how many bits need to be reserved for instructions are controlled by the L2_DATA_PART register and the L2_INST_PART register respectively. The L2 cache data part (L2_DATA_PART) register and the L2 cache instruction part (L2_INST_PART) register belong to the prefetch register representing the execution control parameter of the prefetch operation. The value of the L2_DATA_PART register and the L2_INST_PART register can have multiple situations. Figure 1bIn the example, it is assumed that the parameters of the L2_DATA_PART register and the L2_INST_PART register are both represented by 3 bits, and each has 8 values; if the value of the L2_DATA_PART register is 000, it means that 0 bits are reserved for data in the L2 cache, which is a reset value; if the value of the L2_DATA_PART register is 001, it means that 1 bit is reserved for data in the L2 cache; if the value of the L2_INST_PART register is 111, it means that 7 bits are reserved for instructions in the L2 cache; if the value of the L2_INST_PART register is 101, it means that 5 bits are reserved for instructions in the L2 cache. Different combinations of values ​​of the L2_DATA_PART register and the L2_INST_PART register will form different prefetching schemes, and different prefetching schemes will produce different target application performance during the operation of the target application.

[0040] In this embodiment, each pre-fetch register has at least two values, and there are many combinations of values ​​between multiple pre-fetch registers, which can be expressed as 2 n , n represents the total number of bits involved in multiple prefetch registers. In the embodiment of the present application, a value combination of multiple prefetch registers is called a prefetch parameter combination. How to select a more suitable prefetch parameter combination from so many prefetch parameter combinations and configure it to the prefetch registers, so as to achieve prefetch control of the target processor, is the key problem to be solved in the embodiment of the present application. In other words, the main goal of this embodiment is to select a more suitable prefetch parameter combination from a variety of prefetch parameter combinations, and configure the selected more suitable prefetch parameter combination as a plurality of prefetch registers included in the target processor, so that the target processor performs cache prefetch operations for the target application according to the more suitable prefetch parameter combination, so as to improve the performance data of running the target application.

[0041] Among them, the target processor performs prefetch operations under the control of different prefetch parameter combinations to bring different performance improvements to the target application. In the embodiment of the present application, the performance of the prefetch parameter combination to the target application can be judged from the two dimensions of coverage and accuracy. For example, for coverage, when the prefetch parameter configuration algorithm is not used, 100 cache misses occur. When the prefetch parameter combination Z is determined using the prefetch parameter configuration method, the cache miss is reduced to 30 times, which means that the prefetch parameter combination Z successfully avoids 70 cache misses, that is, the coverage is 70 / 100=70%. For another example, for accuracy, considering the number of prefetch data executed by the prefetch algorithm of the prefetch parameter combination, the prefetch parameter combination Z performs 140 prefetch operations, of which 70 are valid, then the accuracy is 70 / 140=50%. In the embodiment of the present application, a prefetch parameter combination that can bring better performance improvement to the target application can be selected from a plurality of prefetch parameter combinations, which is referred to as selecting a better prefetch parameter combination from a plurality of prefetch parameter combinations.

[0042] Among them, a simple method for selecting a better prefetch parameter combination is: for each prefetch parameter combination, the values ​​in the prefetch parameter combination are respectively configured as the values ​​of multiple prefetch registers of the target processor, so that the target processor can perform a prefetch operation under the control of the prefetch parameter combination in the process of running the target application, and obtain the performance data brought by the prefetch operation to the target application, so that by running each prefetch parameter combination once, the performance data brought by each prefetch parameter combination to the target application can be obtained, and then the prefetch parameter combination with better performance data is selected as the prefetch parameter combination used by the target processor to finally perform cache prefetch. However, there are many types of prefetch parameter combinations. For example, the target processor in the above processes A, B and C performs a prefetch operation involving 35 groups of prefetch registers, and there are 2^56 prefetch parameter combinations between the 35 groups of prefetch registers. The search space is very large, and it takes time to run each prefetch parameter combination. Then, running all the 2^56 prefetch parameter combinations once will consume a lot of time. Obviously, it is impossible to get a better solution by directly traversing multiple prefetch parameter combinations.

[0043] In order to improve the search efficiency of prefetch parameter combinations, in an embodiment of the present application, multiple prefetch parameter combinations are grouped from the dimensions of multiple prefetch algorithms supported by the target processor, and the prefetch parameter combinations are optimized according to the grouping, and a better prefetch parameter combination is selected therefrom. The search space of the prefetch parameter combinations is reduced by grouping, the configuration efficiency of the prefetch parameters is improved, and the configuration cost is saved.

[0044] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0045] Figure 2a The following is a flow chart of a method for configuring pre-fetch parameters provided by an exemplary embodiment of the present application. Figure 2a As shown, the method includes:

[0046] 101. Determine a target application and a target processor responsible for running the target application, wherein the target processor includes a plurality of hardware modules for prefetch control, and value combinations between the plurality of hardware modules form a plurality of prefetch parameter combinations;

[0047] 102. According to the number of prefetch algorithms supported by the target processor, group the prefetch parameter combinations to obtain a plurality of parameter spaces;

[0048] 103. According to the performance distribution model of the target application, optimizing the pre-fetch parameter combination in the plurality of parameter spaces to obtain a target pre-fetch parameter combination;

[0049] 104. According to the target prefetch parameter combination, configure values ​​of multiple hardware modules for prefetch control, so that the target processor performs a prefetch operation according to the target prefetch parameter combination.

[0050] The method provided in this embodiment is used to configure a personalized and targeted prefetch parameter combination for the CPU from the perspective of the application, so that the CPU can more reasonably perform prefetch operations according to the configured prefetch parameter combination, thereby improving the performance of the CPU in performing prefetch operations during the operation of the target application, thereby improving the operation performance of the target application.

[0051] In this embodiment, the target application is not limited, and can be any application that needs to be run by the target processor, such as video applications, online shopping applications, instant messaging applications, novel applications, email service applications, taxi applications, map applications, game applications, etc. The embodiment of the present application also does not limit the model, specification, and manufacturer of the target processor, and any processor that supports the hardware prefetching solution and requires prefetching control is applicable to the embodiment of the present application.

[0052] In the embodiment of the present application, the implementation method of determining the target application and the target processor responsible for running the target application is not limited, and an exemplary description is given below.

[0053] Example A1:In this example, the person responsible for pre-fetch parameter configuration (such as the tenant corresponding to the target application, the relevant personnel of the cloud computing scenario, etc.) is allowed to send the pre-fetch parameter configuration task through the terminal device used by him, and carry the description information of the target application and the description information of the target processor in the pre-fetch parameter configuration task. Among them, the description information of the target application may include but is not limited to: the type information, name information, function information, etc. of the target application; among them, the type information of the target application may be live broadcast, social, learning, shopping or game, etc. The description information of the target processor may include but is not limited to: model, version, manufacturer, device identification, internal architecture, pre-fetch capability, etc. Accordingly, the execution subject of the embodiment of the present application may be various electronic devices, which can receive the pre-fetch parameter configuration task, determine the target application according to the description information of the target application, and determine the target processor responsible for running the target application according to the description information of the target processor.

[0054] Example A2: In this example, the task configuration interface can be displayed to the person responsible for configuring the prefetch parameters, such as Figure 2b As shown, the task configuration interface includes application configuration options and processor configuration options; the person responsible for pre-fetch parameter configuration can perform configuration operations on the application configuration options and processor configuration options. For example, the application configuration options include: a first option name and its corresponding first option value list or input box, the first option name indicates that the application is to be configured, if it is a first option value list, then the list contains multiple information items for describing the application, which can be selected; if it is an input box, it allows input of information for describing the application; the configuration of the application configuration options can be implemented as follows: the person responsible for pre-fetch parameter configuration either selects one or more information items from the first option value list to describe the target application, or enters multiple information in the input box to describe the target application. Similarly, the processor configuration options include: a second option name and its corresponding second option value list or input box, the second option name indicates configuring the processor, if it is a second option value list, then the list contains multiple information items for describing the processor, which can be selected; if it is an input box, it allows input of information for describing the processor; configuring the application configuration options can be implemented as: the person responsible for pre-fetching parameter configuration either selects one or more information items from the second option value list to describe the target processor, or enters multiple information in the input box to describe the target processor. Accordingly, in response to the configuration operations of the application configuration options and the processor configuration options, the description information of the target application and the target processor can be obtained, and then the target application and the target processor can be determined based on the description information of the target application and the target processor. Among them, the task configuration interface can be a remote command interface, a web page, or an application page, which is not limited. In addition, Figure 2b The style of the task configuration interface shown is only an example and is not limited to this.

[0055] When the target application and the target processor are determined, the number of the multiple prefetch algorithms supported by the target processor and the multiple prefetch parameter combinations formed by the value combinations between the multiple hardware modules included in the target processor for prefetch control are also determined. For ease of description and understanding, in the subsequent content of this embodiment, multiple hardware modules will be implemented as multiple prefetch registers as an example for description. In order to facilitate more rapid selection of a more suitable target prefetch parameter combination from a variety of prefetch parameter combinations, in an embodiment of the present application, according to the number of the multiple prefetch algorithms supported by the target processor, the multiple prefetch parameter combinations are grouped to obtain multiple parameter spaces, each parameter space includes a part of the prefetch parameter combination, and the parameter space obtained by grouping in this embodiment is used as the granularity, and the multiple parameter spaces are optimized for the prefetch parameter combination, thereby obtaining the target prefetch parameter combination. Among them, grouping multiple prefetch parameter combinations mainly refers to selecting some prefetch parameter combinations related to each prefetch algorithm from multiple prefetch parameter combinations, and using some prefetch parameter combinations related to the prefetch algorithm as the parameter space of the prefetch algorithm. The parameter space of the prefetch algorithm does not include prefetch parameter combinations that are not related to the prefetch algorithm. Therefore, the search space of the parameter space can be reduced, which is beneficial to improving the optimization efficiency of the prefetch parameters.

[0056] In the embodiment of the present application, the implementation method of grouping multiple prefetch parameter combinations according to the number of multiple prefetch algorithms supported by the target processor is not limited. In an optional embodiment, considering that the prefetch operation execution control parameters required by each prefetch algorithm are not exactly the same, that is, the prefetch registers that different prefetch algorithms need to rely on are not exactly the same, in view of this, for each prefetch algorithm, multiple prefetch registers can be divided into two categories, namely, a first group of prefetch registers that affect the prefetch algorithm and a second group of prefetch registers that do not affect the prefetch algorithm. The first group of prefetch registers may include one or more prefetch registers; the second group of prefetch registers may include one or more prefetch registers. In the embodiment of the present application, it is not limited how to determine which prefetch register is related to which prefetch algorithm or algorithms, and which prefetch register is not related to which prefetch algorithm or algorithms.

[0057] In an optional embodiment, in the process of designing various prefetch algorithms, the prefetch operation execution control parameters related to the prefetch algorithm can be determined, and the prefetch registers related to these prefetch operation execution control parameters are used as the prefetch registers related to the prefetch algorithm, and other prefetch registers are used as prefetch registers unrelated to the prefetch algorithm, that is, whether the value of the prefetch register will affect a certain prefetch algorithm is known and is set when the target processor leaves the factory. In another optional embodiment, it is possible to determine which prefetch registers are related to a prefetch algorithm and which prefetch registers are unrelated to the prefetch algorithm by means of online testing. Specifically, for a certain prefetch algorithm, it is determined whether the prefetch register Y affects the prefetch algorithm, and Y can be set to valid or invalid respectively, and the values ​​of other prefetch registers are kept unchanged, and the corresponding prefetch parameter combination H1 and prefetch parameter combination H2 are obtained when the prefetch register Y is valid and invalid respectively. According to the prefetch parameter combination H1 and the prefetch parameter combination H2, the prefetch register values ​​of the target processor are configured respectively, so that the target processor runs the target application, and the performance data J1 and performance data J2 are obtained respectively. If the performance difference between the performance data J1 and the performance data J2 is less than the set performance difference threshold, it is considered that the prefetch register Y does not affect the prefetch algorithm. If the performance difference between the performance data J1 and the performance data J2 is greater than or equal to the set performance difference threshold, it is considered that the prefetch register Y affects the prefetch algorithm. In this way, it is determined in turn whether each prefetch register affects the prefetch algorithm, and finally the prefetch registers related to the prefetch algorithm and the prefetch registers that are not related are obtained.

[0058] Among them, for any prefetch register, the value of the prefetch register can be divided into two cases, valid and invalid, according to whether it will affect a certain prefetch algorithm from the perspective of the prefetch algorithm, that is, if the prefetch register has an impact on the prefetch algorithm, the various values ​​of the prefetch register are valid for the prefetch algorithm; if the prefetch register has no impact on the prefetch algorithm, a value can be set for the prefetch algorithm to indicate that the prefetch register is invalid for the prefetch algorithm, and this value is called an invalid value. For example, if the value of the prefetch register is 1 bit, then when the prefetch register has no impact on a certain prefetch algorithm, the value of the prefetch register can be set to 0 or 1 for the prefetch algorithm, and 0 or 1 is an invalid value; if the value of the prefetch register is 2 bits, then when the prefetch register has no impact on a certain prefetch algorithm, the value of the prefetch register can be set to one of the four values ​​for the prefetch algorithm, such as 00 or 01, and 00 or 01 is an invalid value. For each prefetch register, its invalid value for a certain prefetch algorithm can be preset when the target processor leaves the factory, and there is no limitation on which specific value indicates invalidity for a certain prefetch algorithm.

[0059] Based on the above analysis, a method for grouping multiple prefetch parameter combinations according to the number of multiple prefetch algorithms supported by the target processor to obtain multiple parameter spaces includes: for any prefetch algorithm, determining a first group of prefetch registers that will affect the prefetch algorithm and a second group of prefetch registers that will not affect the prefetch algorithm among multiple prefetch registers; from the multiple prefetch parameter combinations, selecting some expected parameter combinations in which the values ​​of the first group of prefetch registers are valid and the values ​​of the second group of prefetch registers are invalid as the parameter space corresponding to the prefetch algorithm. For example, the target processor involves three prefetch registers for cache prefetching, which are denoted as registers R1-R3. The prefetch algorithm M1 is related to two prefetch registers, which are denoted as registers R1 and R2. Assume that these two registers use 1 bit and their values ​​are 0 or 1, and are independent of the other prefetch register, denoted as register R3. Assume that this register uses 2 bits and its values ​​can be 00, 01, 10 or 11, then the two registers related to the prefetch algorithm M1 can be divided into the first group of prefetch registers, including registers R1 and R2, and the prefetch register that is not related to the prefetch algorithm M1 can be divided into the second group of prefetch registers, including register R3; for the prefetch algorithm M1, the various values ​​of each prefetch register in the first group of prefetch registers, that is, 0 or 1, are valid for the prefetch algorithm M1. , each prefetch register in the second group of prefetch registers has an invalid value indicating that it does not affect the prefetch algorithm M1. It is assumed that the value indicating that the register R3 is invalid for the prefetch algorithm M1 is 00; based on this, these three prefetch registers form 16 prefetch parameter combinations including: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. Therefore, from the 16 prefetch parameter combinations, the prefetch parameter combination corresponding to the first group of prefetch registers in which all the values ​​are valid and corresponding to the second group of prefetch registers in which all the values ​​are invalid can be selected, that is, 0000, 0100, 1000, 1100, as the parameter space corresponding to the prefetch algorithm M1. It is explained here that in the above embodiment, three prefetch registers are taken as an example to illustrate how to obtain the parameter space corresponding to the prefetch algorithm based on the prefetch algorithm. In actual applications, it is not limited to three prefetch registers. There may be many prefetch registers related to and unrelated to the prefetch algorithm. For example, the prefetch algorithm M1 may be related to 25 prefetch registers and unrelated to the other 10 prefetch registers. However, no matter how many prefetch registers there are, the principle is the same.

[0060] After obtaining the parameter space corresponding to each prefetching algorithm, the prefetching parameter combination of multiple parameter spaces can be optimized according to the performance distribution model of the target application and the parameter space corresponding to each prefetching algorithm as the granularity to obtain the target prefetching parameter combination. In this embodiment, the performance distribution model of the target application can reflect the performance distribution of the target application when it is actually running under various prefetching parameter combinations, and to a certain extent can achieve the effect of simulating the operation of the target application. Among them, the optimization of the prefetching parameter combination of multiple parameter spaces according to the performance distribution model refers to the process of selecting, for each parameter space, some prefetching parameter combinations with relatively better performance from the parameter space according to the performance distribution of the target application when it is actually running under various prefetching parameter combinations reflected by the performance distribution model, and finally selecting the target prefetching parameter combination from the some prefetching parameter combinations with relatively better performance selected from each parameter space.

[0061] In the present embodiment, in order to select the target pre-fetch parameter combination, each pre-fetch parameter combination can be used as an independent variable X, and the operating performance data of the target application in the actual operating environment according to each pre-fetch parameter combination can be used as a dependent variable Y, and the actual operating environment of the target application is regarded as a black box system composed of the target application-operating system-hardware system, which is represented by an objective function. Among them, X can be input into the objective function to obtain Y. The goal of the embodiment of the present application is to find the value of X when Y is better. Since the relationship between X and Y is more complicated, the objective function is not necessarily a convex function, and the traditional gradient descent method may no longer be applicable. Therefore, in the present embodiment, a performance distribution model is constructed for the target application, and the prior distribution of the objective function is assumed by the performance distribution model, that is, the performance distribution model is used to replace the objective function, and then according to the performance distribution model of the target application, the optimization process of the pre-fetch parameter combination is performed on multiple parameter spaces to obtain the target pre-fetch parameter combination.

[0062] In the embodiment of the present application, the performance distribution model used is not limited. The performance distribution model is a distribution function. Any distribution function that can reflect the performance distribution of the target application when it is actually running under various pre-fetch parameter combinations is applicable to the embodiment of the present application. In an optional embodiment, the pre-fetch parameter combination and the performance data of the target application can be sampled, and a performance distribution model is constructed for the target application based on the sampled data. Specifically, a plurality of pre-fetch parameter combinations are initially sampled to obtain at least one initial pre-fetch parameter combination. For example, the initial sampling can be random sampling or quantitative sampling, such as setting the number of samples, which can be 10, 100 or 500, etc., which is not limited. Then, at least one initial pre-fetch parameter combination is respectively configured to multiple pre-fetch registers of the target processor, and the target processor is controlled to run the target application based on the values ​​in the multiple pre-fetch registers to obtain at least one initial performance data brought to the target application by the target processor when the target application is running according to these initial pre-fetch parameter combinations; according to at least one initial pre-fetch parameter combination and at least one initial performance data, a distribution function representing the performance data of the target application about the pre-fetch parameter combination is constructed as a performance distribution model.

[0063] Exemplarily, taking three prefetch registers R1-R3 as an example, and assuming that registers R1 and R2 use 1 bit and register R3 uses 2 bits, these three prefetch registers form 16 prefetch parameter combinations including: 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111; these 16 prefetch parameter combinations can be initially sampled, for example, assuming that four initial prefetch parameter combinations are selected, namely 0000, 0110, 1010 and 1110, each initial prefetch parameter combination represents a prefetch strategy, which includes selecting which prefetch algorithm to use and some control parameters required for the prefetch algorithm to perform the prefetch operation, such as when to perform the prefetch operation, the prefetch How much data is fetched, where the prefetched data is stored in the cache, etc.; then, the four initial prefetch parameter combinations are respectively configured to the three prefetch registers R1-R3 in the target processor. For example, the initial prefetch parameter combination 0000 is configured to the three prefetch registers R1-R3, then the value of R1 in the three prefetch registers is 0, the value of R2 is 0, and the value of R3 is 00. Assume that the value of R1 is 0, which indicates that the prefetch algorithm M0 is selected, the value of R2 is 0, which indicates that the prefetch operation is performed at time t, and the value of R3 is 00, which indicates that the amount of data d0 is prefetched from the memory to L1-cache; after the initial prefetch parameter combination 0000 is configured to the three prefetch registers R1-R3, the target application can be started. At this time, the target processor will run the target application. During the running of the target application, the target processor will preferentially fetch data from L1 Instructions or data are read from the I-Cache / L1 D-Cache. In this process, the prefetch algorithm M0 can be determined to be used according to the values ​​of the three prefetch registers R1-R3, and the prefetch operation is performed when the time t arrives. Specifically, data with a data volume of d0 is read from the memory and the read data is written into the L1 D-cache; the prefetch operation under the control of the initial prefetch parameter combination 0000 will affect the cache hit rate of the target processor, thereby affecting the operating efficiency of the target processor, and indirectly affecting the operating performance of the target application, such as the response speed of the target application, whether the flash back occurs due to insufficient memory, etc. Therefore, the performance data of the target application under the initial prefetch parameter combination 0000 can be obtained. By analogy, the initial prefetch parameter combinations 0110, 1010 and 1110 can be configured to the three prefetch registers R1-R3 in sequence, and the target processor can be controlled to run the target application under different initial parameter combinations in sequence, and the performance data of the target application under the initial prefetch parameter combinations 0110, 1010 and 1110 can be obtained in sequence.After obtaining the performance data of the target application under the initial prefetch parameter combinations 0000, 0110, 1010 and 1110, a statistical analysis of the probability distribution can be performed based on the initial prefetch parameter combinations 0000, 0110, 1010 and 1110 and the performance data of the target application under the initial prefetch parameter combinations 0110, 1010 and 1110 to obtain.

[0064] If the initial prefetch parameter combination 0000 is a better combination, then the data prefetched into the L1 D-cache is likely to be required by the target processor, and can be prefetched into the L1 D-cache before the target processor reads it, which can improve the operating efficiency of the target processor, so that the target application has better operating performance, and the distribution function of the performance data of the target application with respect to the prefetch parameter combination can be obtained. Optionally, in an embodiment of the present application, it is believed that the performance data of the target application with respect to the prefetch parameter combination conforms to the Gaussian distribution, that is, the Gaussian distribution function can be used as the performance distribution model of this embodiment, that is, the prefetch parameter combination and the performance data brought to the target application by the target processor during the operation of the target application according to the prefetch parameter combination are subject to the Gaussian distribution.

[0065] In an optional embodiment, when a performance distribution model is obtained, the performance distribution model can be used to perform optimization processing on multiple parameter spaces by pre-fetching parameter combinations. The number of iterations of the optimization processing T can be set, where T is a positive integer, that is, each parameter space is subjected to T rounds of optimization processing on the pre-fetched parameter combinations, and T is less than the number of pre-fetched parameter combinations in the parameter space, which is beneficial to reducing the number of pre-fetched parameter combinations that need to be processed during the optimization process, saving resources and improving efficiency. The value of T can be flexibly set according to the accuracy requirements of the optimization process. See Figure 2c As shown, a method for optimizing the prefetch parameter combinations of multiple parameter spaces according to a performance distribution model to obtain a target prefetch parameter combination includes: for any parameter space, according to the performance distribution model, performing T rounds of optimization processing on the prefetch parameter combinations in the parameter space to obtain T types of prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T types of prefetch parameter combinations; according to the T target performance data, selecting the target prefetch parameter combination from the T types of prefetch parameter combinations. The performance distribution model can be updated according to the prefetch parameter combinations and target performance data obtained after each round of optimization processing, so that the performance distribution model is continuously updated in the T rounds of optimization processing. During the optimization process, the quality of the prefetch parameter combination selected based on the performance distribution model can be improved by continuously updating the performance distribution model.

[0066] Alternatively, see Figure 2cFor any round of optimization processing, a sampling function (acquisition function) can be used, combined with the performance distribution model of the previous round, to perform sampling of the prefetch parameter combinations in the parameter space in this round to obtain the prefetch parameter combinations of this round; the target processor can be controlled to run the target application according to the prefetch parameter combinations of this round to obtain the target performance data of this round. Specifically, each value in the prefetch parameter combination of this round is configured as the value of the corresponding prefetch register in the target processor, and the target processor is controlled to run the target application. During the operation of the target application, a prefetch operation is performed according to the values ​​of multiple prefetch registers (i.e., the prefetch parameter combination of this round), and then the performance data brought by the prefetch operation to the target application is obtained as the target performance data of this round; then, according to the prefetch parameter combination of this round and the target performance data of this round, the performance distribution model of the previous round is updated to obtain the performance distribution model of this round. Among them, for the first round of optimization processing, a sampling function is used, combined with the initial performance distribution model constructed for the target application, to perform sampling of the pre-fetch parameter combinations in the parameter space in this round, and obtain the pre-fetch parameter combinations of this round; the pre-fetch parameter combinations of this round are configured to multiple pre-fetch registers of the target processor, and the target processor is controlled to run the target application based on the values ​​in the multiple pre-fetch registers to obtain the target performance data of this round; according to the pre-fetch parameter combinations of this round and the target performance data of this round, the performance distribution model created for the target application is updated to obtain the performance distribution model of this round. After obtaining the performance distribution model of this round, it also includes adding 1 to the iteration round and judging whether the iteration round has reached T times. If not, continue to the next round of iteration; if it reaches T times, end the iteration process.

[0067] Among them, the sampling function is mainly used to select new pre-fetch parameter combinations, and it is necessary to balance exploitation and exploration in the selection process. Among them, the sampling function can balance "exploitation" and "exploration" based on the mean and variance of the performance distribution model to find the sampling points (i.e., pre-fetch parameter combinations) for the next round of optimization processing. "Exploitation" means sampling more pre-fetch parameter combinations near the currently known pre-fetch parameter combinations as much as possible for the performance distribution information. Sampling in areas with higher means in the performance distribution information may obtain local optimal solutions, that is, the pre-fetch parameter combinations with the best performance data. "Exploration" means obtaining more unknown pre-fetch parameter combinations, such as sampling in areas with higher variance in the performance distribution information, which is more likely to find the globally optimal pre-fetch parameter combination for performance data. Among them, the sampling function may include but is not limited to: Upper Confidence Bound (UCB), Expected Improvement (EI), and Probability of Improvement (PI) models.

[0068] Further optionally, for any round of optimization processing, combined with the performance distribution model of the previous round, the performance distribution information that the pre-fetch parameter combination of this round needs to meet is obtained. For example, according to the pre-fetch parameter combination of the previous round and its corresponding performance data, the variance and kernel function of the given performance distribution model of the previous round, the performance distribution information that the pre-fetch parameter combination of this round needs to meet can be obtained, and the performance distribution information can be represented by the variance and mean of the performance distribution model of the previous round. According to the sampling function and the performance distribution information, a group of pre-fetch parameter combinations whose performance loss meets the preset conditions are selected as the pre-fetch parameter combination of this round. Among them, the sampling function can determine multiple candidate pre-fetch parameter combinations according to the performance distribution information, and estimate the performance loss of multiple candidate pre-fetch parameter combinations. Among them, the preset conditions are not limited. For example, the pre-fetch parameter combination with the smallest performance loss can be used as the pre-fetch parameter combination of this round; for another example, the candidate pre-fetch parameter combination with a performance loss less than the set first performance loss threshold can be determined, and the pre-fetch parameter combination is randomly selected from the candidate pre-fetch parameter combination with a performance loss less than the set first performance loss threshold as the pre-fetch parameter combination of this round.

[0069] Optionally, the implementation method of selecting a target prefetch parameter combination from T prefetch parameter combinations according to T target performance data is not limited. For example, according to the T target performance data corresponding to the optimized T prefetch parameter combinations, the prefetch parameter combination with the best target performance data is selected from the T prefetch parameter combinations as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the optimized T prefetch parameter combinations, a preliminary prefetch parameter combination with a performance loss less than a set second performance loss threshold is determined from the T prefetch parameter combinations, and one is randomly selected from the preliminary prefetch parameter combinations as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the optimized T prefetch parameter combinations, a prefetch parameter combination with a target performance data within a set range is selected from the T prefetch parameter combinations as the target prefetch parameter combination. For another example, according to the T target performance data corresponding to the optimized T prefetch parameter combinations, a prefetch parameter combination with a target performance data greater than a set performance threshold is selected from the T prefetch parameter combinations as the target prefetch parameter combination.

[0070] After obtaining the target prefetch parameter combination, the values ​​of multiple prefetch registers can be configured according to the target prefetch parameter combination, so that the target processor performs the prefetch operation according to the target prefetch parameter combination. Specifically, each value in the target prefetch parameter combination is configured as the value of the corresponding prefetch register in the multiple prefetch registers, so that the target processor can perform the prefetch operation according to the target prefetch parameter combination corresponding to the values ​​of the prefetch registers and the target prefetch parameter combination corresponding to the values ​​in the process of running the target application.

[0071] In this embodiment, the performance distribution of the target application reflected by the performance distribution model during actual operation under various pre-fetch parameter combinations is used to optimize the pre-fetch parameter combinations of multiple parameter spaces to obtain the optimized partial pre-fetch parameter combinations. The more complex functional relationship between the pre-fetch parameter combination and the performance data is no longer directly expressed, but the performance distribution is used, which has the advantages of simple implementation and high efficiency; then, in conjunction with the actual operating environment, the selected part of the pre-fetch parameter combination is actually operated by the target processor to obtain the target performance data corresponding to the target application. The actual operating environment here can be the actual production environment where the target application is located, or it can be a test environment built for pre-fetching parameter adjustment, which is not limited. Compared with the above-mentioned method of running the pre-fetch parameter combinations one by one, the method provided in the embodiment of the present application only needs to actually run a small number of pre-fetch parameter combinations obtained by optimization, which has higher efficiency, can quickly select the pre-fetch parameter combination with better performance, and can be applied online in time, and can have better cache pre-fetch performance at the beginning of the target application online, and can also continuously update the pre-fetch parameter combination offline to continuously optimize the performance data of the target application.

[0072] In an alternative embodiment, considering Figure 1b The performance of the three prefetch registers A / B / C in the L1-L2-LLC-Memory process affects each other, and the impact on the performance is continuous, so the objective function can be regarded as continuously differentiable and differentiable. Based on this, in this embodiment, all optimization algorithms that can implement the prefetch parameter configuration method are applicable to the embodiments of this application. An example of an optimization algorithm is provided below: According to the Sequential Model-based Global Optimization (SMBO) algorithm, a method for searching for CPU cache prefetch parameter combinations in the parameter space for target applications is designed, which is called the optimized SMBO algorithm (Optimized SMBO, OSMBO).

[0073] The principle of OSMBO algorithm: The parameters involved in OSMBO algorithm are (f, M, T, S), f represents the objective function, M is the performance distribution model created by the target application, T represents the maximum number of iterations, the real-time iteration number is represented by t, S is the sampling function, H[n] = (x 1：k ,f(x 1：k )) is the performance data of the target application, and x is the prefetch parameter combination.

[0074] Step 1: According to the number N of prefetch algorithms supported by the target processor, multiple prefetch parameter combinations are grouped to obtain N parameter spaces, and an optimal prefetch parameter combination is searched in each parameter space.

[0075] Step 2: For each parameter space, according to the performance data function H[n]=(x 1：k ,f(x 1：k ))Update the performance distribution model M; at this time, H[n] records the performance data of k prefetch parameter combinations.

[0076] Step 3: Determine the next prefetch parameter combination x through the sampling function S and the updated performance distribution model M k+1 ;

[0077] Step 4: Use the objective function to obtain a new pre-fetch parameter combination x k+1 Performance data f(x k+1 ), and the performance data of the new prefetch parameter combination (x k+1 ,f(x k+1 )) is added to H[n];

[0078] Step 5: Repeat steps 2-4 until the number of real-time iterations t in each parameter space reaches T;

[0079] Step 6: After all iterations of the parameter space are completed, the prefetch parameter combination with the best performance is selected from the prefetch parameter combinations selected in the iteration process, and is output as the target prefetch parameter combination.

[0080] Step 7: Configure the values ​​of the corresponding prefetch registers of the target processor according to the target prefetch parameter combination, so that the processor performs a prefetch operation according to the values ​​of the multiple prefetch registers.

[0081] In this embodiment, personalized pre-fetch parameter configuration can be performed for the target application, which can effectively solve the performance problem of a single application, and at the same time make the negative impact of other software and hardware caused by the pre-fetch parameter configuration for the target application more controllable; in addition, in the process of pre-fetch parameter configuration for the target application, the OSMBO algorithm is used for tuning and the pre-fetch parameter combinations are grouped, which can reduce the dimension of the parameter search space, for example, from 35 dimensions to within 20 dimensions, thereby reducing the search complexity and search cost; furthermore, the use of the OSMBO algorithm to configure the pre-fetch parameter combination for the target application is more effective than the traditional method of tuning based on manual experience, and the higher degree of automation can save costs.

[0082] In addition to providing Figure 2a In addition to the method shown, a cache prefetch method is also provided, which is applied to a target processor running a target application, and the target processor includes multiple hardware modules for prefetch control. The values ​​of the multiple hardware modules are configured according to the prefetch parameter configuration method provided in the above embodiment of the present application. The specific configuration process can be referred to the above embodiment, which will not be repeated here. This embodiment focuses on the process of the processor performing cache prefetching based on the values ​​of multiple hardware modules.

[0083] like Figure 3 As shown, the method includes:

[0084] 301. Reading values ​​of multiple hardware modules, wherein the values ​​of the multiple hardware modules are combined to form a target prefetch parameter combination for prefetch control;

[0085] 302. During the running of the target application, a prefetch operation is performed based on a target prefetch parameter combination.

[0086] Among them, multiple hardware modules can be implemented as pre-fetch registers. In the following content of this embodiment, the pre-fetch register will be used as an example for description, but it is not limited to the pre-fetch register and can also be other hardware structures.

[0087] Based on the prefetch parameter configuration method provided in the embodiment of the present application, a target prefetch parameter combination for prefetch control can be obtained, and the corresponding prefetch register value of the target processor is configured based on the target prefetch parameter combination. In the cache prefetch process, the target processor reads the values ​​of multiple prefetch registers included in the target processor. In the process of running the target application, a data prefetch operation can be performed based on the target prefetch parameter combination, or an instruction prefetch operation can be performed based on the target prefetch parameter combination, or a data prefetch operation and an instruction prefetch operation can be performed based on the target prefetch parameter combination.

[0088] In an optional embodiment, the target prefetch parameter combination includes: a set of values ​​corresponding to the prefetch algorithm selection parameter and the prefetch operation execution control parameter; the target processor includes a plurality of prefetchers for performing data and / or instruction prefetching, and the prefetchers are used to perform prefetch operations, and the details can be seen above. Based on this, a specific implementation method of performing data and / or instruction prefetch operations based on the target prefetch parameter combination during the running of the target application includes: during the running of the target application, according to the value of the prefetch algorithm selection parameter, selecting a target prefetcher from a plurality of prefetchers supported by the target processor; according to the value of the prefetch operation execution control parameter, controlling the target prefetcher to perform a data prefetch operation or an instruction prefetch operation, or controlling the target prefetcher to perform a data prefetch operation and an instruction prefetch operation at the same time.

[0089] Optionally, the prefetch operation execution control parameters include at least: prefetch time control parameters, prefetch data amount control parameters, prefetch position control parameters and storage position control parameters. The prefetch time control parameter can be how long in advance to prefetch data for the task to be executed, for example, it can be 1ms or 1um, etc.; the prefetch data amount control parameter can include but is not limited to: the prefetch data amount of the L1 cache, the prefetch data amount of the L2 cache, the prefetch data amount of the LLC, and the cache data amount of the memory, etc.; the prefetch position control parameter refers to which storage location to obtain data from, for example, a hard disk or disk, etc.; the storage position control parameter can include but is not limited to: L1 cache, L2 cache, LLC, and memory, etc. An implementation method of controlling a target prefetcher to perform data and / or instruction prefetch operations according to the prefetch operation execution control parameters includes: according to the prefetch time control parameter and the prefetch data amount control parameter, controlling the target prefetcher to read data from the first storage location pointed to by the prefetch position control parameter, and writing the read data to the second storage location pointed to by the storage position control parameter. Wherein, the read and write speed of the second storage location is greater than the read and write speed of the first storage location; for example, the first storage location may be an L1 cache, and the second storage location may be an L2 cache; for another example, the first storage location may be an L2 cache, and the second storage location may be an LLC cache. Alternatively, according to the prefetch time control parameter and the prefetch data amount control parameter, the target prefetcher is controlled to read instructions from the first storage location pointed to by the prefetch position control parameter, and write the read instructions to the second storage location pointed to by the storage location control parameter. Alternatively, according to the prefetch time control parameter and the prefetch data amount control parameter, the target prefetcher is controlled to read data and instructions from the first storage location pointed to by the prefetch position control parameter, and write the read data and instructions to the second storage location pointed to by the storage location control parameter.

[0090] It is explained here that, depending on the different prefetchers supported by the target processor, the prefetch process and the prefetch operation control parameters required in the prefetch process will also be different. Correspondingly, the process of performing the prefetch operation according to the values ​​of multiple prefetch registers will also be different. Based on the disclosed content of the embodiments of the present application, it is easy for technical personnel in this field to think of and implement flexibly. Therefore, any scheme that can configure the values ​​of multiple prefetch registers and perform prefetch control on the prefetcher in the target processor through the values ​​of multiple prefetch registers is within the protection scope of the embodiments of the present application.

[0091] It should be noted that the execution subject of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution subject of steps 101 to 103 can be device A; for another example, the execution subject of steps 101 and 102 can be device A, and the execution subject of step 103 can be device B; and so on.

[0092] In addition, in some of the processes described in the above embodiments and the accompanying drawings, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or executed in parallel, and the sequence numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., do not represent the order of precedence, and do not limit the "first" and "second" to be different types.

[0093] Figure 4 A schematic diagram of the structure of a pre-fetch parameter configuration device provided in an exemplary embodiment of the present application is shown in FIG. Figure 4 As shown, the device includes: a determination module 41, a grouping module 43, an optimization module 44 and a configuration module 45;

[0094] A determination module 41 is used to determine a target application and a target processor responsible for running the target application, wherein the target processor includes a plurality of hardware modules for prefetch control, and the value combinations between the plurality of hardware modules form a plurality of prefetch parameter combinations;

[0095] A grouping module 43, used for grouping the plurality of prefetch parameter combinations according to the number of the plurality of prefetch algorithms supported by the target processor to obtain a plurality of parameter spaces;

[0096] The optimization module 44 is used to optimize the pre-fetch parameter combination for multiple parameter spaces according to the performance distribution model of the target application to obtain a target pre-fetch parameter combination;

[0097] The configuration module 45 is used to configure the values ​​of multiple hardware modules according to the target prefetch parameter combination, so that the target processor performs the prefetch operation according to the target prefetch parameter combination.

[0098] In an optional embodiment, different hardware modules among the multiple hardware modules represent different prefetch parameters, and the multiple hardware modules include a hardware module representing a prefetch algorithm selection parameter and a hardware module representing a prefetch operation execution control parameter; wherein, a prefetch parameter has at least two hardware module values, and different hardware module values ​​are mutually exclusive; and a prefetch parameter combination includes a prefetch algorithm selection parameter and a prefetch operation execution control parameter.

[0099] In an optional embodiment, the determination module 41 is specifically used to: receive a pre-fetch parameter configuration task, which includes description information of the target application and description information of the target processor; determine the target application and the target processor according to the description information of the target application and the description information of the target processor, respectively; or display a task configuration interface, which includes application configuration options and processor configuration options; and determine the target application and the target processor in response to configuration operations on the application configuration options and the processor configuration options.

[0100] In an alternative embodiment, if Figure 4 As shown, the device further includes: a construction module 42, which is used to construct a performance distribution model for the target application, and the performance distribution model is used to reflect the performance distribution of the target application when it is actually running under various pre-fetch parameter combinations.

[0101] Furthermore, the construction module 42 is specifically used to: perform initial sampling on multiple prefetch parameter combinations to obtain at least one initial prefetch parameter combination; control the target processor to run the target application based on the at least one initial prefetch parameter combination to obtain at least one initial performance data; and construct a distribution function of the performance data of the target application with respect to the prefetch parameter combination as a performance distribution model based on at least one initial prefetch parameter combination and at least one initial performance data.

[0102] In an optional embodiment, the grouping module 43 is specifically used to: for any prefetching algorithm, determine a first group of hardware modules that will affect the prefetching algorithm and a second group of hardware modules that will not affect the prefetching algorithm among multiple hardware modules; from a variety of prefetching parameter combinations, select some expected parameter combinations in which the values ​​of the first group of hardware modules are valid and the values ​​of the second group of hardware modules are invalid as the parameter space corresponding to the prefetching algorithm.

[0103] In an optional embodiment, the optimization module 44 is specifically used to: for any parameter space, perform T rounds of optimization processing on the prefetch parameter combinations in the parameter space according to the performance distribution model to obtain T prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T prefetch parameter combinations; based on the T target performance data, select a target prefetch parameter combination from the T prefetch parameter combinations; wherein the performance distribution model is continuously updated during the T rounds of optimization processing, T is a positive integer, and T is less than the number of prefetch parameter combinations in the parameter space.

[0104] Optionally, the optimization module 44 is specifically used to: for any round of optimization processing, use a sampling function, combined with the performance distribution model of the previous round, to perform sampling of the prefetch parameter combinations in the parameter space in this round to obtain the prefetch parameter combinations of this round; based on the prefetch parameter combinations of this round, control the target processor to run the target application to obtain the target performance data of this round; according to the prefetch parameter combinations of this round and the target performance data of this round, update the performance distribution model of the previous round to obtain the performance distribution model of this round.

[0105] Further optionally, the optimization module 44 is specifically used to: for any round of optimization processing, combine the performance distribution model of the previous round to obtain the performance distribution information that the pre-fetching parameter combinations of this round need to meet; based on the sampling function and the performance distribution information, select a group of pre-fetching parameter combinations whose performance loss meets the preset conditions as the pre-fetching parameter combinations of this round.

[0106] In an optional embodiment, the target application is hosted in a virtualized instance, and the virtualized instance exclusively occupies the target processor.

[0107] Figure 5 A schematic diagram of the structure of a cache prefetch device provided in an exemplary embodiment of the present application, the device can be applied to a target processor, the target processor is responsible for running a target application, and the target processor includes multiple hardware modules for prefetch control, and the values ​​of the multiple hardware modules are configured according to the prefetch parameter configuration method provided in an embodiment of the present application; Figure 5 As shown, the device includes: a reading module 51 and a pre-fetching module 52;

[0108] A reading module 51 is used to read values ​​of multiple hardware modules, and the values ​​of the multiple hardware modules are combined to form a target prefetch parameter combination for prefetch control;

[0109] The prefetch module 52 is used to perform a prefetch operation based on a target prefetch parameter combination during the running of the target application.

[0110] In an optional embodiment, the target prefetch parameter combination includes: a prefetch algorithm selection parameter and a prefetch operation execution control parameter; the prefetch module is specifically used to: in the process of running the target application, select a target prefetcher from a variety of prefetchers supported by the target processor according to the value of the prefetch algorithm selection parameter; control the target prefetcher to perform the prefetch operation according to the value of the prefetch operation execution control parameter.

[0111] Optionally, the prefetch operation execution control parameters include at least: a prefetch time control parameter, a prefetch data amount control parameter, a prefetch position control parameter and a storage position control parameter; the prefetch module is specifically used to: according to the prefetch time control parameter and the prefetch data amount control parameter, control the target prefetcher to read data and / or instructions from the first storage location pointed to by the prefetch position control parameter, and write the read data and / or instructions to the second storage location pointed to by the storage position control parameter; wherein the read and write speed of the second storage location is greater than the read and write speed of the first storage location.

[0112] Regarding the embodiments of the present application Figure 4-5 The detailed implementation and beneficial effects of each step in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0113] Figure 6 The following is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present application. Figure 6 As shown, the device includes: a memory 64 and a processor 65.

[0114] The memory 64 is used to store computer programs and can be configured to store various other data to support operations on the electronic device. Examples of such data include instructions for any application program or method operating on the electronic device.

[0115] The memory 64 can be implemented by any type of volatile or nonvolatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0116] The processor 65 is coupled to the memory 64 and is used to execute the computer program in the memory 64 to: determine a target application and a target processor responsible for running the target application, the target processor includes multiple hardware modules for prefetch control, and the value combination between the multiple hardware modules forms a plurality of prefetch parameter combinations; according to the number of multiple prefetch algorithms supported by the target processor, the multiple prefetch parameter combinations are grouped to obtain multiple parameter spaces; according to the performance distribution model of the target application, the multiple parameter spaces are optimized for the prefetch parameter combination to obtain the target prefetch parameter combination; according to the target prefetch parameter combination, the values ​​of the multiple hardware modules are configured so that the target processor performs the prefetch operation according to the target prefetch parameter combination.

[0117] In an optional embodiment, different hardware modules among the multiple hardware modules represent different prefetch parameters, and the multiple hardware modules include a hardware module representing a prefetch algorithm selection parameter and a hardware module representing a prefetch operation execution control parameter; wherein, a prefetch parameter has at least two hardware module values, and different hardware module values ​​are mutually exclusive; and a prefetch parameter combination includes a prefetch algorithm selection parameter and a prefetch operation execution control parameter.

[0118] In an optional embodiment, when determining the target application hosted in the virtualization instance and the target processor responsible for running the target application, the processor 65 is specifically used to: receive a pre-fetch parameter configuration task, which includes description information of the target application and description information of the target processor; determine the target application and the target processor according to the description information of the target application and the description information of the target processor, respectively; or display a task configuration interface, which includes application configuration options and processor configuration options; and respond to configuration operations on the application configuration options and the processor configuration options to determine the target application and the target processor.

[0119] In an optional embodiment, when the processor 65 constructs a performance distribution model for a target application, it is specifically used to: perform initial sampling on multiple prefetch parameter combinations to obtain at least one initial prefetch parameter combination; control the target processor to run the target application based on the at least one initial prefetch parameter combination to obtain at least one initial performance data; and construct a distribution function of the performance data of the target application with respect to the prefetch parameter combination as a performance distribution model based on the at least one initial prefetch parameter combination and the at least one initial performance data.

[0120] In an optional embodiment, when the processor 65 groups multiple prefetch parameter combinations according to the number of multiple prefetch algorithms supported by the target processor to obtain multiple parameter spaces, it is specifically used to: for any prefetch algorithm, determine a first group of hardware modules that will affect the prefetch algorithm and a second group of hardware modules that will not affect the prefetch algorithm among multiple hardware modules; from the multiple prefetch parameter combinations, select some expected parameter combinations in which the values ​​of the first group of hardware modules are valid and the values ​​of the second group of hardware modules are invalid as the parameter space corresponding to the prefetch algorithm.

[0121] In an optional embodiment, when the processor 65 optimizes the prefetch parameter combinations for multiple parameter spaces according to the performance distribution model to obtain the target prefetch parameter combinations, it is specifically used to: for any parameter space, according to the performance distribution model, perform T rounds of optimization processing on the prefetch parameter combinations in the parameter space to obtain T prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T prefetch parameter combinations; according to the T target performance data, select the target prefetch parameter combination from the T prefetch parameter combinations; wherein the performance distribution model is continuously updated during the T rounds of optimization processing, T is a positive integer, and T is less than the number of prefetch parameter combinations in the parameter space.

[0122] Optionally, when the processor 65 performs T rounds of iterative optimization processing on the prefetch parameter combinations in the parameter space according to the performance distribution model to obtain T prefetch parameter combinations and T target performance data generated by the target processor using the T prefetch parameter combinations to run the target application, it is specifically used to: for any round of optimization processing, use a sampling function, combined with the performance distribution model of the previous round, to perform this round of sampling on the prefetch parameter combinations in the parameter space to obtain the prefetch parameter combinations of this round; based on the prefetch parameter combinations of this round, control the target processor to run the target application to obtain the target performance data of this round; and update the performance distribution model of the previous round according to the prefetch parameter combinations of this round and the target performance data of this round to obtain the performance distribution model of this round.

[0123] Further optionally, the processor 65, during any round of optimization processing, uses a sampling function and combines the performance distribution model of the previous round to perform sampling of the prefetch parameter combinations in the parameter space in this round to obtain the prefetch parameter combinations of this round. Specifically, it is used to: during any round of optimization processing, combine the performance distribution model of the previous round to obtain the performance distribution information that the prefetch parameter combinations of this round need to satisfy; and select, based on the sampling function and the performance distribution information, a group of prefetch parameter combinations whose performance loss satisfies preset conditions as the prefetch parameter combinations of this round.

[0124] In an optional embodiment, the target application is hosted in a virtualized instance, and the virtualized instance exclusively occupies the target processor.

[0125] Regarding the embodiments of the present application Figure 6 The detailed implementation and beneficial effects of each step in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0126] Further, if Figure 6 As shown, the electronic device also includes: a communication component 66, a display 67, a power component 68, an audio component 69 and other components. Figure 6Only some components are shown schematically, which does not mean that the electronic device only includes Figure 6 In addition, Figure 6 The components in the dashed box are optional components, not mandatory components, and the specific components depend on the product form of the electronic device. The electronic device of this embodiment can be implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone, or an IOT device, or a server device such as a conventional server, a cloud server, or a server array. If the electronic device of this embodiment is implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone, etc., it can include Figure 6 If the electronic device of this embodiment is implemented as a server device such as a conventional server, a cloud server or a server array, it may not include Figure 6 Components within the dashed box.

[0127] An embodiment of the present application also provides a processor, which is responsible for running a target application. The processor includes: multiple hardware modules for prefetch control, the values ​​of the multiple hardware modules are configured according to the prefetch parameter configuration method provided in the embodiment of the present application, and the processor is used to: read the values ​​of the multiple hardware modules, the values ​​of the multiple hardware modules are combined to form a target prefetch parameter combination for prefetch control; in the process of running the target application, perform a prefetch operation based on the target prefetch parameter combination.

[0128] In an optional embodiment, the target prefetch parameter combination includes: a prefetch algorithm selection parameter and a prefetch operation execution control parameter; when the processor performs a prefetch operation based on the target prefetch parameter combination during the running of the target application, it is specifically used to: during the running of the target application, according to the value of the prefetch algorithm selection parameter, select a target prefetcher from a variety of prefetchers supported by the target processor; according to the value of the prefetch operation execution control parameter, control the target prefetcher to perform the prefetch operation.

[0129] Optionally, the prefetch operation execution control parameters include at least: a prefetch time control parameter, a prefetch data amount control parameter, a prefetch position control parameter and a storage position control parameter; when the processor controls the target prefetcher to perform the prefetch operation according to the prefetch operation execution control parameters, it is specifically used to: control the target prefetcher to read data and / or instructions from the first storage location pointed to by the prefetch position control parameter according to the prefetch time control parameter and the prefetch data amount control parameter, and write the read data and / or instructions to the second storage location pointed to by the storage position control parameter; wherein the read and write speed of the second storage location is greater than the read and write speed of the first storage location.

[0130] Accordingly, the embodiment of the present application further provides a computer-readable storage medium storing a computer program, which can achieve the above-mentioned Figure 2a and Figure 3The steps in the method embodiment are shown.

[0131] The above-mentioned memory can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0132] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0133] The above-mentioned display includes a screen, and the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0134] The power supply assembly provides power to various components of the device where the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device where the power supply assembly is located.

[0135] The above-mentioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (Microphone, MIC), and when the device where the audio component is located is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting an audio signal.

[0136] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-readable storage media (including but not limited to disk storage, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical storage, etc.) containing computer-usable program code.

[0137] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0138] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0139] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0140] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interface, network interface and memory.

[0141] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0142] Computer readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0143] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0144] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for configuring prefetch parameters, characterized in that: include: Determine a target application and a target processor responsible for running the target application, wherein the target processor includes a plurality of hardware modules for prefetch control, and the value combinations between the plurality of hardware modules form a plurality of prefetch parameter combinations; According to the number of the plurality of prefetch algorithms supported by the target processor, the plurality of prefetch parameter combinations are grouped to obtain a plurality of parameter spaces; According to the performance distribution model of the target application, optimizing the pre-fetch parameter combination of the multiple parameter spaces to obtain a target pre-fetch parameter combination; According to the target prefetch parameter combination, the values ​​of the multiple hardware modules are configured so that the target processor performs a prefetch operation according to the target prefetch parameter combination.

2. The method according to claim 1, characterized in that Different hardware modules among the plurality of hardware modules represent different pre-fetch parameters, and the plurality of hardware modules include hardware modules representing pre-fetch algorithm selection parameters and hardware modules representing pre-fetch operation execution control parameters; Among them, a prefetch parameter has at least two values, and different values ​​are mutually exclusive; a prefetch parameter combination includes a prefetch algorithm selection parameter and a prefetch operation execution control parameter.

3. The method according to claim 1, characterized in that Determining a target application and a target processor responsible for running the target application, including: Receiving a pre-fetch parameter configuration task, wherein the pre-fetch parameter configuration task includes description information of a target application and description information of a target processor; determining a target application and a target processor respectively according to the description information of the target application and the description information of the target processor; or A task configuration interface is displayed, wherein the task configuration interface includes application configuration options and processor configuration options; and a target application and a target processor are determined in response to configuration operations on the application configuration options and the processor configuration options.

4. The method according to claim 1, characterized in that: Also includes: Performing initial sampling on the plurality of pre-fetch parameter combinations to obtain at least one initial pre-fetch parameter combination; Controlling the target processor to run the target application based on the at least one initial prefetch parameter combination to obtain at least one initial performance data; According to the at least one initial pre-fetch parameter combination and the at least one initial performance data, a distribution function of the performance data characterizing the target application with respect to the pre-fetch parameter combination is constructed as the performance distribution model.

5. The method according to claim 1, characterized in that According to the number of the plurality of prefetch algorithms supported by the target processor, the plurality of prefetch parameter combinations are grouped to obtain a plurality of parameter spaces, including: For any prefetch algorithm, determining a first group of hardware modules that will affect the prefetch algorithm and a second group of hardware modules that will not affect the prefetch algorithm among the multiple hardware modules; From the multiple pre-fetch parameter combinations, some expected parameter combinations in which the values ​​of the first group of hardware modules are valid and the values ​​of the second group of hardware modules are invalid are selected as the parameter space corresponding to the pre-fetch algorithm.

6. The method according to claim 1, characterized in that According to the performance distribution model of the target application, the plurality of parameter spaces are optimized for pre-fetching parameter combinations to obtain a target pre-fetching parameter combination, including: For any parameter space, according to the performance distribution model, T rounds of optimization processing are performed on the prefetch parameter combinations in the parameter space to obtain T prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T prefetch parameter combinations; According to the T target performance data, a target prefetch parameter combination is selected from the T prefetch parameter combinations; wherein the performance distribution model is continuously updated in T rounds of optimization processing, T is a positive integer, and T is less than the number of prefetch parameter combinations in the parameter space.

7. The method according to claim 6, characterized in that According to the performance distribution model, T rounds of iterative optimization processing are performed on the prefetch parameter combinations in the parameter space to obtain T prefetch parameter combinations and T target performance data generated by the target processor running the target application using the T prefetch parameter combinations, including: For any round of optimization, a sampling function is used to sample the pre-fetch parameter combinations in the parameter space in combination with the performance distribution model of the previous round to obtain the pre-fetch parameter combinations of this round. Controlling the target processor to run the target application based on the prefetch parameter combination of this round to obtain target performance data of this round; According to the pre-fetch parameter combination of this round and the target performance data of this round, the performance distribution model of the previous round is updated to obtain the performance distribution model of this round.

8. The method according to claim 7, characterized in that For any round of optimization, the sampling function is used to sample the pre-fetch parameter combinations in the parameter space in combination with the performance distribution model of the previous round, and the pre-fetch parameter combinations of this round are obtained, including: For any round of optimization, the performance distribution model of the previous round is combined to obtain the performance distribution information that the prefetch parameter combination of this round needs to meet; According to the sampling function and the performance distribution information, a group of pre-fetch parameter combinations whose performance loss meets a preset condition is selected as the pre-fetch parameter combination of this round.

9. The method according to any one of claims 1 to 8, characterized in that: The target application is hosted in a virtualized instance, and the virtualized instance exclusively occupies the target processor.

10. A cache prefetching method, characterized in that: A target processor for running a target application, the target processor comprising a plurality of hardware modules for prefetch control, wherein values ​​of the plurality of hardware modules are configured according to a method according to any one of claims 1 to 9; the method comprising: Reading values ​​of the multiple hardware modules, wherein the values ​​of the multiple hardware modules are combined to form a target prefetch parameter combination for prefetch control; During the running of the target application, a prefetch operation is performed based on the target prefetch parameter combination.

11. The method according to claim 10, characterized in that The target prefetch parameter combination includes: prefetch algorithm selection parameters and prefetch operation execution control parameters; In the process of running the target application, performing a prefetch operation based on the target prefetch parameter combination includes: In the process of running the target application, selecting a target prefetcher from a plurality of prefetchers supported by the target processor according to a value of a parameter selected by the prefetch algorithm; According to the value of the prefetch operation execution control parameter, the target prefetcher is controlled to execute the prefetch operation.

12. The method according to claim 11, characterized in that The pre-fetch operation execution control parameters at least include: pre-fetch time control parameters, pre-fetch data amount control parameters, pre-fetch position control parameters and storage position control parameters; Controlling the target prefetcher to perform the prefetch operation according to the prefetch operation execution control parameter includes: According to the prefetch time control parameter and the prefetch data amount control parameter, the target prefetcher is controlled to read data and / or instructions from the first storage location pointed to by the prefetch position control parameter, and write the read data and / or instructions to the second storage location pointed to by the storage position control parameter; wherein the reading and writing speed of the second storage location is greater than the reading and writing speed of the first storage location.

13. An electronic device, characterized in that: include: Memory and processor; The memory is used for computer programs; the processor is coupled to the memory and is used to execute the computer program to implement the steps in the method according to any one of claims 1 to 9.

14. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is caused to implement the steps in the method according to any one of claims 1 to 9 and claims 10 to 12.

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